From: hadeshyp Date: Mon, 18 Jul 2011 17:44:52 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~112 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=15680773345997598ab217ddf505a6e1e4f9de54;p=trbnet.git *** empty log message *** --- diff --git a/special/handler_lvl1.vhd b/special/handler_lvl1.vhd index 6dfb5d7..695cfa4 100644 --- a/special/handler_lvl1.vhd +++ b/special/handler_lvl1.vhd @@ -12,6 +12,7 @@ generic( ); port( RESET : in std_logic; + RESET_FLAGS_IN : in std_logic; RESET_STATS_IN : in std_logic; CLOCK : in std_logic; --Timing Trigger @@ -537,7 +538,7 @@ end process COUNT_EDGES_AND_LENGTH_PROC; WRONG_POLAR_PROC : process(CLOCK) begin if rising_edge(CLOCK) then - if (RESET = '1') or (RESET_STATS_IN = '1') then + if (RESET = '1') or (RESET_FLAGS_IN = '1') then wrong_polarity <= '0'; elsif (trigger_length > 100) then wrong_polarity <= '1'; @@ -612,7 +613,7 @@ begin STATUS_OUT(10 downto 8) <= (others => '0'); STATUS_OUT(3 downto 0) <= bsm_x; - if (RESET = '1') or (RESET_STATS_IN = '1') then + if (RESET = '1') or (RESET_FLAGS_IN = '1') then STATUS_OUT(7 downto 4) <= (others => '0'); STATUS_OUT(13) <= '0'; elsif (val_trg = '1') or (invalid_trg = '1') then diff --git a/special/trb_net_bridge_pcie_endpoint_hub.vhd b/special/trb_net_bridge_pcie_endpoint_hub.vhd index 6082731..537df7d 100644 --- a/special/trb_net_bridge_pcie_endpoint_hub.vhd +++ b/special/trb_net_bridge_pcie_endpoint_hub.vhd @@ -16,6 +16,7 @@ entity trb_net_bridge_pcie_endpoint_hub is ); port( RESET : in std_logic; + RESET_TRBNET : in std_logic; CLK : in std_logic; CLK_125_IN : in std_logic; @@ -205,8 +206,6 @@ architecture trb_net_bridge_pcie_endpoint_hub_arch of trb_net_bridge_pcie_endpoi signal spimem_data_out : std_logic_vector(31 downto 0); signal spi_fake_ack : std_logic; - signal dma_start_address_i : std_logic_vector(31 downto 0); - signal dma_length_i : std_logic_vector(31 downto 0); signal dma_control_i : std_logic_vector(31 downto 0); signal dma_status_i : std_logic_vector(31 downto 0); signal dma_config_i : std_logic_vector(31 downto 0); @@ -228,7 +227,6 @@ architecture trb_net_bridge_pcie_endpoint_hub_arch of trb_net_bridge_pcie_endpoi begin - RESET_i <= RESET; APL_MY_ADDRESS_IN <= x"FCCC"; THE_HUB : trb_net16_hub_base @@ -243,7 +241,7 @@ begin USE_ONEWIRE => c_NO, BROADCAST_SPECIAL_ADDR => x"FF", MII_NUMBER => NUM_LINKS, - MII_IS_UPLINK => (NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES, others => c_NO), --NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES, + MII_IS_UPLINK => (NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES, 0 => c_YES, others => c_NO), --NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES, MII_IS_DOWNLINK => (others => c_YES), --NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES, MII_IS_UPLINK_ONLY => (others => c_NO), --NUM_LINKS => c_YES, INIT_ENDPOINT_ID => x"0001", @@ -252,7 +250,7 @@ begin ) port map ( CLK => CLK, - RESET => RESET, + RESET => RESET_TRBNET, CLK_EN => '1', --Media interfacces @@ -327,7 +325,7 @@ begin port map ( -- Misc CLK => CLK, - RESET => RESET_i, + RESET => RESET_TRBNET, CLK_EN => '1', -- APL Transmitter port APL_DATA_IN => APL_DATA_IN(i*16+15 downto i*16), @@ -447,10 +445,6 @@ begin & "00000" & apl_fifo_count_out(11*channel_address+10 downto 11*channel_address); when x"30" => bus_data_i <= api_status(channel_address*32+31 downto channel_address*32); - when x"70" => - bus_data_i <= dma_start_address_i; - when x"71" => - bus_data_i <= dma_length_i; when x"72" => bus_data_i <= dma_status_i; when x"73" => @@ -484,7 +478,7 @@ begin sender_error <= (others => '0'); dma_control_i <= (others => '0'); reg_extended_trigger_information <= (others => '0'); - dma_config_i <= x"00000030"; + dma_config_i <= x"00000020"; wren_length_fifo <= '0'; wren_addr_fifo <= '0'; else @@ -616,7 +610,7 @@ df_read(1) <= '1' when BUS_ADDR_IN(15 downto 0) = x"0e01" and bus_read_i = '1' e THE_DMA_CORE : dma_core port map( - RESET_IN => reset_i, + RESET_IN => RESET, CLK_IN => CLK, CLK_125_IN => CLK_125_IN, diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index 1227956..6ff5e2a 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -842,7 +842,7 @@ begin if buf_REGIO_COMMON_CTRL_REG_OUT(4) = '1' then lvl1_tmg_trg_missing_flag <= '0'; - elsif int_lvl1_missing_tmg_trg = '1' then + elsif int_lvl1_missing_tmg_trg = '1' or int_lvl1_spurious_trg = '1' or int_spike_detected = '1' then lvl1_tmg_trg_missing_flag <= '1'; end if; @@ -887,6 +887,7 @@ begin ) port map( RESET => reset_trg_logic, + RESET_FLAGS_IN => buf_REGIO_COMMON_CTRL_REG_OUT(4), RESET_STATS_IN => buf_REGIO_COMMON_CTRL_REG_OUT(5), CLOCK => CLK, --Timing Trigger diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index 4db9bbf..c2231e2 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -59,6 +59,7 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal INIT_POOL_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal init_has_read_from_pool : std_logic_vector(POINT_NUMBER-1 downto 0); signal saved_INIT_TYPE, current_INIT_TYPE : std_logic_vector(2 downto 0); + signal buf_INIT_DATAREADY_OUT : std_logic_vector (POINT_NUMBER-1 downto 0); signal buf_INIT_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); signal buf_REPLY_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); @@ -300,11 +301,11 @@ begin --Output init data to obufs ---------------------------------- gen_init_data_out: for i in 0 to POINT_NUMBER-1 generate - INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_has_read_from_pool(i) and real_activepoints(i) and not locking_point(i); + buf_INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_has_read_from_pool(i) and real_activepoints(i) and not locking_point(i); INIT_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= INIT_POOL_DATA; INIT_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= INIT_POOL_PACKET_NUM; end generate; - +INIT_DATAREADY_OUT <= buf_INIT_DATAREADY_OUT; ---------------------------------- --Locking of channels @@ -584,7 +585,7 @@ begin -- elsif timer_ms_tick = '1' and INIT_READ_IN(i) = '0' and INIT_DATAREADY_OUT(i) = '1' then -- timeout_counter(i) <= timeout_counter(i) + to_unsigned(2,2); elsif timer_ms_tick = '1' and ((REPLY_POOL_next_read = '1') -- and got_trm(i) = '0' - or (INIT_READ_IN(i) = '0' and INIT_DATAREADY_OUT(i) = '1')) then + or (INIT_READ_IN(i) = '0' and buf_INIT_DATAREADY_OUT(i) = '1')) then timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1); end if; end if; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 04f5345..7477270 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -354,6 +354,7 @@ component trb_net_bridge_pcie_endpoint_hub is ); port( RESET : in std_logic; + RESET_TRBNET : in std_logic; CLK : in std_logic; CLK_125_IN : in std_logic; @@ -1157,6 +1158,7 @@ end component; ); port( RESET : in std_logic; + RESET_FLAGS_IN : in std_logic; RESET_STATS_IN : in std_logic; CLOCK : in std_logic; --Timing Trigger