From: Jan Michel <michel@physik.uni-frankfurt.de>
Date: Fri, 12 May 2023 13:49:04 +0000 (+0200)
Subject: add option of reference time output on output multiplexers to CTS
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=15c5c7a370e1b268f07617510c01d6772dd956df;p=trb3.git

add option of reference time output on output multiplexers to CTS
---

diff --git a/cts/compile_central_frankfurt.pl b/cts/compile_central_frankfurt.pl
index 3101f63..7cebf74 100755
--- a/cts/compile_central_frankfurt.pl
+++ b/cts/compile_central_frankfurt.pl
@@ -16,8 +16,8 @@ my $CbmNetPath                   = "../../cbmnet";
 my $lm_license_file_for_synplify = "27020\@jspc29"; #"27000\@lxcad01.gsi.de";
 my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
 
-my $lattice_path                 = '/d/jspc29/lattice/diamond/3.10_x64';
-my $synplify_path                = '/d/jspc29/lattice/synplify/P-2019.09-SP1';
+my $lattice_path                 = '/d/jspc29/lattice/diamond/3.12';
+my $synplify_path                = '/d/jspc29/lattice/synplify/T-2022.09-SP2';
 ###################################################################################
 
 
diff --git a/cts/config_straw.vhd b/cts/config_straw.vhd
index 302d0dc..5704988 100644
--- a/cts/config_straw.vhd
+++ b/cts/config_straw.vhd
@@ -57,6 +57,7 @@ package config is
     constant ADDON_LINE_COUNT        : integer := 38;    
     constant CTS_OUTPUT_MULTIPLEXERS : integer := 8;
     
+
 ------------------------------------------------------------------------------
 --End of configuration
 ------------------------------------------------------------------------------
@@ -103,6 +104,7 @@ package config is
     constant IS_DOWNLINK          : hub_ct;
     constant IS_UPLINK_ONLY       : hub_ct;
     constant HARDWARE_INFO        : std_logic_vector(31 downto 0);
+    constant BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"c0";
     
     -- MII_NUMBER        => 5, --(8)
     -- INT_NUMBER        => 5,
diff --git a/cts/source/cts.vhd b/cts/source/cts.vhd
index 580b87b..df84a69 100755
--- a/cts/source/cts.vhd
+++ b/cts/source/cts.vhd
@@ -344,7 +344,7 @@ architecture RTL of CTS is
    signal eb_regio_updated_i : std_logic := '0';
    
    signal trg_information_reg : std_logic_vector(23 downto 0);
-   
+   signal time_reference_i : std_logic;
    signal busy_out_i : std_logic;
    --japanese synchronous read-out option
    --signal busy_out_counter : unsigned(3 downto 0);
@@ -692,24 +692,25 @@ TRIGGER_BUSY_OUT <= busy_out_i;
       variable time_reference_counter_v : integer range 0 to TIME_REFERENCE_COUNT := TIME_REFERENCE_COUNT;
    begin
       if rising_edge(CLK) then
-         TIME_REFERENCE_OUT <= '0';
+         time_reference_i <= '0';
          if RESET = '1' then
             time_reference_counter_v := TIME_REFERENCE_COUNT - 1;
          else
             if time_reference_start_i = '1' then
                -- start
                time_reference_counter_v := 0;
-               TIME_REFERENCE_OUT <= '1';
+               time_reference_i <= '1';
             
             elsif time_reference_counter_v /= TIME_REFERENCE_COUNT - 1 then
                -- increment
                time_reference_counter_v := time_reference_counter_v + 1;
-               TIME_REFERENCE_OUT <= '1';
+               time_reference_i <= '1';
 
             end if;
          end if;
       end if;
    end process;
+TIME_REFERENCE_OUT <= time_reference_i;
 
 -- Pseudo Random Number Generation
 -----------------------------------------
@@ -818,6 +819,7 @@ TRIGGER_BUSY_OUT <= busy_out_i;
       PERIPH_TRIGGER_IN => PERIPH_TRIGGER_IN,
       
       OUTPUT_MULTIPLEXERS_OUT => OUTPUT_MULTIPLEXERS_OUT,
+      TIME_REFERENCE_IN       => time_reference_i,
       
       EXT_TRIGGER_IN  => EXT_TRIGGER_IN,
       EXT_STATUS_IN   => EXT_STATUS_IN,
diff --git a/cts/source/cts_pkg.vhd b/cts/source/cts_pkg.vhd
index a3011a0..094e62b 100755
--- a/cts/source/cts_pkg.vhd
+++ b/cts/source/cts_pkg.vhd
@@ -209,6 +209,7 @@ package cts_pkg is
          PERIPH_TRIGGER_IN : in std_logic_vector(19 downto 0) := (others => '0');
          
          OUTPUT_MULTIPLEXERS_OUT : out std_logic_vector(OUTPUT_MULTIPLEXERS-1 downto 0);
+         TIME_REFERENCE_IN : in std_logic;
          
       -- External 
          EXT_TRIGGER_IN  : in std_logic;
diff --git a/cts/source/cts_trigger.vhd b/cts/source/cts_trigger.vhd
index af0629e..1254555 100755
--- a/cts/source/cts_trigger.vhd
+++ b/cts/source/cts_trigger.vhd
@@ -41,6 +41,8 @@ entity CTS_TRIGGER is
 
       OUTPUT_MULTIPLEXERS_OUT : out std_logic_vector(OUTPUT_MULTIPLEXERS-1 downto 0);
       
+      TIME_REFERENCE_IN : in std_logic;
+      
     -- External 
       EXT_TRIGGER_IN  : in std_logic;
       EXT_STATUS_IN   : in std_logic_vector(31 downto 0) := X"00000000";
@@ -147,7 +149,7 @@ architecture RTL of CTS_TRIGGER is
    
    type output_multiplexer_configs_t is array(MAX(0,OUTPUT_MULTIPLEXERS - 1) downto 0) of std_logic_vector(7 downto 0);
    signal output_multiplexer_configs_i : output_multiplexer_configs_t;
-   signal output_multiplexer_ins_i : std_logic_vector(16 + 2*TRIGGER_INPUT_COUNT + ADDON_LINE_COUNT + TRIGGER_ADDON_COUNT + 1 downto 0);
+   signal output_multiplexer_ins_i : std_logic_vector(16 + 2*TRIGGER_INPUT_COUNT + ADDON_LINE_COUNT + TRIGGER_ADDON_COUNT + 2 downto 0);
    
 -- Trigger Type Assoc 
    type trigger_type_assoc_t is array(0 to 15) of std_logic_vector(3 downto 0);
@@ -217,7 +219,9 @@ begin
       i := i + 1;
       output_multiplexer_ins_i(i) <= TRIGGER_BUSY_IN;
       i := i + 1;
-      
+      output_multiplexer_ins_i(i) <= TIME_REFERENCE_IN;
+      i := i + 1;
+
    end process;
    
    proc_out_mux: process (output_multiplexer_ins_i, output_multiplexer_configs_i) is