From: Cahit Date: Thu, 3 Dec 2015 17:30:27 +0000 (+0100) Subject: added some more multicycle constraints to ease the placement X-Git-Tag: v2.3~63 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1641091ca73ce955f875a7ee64b6495ffa008f4f;p=tdc.git added some more multicycle constraints to ease the placement --- diff --git a/releases/tdc_v2.2/TDC_record.vhd b/releases/tdc_v2.2/TDC_record.vhd index ec08d8f..6afe545 100644 --- a/releases/tdc_v2.2/TDC_record.vhd +++ b/releases/tdc_v2.2/TDC_record.vhd @@ -211,7 +211,7 @@ begin -- Slow Control ------------------------------------------------------------------------------- - BUS_SLOWCTRL: entity work.BusHandler_record + TheSlowcontrolBus: entity work.BusHandler_record generic map ( BUS_LENGTH => 8) port map ( @@ -224,9 +224,9 @@ begin -- Slow control signals - logic_anal_control <= ctrl_reg(0)(3 downto 0) when rising_edge(CLK_READOUT); + logic_anal_control <= ctrl_reg(0)(3 downto 0); debug_mode_en <= ctrl_reg(0)(4); - light_mode_en <= ctrl_reg(0)(5) when rising_edge(CLK_READOUT); + light_mode_en <= ctrl_reg(0)(5); reset_counters <= ctrl_reg(0)(8) or reset_tdc when rising_edge(CLK_TDC); --run_mode <= ctrl_reg(0)(12); --run_mode_200 <= run_mode when rising_edge(CLK_TDC); @@ -236,9 +236,8 @@ begin trg_win_pre <= ctrl_reg(1)(10 downto 0); trg_win_post <= ctrl_reg(1)(26 downto 16); trg_win_en <= ctrl_reg(1)(31); - ch_en <= ctrl_reg(3) & ctrl_reg(2); - ring_buffer_full_thres <= ctrl_reg(4)(6 downto 0) when rising_edge(CLK_READOUT); + ring_buffer_full_thres <= ctrl_reg(4)(6 downto 0); ch_invert <= ctrl_reg(6) & ctrl_reg(5); -- Reset signals @@ -678,7 +677,7 @@ begin end generate GenHitDetectNumber; -- Status register - BusHandler_record_1: entity work.BusHandler_record + TheStatusRegisterBus: entity work.BusHandler_record generic map ( BUS_LENGTH => STATUS_REG_NR-1) port map ( @@ -730,7 +729,7 @@ begin -- Channel debug - BusHandler_record_2: entity work.BusHandler_record + TheChannelDebugBus: entity work.BusHandler_record generic map ( BUS_LENGTH => CHANNEL_NUMBER-1) port map ( diff --git a/releases/tdc_v2.2/trb3_periph_32PinAddOn.vhd b/releases/tdc_v2.2/trb3_periph_32PinAddOn.vhd index 879a22e..edd0412 100644 --- a/releases/tdc_v2.2/trb3_periph_32PinAddOn.vhd +++ b/releases/tdc_v2.2/trb3_periph_32PinAddOn.vhd @@ -423,13 +423,14 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 6, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d400", 2 => x"c000", 3 => x"cf00", 4 => x"cf80", - 5 => x"d500", - others => x"0000"), - PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 12, 3 => 6, 4 => 7, - 5 => 4, - others => 0) + PORT_NUMBER => 6, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d400", 2 => x"c000", 3 => x"cf00", 4 => x"cf80", + 5 => x"d500", + others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 12, 3 => 6, 4 => 7, + 5 => 4, + others => 0), + PORT_MASK_ENABLE => 1 ) port map( CLK => clk_100_i, @@ -504,15 +505,15 @@ begin BUS_NO_MORE_DATA_IN(4) => '0', BUS_UNKNOWN_ADDR_IN(4) => stat_nack, --SEU Detection - BUS_READ_ENABLE_OUT(5) => bussed_rx.read, - BUS_WRITE_ENABLE_OUT(5) => bussed_rx.write, - BUS_DATA_OUT(5*32+31 downto 5*32) => bussed_rx.data, - BUS_ADDR_OUT(5*16+15 downto 5*16) => bussed_rx.addr, + BUS_READ_ENABLE_OUT(5) => bussed_rx.read, + BUS_WRITE_ENABLE_OUT(5) => bussed_rx.write, + BUS_DATA_OUT(5*32+31 downto 5*32) => bussed_rx.data, + BUS_ADDR_OUT(5*16+15 downto 5*16) => bussed_rx.addr, BUS_TIMEOUT_OUT(5) => bussed_rx.timeout, - BUS_DATA_IN(5*32+31 downto 5*32) => bussed_tx.data, - BUS_DATAREADY_IN(5) => bussed_tx.ack, - BUS_WRITE_ACK_IN(5) => bussed_tx.ack, - BUS_NO_MORE_DATA_IN(5) => bussed_tx.nack, + BUS_DATA_IN(5*32+31 downto 5*32) => bussed_tx.data, + BUS_DATAREADY_IN(5) => bussed_tx.ack, + BUS_WRITE_ACK_IN(5) => bussed_tx.ack, + BUS_NO_MORE_DATA_IN(5) => bussed_tx.nack, BUS_UNKNOWN_ADDR_IN(5) => bussed_tx.unknown, STAT_DEBUG => open diff --git a/releases/tdc_v2.2/unimportant_lines_constraints.lpf b/releases/tdc_v2.2/unimportant_lines_constraints.lpf index 28c5611..3ff9c03 100644 --- a/releases/tdc_v2.2/unimportant_lines_constraints.lpf +++ b/releases/tdc_v2.2/unimportant_lines_constraints.lpf @@ -1,7 +1,15 @@ ############################################################################# ## Unimportant Data Lines ## ############################################################################# +BLOCK PATH FROM CLKNET "THE_TDC/edge_rising[*]"; +BLOCK NET "THE_TDC/hit_in_s*"; + +USE SECONDARY NET "THE_TDC/coarse_cntr_reset"; +USE SECONDARY NET "THE_TDC/trg_win_end_tdc"; + + MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x; +MULTICYCLE FROM CELL "THE_TDC/reset_tdc" 4x; MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/ReferenceChannel/Channel200/ringBuffer_almost_full_sync*" 2x; MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/ringBuffer_almost_full_sync*" 2x; @@ -14,32 +22,24 @@ MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_post*" 4 x; MULTICYCLE FROM CELL "THE_TDC/hit_edge[*]" TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/memory_ram" 2.000000 X ; -#MULTICYCLE TO CELL "THE_TDC/TheChannelDebugBus/data_out_reg[*]" 4 x; - -#MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "CLK_OSC_c" 4.000000 X ; - MULTICYCLE TO CELL "THE_TDC/edge_rising_100_r[*]" 4 x; MULTICYCLE FROM CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/ringBuffer_almost_full_flag*" TO CELL "THE_TDC/TheReadout/data_out_r[*]" 2 x; MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*" 4x; MULTICYCLE TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/SimAdderNo.FC/FF*" 4x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/CHANNEL_200_DEBUG_OUT_1[*]" 4x; +MULTICYCLE TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/CHANNEL_200_DEBUG_OUT_1[*]" 4x; -BLOCK NET "THE_TDC/hit_in_s*"; +MULTICYCLE FROM CELL "THE_TDC/TheSlowcontrolBus/DATA_OUT*" 20 ns; +MULTICYCLE TO CELL "THE_TDC/TheHitCounterBus/BUS_TX[data][*]" 20 ns; +MULTICYCLE TO CELL "THE_TDC/TheStatusRegisterBus/BUS_TX[data][*]" 20 ns; +MULTICYCLE TO CELL "THE_TDC/TheChannelDebugBus/BUS_TX[data][*]" 20 ns; +MULTICYCLE FROM CELL "THE_ENDPOINT/THE_ENDPOINT/*" TO CELL "THE_TDC/TheTriggerHandler/STATE_TW_CURRENT*" 10 ns; MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS; #DATAPATH_ONLY ; -USE SECONDARY NET "THE_TDC/coarse_cntr_reset"; -USE SECONDARY NET "THE_TDC/trg_win_end_tdc"; - - - -# MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x; - -## Maybe effective - -# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X; @@ -108,5 +108,3 @@ PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.61.Channels/Channel200/ff_array_en" PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.62.Channels/Channel200/ff_array_en"; PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.63.Channels/Channel200/ff_array_en"; PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.64.Channels/Channel200/ff_array_en"; - -