From: Jan Michel Date: Tue, 25 Jun 2024 15:40:27 +0000 (+0200) Subject: update digitizer AddOn files X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1691f182eb9a12afb771c1fb9b7a3c0eaa7517ea;p=trb5sc.git update digitizer AddOn files --- diff --git a/adc/config.vhd b/adc/config.vhd index d5183f8..9df133e 100644 --- a/adc/config.vhd +++ b/adc/config.vhd @@ -35,8 +35,8 @@ package config is -- -- 14: Debug - single fine time and the ROM addresses for the two transitions -- -- 15: Debug - complete carry chain dump - constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 9; -- size of the event buffer, 2**N - constant EVENT_MAX_SIZE : integer := 200; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 10; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 constant USE_GBE : integer := c_NO; --Runs with 120 MHz instead of 100 MHz diff --git a/adc/cores/adc_1ch/adc_1ch.lpc b/adc/cores/adc_1ch/adc_1ch.lpc new file mode 100644 index 0000000..dad2083 --- /dev/null +++ b/adc/cores/adc_1ch/adc_1ch.lpc @@ -0,0 +1,66 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=6.0 +ModuleName=adc_1ch +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=06/25/2024 +Time=16:53:10 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Receive +trioddr=0 +io_type=LVDS +width=2 +freq_in=200 +bandwidth=800 +aligned=Edge-to-Edge +pre-configuration=DISABLED +mode2=Receive +trioddr2=0 +io_type2=LVDS +freq_in2=200 +gear=2:1 +aligned2=Edge-to-Edge +width2=2 +DataLane=By Lane +EnECLK=0 +Interface=GDDRX1_RX.SCLK.Aligned +Delay=Dynamic User Defined +DelVal=11 +EnInEdge= +NumEdge=BOTH +EnDynamic=0 +GenPll=0 +Freq= +AFreq= +Reference=0 +IOBUF= +ReceiverSync=0 +EnDynamicAlign= +DynamicAlign= +MIPIFilter=0 +enClkIBuf=0 +ClkIBuf=LVDS + +[Command] +cmd_line= -w -n adc_1ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 2 -freq_in 200 -gear 2 -aligned -del 11 -dynamic_delay -data_lane diff --git a/adc/cores/adc_1ch/adc_1ch.sbx b/adc/cores/adc_1ch/adc_1ch.sbx new file mode 100644 index 0000000..7bbeac8 --- /dev/null +++ b/adc/cores/adc_1ch/adc_1ch.sbx @@ -0,0 +1,322 @@ + + + + Lattice Semiconductor Corporation + LEGACY + DDR_GENERIC + 6.0 + + + Diamond_Simulation + simulation + + ./adc_1ch.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./adc_1ch.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + + LFE5UM-85F-8BG756C + synplify + 2024-06-25.16:53:16 + 2024-06-25.16:53:16 + 3.12.1.454 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + DDR_GENERIC + + + CoreRevision + 6.0 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 06/25/2024 + + + ModuleName + adc_1ch + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 16:53:10 + + + VendorName + Lattice Semiconductor Corporation + + + + AFreq + + + + ClkIBuf + LVDS + + + DataLane + By Lane + + + DelVal + 11 + + + Delay + Dynamic User Defined + + + Destination + Synplicity + + + DynamicAlign + + + + EDIF + 1 + + + EnDynamic + 0 + + + EnDynamicAlign + + + + EnECLK + 0 + + + EnInEdge + + + + Expression + BusA(0 to 7) + + + Freq + + + + GenPll + 0 + + + IO + 0 + + + IOBUF + + + + Interface + GDDRX1_RX.SCLK.Aligned + + + MIPIFilter + 0 + + + NumEdge + BOTH + + + Order + Big Endian [MSB:LSB] + + + ReceiverSync + 0 + + + Reference + 0 + + + VHDL + 1 + + + Verilog + 0 + + + aligned + Edge-to-Edge + + + aligned2 + Edge-to-Edge + + + bandwidth + 800 + + + enClkIBuf + 0 + + + freq_in + 200 + + + freq_in2 + 200 + + + gear + 2:1 + + + io_type + LVDS + + + io_type2 + LVDS + + + mode + Receive + + + mode2 + Receive + + + pre-configuration + DISABLED + + + trioddr + 0 + + + trioddr2 + 0 + + + width + 2 + + + width2 + 2 + + + + cmd_line + -w -n adc_1ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 2 -freq_in 200 -gear 2 -aligned -del 11 -dynamic_delay -data_lane + + + + + + + LATTICE + LOCAL + adc_1ch + 1.0 + + + + diff --git a/adc/cores/adc_1ch/adc_1ch.vhd b/adc/cores/adc_1ch/adc_1ch.vhd new file mode 100644 index 0000000..94f2e74 --- /dev/null +++ b/adc/cores/adc_1ch/adc_1ch.vhd @@ -0,0 +1,1255 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n adc_1ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 2 -freq_in 200 -gear 2 -aligned -del 11 -dynamic_delay -data_lane -fdc /local/trb/git/trb5sc/adc/cores/adc_1ch/adc_1ch.fdc + +-- Tue Jun 25 16:53:16 2024 + + + +-- +-- Verific VHDL Description of OPERATOR equal_32 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity equal_32 is + port (a: in std_logic_vector(31 downto 0); + b: in std_logic_vector(31 downto 0); + o: out std_logic + ); + +end entity equal_32; + +architecture INTERFACE of equal_32 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15, + n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29, + n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43, + n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57, + n58,n59,n60,n61,n62,n63 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= a(1) xor b(1); + n3 <= a(2) xor b(2); + n4 <= a(3) xor b(3); + n5 <= a(4) xor b(4); + n6 <= a(5) xor b(5); + n7 <= a(6) xor b(6); + n8 <= a(7) xor b(7); + n9 <= a(8) xor b(8); + n10 <= a(9) xor b(9); + n11 <= a(10) xor b(10); + n12 <= a(11) xor b(11); + n13 <= a(12) xor b(12); + n14 <= a(13) xor b(13); + n15 <= a(14) xor b(14); + n16 <= a(15) xor b(15); + n17 <= a(16) xor b(16); + n18 <= a(17) xor b(17); + n19 <= a(18) xor b(18); + n20 <= a(19) xor b(19); + n21 <= a(20) xor b(20); + n22 <= a(21) xor b(21); + n23 <= a(22) xor b(22); + n24 <= a(23) xor b(23); + n25 <= a(24) xor b(24); + n26 <= a(25) xor b(25); + n27 <= a(26) xor b(26); + n28 <= a(27) xor b(27); + n29 <= a(28) xor b(28); + n30 <= a(29) xor b(29); + n31 <= a(30) xor b(30); + n32 <= a(31) xor b(31); + n33 <= n1 or n2; + n34 <= n3 or n4; + n35 <= n33 or n34; + n36 <= n5 or n6; + n37 <= n7 or n8; + n38 <= n36 or n37; + n39 <= n35 or n38; + n40 <= n9 or n10; + n41 <= n11 or n12; + n42 <= n40 or n41; + n43 <= n13 or n14; + n44 <= n15 or n16; + n45 <= n43 or n44; + n46 <= n42 or n45; + n47 <= n39 or n46; + n48 <= n17 or n18; + n49 <= n19 or n20; + n50 <= n48 or n49; + n51 <= n21 or n22; + n52 <= n23 or n24; + n53 <= n51 or n52; + n54 <= n50 or n53; + n55 <= n25 or n26; + n56 <= n27 or n28; + n57 <= n55 or n56; + n58 <= n29 or n30; + n59 <= n31 or n32; + n60 <= n58 or n59; + n61 <= n57 or n60; + n62 <= n54 or n61; + n63 <= n47 or n62; + o <= not n63; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR mux_5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity mux_5 is + port (d0: in std_logic_vector(4 downto 0); + d1: in std_logic_vector(4 downto 0); + cond: in std_logic; + o: out std_logic_vector(4 downto 0) + ); + +end entity mux_5; + +architecture INTERFACE of mux_5 is + +begin + o(0) <= d1(0) when cond='1' else d0(0); + o(1) <= d1(1) when cond='1' else d0(1); + o(2) <= d1(2) when cond='1' else d0(2); + o(3) <= d1(3) when cond='1' else d0(3); + o(4) <= d1(4) when cond='1' else d0(4); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR equal_5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity equal_5 is + port (a: in std_logic_vector(4 downto 0); + b: in std_logic_vector(4 downto 0); + o: out std_logic + ); + +end entity equal_5; + +architecture INTERFACE of equal_5 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= a(1) xor b(1); + n3 <= a(2) xor b(2); + n4 <= a(3) xor b(3); + n5 <= a(4) xor b(4); + n6 <= n1 or n2; + n7 <= n4 or n5; + n8 <= n3 or n7; + n9 <= n6 or n8; + o <= not n9; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR reduce_nor_6 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity reduce_nor_6 is + port (a: in std_logic_vector(5 downto 0); + o: out std_logic + ); + +end entity reduce_nor_6; + +architecture INTERFACE of reduce_nor_6 is + signal n1,n2,n3,n4,n5 : std_logic; +begin + n1 <= a(1) or a(2); + n2 <= a(0) or n1; + n3 <= a(4) or a(5); + n4 <= a(3) or n3; + n5 <= n2 or n4; + o <= not n5; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR Select_7 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity Select_7 is + port (sel: in std_logic_vector(6 downto 0); + data: in std_logic_vector(6 downto 0); + o: out std_logic + ); + +end entity Select_7; + +architecture INTERFACE of Select_7 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12 : std_logic; +begin + n1 <= data(0) and sel(0); + n2 <= data(1) and sel(1); + n3 <= data(2) and sel(2); + n4 <= data(3) and sel(3); + n5 <= data(4) and sel(4); + n6 <= data(5) and sel(5); + n7 <= data(6) and sel(6); + n8 <= n2 or n3; + n9 <= n1 or n8; + n10 <= n4 or n5; + n11 <= n6 or n7; + n12 <= n10 or n11; + o <= n9 or n12; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR wide_select_7_35 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity wide_select_7_35 is + port (sel: in std_logic_vector(6 downto 0); + data: in std_logic_vector(34 downto 0); + o: out std_logic_vector(4 downto 0) + ); + +end entity wide_select_7_35; + +architecture INTERFACE of wide_select_7_35 is + +begin + Select_0: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(30),data(5)=>data(25),data(4)=>data(20), + data(3)=>data(15),data(2)=>data(10),data(1)=>data(5),data(0)=>data(0), + o=>o(0)); + Select_1: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(31),data(5)=>data(26),data(4)=>data(21), + data(3)=>data(16),data(2)=>data(11),data(1)=>data(6),data(0)=>data(1), + o=>o(1)); + Select_2: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(32),data(5)=>data(27),data(4)=>data(22), + data(3)=>data(17),data(2)=>data(12),data(1)=>data(7),data(0)=>data(2), + o=>o(2)); + Select_3: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(33),data(5)=>data(28),data(4)=>data(23), + data(3)=>data(18),data(2)=>data(13),data(1)=>data(8),data(0)=>data(3), + o=>o(3)); + Select_4: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(34),data(5)=>data(29),data(4)=>data(24), + data(3)=>data(19),data(2)=>data(14),data(1)=>data(9),data(0)=>data(4), + o=>o(4)); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR LessThan_3u_3u +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity LessThan_3u_3u is + port (cin: in std_logic; + a: in std_logic_vector(2 downto 0); + b: in std_logic_vector(2 downto 0); + o: out std_logic + ); + +end entity LessThan_3u_3u; + +architecture INTERFACE of LessThan_3u_3u is + signal n1,n2,n3,n4,n5 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= b(0) when n1='1' else cin; + n3 <= a(1) xor b(1); + n4 <= b(1) when n3='1' else n2; + n5 <= a(2) xor b(2); + o <= b(2) when n5='1' else n4; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR add_32u_32u +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity add_32u_32u is + port (cin: in std_logic; + a: in std_logic_vector(31 downto 0); + b: in std_logic_vector(31 downto 0); + o: out std_logic_vector(31 downto 0); + cout: out std_logic + ); + +end entity add_32u_32u; + +architecture INTERFACE of add_32u_32u is + signal n2,n4,n6,n8,n10,n12,n14,n16,n18,n20,n22,n24,n26,n28, + n30,n32,n34,n36,n38,n40,n42,n44,n46,n48,n50,n52,n54,n56, + n58,n60,n62 : std_logic; +begin + n2 <= a(0) or b(0) when cin='1' else a(0) and b(0); + o(0) <= a(0) xor b(0) xor cin; + n4 <= a(1) or b(1) when n2='1' else a(1) and b(1); + o(1) <= a(1) xor b(1) xor n2; + n6 <= a(2) or b(2) when n4='1' else a(2) and b(2); + o(2) <= a(2) xor b(2) xor n4; + n8 <= a(3) or b(3) when n6='1' else a(3) and b(3); + o(3) <= a(3) xor b(3) xor n6; + n10 <= a(4) or b(4) when n8='1' else a(4) and b(4); + o(4) <= a(4) xor b(4) xor n8; + n12 <= a(5) or b(5) when n10='1' else a(5) and b(5); + o(5) <= a(5) xor b(5) xor n10; + n14 <= a(6) or b(6) when n12='1' else a(6) and b(6); + o(6) <= a(6) xor b(6) xor n12; + n16 <= a(7) or b(7) when n14='1' else a(7) and b(7); + o(7) <= a(7) xor b(7) xor n14; + n18 <= a(8) or b(8) when n16='1' else a(8) and b(8); + o(8) <= a(8) xor b(8) xor n16; + n20 <= a(9) or b(9) when n18='1' else a(9) and b(9); + o(9) <= a(9) xor b(9) xor n18; + n22 <= a(10) or b(10) when n20='1' else a(10) and b(10); + o(10) <= a(10) xor b(10) xor n20; + n24 <= a(11) or b(11) when n22='1' else a(11) and b(11); + o(11) <= a(11) xor b(11) xor n22; + n26 <= a(12) or b(12) when n24='1' else a(12) and b(12); + o(12) <= a(12) xor b(12) xor n24; + n28 <= a(13) or b(13) when n26='1' else a(13) and b(13); + o(13) <= a(13) xor b(13) xor n26; + n30 <= a(14) or b(14) when n28='1' else a(14) and b(14); + o(14) <= a(14) xor b(14) xor n28; + n32 <= a(15) or b(15) when n30='1' else a(15) and b(15); + o(15) <= a(15) xor b(15) xor n30; + n34 <= a(16) or b(16) when n32='1' else a(16) and b(16); + o(16) <= a(16) xor b(16) xor n32; + n36 <= a(17) or b(17) when n34='1' else a(17) and b(17); + o(17) <= a(17) xor b(17) xor n34; + n38 <= a(18) or b(18) when n36='1' else a(18) and b(18); + o(18) <= a(18) xor b(18) xor n36; + n40 <= a(19) or b(19) when n38='1' else a(19) and b(19); + o(19) <= a(19) xor b(19) xor n38; + n42 <= a(20) or b(20) when n40='1' else a(20) and b(20); + o(20) <= a(20) xor b(20) xor n40; + n44 <= a(21) or b(21) when n42='1' else a(21) and b(21); + o(21) <= a(21) xor b(21) xor n42; + n46 <= a(22) or b(22) when n44='1' else a(22) and b(22); + o(22) <= a(22) xor b(22) xor n44; + n48 <= a(23) or b(23) when n46='1' else a(23) and b(23); + o(23) <= a(23) xor b(23) xor n46; + n50 <= a(24) or b(24) when n48='1' else a(24) and b(24); + o(24) <= a(24) xor b(24) xor n48; + n52 <= a(25) or b(25) when n50='1' else a(25) and b(25); + o(25) <= a(25) xor b(25) xor n50; + n54 <= a(26) or b(26) when n52='1' else a(26) and b(26); + o(26) <= a(26) xor b(26) xor n52; + n56 <= a(27) or b(27) when n54='1' else a(27) and b(27); + o(27) <= a(27) xor b(27) xor n54; + n58 <= a(28) or b(28) when n56='1' else a(28) and b(28); + o(28) <= a(28) xor b(28) xor n56; + n60 <= a(29) or b(29) when n58='1' else a(29) and b(29); + o(29) <= a(29) xor b(29) xor n58; + n62 <= a(30) or b(30) when n60='1' else a(30) and b(30); + o(30) <= a(30) xor b(30) xor n60; + cout <= a(31) or b(31) when n62='1' else a(31) and b(31); + o(31) <= a(31) xor b(31) xor n62; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR mux_3 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity mux_3 is + port (d0: in std_logic_vector(2 downto 0); + d1: in std_logic_vector(2 downto 0); + cond: in std_logic; + o: out std_logic_vector(2 downto 0) + ); + +end entity mux_3; + +architecture INTERFACE of mux_3 is + +begin + o(0) <= d1(0) when cond='1' else d0(0); + o(1) <= d1(1) when cond='1' else d0(1); + o(2) <= d1(2) when cond='1' else d0(2); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR not_equal_32 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity not_equal_32 is + port (a: in std_logic_vector(31 downto 0); + b: in std_logic_vector(31 downto 0); + o: out std_logic + ); + +end entity not_equal_32; + +architecture INTERFACE of not_equal_32 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15, + n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29, + n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43, + n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57, + n58,n59,n60,n61,n62,n63,n64 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= a(1) xor b(1); + n3 <= a(2) xor b(2); + n4 <= a(3) xor b(3); + n5 <= a(4) xor b(4); + n6 <= a(5) xor b(5); + n7 <= a(6) xor b(6); + n8 <= a(7) xor b(7); + n9 <= a(8) xor b(8); + n10 <= a(9) xor b(9); + n11 <= a(10) xor b(10); + n12 <= a(11) xor b(11); + n13 <= a(12) xor b(12); + n14 <= a(13) xor b(13); + n15 <= a(14) xor b(14); + n16 <= a(15) xor b(15); + n17 <= a(16) xor b(16); + n18 <= a(17) xor b(17); + n19 <= a(18) xor b(18); + n20 <= a(19) xor b(19); + n21 <= a(20) xor b(20); + n22 <= a(21) xor b(21); + n23 <= a(22) xor b(22); + n24 <= a(23) xor b(23); + n25 <= a(24) xor b(24); + n26 <= a(25) xor b(25); + n27 <= a(26) xor b(26); + n28 <= a(27) xor b(27); + n29 <= a(28) xor b(28); + n30 <= a(29) xor b(29); + n31 <= a(30) xor b(30); + n32 <= a(31) xor b(31); + n33 <= n1 or n2; + n34 <= n3 or n4; + n35 <= n33 or n34; + n36 <= n5 or n6; + n37 <= n7 or n8; + n38 <= n36 or n37; + n39 <= n35 or n38; + n40 <= n9 or n10; + n41 <= n11 or n12; + n42 <= n40 or n41; + n43 <= n13 or n14; + n44 <= n15 or n16; + n45 <= n43 or n44; + n46 <= n42 or n45; + n47 <= n39 or n46; + n48 <= n17 or n18; + n49 <= n19 or n20; + n50 <= n48 or n49; + n51 <= n21 or n22; + n52 <= n23 or n24; + n53 <= n51 or n52; + n54 <= n50 or n53; + n55 <= n25 or n26; + n56 <= n27 or n28; + n57 <= n55 or n56; + n58 <= n29 or n30; + n59 <= n31 or n32; + n60 <= n58 or n59; + n61 <= n57 or n60; + n62 <= n54 or n61; + n63 <= n47 or n62; + n64 <= not n63; + o <= not n64; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR not_equal_5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity not_equal_5 is + port (a: in std_logic_vector(4 downto 0); + b: in std_logic_vector(4 downto 0); + o: out std_logic + ); + +end entity not_equal_5; + +architecture INTERFACE of not_equal_5 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= a(1) xor b(1); + n3 <= a(2) xor b(2); + n4 <= a(3) xor b(3); + n5 <= a(4) xor b(4); + n6 <= n1 or n2; + n7 <= n4 or n5; + n8 <= n3 or n7; + n9 <= n6 or n8; + n10 <= not n9; + o <= not n10; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR wide_dffrs_3 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity wide_dffrs_3 is + port (d: in std_logic_vector(2 downto 0); + set: in std_logic_vector(2 downto 0); + reset: in std_logic_vector(2 downto 0); + clock: in std_logic; + q: out std_logic_vector(2 downto 0) + ); + +end entity wide_dffrs_3; + +architecture INTERFACE of wide_dffrs_3 is + procedure VERIFIC_DFFRS (d: in std_logic; + signal clk: in std_logic; + s: in std_logic; + r: in std_logic; + signal q: inout std_logic + ) is begin + if (s='1') then + q <= '1' ; + elsif (r='1') then + q <= '0' ; + elsif (clk'event and clk='1') then + q <= d ; + end if ; + end procedure VERIFIC_DFFRS; + signal \q[0]_c\,\q[1]_c\,\q[2]_c\ : std_logic; +begin + q(2) <= \q[2]_c\; + q(1) <= \q[1]_c\; + q(0) <= \q[0]_c\; + i1: VERIFIC_DFFRS (d=>d(0),clk=>clock,s=>set(0),r=>reset(0),q=>\q[0]_c\); + i2: VERIFIC_DFFRS (d=>d(1),clk=>clock,s=>set(1),r=>reset(1),q=>\q[1]_c\); + i3: VERIFIC_DFFRS (d=>d(2),clk=>clock,s=>set(2),r=>reset(2),q=>\q[2]_c\); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR wide_dffrs_5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity wide_dffrs_5 is + port (d: in std_logic_vector(4 downto 0); + set: in std_logic_vector(4 downto 0); + reset: in std_logic_vector(4 downto 0); + clock: in std_logic; + q: out std_logic_vector(4 downto 0) + ); + +end entity wide_dffrs_5; + +architecture INTERFACE of wide_dffrs_5 is + procedure VERIFIC_DFFRS (d: in std_logic; + signal clk: in std_logic; + s: in std_logic; + r: in std_logic; + signal q: inout std_logic + ) is begin + if (s='1') then + q <= '1' ; + elsif (r='1') then + q <= '0' ; + elsif (clk'event and clk='1') then + q <= d ; + end if ; + end procedure VERIFIC_DFFRS; + signal \q[0]_c\,\q[1]_c\,\q[2]_c\,\q[3]_c\,\q[4]_c\ : std_logic; +begin + q(4) <= \q[4]_c\; + q(3) <= \q[3]_c\; + q(2) <= \q[2]_c\; + q(1) <= \q[1]_c\; + q(0) <= \q[0]_c\; + i1: VERIFIC_DFFRS (d=>d(0),clk=>clock,s=>set(0),r=>reset(0),q=>\q[0]_c\); + i2: VERIFIC_DFFRS (d=>d(1),clk=>clock,s=>set(1),r=>reset(1),q=>\q[1]_c\); + i3: VERIFIC_DFFRS (d=>d(2),clk=>clock,s=>set(2),r=>reset(2),q=>\q[2]_c\); + i4: VERIFIC_DFFRS (d=>d(3),clk=>clock,s=>set(3),r=>reset(3),q=>\q[3]_c\); + i5: VERIFIC_DFFRS (d=>d(4),clk=>clock,s=>set(4),r=>reset(4),q=>\q[4]_c\); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of module adc_1chrxdll_sync +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +library ecp5um ; +use ecp5um.components.all ; + +entity adc_1chrxdll_sync is + port (rst: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(47) + sync_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(48) + update: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(49) + dll_lock: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(50) + dll_reset: out std_logic; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(58) + uddcntln: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(53) + freeze: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(54) + stop: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(55) + ddr_reset: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(56) + ready: out std_logic -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(57) + ); + +end entity adc_1chrxdll_sync; -- syn_module_defined=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(25) + +architecture adc_1chrxdll_sync of adc_1chrxdll_sync is + procedure VERIFIC_DFFRS (d: in std_logic; + signal clk: in std_logic; + s: in std_logic; + r: in std_logic; + signal q: inout std_logic + ) is begin + if (s='1') then + q <= '1' ; + elsif (r='1') then + q <= '0' ; + elsif (clk'event and clk='1') then + q <= d ; + end if ; + end procedure VERIFIC_DFFRS; + signal uddcntln_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(53) + signal freeze_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(54) + signal stop_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(55) + signal ready_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(57) + signal dll_reset_c : std_logic; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(58) + signal ddr_reset_d : std_logic; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(75) + signal ctrl_cnt : std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(77) + signal dll_lock_cnt : std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(78) + signal ready_cnt : std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(79) + signal cs_rx_sync : std_logic_vector(4 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(81) + signal ns_rx_sync : std_logic_vector(4 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(82) + signal dll_lock_q1 : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(84) + signal dll_lock_q2 : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(85) + signal not_uddcntln : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(87) + signal assert_stop : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(88) + signal not_reset : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(89) + signal not_stop : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(90) + signal not_freeze : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(91) + signal get_ready : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(92) + signal n303,pwr,n3,n4,n5,n6,n8 : std_logic; + signal n9 : std_logic_vector(4 downto 0); + signal n15 : std_logic_vector(4 downto 0); + signal n21 : std_logic; + signal n24 : std_logic_vector(4 downto 0); + signal n30 : std_logic_vector(4 downto 0); + signal n36 : std_logic_vector(4 downto 0); + signal n42,n44 : std_logic; + signal n45 : std_logic_vector(4 downto 0); + signal n51 : std_logic; + signal n53 : std_logic_vector(4 downto 0); + signal n59 : std_logic_vector(4 downto 0); + signal n65,n67 : std_logic; + signal n68 : std_logic_vector(4 downto 0); + signal n74,n75 : std_logic; + signal n76 : std_logic_vector(4 downto 0); + signal n82,n83,n84,n85,n86,n87,n88,n97,n98,n99 : std_logic; + signal n101 : std_logic_vector(31 downto 0); + signal n134 : std_logic_vector(2 downto 0); + signal n138,n139,n140,n141,n142 : std_logic; + signal n144 : std_logic_vector(31 downto 0); + signal n177 : std_logic_vector(2 downto 0); + signal n181 : std_logic_vector(2 downto 0); + signal n185 : std_logic_vector(2 downto 0); + signal n189,n190 : std_logic; + signal n192 : std_logic_vector(31 downto 0); + signal n225 : std_logic_vector(2 downto 0); + signal n229,n230,n231,n232,n233,n234,n235,n236,n237,n238,n239, + n240,n241,n242,n243,n244,n245,n246,n247,n248,n249,n250,n251, + n252,n253,n254,n255,n256,n257,n258,n259,n260,n261,n262 : std_logic; + signal n263 : std_logic_vector(2 downto 0); + signal n267 : std_logic_vector(2 downto 0); + signal n271 : std_logic_vector(2 downto 0); + signal gnd : std_logic; signal OPEN_net : std_logic_vector(0 to 87); + +begin + dll_reset <= dll_reset_c; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(58) + uddcntln <= uddcntln_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(53) + freeze <= freeze_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(54) + stop <= stop_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(55) + ready <= ready_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(57) + n303 <= '0' ; + pwr <= '1' ; + ddr_reset <= cs_rx_sync(2) or ddr_reset_d; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(114) + equal_4: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1),a(0)=>dll_lock_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>pwr,b(1)=>n303,b(0)=>pwr, + o=>n3); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(124) + n4 <= not not_uddcntln; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(124) + n5 <= n3 and n4; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(124) + equal_7: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ready_cnt(2),a(1)=>ready_cnt(1),a(0)=>ready_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>pwr,b(1)=>pwr,b(0)=>pwr, + o=>n6); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(128) + n8 <= n6 and get_ready; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(128) + mux_10: entity work.mux_5(INTERFACE) port map (d0(4)=>n303,d0(3)=>n303, + d0(2)=>n303,d0(1)=>pwr,d0(0)=>n303,d1(4)=>n303,d1(3)=>n303, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>pwr,cond=>n8,o(4)=>n9(4),o(3)=>n9(3), + o(2)=>n9(2),o(1)=>n9(1),o(0)=>n9(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(135) + mux_11: entity work.mux_5(INTERFACE) port map (d0(4)=>n9(4),d0(3)=>n9(3), + d0(2)=>n9(2),d0(1)=>n9(1),d0(0)=>n9(0),d1(4)=>pwr,d1(3)=>n303, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>n5,o(4)=>n15(4),o(3)=>n15(3), + o(2)=>n15(2),o(1)=>n15(1),o(0)=>n15(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(135) + equal_12: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n21); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(140) + mux_15: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>n303, + d0(2)=>n303,d0(1)=>n303,d0(0)=>n303,d1(4)=>n303,d1(3)=>n303, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>not_freeze,o(4)=>n24(4), + o(3)=>n24(3),o(2)=>n24(2),o(1)=>n24(1),o(0)=>n24(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(153) + mux_16: entity work.mux_5(INTERFACE) port map (d0(4)=>n24(4),d0(3)=>n24(3), + d0(2)=>n24(2),d0(1)=>n24(1),d0(0)=>n24(0),d1(4)=>pwr,d1(3)=>pwr, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>assert_stop,o(4)=>n30(4), + o(3)=>n30(3),o(2)=>n30(2),o(1)=>n30(1),o(0)=>n30(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(153) + mux_17: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>n303, + d0(2)=>n303,d0(1)=>pwr,d0(0)=>n303,d1(4)=>n30(4),d1(3)=>n30(3), + d1(2)=>n30(2),d1(1)=>n30(1),d1(0)=>n30(0),cond=>n21,o(4)=>n36(4), + o(3)=>n36(3),o(2)=>n36(2),o(1)=>n36(1),o(0)=>n36(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(158) + equal_18: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n42); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(163) + n44 <= n42 and not_uddcntln; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(163) + mux_21: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>n303, + d0(2)=>n303,d0(1)=>n303,d0(0)=>n303,d1(4)=>pwr,d1(3)=>n303, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>n44,o(4)=>n45(4),o(3)=>n45(3), + o(2)=>n45(2),o(1)=>n45(1),o(0)=>n45(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(170) + equal_22: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n51); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(175) + mux_24: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>pwr, + d0(2)=>pwr,d0(1)=>pwr,d0(0)=>n303,d1(4)=>pwr,d1(3)=>n303,d1(2)=>n303, + d1(1)=>pwr,d1(0)=>n303,cond=>not_stop,o(4)=>n53(4),o(3)=>n53(3), + o(2)=>n53(2),o(1)=>n53(1),o(0)=>n53(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(184) + mux_25: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>pwr, + d0(2)=>n303,d0(1)=>pwr,d0(0)=>n303,d1(4)=>n53(4),d1(3)=>n53(3), + d1(2)=>n53(2),d1(1)=>n53(1),d1(0)=>n53(0),cond=>n51,o(4)=>n59(4), + o(3)=>n59(3),o(2)=>n59(2),o(1)=>n59(1),o(0)=>n59(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(189) + equal_26: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n65); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(194) + n67 <= n65 and not_reset; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(194) + mux_29: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>pwr, + d0(2)=>pwr,d0(1)=>pwr,d0(0)=>n303,d1(4)=>pwr,d1(3)=>pwr,d1(2)=>n303, + d1(1)=>pwr,d1(0)=>n303,cond=>n67,o(4)=>n68(4),o(3)=>n68(3), + o(2)=>n68(2),o(1)=>n68(1),o(0)=>n68(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(201) + n74 <= not dll_lock_q2; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(206) + n75 <= n74 or update; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(206) + mux_32: entity work.mux_5(INTERFACE) port map (d0(4)=>n303,d0(3)=>n303, + d0(2)=>n303,d0(1)=>pwr,d0(0)=>pwr,d1(4)=>n303,d1(3)=>n303,d1(2)=>n303, + d1(1)=>pwr,d1(0)=>n303,cond=>n75,o(4)=>n76(4),o(3)=>n76(3), + o(2)=>n76(2),o(1)=>n76(1),o(0)=>n76(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(213) + equal_33: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>n303, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n82); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(122) + equal_34: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n83); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(138) + equal_35: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>n303,o=>n84); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(161) + equal_36: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n85); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(173) + equal_37: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>pwr,b(1)=>pwr,b(0)=>n303,o=>n86); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(192) + equal_38: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>n303, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,o=>n87); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(204) + reduce_nor_39: entity work.reduce_nor_6(INTERFACE) port map (a(5)=>n82, + a(4)=>n83,a(3)=>n84,a(2)=>n85,a(1)=>n86,a(0)=>n87,o=>n88); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(221) + select_40: entity work.wide_select_7_35(INTERFACE) port map (sel(6)=>n82, + sel(5)=>n83,sel(4)=>n84,sel(3)=>n85,sel(2)=>n86,sel(1)=>n87, + sel(0)=>n88,data(34)=>n15(4),data(33)=>n15(3),data(32)=>n15(2), + data(31)=>n15(1),data(30)=>n15(0),data(29)=>n36(4),data(28)=>n36(3), + data(27)=>n36(2),data(26)=>n36(1),data(25)=>n36(0),data(24)=>n45(4), + data(23)=>n45(3),data(22)=>n45(2),data(21)=>n45(1),data(20)=>n45(0), + data(19)=>n59(4),data(18)=>n59(3),data(17)=>n59(2),data(16)=>n59(1), + data(15)=>n59(0),data(14)=>n68(4),data(13)=>n68(3),data(12)=>n68(2), + data(11)=>n68(1),data(10)=>n68(0),data(9)=>n76(4),data(8)=>n76(3), + data(7)=>n76(2),data(6)=>n76(1),data(5)=>n76(0),data(4)=>freeze_c, + data(3)=>stop_c,data(2)=>cs_rx_sync(2),data(1)=>uddcntln_c,data(0)=>ready_c, + o(4)=>ns_rx_sync(4),o(3)=>ns_rx_sync(3),o(2)=>ns_rx_sync(2),o(1)=>ns_rx_sync(1), + o(0)=>ns_rx_sync(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(221) + dll_lock_q2_112: VERIFIC_DFFRS (d=>dll_lock_q1,clk=>sync_clk,s=>n303, + r=>rst,q=>dll_lock_q2); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(238) + gnd <= '0' ; + n97 <= dll_lock_q2 and dll_lock; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(264) + LessThan_44: entity work.LessThan_3u_3u(INTERFACE) port map (cin=>n303, + a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1),a(0)=>dll_lock_cnt(0), + b(2)=>pwr,b(1)=>n303,b(0)=>pwr,o=>n98); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(264) + n99 <= n97 and n98; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(264) + add_46: entity work.add_32u_32u(INTERFACE) port map (cin=>n303,a(31)=>n303, + a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303, + a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303, + a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303, + a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303, + a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303, + a(4)=>n303,a(3)=>n303,a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1), + a(0)=>dll_lock_cnt(0),b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303, + b(27)=>n303,b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303, + b(22)=>n303,b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303, + b(17)=>n303,b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303, + b(12)=>n303,b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303, + b(6)=>n303,b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>n303, + b(0)=>pwr,o(31)=>OPEN_net(87),o(30)=>OPEN_net(86),o(29)=>OPEN_net(85), + o(28)=>OPEN_net(84),o(27)=>OPEN_net(83),o(26)=>OPEN_net(82),o(25)=>OPEN_net(81), + o(24)=>OPEN_net(80),o(23)=>OPEN_net(79),o(22)=>OPEN_net(78),o(21)=>OPEN_net(77), + o(20)=>OPEN_net(76),o(19)=>OPEN_net(75),o(18)=>OPEN_net(74),o(17)=>OPEN_net(73), + o(16)=>OPEN_net(72),o(15)=>OPEN_net(71),o(14)=>OPEN_net(70),o(13)=>OPEN_net(69), + o(12)=>OPEN_net(68),o(11)=>OPEN_net(67),o(10)=>OPEN_net(66),o(9)=>OPEN_net(65), + o(8)=>OPEN_net(64),o(7)=>OPEN_net(63),o(6)=>OPEN_net(62),o(5)=>OPEN_net(61), + o(4)=>OPEN_net(60),o(3)=>OPEN_net(59),o(2)=>n101(2),o(1)=>n101(1), + o(0)=>n101(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(266) + mux_47: entity work.mux_3(INTERFACE) port map (d0(2)=>dll_lock_cnt(2), + d0(1)=>dll_lock_cnt(1),d0(0)=>dll_lock_cnt(0),d1(2)=>n101(2), + d1(1)=>n101(1),d1(0)=>n101(0),cond=>n99,o(2)=>n134(2),o(1)=>n134(1), + o(0)=>n134(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(267) + not_equal_48: entity work.not_equal_32(INTERFACE) port map (a(31)=>n303, + a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303, + a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303, + a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303, + a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303, + a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303, + a(4)=>n303,a(3)=>n303,a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1), + a(0)=>dll_lock_cnt(0),b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303, + b(27)=>n303,b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303, + b(22)=>n303,b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303, + b(17)=>n303,b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303, + b(12)=>n303,b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303, + b(6)=>n303,b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>pwr,b(1)=>n303, + b(0)=>pwr,o=>n138); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(271) + equal_49: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n139); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(275) + not_equal_50: entity work.not_equal_5(INTERFACE) port map (a(4)=>freeze_c, + a(3)=>stop_c,a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c, + b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,o=>n140); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(275) + n141 <= n139 and n140; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(275) + LessThan_52: entity work.LessThan_3u_3u(INTERFACE) port map (cin=>n303, + a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0),b(2)=>pwr, + b(1)=>n303,b(0)=>n303,o=>n142); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(280) + add_53: entity work.add_32u_32u(INTERFACE) port map (cin=>n303,a(31)=>n303, + a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303, + a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303, + a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303, + a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303, + a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303, + a(4)=>n303,a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>pwr, + o(31)=>OPEN_net(58),o(30)=>OPEN_net(57),o(29)=>OPEN_net(56),o(28)=>OPEN_net(55), + o(27)=>OPEN_net(54),o(26)=>OPEN_net(53),o(25)=>OPEN_net(52),o(24)=>OPEN_net(51), + o(23)=>OPEN_net(50),o(22)=>OPEN_net(49),o(21)=>OPEN_net(48),o(20)=>OPEN_net(47), + o(19)=>OPEN_net(46),o(18)=>OPEN_net(45),o(17)=>OPEN_net(44),o(16)=>OPEN_net(43), + o(15)=>OPEN_net(42),o(14)=>OPEN_net(41),o(13)=>OPEN_net(40),o(12)=>OPEN_net(39), + o(11)=>OPEN_net(38),o(10)=>OPEN_net(37),o(9)=>OPEN_net(36),o(8)=>OPEN_net(35), + o(7)=>OPEN_net(34),o(6)=>OPEN_net(33),o(5)=>OPEN_net(32),o(4)=>OPEN_net(31), + o(3)=>OPEN_net(30),o(2)=>n144(2),o(1)=>n144(1),o(0)=>n144(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(282) + mux_54: entity work.mux_3(INTERFACE) port map (d0(2)=>ctrl_cnt(2),d0(1)=>ctrl_cnt(1), + d0(0)=>ctrl_cnt(0),d1(2)=>n144(2),d1(1)=>n144(1),d1(0)=>n144(0), + cond=>n142,o(2)=>n177(2),o(1)=>n177(1),o(0)=>n177(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(283) + mux_55: entity work.mux_3(INTERFACE) port map (d0(2)=>n177(2),d0(1)=>n177(1), + d0(0)=>n177(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n141, + o(2)=>n181(2),o(1)=>n181(1),o(0)=>n181(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(283) + mux_56: entity work.mux_3(INTERFACE) port map (d0(2)=>n181(2),d0(1)=>n181(1), + d0(0)=>n181(0),d1(2)=>n303,d1(1)=>pwr,d1(0)=>pwr,cond=>n138, + o(2)=>n185(2),o(1)=>n185(1),o(0)=>n185(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(283) + LessThan_57: entity work.LessThan_3u_3u(INTERFACE) port map (cin=>n303, + a(2)=>ready_cnt(2),a(1)=>ready_cnt(1),a(0)=>ready_cnt(0),b(2)=>pwr, + b(1)=>pwr,b(0)=>pwr,o=>n189); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(287) + n190 <= get_ready and n189; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(287) + add_59: entity work.add_32u_32u(INTERFACE) port map (cin=>n303,a(31)=>n303, + a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303, + a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303, + a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303, + a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303, + a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303, + a(4)=>n303,a(3)=>n303,a(2)=>ready_cnt(2),a(1)=>ready_cnt(1), + a(0)=>ready_cnt(0),b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303, + b(27)=>n303,b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303, + b(22)=>n303,b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303, + b(17)=>n303,b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303, + b(12)=>n303,b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303, + b(6)=>n303,b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>n303, + b(0)=>pwr,o(31)=>OPEN_net(29),o(30)=>OPEN_net(28),o(29)=>OPEN_net(27), + o(28)=>OPEN_net(26),o(27)=>OPEN_net(25),o(26)=>OPEN_net(24),o(25)=>OPEN_net(23), + o(24)=>OPEN_net(22),o(23)=>OPEN_net(21),o(22)=>OPEN_net(20),o(21)=>OPEN_net(19), + o(20)=>OPEN_net(18),o(19)=>OPEN_net(17),o(18)=>OPEN_net(16),o(17)=>OPEN_net(15), + o(16)=>OPEN_net(14),o(15)=>OPEN_net(13),o(14)=>OPEN_net(12),o(13)=>OPEN_net(11), + o(12)=>OPEN_net(10),o(11)=>OPEN_net(9),o(10)=>OPEN_net(8),o(9)=>OPEN_net(7), + o(8)=>OPEN_net(6),o(7)=>OPEN_net(5),o(6)=>OPEN_net(4),o(5)=>OPEN_net(3), + o(4)=>OPEN_net(2),o(3)=>OPEN_net(1),o(2)=>n192(2),o(1)=>n192(1), + o(0)=>n192(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(290) + mux_60: entity work.mux_3(INTERFACE) port map (d0(2)=>ready_cnt(2),d0(1)=>ready_cnt(1), + d0(0)=>ready_cnt(0),d1(2)=>n192(2),d1(1)=>n192(1),d1(0)=>n192(0), + cond=>n190,o(2)=>n225(2),o(1)=>n225(1),o(0)=>n225(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(291) + equal_61: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n229); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(294) + equal_62: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>n303,o=>n230); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(294) + n231 <= n229 and n230; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(294) + n232 <= pwr when n231='1' else not_uddcntln; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(297) + equal_65: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>n303,o=>n233); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(300) + equal_66: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n234); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(300) + n235 <= n233 and n234; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(300) + n236 <= pwr when n235='1' else assert_stop; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(303) + equal_69: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n237); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(306) + equal_70: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>pwr,b(2)=>pwr,b(1)=>pwr,b(0)=>n303,o=>n238); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(306) + n239 <= n237 and n238; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(306) + n240 <= pwr when n239='1' else not_reset; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(309) + equal_73: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>pwr,b(1)=>pwr,b(0)=>n303,o=>n241); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(312) + equal_74: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n242); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(312) + n243 <= n241 and n242; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(312) + n244 <= pwr when n243='1' else not_stop; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(315) + equal_77: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n245); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(318) + equal_78: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n246); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(318) + n247 <= n245 and n246; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(318) + n248 <= pwr when n247='1' else not_freeze; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(322) + n249 <= n303 when n247='1' else n236; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(322) + equal_82: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n250); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(325) + equal_83: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n251); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(325) + n252 <= n250 and n251; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(325) + n253 <= pwr when n252='1' else get_ready; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(328) + equal_86: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>n303, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,o=>n254); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(332) + equal_87: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n255); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(332) + n256 <= n254 and n255; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(332) + n257 <= n303 when n256='1' else n248; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n258 <= n303 when n256='1' else n249; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n259 <= n303 when n256='1' else n244; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n260 <= n303 when n256='1' else n240; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n261 <= n303 when n256='1' else n232; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n262 <= n303 when n256='1' else n253; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + mux_95: entity work.mux_3(INTERFACE) port map (d0(2)=>n225(2),d0(1)=>n225(1), + d0(0)=>n225(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n256, + o(2)=>n263(2),o(1)=>n263(1),o(0)=>n263(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + mux_96: entity work.mux_3(INTERFACE) port map (d0(2)=>n134(2),d0(1)=>n134(1), + d0(0)=>n134(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n256, + o(2)=>n267(2),o(1)=>n267(1),o(0)=>n267(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + mux_97: entity work.mux_3(INTERFACE) port map (d0(2)=>n185(2),d0(1)=>n185(1), + d0(0)=>n185(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n256, + o(2)=>n271(2),o(1)=>n271(1),o(0)=>n271(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + ctrl_cnt_c: entity work.wide_dffrs_3(INTERFACE) port map (d(2)=>n271(2), + d(1)=>n271(1),d(0)=>n271(0),set(2)=>n303,set(1)=>n303,set(0)=>n303, + reset(2)=>rst,reset(1)=>rst,reset(0)=>rst,clock=>sync_clk,q(2)=>ctrl_cnt(2), + q(1)=>ctrl_cnt(1),q(0)=>ctrl_cnt(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + dll_lock_cnt_c: entity work.wide_dffrs_3(INTERFACE) port map (d(2)=>n267(2), + d(1)=>n267(1),d(0)=>n267(0),set(2)=>n303,set(1)=>n303,set(0)=>n303, + reset(2)=>rst,reset(1)=>rst,reset(0)=>rst,clock=>sync_clk,q(2)=>dll_lock_cnt(2), + q(1)=>dll_lock_cnt(1),q(0)=>dll_lock_cnt(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + ready_cnt_c: entity work.wide_dffrs_3(INTERFACE) port map (d(2)=>n263(2), + d(1)=>n263(1),d(0)=>n263(0),set(2)=>n303,set(1)=>n303,set(0)=>n303, + reset(2)=>rst,reset(1)=>rst,reset(0)=>rst,clock=>sync_clk,q(2)=>ready_cnt(2), + q(1)=>ready_cnt(1),q(0)=>ready_cnt(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + ddr_reset_d_118: VERIFIC_DFFRS (d=>n303,clk=>sync_clk,s=>rst,r=>gnd, + q=>ddr_reset_d); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + dll_reset_119: VERIFIC_DFFRS (d=>n256,clk=>sync_clk,s=>rst,r=>gnd,q=>dll_reset_c); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + not_uddcntln_120: VERIFIC_DFFRS (d=>n261,clk=>sync_clk,s=>n303,r=>rst, + q=>not_uddcntln); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + assert_stop_121: VERIFIC_DFFRS (d=>n258,clk=>sync_clk,s=>n303,r=>rst, + q=>assert_stop); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + not_reset_122: VERIFIC_DFFRS (d=>n260,clk=>sync_clk,s=>n303,r=>rst,q=>not_reset); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + not_stop_123: VERIFIC_DFFRS (d=>n259,clk=>sync_clk,s=>n303,r=>rst,q=>not_stop); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + not_freeze_124: VERIFIC_DFFRS (d=>n257,clk=>sync_clk,s=>n303,r=>rst, + q=>not_freeze); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + get_ready_125: VERIFIC_DFFRS (d=>n262,clk=>sync_clk,s=>n303,r=>rst,q=>get_ready); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + dll_lock_q1_111: VERIFIC_DFFRS (d=>dll_lock,clk=>sync_clk,s=>n303,r=>rst, + q=>dll_lock_q1); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(238) + cs_rx_sync_c: entity work.wide_dffrs_5(INTERFACE) port map (d(4)=>ns_rx_sync(4), + d(3)=>ns_rx_sync(3),d(2)=>ns_rx_sync(2),d(1)=>ns_rx_sync(1),d(0)=>ns_rx_sync(0), + set(4)=>n303,set(3)=>n303,set(2)=>n303,set(1)=>rst,set(0)=>n303, + reset(4)=>rst,reset(3)=>rst,reset(2)=>rst,reset(1)=>gnd,reset(0)=>rst, + clock=>sync_clk,q(4)=>freeze_c,q(3)=>stop_c,q(2)=>cs_rx_sync(2), + q(1)=>uddcntln_c,q(0)=>ready_c); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + +end architecture adc_1chrxdll_sync; -- syn_module_defined=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(25) + + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity adc_1ch is + port ( + clkin: in std_logic; + dcntl: out std_logic_vector(7 downto 0); + ready: out std_logic; + sclk: out std_logic; + sync_clk: in std_logic; + sync_reset: in std_logic; + update: in std_logic; + data_cflag: out std_logic_vector(1 downto 0); + data_direction: in std_logic_vector(1 downto 0); + data_loadn: in std_logic_vector(1 downto 0); + data_move: in std_logic_vector(1 downto 0); + datain: in std_logic_vector(1 downto 0); + q: out std_logic_vector(3 downto 0)); +end adc_1ch; + +architecture Structure of adc_1ch is + + -- internal signal declarations + signal stop: std_logic; + signal scuba_vlo: std_logic; + signal dll_lock: std_logic; + signal freeze: std_logic; + signal uddcntln: std_logic; + signal dll_reset: std_logic; + signal clock_cflag: std_logic; + signal clock_direction: std_logic; + signal clock_move: std_logic; + signal clock_loadn: std_logic; + signal ddrdel: std_logic; + signal buf_clkin: std_logic; + signal qb1: std_logic; + signal qa1: std_logic; + signal qb0: std_logic; + signal qa0: std_logic; + signal reset: std_logic; + signal sclk_t: std_logic; + signal dataini_t1: std_logic; + signal dataini_t0: std_logic; + signal buf_dataini1: std_logic; + signal buf_dataini0: std_logic; + + component adc_1chrxdll_sync + port (rst: in std_logic; sync_clk: in std_logic; + update: in std_logic; dll_lock: in std_logic; + dll_reset: out std_logic; uddcntln: out std_logic; + freeze: out std_logic; stop: out std_logic; + ddr_reset: out std_logic; ready: out std_logic); + end component; + attribute IO_TYPE : string; + attribute IO_TYPE of Inst5_IB : label is "LVDS"; + attribute IO_TYPE of Inst1_IB1 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB0 : label is "LVDS"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + Inst5_IB: IB + port map (I=>clkin, O=>buf_clkin); + + Inst_rxdll_sync: adc_1chrxdll_sync + port map (rst => sync_reset, sync_clk => sync_clk, update => update, + dll_lock => dll_lock, dll_reset => dll_reset, uddcntln => uddcntln, + freeze => freeze, stop => stop, ddr_reset => reset, + ready => ready); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + Inst4_DDRDLLA: DDRDLLA + generic map (FORCE_MAX_DELAY=> "NO") + port map (CLK=>sclk_t, RST=>dll_reset, UDDCNTLN=>uddcntln, + FREEZE=>freeze, DDRDEL=>ddrdel, LOCK=>dll_lock, + DCNTL7=>dcntl(7), DCNTL6=>dcntl(6), DCNTL5=>dcntl(5), + DCNTL4=>dcntl(4), DCNTL3=>dcntl(3), DCNTL2=>dcntl(2), + DCNTL1=>dcntl(1), DCNTL0=>dcntl(0)); + + Inst3_DLLDELD: DLLDELD + port map (A=>buf_clkin, DDRDEL=>ddrdel, LOADN=>clock_loadn, + MOVE=>clock_move, DIRECTION=>clock_direction, Z=>sclk_t, + CFLAG=>clock_cflag); + + Inst2_IDDRX1F1: IDDRX1F + port map (D=>dataini_t1, SCLK=>sclk_t, RST=>reset, Q0=>qa1, + Q1=>qb1); + + Inst2_IDDRX1F0: IDDRX1F + port map (D=>dataini_t0, SCLK=>sclk_t, RST=>reset, Q0=>qa0, + Q1=>qb0); + + udel_dataini1: DELAYF + generic map (DEL_VALUE=> 11, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini1, LOADN=>data_loadn(1), + MOVE=>data_move(1), DIRECTION=>data_direction(1), + Z=>dataini_t1, CFLAG=>data_cflag(1)); + + udel_dataini0: DELAYF + generic map (DEL_VALUE=> 11, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini0, LOADN=>data_loadn(0), + MOVE=>data_move(0), DIRECTION=>data_direction(0), + Z=>dataini_t0, CFLAG=>data_cflag(0)); + + Inst1_IB1: IB + port map (I=>datain(1), O=>buf_dataini1); + + Inst1_IB0: IB + port map (I=>datain(0), O=>buf_dataini0); + + sclk <= sclk_t; + q(3) <= qb1; + q(2) <= qa1; + q(1) <= qb0; + q(0) <= qa0; + clock_direction <= scuba_vlo; + clock_move <= scuba_vlo; + clock_loadn <= uddcntln; +end Structure; diff --git a/adc/cores/adc_1ch/adc_1ch_edited.vhd b/adc/cores/adc_1ch/adc_1ch_edited.vhd new file mode 100644 index 0000000..39ddbbf --- /dev/null +++ b/adc/cores/adc_1ch/adc_1ch_edited.vhd @@ -0,0 +1,85 @@ + + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity adc_1ch_inp is + port ( + clkin: in std_logic; + sclk: out std_logic; + data_cflag: out std_logic; + data_direction: in std_logic; + data_loadn: in std_logic; + data_move: in std_logic; + datain: in std_logic_vector(1 downto 0); + q: out std_logic_vector(3 downto 0)); +end adc_1ch_inp; + +architecture Structure of adc_1ch_inp is + + -- internal signal declarations + signal buf_clkin: std_logic; + + signal qb1: std_logic; + signal qa1: std_logic; + signal qb0: std_logic; + signal qa0: std_logic; + signal sclk_t: std_logic; + + signal dataini_t1: std_logic; + signal dataini_t0: std_logic; + + signal buf_dataini1: std_logic; + signal buf_dataini0: std_logic; + + attribute IO_TYPE : string; +-- attribute IO_TYPE of Inst3_IB : label is "LVDS"; + attribute IO_TYPE of Inst1_IB1 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB0 : label is "LVDS"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements +-- Inst3_IB: IB +-- port map (I=>clkin, O=>buf_clkin); +buf_clkin <= clkin; + + Inst2_IDDRX1F1: IDDRX1F + port map (D=>dataini_t1, SCLK=>sclk_t, RST=>'0', Q0=>qa1, + Q1=>qb1); + + Inst2_IDDRX1F0: IDDRX1F + port map (D=>dataini_t0, SCLK=>sclk_t, RST=>'0', Q0=>qa0, + Q1=>qb0); + + udel_dataini1: DELAYF + generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini1, LOADN=>data_loadn, + MOVE=>data_move, DIRECTION=>data_direction, + Z=>dataini_t1, CFLAG=>open); + + udel_dataini0: DELAYF + generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini0, LOADN=>data_loadn, + MOVE=>data_move, DIRECTION=>data_direction, + Z=>dataini_t0, CFLAG=>data_cflag); + + + Inst1_IB1: IB + port map (I=>datain(1), O=>buf_dataini1); + + Inst1_IB0: IB + port map (I=>datain(0), O=>buf_dataini0); + + sclk <= sclk_t; + + q(2) <= qb1; + q(3) <= qa1; + q(0) <= qb0; + q(1) <= qa0; + sclk_t <= buf_clkin; +end Structure; diff --git a/adc/cores/adc_1ch_clk/adc_1ch_clk.lpc b/adc/cores/adc_1ch_clk/adc_1ch_clk.lpc new file mode 100644 index 0000000..a0db5cd --- /dev/null +++ b/adc/cores/adc_1ch_clk/adc_1ch_clk.lpc @@ -0,0 +1,66 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=6.0 +ModuleName=adc_1ch_clk +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=06/25/2024 +Time=16:54:00 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Transmit +trioddr=0 +io_type=LVDS +width=1 +freq_in=200 +bandwidth=400 +aligned=Edge-to-Edge +pre-configuration=DISABLED +mode2=Transmit +trioddr2=0 +io_type2=LVDS +freq_in2=200 +gear=2:1 +aligned2=Edge-to-Edge +width2=1 +DataLane=By Time +EnECLK=0 +Interface=GDDRX1_TX.SCLK.Aligned +Delay=Bypass +DelVal= +EnInEdge= +NumEdge=BOTH +EnDynamic=0 +GenPll=0 +Freq= +AFreq= +Reference=0 +IOBUF= +ReceiverSync=0 +EnDynamicAlign= +DynamicAlign= +MIPIFilter=0 +enClkIBuf=0 +ClkIBuf=LVDS + +[Command] +cmd_line= -w -n adc_1ch_clk -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 1 -freq_in 200 -gear 2 -aligned -del -1 diff --git a/adc/cores/adc_1ch_clk/adc_1ch_clk.sbx b/adc/cores/adc_1ch_clk/adc_1ch_clk.sbx new file mode 100644 index 0000000..5b8443e --- /dev/null +++ b/adc/cores/adc_1ch_clk/adc_1ch_clk.sbx @@ -0,0 +1,322 @@ + + + + Lattice Semiconductor Corporation + LEGACY + DDR_GENERIC + 6.0 + + + Diamond_Simulation + simulation + + ./adc_1ch_clk.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./adc_1ch_clk.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + + LFE5UM-85F-8BG756C + synplify + 2024-06-25.16:54:02 + 2024-06-25.16:54:02 + 3.12.1.454 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + DDR_GENERIC + + + CoreRevision + 6.0 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 06/25/2024 + + + ModuleName + adc_1ch_clk + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 16:54:00 + + + VendorName + Lattice Semiconductor Corporation + + + + AFreq + + + + ClkIBuf + LVDS + + + DataLane + By Time + + + DelVal + + + + Delay + Bypass + + + Destination + Synplicity + + + DynamicAlign + + + + EDIF + 1 + + + EnDynamic + 0 + + + EnDynamicAlign + + + + EnECLK + 0 + + + EnInEdge + + + + Expression + BusA(0 to 7) + + + Freq + + + + GenPll + 0 + + + IO + 0 + + + IOBUF + + + + Interface + GDDRX1_TX.SCLK.Aligned + + + MIPIFilter + 0 + + + NumEdge + BOTH + + + Order + Big Endian [MSB:LSB] + + + ReceiverSync + 0 + + + Reference + 0 + + + VHDL + 1 + + + Verilog + 0 + + + aligned + Edge-to-Edge + + + aligned2 + Edge-to-Edge + + + bandwidth + 400 + + + enClkIBuf + 0 + + + freq_in + 200 + + + freq_in2 + 200 + + + gear + 2:1 + + + io_type + LVDS + + + io_type2 + LVDS + + + mode + Transmit + + + mode2 + Transmit + + + pre-configuration + DISABLED + + + trioddr + 0 + + + trioddr2 + 0 + + + width + 1 + + + width2 + 1 + + + + cmd_line + -w -n adc_1ch_clk -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 1 -freq_in 200 -gear 2 -aligned -del -1 + + + + + + + LATTICE + LOCAL + adc_1ch_clk + 1.0 + + + + diff --git a/adc/cores/adc_1ch_clk/adc_1ch_clk.vhd b/adc/cores/adc_1ch_clk/adc_1ch_clk.vhd new file mode 100644 index 0000000..565a18d --- /dev/null +++ b/adc/cores/adc_1ch_clk/adc_1ch_clk.vhd @@ -0,0 +1,53 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n adc_1ch_clk -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 1 -freq_in 200 -gear 2 -aligned -del -1 -fdc /local/trb/git/trb5sc/adc/project/adc_1ch_clk/adc_1ch_clk.fdc + +-- Tue Jun 25 16:54:02 2024 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity adc_1ch_clk is + port ( + refclk: in std_logic; + reset: in std_logic; + data: in std_logic_vector(1 downto 0); + dout: out std_logic_vector(0 downto 0)); +end adc_1ch_clk; + +architecture Structure of adc_1ch_clk is + + -- internal signal declarations + signal db0: std_logic; + signal da0: std_logic; + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal sclk_t: std_logic; + signal clkos: std_logic; + signal clkop: std_logic; + signal buf_clkout: std_logic; + signal buf_douto0: std_logic; + + attribute IO_TYPE : string; + attribute IO_TYPE of Inst1_OB0 : label is "LVDS"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + Inst4_ODDRX1F0: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da0, D1=>db0, + Q=>buf_douto0); + + Inst1_OB0: OB + port map (I=>buf_douto0, O=>dout(0)); + + db0 <= data(1); + da0 <= data(0); + sclk_t <= clkop; + clkos <= refclk; + clkop <= refclk; +end Structure; diff --git a/adc/cores/input_4ch/input_4ch.lpc b/adc/cores/input_4ch/input_4ch.lpc index 68f5b98..b7211f9 100644 --- a/adc/cores/input_4ch/input_4ch.lpc +++ b/adc/cores/input_4ch/input_4ch.lpc @@ -16,8 +16,8 @@ CoreRevision=6.0 ModuleName=input_4ch SourceFormat=vhdl ParameterFileVersion=1.0 -Date=04/30/2024 -Time=11:23:01 +Date=06/04/2024 +Time=12:32:38 [Parameters] Verilog=0 @@ -45,7 +45,7 @@ width2=5 DataLane=By Lane EnECLK=0 Interface=GDDRX2_RX.ECLK.Aligned -Delay=Static User Defined +Delay=Dynamic User Defined DelVal=59 EnInEdge= NumEdge=BOTH @@ -63,4 +63,4 @@ enClkIBuf=0 ClkIBuf=LVDS [Command] -cmd_line= -w -n input_4ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 5 -freq_in 350 -gear 4 -aligned -del 59 -data_lane +cmd_line= -w -n input_4ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 5 -freq_in 350 -gear 4 -aligned -del 59 -dynamic_delay -data_lane diff --git a/adc/cores/input_4ch/input_4ch.sbx b/adc/cores/input_4ch/input_4ch.sbx index 49e7d6a..7c78929 100644 --- a/adc/cores/input_4ch/input_4ch.sbx +++ b/adc/cores/input_4ch/input_4ch.sbx @@ -45,7 +45,7 @@ LFE5UM-85F-8BG756C synplify 2024-04-30.10:34:12 AM - 2024-04-30.01:43:04 PM + 2024-06-04.12:32:40 3.12.1.454 VHDL @@ -115,7 +115,7 @@ Date - 04/30/2024 + 06/04/2024 ModuleName @@ -131,7 +131,7 @@ Time - 11:23:01 + 12:32:38 VendorName @@ -156,7 +156,7 @@ Delay - Static User Defined + Dynamic User Defined Destination @@ -305,7 +305,7 @@ cmd_line - -w -n input_4ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 5 -freq_in 350 -gear 4 -aligned -del 59 -data_lane + -w -n input_4ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 5 -freq_in 350 -gear 4 -aligned -del 59 -dynamic_delay -data_lane diff --git a/adc/cores/input_4ch/input_4ch.vhd b/adc/cores/input_4ch/input_4ch.vhd index 56ab7b4..8e10e51 100644 --- a/adc/cores/input_4ch/input_4ch.vhd +++ b/adc/cores/input_4ch/input_4ch.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 -- Module Version: 5.8 ---/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n input_4ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 5 -freq_in 350 -gear 4 -aligned -del 59 -data_lane +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n input_4ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 5 -freq_in 350 -gear 4 -aligned -del 59 -dynamic_delay -data_lane -fdc /local/trb/git/trb5sc/adc/cores/input_4ch/input_4ch.fdc --- Tue Apr 30 11:23:01 2024 +-- Tue Jun 4 12:32:40 2024 @@ -1143,6 +1143,10 @@ entity input_4ch is sync_clk: in std_logic; sync_reset: in std_logic; update: in std_logic; + data_cflag: out std_logic_vector(4 downto 0); + data_direction: in std_logic_vector(4 downto 0); + data_loadn: in std_logic_vector(4 downto 0); + data_move: in std_logic_vector(4 downto 0); datain: in std_logic_vector(4 downto 0); q: out std_logic_vector(19 downto 0)); end input_4ch; @@ -1205,7 +1209,7 @@ architecture Structure of input_4ch is ddr_reset: out std_logic; ready: out std_logic); end component; attribute IO_TYPE : string; - -- attribute IO_TYPE of Inst7_IB : label is "LVDS"; + attribute IO_TYPE of Inst7_IB : label is "LVDS"; attribute IO_TYPE of Inst1_IB4 : label is "LVDS"; attribute IO_TYPE of Inst1_IB3 : label is "LVDS"; attribute IO_TYPE of Inst1_IB2 : label is "LVDS"; @@ -1217,33 +1221,33 @@ architecture Structure of input_4ch is begin -- component instantiation statements - -- Inst7_IB: IB - -- port map (I=>clkin, O=>buf_clkin); + Inst7_IB: IB + port map (I=>clkin, O=>buf_clkin); Inst6_CLKDIVF: CLKDIVF generic map (DIV=> "2.0") port map (CLKI=>eclko, RST=>reset, ALIGNWD=>alignwd, CDIVX=>sclk_t); -eclko <= clkin; - -- Inst5_ECLKSYNCB: ECLKSYNCB - -- port map (ECLKI=>eclki, STOP=>stop, ECLKO=>eclko); - -- - -- Inst_rxdll_sync: input_4chrxdll_sync - -- port map (rst => sync_reset, sync_clk => sync_clk, update => update, - -- dll_lock => dll_lock, dll_reset => dll_reset, uddcntln => uddcntln, - -- freeze => freeze, stop => stop, ddr_reset => reset, - -- ready => ready); + + Inst5_ECLKSYNCB: ECLKSYNCB + port map (ECLKI=>eclki, STOP=>stop, ECLKO=>eclko); + + Inst_rxdll_sync: input_4chrxdll_sync + port map (rst => sync_reset, sync_clk => sync_clk, update => update, + dll_lock => dll_lock, dll_reset => dll_reset, uddcntln => uddcntln, + freeze => freeze, stop => stop, ddr_reset => reset, + ready => ready); scuba_vlo_inst: VLO port map (Z=>scuba_vlo); - -- Inst4_DDRDLLA: DDRDLLA - -- generic map (FORCE_MAX_DELAY=> "NO") - -- port map (CLK=>eclko, RST=>dll_reset, UDDCNTLN=>uddcntln, - -- FREEZE=>freeze, DDRDEL=>ddrdel, LOCK=>dll_lock, - -- DCNTL7=>dcntl(7), DCNTL6=>dcntl(6), DCNTL5=>dcntl(5), - -- DCNTL4=>dcntl(4), DCNTL3=>dcntl(3), DCNTL2=>dcntl(2), - -- DCNTL1=>dcntl(1), DCNTL0=>dcntl(0)); + Inst4_DDRDLLA: DDRDLLA + generic map (FORCE_MAX_DELAY=> "NO") + port map (CLK=>eclko, RST=>dll_reset, UDDCNTLN=>uddcntln, + FREEZE=>freeze, DDRDEL=>ddrdel, LOCK=>dll_lock, + DCNTL7=>dcntl(7), DCNTL6=>dcntl(6), DCNTL5=>dcntl(5), + DCNTL4=>dcntl(4), DCNTL3=>dcntl(3), DCNTL2=>dcntl(2), + DCNTL1=>dcntl(1), DCNTL0=>dcntl(0)); Inst3_DLLDELD: DLLDELD port map (A=>buf_clkin, DDRDEL=>ddrdel, LOADN=>clock_loadn, @@ -1270,25 +1274,35 @@ eclko <= clkin; port map (D=>dataini_t0, SCLK=>sclk_t, ECLK=>eclko, RST=>reset, ALIGNWD=>alignwd, Q3=>qd0, Q2=>qc0, Q1=>qb0, Q0=>qa0); - udel_dataini4: DELAYG + udel_dataini4: DELAYF generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini4, Z=>dataini_t4); + port map (A=>buf_dataini4, LOADN=>data_loadn(4), + MOVE=>data_move(4), DIRECTION=>data_direction(4), + Z=>dataini_t4, CFLAG=>data_cflag(4)); - udel_dataini3: DELAYG + udel_dataini3: DELAYF generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini3, Z=>dataini_t3); + port map (A=>buf_dataini3, LOADN=>data_loadn(3), + MOVE=>data_move(3), DIRECTION=>data_direction(3), + Z=>dataini_t3, CFLAG=>data_cflag(3)); - udel_dataini2: DELAYG + udel_dataini2: DELAYF generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini2, Z=>dataini_t2); + port map (A=>buf_dataini2, LOADN=>data_loadn(2), + MOVE=>data_move(2), DIRECTION=>data_direction(2), + Z=>dataini_t2, CFLAG=>data_cflag(2)); - udel_dataini1: DELAYG + udel_dataini1: DELAYF generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini1, Z=>dataini_t1); + port map (A=>buf_dataini1, LOADN=>data_loadn(1), + MOVE=>data_move(1), DIRECTION=>data_direction(1), + Z=>dataini_t1, CFLAG=>data_cflag(1)); - udel_dataini0: DELAYG + udel_dataini0: DELAYF generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini0, Z=>dataini_t0); + port map (A=>buf_dataini0, LOADN=>data_loadn(0), + MOVE=>data_move(0), DIRECTION=>data_direction(0), + Z=>dataini_t0, CFLAG=>data_cflag(0)); Inst1_IB4: IB port map (I=>datain(4), O=>buf_dataini4); diff --git a/adc/cores/input_4ch/input_4ch_edited.vhd b/adc/cores/input_4ch/input_4ch_edited.vhd index 5a3aab4..0e4d0e1 100644 --- a/adc/cores/input_4ch/input_4ch_edited.vhd +++ b/adc/cores/input_4ch/input_4ch_edited.vhd @@ -1138,6 +1138,10 @@ entity input_4ch is alignwd: in std_logic; clkin: in std_logic; sclk: out std_logic; + data_cflag: out std_logic; + data_direction: in std_logic; + data_loadn: in std_logic; + data_move: in std_logic; datain: in std_logic_vector(4 downto 0); q: out std_logic_vector(19 downto 0)); end input_4ch; @@ -1265,26 +1269,57 @@ eclko <= clkin; port map (D=>dataini_t0, SCLK=>sclk_t, ECLK=>eclko, RST=>reset, ALIGNWD=>alignwd, Q3=>qd0, Q2=>qc0, Q1=>qb0, Q0=>qa0); - udel_dataini4: DELAYG - generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini4, Z=>dataini_t4); + -- udel_dataini4: DELAYG + -- generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + -- port map (A=>buf_dataini4, Z=>dataini_t4); + -- + -- udel_dataini3: DELAYG + -- generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + -- port map (A=>buf_dataini3, Z=>dataini_t3); + -- + -- udel_dataini2: DELAYG + -- generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + -- port map (A=>buf_dataini2, Z=>dataini_t2); + -- + -- udel_dataini1: DELAYG + -- generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + -- port map (A=>buf_dataini1, Z=>dataini_t1); + -- + -- udel_dataini0: DELAYG + -- generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + -- port map (A=>buf_dataini0, Z=>dataini_t0); - udel_dataini3: DELAYG + udel_dataini4: DELAYF generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini3, Z=>dataini_t3); + port map (A=>buf_dataini4, LOADN=>data_loadn, + MOVE=>data_move, DIRECTION=>data_direction, + Z=>dataini_t4, CFLAG=>data_cflag); - udel_dataini2: DELAYG + udel_dataini3: DELAYF generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini2, Z=>dataini_t2); + port map (A=>buf_dataini3, LOADN=>data_loadn, + MOVE=>data_move, DIRECTION=>data_direction, + Z=>dataini_t3, CFLAG=>open); - udel_dataini1: DELAYG + udel_dataini2: DELAYF generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini1, Z=>dataini_t1); + port map (A=>buf_dataini2, LOADN=>data_loadn, + MOVE=>data_move, DIRECTION=>data_direction, + Z=>dataini_t2, CFLAG=>open); - udel_dataini0: DELAYG + udel_dataini1: DELAYF generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini0, Z=>dataini_t0); + port map (A=>buf_dataini1, LOADN=>data_loadn, + MOVE=>data_move, DIRECTION=>data_direction, + Z=>dataini_t1, CFLAG=>open); + udel_dataini0: DELAYF + generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini0, LOADN=>data_loadn, + MOVE=>data_move, DIRECTION=>data_direction, + Z=>dataini_t0, CFLAG=>open); + + Inst1_IB4: IB port map (I=>datain(4), O=>buf_dataini4); @@ -1301,26 +1336,26 @@ eclko <= clkin; port map (I=>datain(0), O=>buf_dataini0); sclk <= sclk_t; - q(19) <= qd4; - q(18) <= qc4; - q(17) <= qb4; - q(16) <= qa4; - q(15) <= qd3; - q(14) <= qc3; - q(13) <= qb3; - q(12) <= qa3; - q(11) <= qd2; - q(10) <= qc2; - q(9) <= qb2; - q(8) <= qa2; - q(7) <= qd1; - q(6) <= qc1; - q(5) <= qb1; - q(4) <= qa1; - q(3) <= qd0; - q(2) <= qc0; - q(1) <= qb0; - q(0) <= qa0; + q(16) <= qd4; + q(17) <= qc4; + q(18) <= qb4; + q(19) <= qa4; + q(12) <= qd3; + q(13) <= qc3; + q(14) <= qb3; + q(15) <= qa3; + q(8) <= qd2; + q(9) <= qc2; + q(10) <= qb2; + q(11) <= qa2; + q(4) <= qd1; + q(5) <= qc1; + q(6) <= qb1; + q(7) <= qa1; + q(0) <= qd0; + q(1) <= qc0; + q(2) <= qb0; + q(3) <= qa0; clock_direction <= scuba_vlo; clock_move <= scuba_vlo; clock_loadn <= uddcntln; diff --git a/adc/source/adc_18bit_input.vhd b/adc/source/adc_18bit_input.vhd new file mode 100644 index 0000000..3c0ad82 --- /dev/null +++ b/adc/source/adc_18bit_input.vhd @@ -0,0 +1,73 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.adc_package.all; + + +entity adc_18bit_input is + port( + CLK : in std_logic; -- 100 MHz + RESET : in std_logic; + RESET_ADC : in std_logic; + + CLK_ADCRAW : in std_logic; --200 MHz + ADC_DATA : in std_logic_vector(1 downto 0); + + SHIFT_ALIGN_IN : in std_logic; + DEL_CFLAG : out std_logic; + DEL_DIRECTION : in std_logic; + DEL_LOADN : in std_logic; + DEL_MOVE : in std_logic; + + ADC_CLK_OUT : out std_logic; + ADC_CNV_OUT : out std_logic; + + DATA_OUT : out std_logic_vector(17 downto 0); + DATA_VALID_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + +architecture arch of adc_18bit_input is + +signal data_in : std_logic_vector(3 downto 0); +signal clock_enable : std_logic; + +signal cycle_counter : integer range 0 to 12; + + +begin + + +THE_INPUT : adc_1ch_inp + port map ( + clkin => CLK_ADCRAW, + data_cflag => DEL_CFLAG, + data_direction => DEL_DIRECTION, + data_loadn => DEL_LOADN, + data_move => DEL_MOVE, + datain => ADC_DATA, + q => data_in + ); + + +THE_CLOCK_OUT : adc_1ch_clk + port map( + refclk => CLK_ADCRAW, + reset => '0', + data => '0' & clock_enable, + dout => ADC_CLK_OUT + ); + + +end architecture; + + + + + + diff --git a/adc/source/adc_addon.vhd b/adc/source/adc_addon.vhd index 390d9a9..12c59f9 100644 --- a/adc/source/adc_addon.vhd +++ b/adc/source/adc_addon.vhd @@ -20,6 +20,13 @@ entity adc_addon is DATA_A : in std_logic_vector(3 downto 0); DCO_A : in std_logic; + DCO_B : in std_logic; + DATA_B : in std_logic; + CLK_B : out std_logic; + CNV_B : out std_logic; + TESTPAT_B : out std_logic; + + READOUT_RX : in READOUT_RX; READOUT_TX : out readout_tx_array_t(0 to ACTIVE_CHANNELS-1); @@ -39,14 +46,27 @@ architecture arch of adc_addon is signal data_valid_a : std_logic; signal debug_a : std_logic_vector(31 downto 0); + type adc_data_arr is array(0 to 4) of std_logic_vector(17 downto 0); + signal data_processor_in : adc_data_arr; + signal data_processor_valid: std_logic_vector(4 downto 0); + signal basic_control_strobes : std_logic_vector(31 downto 0); alias STROBE_reset_a : std_logic is basic_control_strobes(0); alias STROBE_shift_align_a : std_logic is basic_control_strobes(1); + alias STROBE_del_move : std_logic is basic_control_strobes(3); + + alias STROBE_reset_b : std_logic is basic_control_strobes(8); + alias STROBE_shift_align_b : std_logic is basic_control_strobes(9); + alias STROBE_del_move_b : std_logic is basic_control_strobes(11); signal basic_control : std_logic_vector(31 downto 0); alias CONF_adc_stop : std_logic is basic_control(0); - alias CONF_baseline_always_on : std_logic is basic_control(1); + -- alias CONF_baseline_always_on : std_logic is basic_control(1); + alias CONF_del_direction : std_logic is basic_control(2); + alias CONF_del_loadn : std_logic is basic_control(3); + signal CONF_input_select : std_logic_vector(31 downto 0) := x"21043210"; + type config_arr_t is array(0 to ACTIVE_CHANNELS-1) of cfg_t; signal config : config_arr_t; @@ -84,11 +104,38 @@ THE_INPUT_A : entity work.adc_input ADC_DATA => FCO_A & DATA_A, SHIFT_ALIGN_IN => STROBE_shift_align_a, + DEL_CFLAG => open, + DEL_DIRECTION => CONF_del_direction, + DEL_LOADN => CONF_del_loadn, + DEL_MOVE => STROBE_del_move, + DATA_OUT => data_in_a, DATA_VALID_OUT => data_valid_a, DEBUG_OUT => debug_a ); + +------------------------------------------------------------------------------- +-- ADC Input Multiplexer +------------------------------------------------------------------------------- +gen_inputs : for i in 0 to ACTIVE_CHANNELS-1 generate + process begin + wait until rising_edge(CLK); + case CONF_input_select(i*4+3 downto i*4) is + when x"0" => data_processor_in(i) <= x"0" & data_in_a((0+1)*14-1 downto 0*14); + data_processor_valid(i) <= data_valid_a; + when x"1" => data_processor_in(i) <= x"0" & data_in_a((1+1)*14-1 downto 1*14); + data_processor_valid(i) <= data_valid_a; + when x"2" => data_processor_in(i) <= x"0" & data_in_a((2+1)*14-1 downto 2*14); + data_processor_valid(i) <= data_valid_a; + when x"3" => data_processor_in(i) <= x"0" & data_in_a((3+1)*14-1 downto 3*14); + data_processor_valid(i) <= data_valid_a; + --case x"4" => data_processor_in <= data_in_b; + end case; + end process; + +end generate; + ------------------------------------------------------------------------------- -- ADC Data Processors @@ -101,8 +148,8 @@ gen_processors : for i in 0 to ACTIVE_CHANNELS-1 generate port map( CLK => CLK, - ADC_DATA => data_in_a((i+1)*14-1 downto i*14), - ADC_VALID => data_valid_a, + ADC_DATA => data_processor_in(i), + ADC_VALID => data_processor_valid(i), STOP_IN => CONF_adc_stop, TRIGGER_OUT => TRIGGER_OUT(i), @@ -180,6 +227,7 @@ begin case BUS_RX.addr(7 downto 0) is when x"00" => basic_control_strobes <= BUS_RX.data; when x"01" => basic_control <= BUS_RX.data; + when x"02" => CONF_input_select <= BUS_RX.data; when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; elsif BUS_RX.addr(11 downto 8) = x"1" and ch < ACTIVE_CHANNELS then --100-19f basic configuration registers per channel @@ -194,8 +242,10 @@ begin config(ch).trigger_enable <= BUS_RX.data(28); when x"3" => config(ch).readout_threshold <= unsigned(BUS_RX.data(19 downto 0)); config(ch).readout_abovebelow <= BUS_RX.data(24); - when x"4" => config(ch).baseline_fix_value <= unsigned(BUS_RX.data); + when x"4" => config(ch).baseline_fix_value <= unsigned(BUS_RX.data(19 downto 0)); config(ch).baseline_subtract <= BUS_RX.data(29); + config(ch).baseline_always_on <= BUS_RX.data(30); + config(ch).baseline_fix <= BUS_RX.data(31); when x"5" => config(ch).channel_disable <= BUS_RX.data(0); config(ch).processing_mode <= to_integer(unsigned(BUS_RX.data(5 downto 4))); when x"6" => config(ch).check_word1 <= BUS_RX.data(17 downto 0); @@ -230,6 +280,7 @@ begin case BUS_RX.addr(7 downto 0) is when x"00" => BUS_TX.data <= (others => '0'); when x"01" => BUS_TX.data <= basic_control; + when x"02" => BUS_TX.data <= CONF_input_select; when x"10" => BUS_TX.data(13 downto 0) <= data_in_a(13 downto 0); when x"11" => BUS_TX.data(13 downto 0) <= data_in_a(27 downto 14); when x"12" => BUS_TX.data(13 downto 0) <= data_in_a(41 downto 28); @@ -262,26 +313,26 @@ end process; -- Baselines settings ------------------------------------------------------------------------------- ---TODO should be moved to processors & simplified -gen_copy_settings : for ch in 0 to ACTIVE_CHANNELS-1 generate - config(ch).baseline_always_on <= CONF_baseline_always_on; - - proc_baseline_reset_value : process begin - wait until rising_edge(CLK); - baseline_reset_value(ch, 3) <= (others => '0'); - baseline_reset_value(ch, 3)(to_integer(config(ch).averaging)+14-1 downto to_integer(config(ch).averaging)) <= (others => not config(ch).trigger_threshold(16)); - baseline_reset_value(ch, 2) <= baseline_reset_value(ch, 3); - baseline_reset_value(ch, 1) <= baseline_reset_value(ch, 2) (23 downto 0) * resize(config(ch).presum+1,8); - baseline_reset_value(ch, 0) <= baseline_reset_value(ch, 1); - - -- config(ch).baseline_subtract <= config(ch).baseline_fix_value(29); - - if config(ch).baseline_fix_value(30) = '0' then - config(ch).baseline_reset_value <= baseline_reset_value(ch,0); - else - config(ch).baseline_reset_value <= config(ch).baseline_fix_value(31) & '0' & config(ch).baseline_fix_value(29 downto 0); - end if; - end process; -end generate; +-- --TODO should be moved to processors & simplified +-- gen_copy_settings : for ch in 0 to ACTIVE_CHANNELS-1 generate +-- config(ch).baseline_always_on <= CONF_baseline_always_on; +-- +-- proc_baseline_reset_value : process begin +-- wait until rising_edge(CLK); +-- baseline_reset_value(ch, 3) <= (others => '0'); +-- baseline_reset_value(ch, 3)(to_integer(config(ch).averaging)+14-1 downto to_integer(config(ch).averaging)) <= (others => not config(ch).trigger_threshold(16)); +-- baseline_reset_value(ch, 2) <= baseline_reset_value(ch, 3); +-- baseline_reset_value(ch, 1) <= baseline_reset_value(ch, 2) (23 downto 0) * resize(config(ch).presum+1,8); +-- baseline_reset_value(ch, 0) <= baseline_reset_value(ch, 1); +-- +-- -- config(ch).baseline_subtract <= config(ch).baseline_fix_value(29); +-- +-- if config(ch).baseline_fix_value(30) = '0' then +-- config(ch).baseline_reset_value <= baseline_reset_value(ch,0); +-- else +-- config(ch).baseline_reset_value <= config(ch).baseline_fix_value(31) & '0' & config(ch).baseline_fix_value(29 downto 0); +-- end if; +-- end process; +-- end generate; end architecture; diff --git a/adc/source/adc_input.vhd b/adc/source/adc_input.vhd index 3e137ae..5360c57 100644 --- a/adc/source/adc_input.vhd +++ b/adc/source/adc_input.vhd @@ -16,6 +16,10 @@ entity adc_input is CLK_ADCRAW : in std_logic; --350 MHz ADC_DATA : in std_logic_vector(4 downto 0); SHIFT_ALIGN_IN : in std_logic; + DEL_CFLAG : out std_logic; + DEL_DIRECTION : in std_logic; + DEL_LOADN : in std_logic; + DEL_MOVE : in std_logic; DATA_OUT : out std_logic_vector(4*14-1 downto 0); DATA_VALID_OUT : out std_logic; @@ -59,6 +63,11 @@ THE_INPUT : entity work.input_4ch alignwd => SHIFT_ALIGN_IN, clkin => CLK_ADCRAW, sclk => clk_data, + data_cflag => del_cflag, + data_direction => del_direction, + data_loadn => del_loadn, + data_move => del_move, + datain => ADC_DATA, q => data_in ); diff --git a/adc/source/adc_package.vhd b/adc/source/adc_package.vhd index 6dc8c77..810c6a2 100644 --- a/adc/source/adc_package.vhd +++ b/adc/source/adc_package.vhd @@ -19,8 +19,8 @@ type cfg_t is record presum : unsigned( 6 downto 0); averaging : unsigned( 3 downto 0); baseline_always_on : std_logic; - baseline_reset_value : unsigned(31 downto 0); - baseline_fix_value : unsigned(31 downto 0); + baseline_fix : std_logic; + baseline_fix_value : unsigned(19 downto 0); baseline_subtract : std_logic; block_avg : unsigned_array_8(0 to 3); block_sums : unsigned_array_8(0 to 3); diff --git a/adc/source/adc_processor.vhd b/adc/source/adc_processor.vhd index c51321e..44aab61 100644 --- a/adc/source/adc_processor.vhd +++ b/adc/source/adc_processor.vhd @@ -10,7 +10,7 @@ use work.adc_package.all; entity adc_processor is generic( DEVICE : integer range 0 to 15 := 15; - RESOLUTION : integer range 10 to 18 := 14 + RESOLUTION : integer range 10 to 18 := 18 ); port( CLK : in std_logic; @@ -66,7 +66,6 @@ signal ram_rd_move_value : unsigned( 9 downto 0) := (others => '0'); signal ram_wr_pointer : unsigned( 9 downto 0) := (others => '0'); signal ram_rd_pointer : unsigned( 9 downto 0) := (others => '0'); signal ram_count : unsigned( 9 downto 0) := (others => '0'); -signal ram_reset : std_logic; signal ram_clear : std_logic; signal last_ramread : std_logic; signal ram_valid : std_logic; @@ -94,7 +93,7 @@ signal rdostatebits : std_logic_vector(3 downto 0); signal reg_CONTROL : std_logic_vector(15 downto 0); alias CONTROL_adc_stop : std_logic is reg_CONTROL(0); -alias CONTROL_baseline_always_on : std_logic is reg_CONTROL(1); +-- alias CONTROL_baseline_always_on : std_logic is reg_CONTROL(1); alias CONTROL_ram_clear : std_logic is reg_CONTROL(4); alias CONTROL_ram_reset : std_logic is reg_CONTROL(5); alias CONTROL_baseline_reset : std_logic is reg_CONTROL(8); @@ -103,7 +102,7 @@ alias CONTROL_readout_reset : std_logic is reg_CONTROL(12); signal reg_CONFIG : cfg_t; signal invalid_word_count : unsigned(31 downto 0); - +signal last_CONTROL_baseline_reset : std_logic; signal thresh_counter : unsigned( 9 downto 0); signal readout_flag : std_logic; signal reset_threshold_counter : std_logic; @@ -154,6 +153,9 @@ signal myavg : unsigned(7 downto 0); signal current_baseline : unsigned(19 downto 0); +signal reg_buffer_addr : std_logic_vector(3 downto 0); +signal reg_buffer_read : std_logic; + begin reg_CONFIG <= CONFIG when rising_edge(CLK); @@ -163,7 +165,30 @@ reg_CONTROL <= CONTROL when rising_edge(CLK); ------------------------------------------------------------------------------- -- Status registers --TODO ------------------------------------------------------------------------------- - +PROC_REGS : process + variable c : integer range 0 to 3; +begin + wait until rising_edge(CLK); + reg_buffer_addr <= PROC_REG_ADDR; + reg_buffer_read <= PROC_REG_READ; + PROC_REG_DATA <= (others => '0'); + PROC_REG_READY <= '0'; + c := to_integer(unsigned(reg_buffer_addr(1 downto 0))); + if reg_buffer_read = '1' then + PROC_REG_READY <= '1'; + case reg_buffer_addr is + when x"0" => PROC_REG_DATA( 9 downto 0) <= std_logic_vector(ram_count); + when x"1" => PROC_REG_DATA( 7 downto 0) <= statebits; + PROC_REG_DATA(11 downto 8) <= rdostatebits; + when x"2" => PROC_REG_DATA(19 downto 0) <= std_logic_vector(baseline); + when x"3" => PROC_REG_DATA <= std_logic_vector(invalid_word_count); + when x"4" => PROC_REG_DATA(0) <= ram_remove; + PROC_REG_DATA(1) <= trigger_gen; + PROC_REG_DATA(2) <= stop_writing; + PROC_REG_DATA(3) <= readout_flag; + end case; + end if; +end process; ------------------------------------------------------------------------------- @@ -245,7 +270,7 @@ reg_CONTROL <= CONTROL when rising_edge(CLK); proc_buffer_write : process begin wait until rising_edge(CLK); - if ram_reset = '1' then + if CONTROL_ram_reset = '1' then ram_wr_pointer <= (others => '0'); elsif ram_write = '1' then ram_wr_pointer <= ram_wr_pointer + 1; @@ -276,7 +301,7 @@ reg_CONTROL <= CONTROL when rising_edge(CLK); ram_count <= ram_wr_pointer - ram_rd_pointer +1; end if; - if ram_reset = '1' then + if CONTROL_ram_reset = '1' then ram_rd_pointer <= (others => '1'); --one behind write pointer elsif ram_clear = '1' then ram_rd_pointer <= ram_wr_pointer; @@ -296,8 +321,13 @@ reg_CONTROL <= CONTROL when rising_edge(CLK); ------------------------------------------------------------------------------- proc_baseline_calc : process begin wait until rising_edge(CLK); - if CONTROL_baseline_reset = '1' or reg_CONFIG.baseline_reset_value(31) = '1' then - baseline_averages <= "00" & reg_CONFIG.baseline_reset_value(29 downto 0); + if CONTROL_baseline_reset = '1' or reg_CONFIG.baseline_fix = '1' then + baseline_averages <= x"000" & reg_CONFIG.baseline_fix_value; + last_CONTROL_baseline_reset <= CONTROL_baseline_reset; + elsif last_CONTROL_baseline_reset = '1' and reg2_ram_remove = '1' then + last_CONTROL_baseline_reset <= '0'; + baseline_averages <= (others => '0'); + baseline_averages(to_integer(reg_CONFIG.averaging)+19 downto to_integer(reg_CONFIG.averaging)) <= resize(reg_ram_data_out(19 downto 0),20); elsif reg2_ram_remove = '1' and (reg_ram_data_out(23) = '0' or reg_CONFIG.baseline_always_on = '1') then baseline_averages <= baseline_averages + resize(reg_ram_data_out(19 downto 0),32) @@ -524,6 +554,9 @@ begin readout_state <= RDO_IDLE; end case; + if CONTROL_readout_reset = '1' then + readout_state <= RDO_IDLE; + end if; end process; @@ -574,7 +607,7 @@ begin end process; - +-- 0--CVVVVV -- ADC data, 20 bit data, MSN=0x0, C: channel ------------------------------------------------------------------------------- -- PSA State Machine ------------------------------------------------------------------------------- @@ -669,6 +702,10 @@ begin end case; + + if CONTROL_readout_reset = '1' then + psa_state <= PSA_IDLE; + end if; end process; diff --git a/adc/trb5sc_adc.vhd b/adc/trb5sc_adc.vhd index abb2bad..16f5b48 100644 --- a/adc/trb5sc_adc.vhd +++ b/adc/trb5sc_adc.vhd @@ -96,7 +96,7 @@ end entity; architecture arch of trb5sc_adc is - constant ACTIVE_CHANNELS : integer := 2; + constant ACTIVE_CHANNELS : integer := 5; attribute syn_keep : boolean; attribute syn_preserve : boolean;