From: Jan Michel Date: Fri, 9 Feb 2018 17:10:14 +0000 (+0100) Subject: fix config files X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=17eda8c5d171e65d5211ef3ee99ce5f31f48c27f;p=trb3sc.git fix config files --- diff --git a/hub/config.vhd b/hub/config.vhd index b43f22f..ca579d5 100644 --- a/hub/config.vhd +++ b/hub/config.vhd @@ -13,7 +13,7 @@ package config is --design options: backplane or front SFP, with or without GBE constant USE_BACKPLANE : integer := c_YES; - constant INCLUDE_GBE : integer := c_YES; + constant INCLUDE_GBE : integer := c_NO; --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; @@ -140,10 +140,10 @@ function generateIncludedFeatures return std_logic_vector is begin t := (others => '0'); t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 - t(22 downto 17) := "0100111"; --sctrl via GbE + t(22 downto 16) := "0100111"; --sctrl via GbE t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); t(27 downto 24) := std_logic_vector(to_unsigned(INTERFACE_NUM-USE_BACKPLANE,4)); --num SFPs with TrbNet - t(28) := std_logic_vector(to_unsigned(USE_BACKPLANE,1)); + t(28 downto 28) := std_logic_vector(to_unsigned(USE_BACKPLANE,1)); t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); diff --git a/tdctemplate/config_32_sfp_kel.vhd b/tdctemplate/config_32_sfp_kel.vhd index 06d4558..1aa4584 100644 --- a/tdctemplate/config_32_sfp_kel.vhd +++ b/tdctemplate/config_32_sfp_kel.vhd @@ -37,7 +37,7 @@ package config is --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; - constant USE_200MHZOSCILLATOR : integer := c_NO; + constant USE_200MHZOSCILLATOR : integer := c_YES; constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? @@ -90,7 +90,7 @@ package config is ------------------------------------------------------------------------------ type intlist_t is array(0 to 7) of integer; type hw_info_t is array(0 to 7) of unsigned(31 downto 0); - constant HW_INFO_BASE : unsigned(31 downto 0) := x"95000000"; + constant HW_INFO_BASE : unsigned(31 downto 0) := x"9500B000"; --Change depening on pinout constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); @@ -125,7 +125,7 @@ function generateIncludedFeatures return std_logic_vector is t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); t(15) := '1'; --TDC t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); - t(28) := std_logic_vector(to_unsigned(3-SERDES_NUM,1)); + t(28 downto 28) := std_logic_vector(to_unsigned(3-SERDES_NUM,1)); t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); diff --git a/tdctemplate/config_48_crate_4conn.vhd b/tdctemplate/config_48_crate_4conn.vhd index 147e599..0224d6d 100644 --- a/tdctemplate/config_48_crate_4conn.vhd +++ b/tdctemplate/config_48_crate_4conn.vhd @@ -49,7 +49,7 @@ package config is constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"70"; --set to 0 for backplane serdes, set to 3 for front SFP serdes - constant SERDES_NUM : integer := 3; + constant SERDES_NUM : integer := 0; constant INCLUDE_UART : integer := c_NO; constant INCLUDE_SPI : integer := c_YES; @@ -125,7 +125,7 @@ function generateIncludedFeatures return std_logic_vector is t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); t(15) := '1'; --TDC t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); - t(28) := std_logic_vector(to_unsigned(3-SERDES_NUM,1)); + t(28 downto 28) := std_logic_vector(to_unsigned(3-SERDES_NUM,1)); t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index e6a7573..7e30989 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -183,11 +183,11 @@ begin DEBUG_OUT => debug_clock_reset ); - pll_calibration : entity work.pll_in125_out33 - port map ( - CLK => CLK_SUPPL_PCLK, - CLKOP => clk_cal, - LOCK => open); +-- pll_calibration : entity work.pll_in125_out33 +-- port map ( +-- CLK => CLK_SUPPL_PCLK, +-- CLKOP => clk_cal, +-- LOCK => open); -- GSR_N <= reset_i; @@ -480,7 +480,7 @@ TEST_LINE <= med_stat_debug(15 downto 0); CLK_READOUT => clk_sys, -- Clock for the readout REFERENCE_TIME => TRIG_LEFT, -- Reference time input HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals - HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + HIT_CAL_IN => CLK_SUPPL_PCLK, -- Hits for calibrating the TDC -- Trigger signals from handler BUSRDO_RX => readout_rx, BUSRDO_TX => readout_tx(0), diff --git a/template/config.vhd b/template/config.vhd index 1fa56af..ff252d8 100644 --- a/template/config.vhd +++ b/template/config.vhd @@ -95,7 +95,7 @@ function generateIncludedFeatures return std_logic_vector is begin t := (others => '0'); t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 - t(28) := std_logic_vector(to_unsigned(3-SERDES_NUM,1)); + t(28 downto 28) := std_logic_vector(to_unsigned(3-SERDES_NUM,1)); t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));