From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Wed, 18 Feb 2015 09:52:30 +0000 (+0100)
Subject: Restart FIFO properly, otherwise sim does not work
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=185c195b75f20b4c2ade46e6a8dd7f54c53f8dd3;p=trb3.git

Restart FIFO properly, otherwise sim does not work
---

diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd
index c927e85..2f777e6 100644
--- a/ADC/source/adc_ad9219.vhd
+++ b/ADC/source/adc_ad9219.vhd
@@ -239,7 +239,7 @@ begin
         RdClock            => CLK,
         WrEn               => fifo_write(i),
         RdEn               => '1',
-        Reset              => '0',
+        Reset              => RESTART_IN,
         RPReset            => RESTART_IN,
         Q(49 downto 0)     => fifo_output(i),
         Empty              => fifo_empty(i),