From: Jan Michel <j.michel@gsi.de>
Date: Mon, 18 Dec 2017 12:55:45 +0000 (+0100)
Subject: add 200 MHz oscillator option to hubs
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=187280330c3dd5dd98403c16db2b2a7005b7bbe3;p=trb3sc.git

add 200 MHz oscillator option to hubs
---

diff --git a/backplanemaster/config.vhd b/backplanemaster/config.vhd
index 870783b..2aea6ce 100644
--- a/backplanemaster/config.vhd
+++ b/backplanemaster/config.vhd
@@ -13,15 +13,16 @@ package config is
 
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
+    constant USE_200MHZOSCILLATOR   : integer := c_YES;
     constant USE_EXTERNAL_CLOCK     : integer := c_YES; --'no' not implemented.
-    constant CLOCK_FAST_SELECT        : integer := c_YES; --fast clock select (135us) or slow (280ms)?
+    constant CLOCK_FAST_SELECT      : integer := c_YES; --fast clock select (135us) or slow (280ms)?
     
 --Use sync mode, RX clock for all parts of the FPGA
     constant USE_RXCLOCK            : integer := c_NO;
    
 --Address settings   
     constant INIT_ADDRESS           : std_logic_vector := x"F3CE";
-    constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"60";
+    constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"61";
    
 
     constant INCLUDE_UART           : integer  := c_YES;
diff --git a/backplanemaster/par.p2t b/backplanemaster/par.p2t
index d03f522..7610522 100644
--- a/backplanemaster/par.p2t
+++ b/backplanemaster/par.p2t
@@ -1,10 +1,9 @@
 -w
 -i 15
 -l 5
--n 1
 -y
 -s 12
--t 15
+-t 16
 -c 1
 -e 2
 #-g guidefile.ncd
diff --git a/backplanemaster/trb3sc_master.prj b/backplanemaster/trb3sc_master.prj
index e564ff2..03522a9 100644
--- a/backplanemaster/trb3sc_master.prj
+++ b/backplanemaster/trb3sc_master.prj
@@ -66,6 +66,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd"
 add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
diff --git a/hub/config.vhd b/hub/config.vhd
index 4df0e1f..ebfae8b 100644
--- a/hub/config.vhd
+++ b/hub/config.vhd
@@ -12,11 +12,12 @@ package config is
 ------------------------------------------------------------------------------
 
 --design options: backplane or front SFP, with or without GBE
-    constant USE_BACKPLANE : integer := c_NO;
-    constant INCLUDE_GBE   : integer := c_YES;
+    constant USE_BACKPLANE : integer := c_YES;
+    constant INCLUDE_GBE   : integer := c_NO;
 
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
+    constant USE_200MHZOSCILLATOR   : integer := c_YES;
     constant USE_EXTERNAL_CLOCK     : integer := c_YES; --'no' not implemented.
     constant CLOCK_FAST_SELECT      : integer := c_NO; --fast clock select (135us) or slow (280ms)?
     
@@ -150,6 +151,7 @@ function generateIncludedFeatures return std_logic_vector is
     t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
     t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
     t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+    t(55 downto 55) := std_logic_vector(to_unsigned(USE_200MHZOSCILLATOR,1));
     return t;
   end function;  
 
diff --git a/hub/par.p2t b/hub/par.p2t
index f72683d..cb0ad8d 100644
--- a/hub/par.p2t
+++ b/hub/par.p2t
@@ -4,7 +4,7 @@
 -n 1
 -y
 -s 12
--t 24
+-t 26
 -c 1
 -e 2
 #-g guidefile.ncd
diff --git a/hub/trb3sc_hub.prj b/hub/trb3sc_hub.prj
index b39d4f2..052ecb5 100644
--- a/hub/trb3sc_hub.prj
+++ b/hub/trb3sc_hub.prj
@@ -65,6 +65,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
 #Basic Infrastructure
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
 add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
@@ -215,6 +216,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd"
 add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v"
 add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v"