From: a.weber Date: Thu, 21 Jun 2018 09:18:05 +0000 (+0200) Subject: AW: Vhdl code for Rich Sensor board ; new OneWire , new parsing X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=19b546f9a71d4c6fc6a7fb5a5a7b4bb9d59e6494;p=trb3sc.git AW: Vhdl code for Rich Sensor board ; new OneWire , new parsing --- diff --git a/pinout/trb3sc_richSensor.lpf b/pinout/trb3sc_richSensor.lpf new file mode 100644 index 0000000..76db20c --- /dev/null +++ b/pinout/trb3sc_richSensor.lpf @@ -0,0 +1,548 @@ +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_SUPPL_PLL_RIGHT" SITE "Y28"; #was SUPPL_CLOCK1_P +LOCATE COMP "CLK_SUPPL_PLL_LEFT" SITE "Y9"; #was SUPPL_CLOCK2_P +LOCATE COMP "CLK_SUPPL_PCLK" SITE "V9"; #was SUPPL_CLOCK3_P +LOCATE COMP "CLK_CORE_PCLK" SITE "U9"; #was "CORE_CLOCK0_P" +LOCATE COMP "CLK_CORE_PLL_LEFT" SITE "U6"; #was "CORE_CLOCK1_P" +LOCATE COMP "CLK_CORE_PLL_RIGHT" SITE "V34"; #was "CORE_CLOCK2_P" +LOCATE COMP "CLK_EXT_PCLK" SITE "U28"; #was "EXT_CLOCK0_P" +LOCATE COMP "CLK_EXT_PLL_RIGHT" SITE "P30"; #was "EXT_CLOCK1_P" +LOCATE COMP "CLK_EXT_PLL_LEFT" SITE "N7"; #was "EXT_CLOCK2_P" +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +LOCATE COMP "TRIG_PLL" SITE "AJ34"; +LOCATE COMP "TRIG_RIGHT" SITE "P34"; +LOCATE COMP "TRIG_LEFT" SITE "T6"; +DEFINE PORT GROUP "TRIG_group" "TRIG*" ; +IOBUF GROUP "TRIG_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + + + +################################################################# +# Backplane I/O +################################################################# +LOCATE COMP "BACK_GPIO_0" SITE "C26"; +LOCATE COMP "BACK_GPIO_1" SITE "D26"; +LOCATE COMP "BACK_GPIO_2" SITE "B27"; +LOCATE COMP "BACK_GPIO_3" SITE "C27"; +LOCATE COMP "BACK_GPIO_4" SITE "D27"; +LOCATE COMP "BACK_GPIO_5" SITE "E27"; +LOCATE COMP "BACK_GPIO_6" SITE "B28"; +LOCATE COMP "BACK_GPIO_7" SITE "A28"; +LOCATE COMP "BACK_GPIO_8" SITE "A26"; +LOCATE COMP "BACK_GPIO_9" SITE "A27"; +LOCATE COMP "BACK_GPIO_10" SITE "A29"; +LOCATE COMP "BACK_GPIO_11" SITE "A30"; +LOCATE COMP "BACK_GPIO_12" SITE "H26"; +LOCATE COMP "BACK_GPIO_13" SITE "H25"; +LOCATE COMP "BACK_GPIO_14" SITE "A31"; +LOCATE COMP "BACK_GPIO_15" SITE "B31"; +DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ; +IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + +LOCATE COMP "BACK_LVDS_0" SITE "V2"; +LOCATE COMP "BACK_LVDS_1" SITE "T4"; +# LOCATE COMP "BACK_LVDS_0_N" SITE "V1"; +# LOCATE COMP "BACK_LVDS_1_N" SITE "T3"; +DEFINE PORT GROUP "BACK_LVDS_group" "BACK_LVDS*" ; +IOBUF GROUP "BACK_LVDS_group" IO_TYPE=LVDS25; + +LOCATE COMP "BACK_3V3_0" SITE "E11"; +LOCATE COMP "BACK_3V3_1" SITE "F12"; +LOCATE COMP "BACK_3V3_2" SITE "F10"; +LOCATE COMP "BACK_3V3_3" SITE "E10"; +DEFINE PORT GROUP "BACK_3V3_group" "BACK_3V3*" ; +IOBUF GROUP "BACK_3V3_group" IO_TYPE=LVTTL33 PULLMODE=DOWN; + +################################################################# +# AddOn Connector +################################################################# + +### UART_RX -> MagBoard #### + +LOCATE COMP "INP_0" SITE "AA2"; #INP_CH00 #0 +LOCATE COMP "INP_1" SITE "AA4"; #INP_CH02 #1 +LOCATE COMP "INP_2" SITE "AA5"; #INP_CH04 #2 +LOCATE COMP "INP_3" SITE "AC5"; #INP_CH06 #3 +LOCATE COMP "INP_4" SITE "AB4"; #INP_CH08 #4 +LOCATE COMP "INP_5" SITE "AA9"; #INP_CH10 #5 +LOCATE COMP "INP_6" SITE "N4"; #INP_CH12 #6 +LOCATE COMP "INP_7" SITE "M5"; #INP_CH14 #7 + +DEFINE PORT GROUP "INP_group" "INP*" ; +IOBUF GROUP "INP_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + +### UART_TX -> RELAIS #### +LOCATE COMP "OUTP_0" SITE "AE4"; #INP_CH16 #8 +LOCATE COMP "OUTP_1" SITE "AE2"; #INP_CH18 #9 +DEFINE PORT GROUP "OUTP_group" "OUTP*" ; +IOBUF GROUP "OUTP_group" IO_TYPE=LVCMOS25 DRIVE=8; + + +### ONEWIRE #### +LOCATE COMP "ONEWIRE_0" SITE "AD4"; #INP_CH20 #10 +LOCATE COMP "ONEWIRE_1" SITE "Y2"; #INP_CH22 #11 +LOCATE COMP "ONEWIRE_2" SITE "W2"; #INP_CH24 #12 + +DEFINE PORT GROUP "ONEWIRE_group" "ONEWIRE*" ; +IOBUF GROUP "ONEWIRE_group" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=12; + +### INTERLOCK ### +LOCATE COMP "INTERLOCK_OUT" SITE "W8"; #INP_CH26 #13 +IOBUF PORT "INTERLOCK_OUT" IO_TYPE=LVCMOS25; +LOCATE COMP "INTERLOCK_GND_OUT" SITE "Y8"; #INP_CH27 +IOBUF PORT "INTERLOCK_GND_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN; + + +# # LOCATE COMP "DQLL0_0_N" SITE "AA1"; +# # LOCATE COMP "DQLL0_1_N" SITE "AB1"; +# # LOCATE COMP "DQLL0_2_N" SITE "AA3"; +# # LOCATE COMP "DQLL0_3_N" SITE "AB5"; +# # LOCATE COMP "DQLL0_4_N" SITE "AA7"; +# # LOCATE COMP "DQLL1_0_N" SITE "Y1"; +# # LOCATE COMP "DQLL1_1_N" SITE "W3"; +# # LOCATE COMP "DQLL1_2_N" SITE "W1"; +# # LOCATE COMP "DQLL1_3_N" SITE "W9"; +# # LOCATE COMP "DQLL1_4_N" SITE "AA8"; +# # LOCATE COMP "DQLL2_0_N" SITE "AC4"; +# # LOCATE COMP "DQLL2_1_N" SITE "AC1"; +# # LOCATE COMP "DQLL2_2_N" SITE "AB3"; +# # LOCATE COMP "DQLL2_3_N" SITE "AB8"; +# # LOCATE COMP "DQLL2_4_N" SITE "AB6"; +# # LOCATE COMP "DQLL3_0_N" SITE "AE3"; +# # LOCATE COMP "DQLL3_1_N" SITE "AC10" +# # LOCATE COMP "DQLL3_2_N" SITE "AE1"; +# # LOCATE COMP "DQLL3_3_N" SITE "AD3"; +# # LOCATE COMP "DQLL3_4_N" SITE "AC8"; +# # LOCATE COMP "DQLR0_0_N" SITE "AB33" +# # LOCATE COMP "DQLR0_1_N" SITE "AA26" +# # LOCATE COMP "DQLR0_2_N" SITE "AC33" +# # LOCATE COMP "DQLR0_3_N" SITE "AA30" +# # LOCATE COMP "DQLR0_4_N" SITE "AA27" +# # LOCATE COMP "DQLR1_0_N" SITE "AD30" +# # LOCATE COMP "DQLR1_1_N" SITE "AB31" +# # LOCATE COMP "DQLR1_2_N" SITE "AE33" +# # LOCATE COMP "DQLR1_3_N" SITE "AD34" +# # LOCATE COMP "DQLR1_4_N" SITE "AG34" +# # LOCATE COMP "DQLR2_0_N" SITE "W29"; +# # LOCATE COMP "DQLR2_1_N" SITE "W26"; +# # LOCATE COMP "DQLR2_2_N" SITE "W33";; +# # LOCATE COMP "DQLR2_3_N" SITE "Y33";; +# # LOCATE COMP "DQLR2_4_N" SITE "Y25"; +# # LOCATE COMP "DQSLL0_C" SITE "AB9"; +# # LOCATE COMP "DQSLL1_C" SITE "Y6"; +# # LOCATE COMP "DQSLL2_C" SITE "AE5"; +# # LOCATE COMP "DQSLL3_C" SITE "AK1"; +# # LOCATE COMP "DQSLR0_C" SITE "AC30" +# # LOCATE COMP "DQSLR1_C" SITE "AB25"; +# # LOCATE COMP "DQSLR2_C" SITE "AA29"; +# # LOCATE COMP "DQSUL0_C" SITE "M9";; +# # LOCATE COMP "DQSUL1_C" SITE "L9";; +# # LOCATE COMP "DQSUL2_C" SITE "H3";; +# # LOCATE COMP "DQSUL3_C" SITE "N10";; +# # LOCATE COMP "DQSUR0_C" SITE "M27";; +# # LOCATE COMP "DQSUR1_C" SITE "N28";; +# # LOCATE COMP "DQSUR2_C" SITE "U30";; +# # LOCATE COMP "DQUL0_0_N" SITE "L4";; +# # LOCATE COMP "DQUL0_1_N" SITE "M3";; +# # LOCATE COMP "DQUL0_2_N" SITE "K5";; +# # LOCATE COMP "DQUL0_3_N" SITE "M1";; +# # LOCATE COMP "DQUL0_4_N" SITE "L6";; +# # LOCATE COMP "DQUL1_0_N" SITE "L1";; +# # LOCATE COMP "DQUL1_1_N" SITE "K1";; +# # LOCATE COMP "DQUL1_2_N" SITE "K3";; +# # LOCATE COMP "DQUL1_3_N" SITE "L7";; +# # LOCATE COMP "DQUL1_4_N" SITE "J6";; +# # LOCATE COMP "DQUL2_0_N" SITE "F1";; +# # LOCATE COMP "DQUL2_1_N" SITE "E3"; +# # LOCATE COMP "DQUL2_2_N" SITE "G1"; +# # LOCATE COMP "DQUL2_3_N" SITE "J1"; +# # LOCATE COMP "DQUL2_4_N" SITE "H2"; +# # LOCATE COMP "DQUL3_0_N" SITE "N3"; +# # LOCATE COMP "DQUL3_1_N" SITE "N1"; +# # LOCATE COMP "DQUL3_2_N" SITE "N5"; +# # LOCATE COMP "DQUL3_3_N" SITE "P4"; +# # LOCATE COMP "DQUL3_4_N" SITE "P8"; +# # LOCATE COMP "DQUR0_0_N" SITE "M25"; +# # LOCATE COMP "DQUR0_1_N" SITE "L31"; +# # LOCATE COMP "DQUR0_2_N" SITE "L33";; +# # LOCATE COMP "DQUR0_3_N" SITE "K30"; +# # LOCATE COMP "DQUR0_4_N" SITE "K33"; +# # LOCATE COMP "DQUR1_0_N" SITE "N29"; +# # LOCATE COMP "DQUR1_1_N" SITE "P26"; +# # LOCATE COMP "DQUR1_2_N" SITE "N31"; +# # LOCATE COMP "DQUR1_3_N" SITE "N33"; +# # LOCATE COMP "DQUR1_4_N" SITE "P27";; +# # LOCATE COMP "DQUR2_0_N" SITE "T31";; +# # LOCATE COMP "DQUR2_1_N" SITE "T27";; +# # LOCATE COMP "DQUR2_2_N" SITE "U31";; +# # LOCATE COMP "DQUR2_3_N" SITE "T33";; +# # LOCATE COMP "DQUR2_4_N" SITE "U27"; +# +# LOCATE COMP "DQLL0_0" SITE "AA2"; #was "DQLL0_0_P" 1 +# LOCATE COMP "DQLL0_1" SITE "AB2"; #was "DQLL0_1_P" 5 +# LOCATE COMP "DQLL0_2" SITE "AA4"; #was "DQLL0_2_P" 9 +# LOCATE COMP "DQSLL0" SITE "AA10"; #was "DQSLL0_T" 13 +# LOCATE COMP "DQLL0_3" SITE "AA5"; #was "DQLL0_3_P" 17 +# LOCATE COMP "DQLL0_4" SITE "Y7"; #was "DQLL0_4_P" 21 +# LOCATE COMP "DQLL2_0" SITE "AC5"; #was "DQLL2_0_P" 25 +# LOCATE COMP "DQLL2_1" SITE "AC2"; #was "DQLL2_1_P" 29 +# LOCATE COMP "DQLL2_2" SITE "AB4"; #was "DQLL2_2_P" 33 +# LOCATE COMP "DQSLL2" SITE "AD5"; #was "DQSLL2_T" 37 +# LOCATE COMP "DQLL2_3" SITE "AA9"; #was "DQLL2_3_P" 41 +# LOCATE COMP "DQLL2_4" SITE "AB7"; #was "DQLL2_4_P" 45 +# LOCATE COMP "DQUL3_0" SITE "N4"; #was "DQUL3_0_P" 49 +# LOCATE COMP "DQUL3_1" SITE "N2"; #was "DQUL3_1_P" 53 +# LOCATE COMP "DQUL3_2" SITE "M5"; #was "DQUL3_2_P" 57 +# LOCATE COMP "DQSUL3" SITE "M10"; #was "DQSUL3_T" 61 +# LOCATE COMP "DQUL3_3" SITE "P5"; #was "DQUL3_3_P" 65 +# LOCATE COMP "DQUL3_4" SITE "N8"; #was "DQUL3_4_P" 69 +# LOCATE COMP "DQUL1_0" SITE "L2"; #was "DQUL1_0_P" 73 +# LOCATE COMP "DQUL1_1" SITE "K2"; #was "DQUL1_1_P" 77 +# LOCATE COMP "DQUL1_2" SITE "K4"; #was "DQUL1_2_P" 81 +# LOCATE COMP "DQSUL1" SITE "L10"; #was "DQSUL1_T" 85 +# LOCATE COMP "DQUL1_3" SITE "M8"; #was "DQUL1_3_P" 89 +# LOCATE COMP "DQUL1_4" SITE "K7"; #was "DQUL1_4_P" 93 +# +# LOCATE COMP "DQUR0_0" SITE "L26"; #was "DQUR0_0_P" 105 +# LOCATE COMP "DQUR0_1" SITE "L32"; #was "DQUR0_1_P" 109 +# LOCATE COMP "DQSUR0" SITE "M26"; #was "DQSUR0_T" 113 +# LOCATE COMP "DQUR0_2" SITE "L34"; #was "DQUR0_2_P" 117 +# LOCATE COMP "DQUR0_3" SITE "K29"; #was "DQUR0_3_P" 121 +# LOCATE COMP "DQUR0_4" SITE "K34"; #was "DQUR0_4_P" 125 +# LOCATE COMP "DQLR0_0" SITE "AB34"; #was "DQLR0_0_P" 129 +# LOCATE COMP "DQLR0_1" SITE "AA25"; #was "DQLR0_1_P" 133 +# LOCATE COMP "DQLR0_2" SITE "AC34"; #was "DQLR0_2_P" 137 +# LOCATE COMP "DQSLR0" SITE "AB30"; #was "DQSLR0_T" 141 +# LOCATE COMP "DQLR0_3" SITE "AA31"; #was "DQLR0_3_P" 145 +# LOCATE COMP "DQLR0_4" SITE "AA28"; #was "DQLR0_4_P" 149 +# +# LOCATE COMP "DQLR1_0" SITE "AD31"; #was "DQLR1_0_P" 169 +# LOCATE COMP "DQLR1_1" SITE "AB32"; #was "DQLR1_1_P" 173 +# LOCATE COMP "DQLR1_2" SITE "AE34"; #was "DQLR1_2_P" 177 +# LOCATE COMP "DQSLR1" SITE "AB26"; #was "DQSLR1_T" 181 +# LOCATE COMP "DQLR1_3" SITE "AD33"; #was "DQLR1_3_P" 185 +# LOCATE COMP "DQLR1_4" SITE "AF34"; #was "DQLR1_4_P" 189 +# +# +# LOCATE COMP "DQLL3_0" SITE "AE4"; #was "DQLL3_0_P" 2 +# LOCATE COMP "DQLL3_1" SITE "AB10"; #was "DQLL3_1_P" 6 +# LOCATE COMP "DQLL3_2" SITE "AE2"; #was "DQLL3_2_P" 10 +# LOCATE COMP "DQSLL3" SITE "AJ1"; #was "DQSLL3_T" 14 +# LOCATE COMP "DQLL3_3" SITE "AD4"; #was "DQLL3_3_P" 18 +# LOCATE COMP "DQLL3_4" SITE "AC9"; #was "DQLL3_4_P" 22 +# LOCATE COMP "DQLL1_0" SITE "Y2"; #was "DQLL1_0_P" 26 +# LOCATE COMP "DQLL1_1" SITE "W4"; #was "DQLL1_1_P" 30 +# LOCATE COMP "DQLL1_2" SITE "W2"; #was "DQLL1_2_P" 34 +# LOCATE COMP "DQSLL1" SITE "W6"; #was "DQSLL1_T" 38 +# LOCATE COMP "DQLL1_3" SITE "W8"; #was "DQLL1_3_P" 42 +# LOCATE COMP "DQLL1_4" SITE "Y8"; #was "DQLL1_4_P" 46 +# LOCATE COMP "DQUL2_0" SITE "F2"; #was "DQUL2_0_P" 50 +# LOCATE COMP "DQUL2_1" SITE "F3"; #was "DQUL2_1_P" 54 +# LOCATE COMP "DQUL2_2" SITE "G2"; #was "DQUL2_2_P" 58 +# LOCATE COMP "DQSUL2" SITE "G3"; #was "DQSUL2_T" 62 +# LOCATE COMP "DQUL2_3" SITE "H1"; #was "DQUL2_3_P" 66 +# LOCATE COMP "DQUL2_4" SITE "J3"; #was "DQUL2_4_P" 70 +# LOCATE COMP "DQUL0_0" SITE "L5"; #was "DQUL0_0_P" 74 +# LOCATE COMP "DQUL0_1" SITE "M4"; #was "DQUL0_1_P" 78 +# LOCATE COMP "DQUL0_2" SITE "K6"; #was "DQUL0_2_P" 82 +# LOCATE COMP "DQSUL0" SITE "N9"; #was "DQSUL0_T" 86 +# LOCATE COMP "DQUL0_3" SITE "M2"; #was "DQUL0_3_P" 90 +# LOCATE COMP "DQUL0_4" SITE "M7"; #was "DQUL0_4_P" 94 +# +# LOCATE COMP "DQUR1_0" SITE "N30"; #was "DQUR1_0_P" 106 +# LOCATE COMP "DQUR1_1" SITE "N26"; #was "DQUR1_1_P" 110 +# LOCATE COMP "DQUR1_2" SITE "N32"; #was "DQUR1_2_P" 114 +# LOCATE COMP "DQSUR1" SITE "N27"; #was "DQSUR1_T" 118 +# LOCATE COMP "DQUR1_3" SITE "N34"; #was "DQUR1_3_P" 122 +# LOCATE COMP "DQUR1_4" SITE "P28"; #was "DQUR1_4_P" 126 +# LOCATE COMP "DQUR2_0" SITE "T32"; #was "DQUR2_0_P" 130 +# LOCATE COMP "DQUR2_1" SITE "T26"; #was "DQUR2_1_P" 134 +# LOCATE COMP "DQUR2_2" SITE "U32"; #was "DQUR2_2_P" 138 +# LOCATE COMP "DQSUR2" SITE "T30"; #was "DQSUR2_T" 142 +# LOCATE COMP "DQUR2_3" SITE "T34"; #was "DQUR2_3_P" 146 +# LOCATE COMP "DQUR2_4" SITE "U26"; #was "DQUR2_4_P" 150 +# +# LOCATE COMP "DQLR2_0" SITE "W30"; #was "DQLR2_0_P" 170 +# LOCATE COMP "DQLR2_1" SITE "W27"; #was "DQLR2_1_P" 174 +# LOCATE COMP "DQLR2_2" SITE "W34"; #was "DQLR2_2_P" 178 +# LOCATE COMP "DQSLR2" SITE "Y30"; #was "DQSLR2_T" 182 +# LOCATE COMP "DQLR2_3" SITE "Y34"; #was "DQLR2_3_P" 186 +# LOCATE COMP "DQLR2_4" SITE "Y26"; #was "DQLR2_4_P" 190 +# +# DEFINE PORT GROUP "DQ_group" "DQ*" ; +# IOBUF GROUP "DQ_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + + + +################################################################# +# Pin-header IO +################################################################# +LOCATE COMP "HDR_IO_1" SITE "AP28"; +LOCATE COMP "HDR_IO_2" SITE "AN28"; +LOCATE COMP "HDR_IO_3" SITE "AP27"; +LOCATE COMP "HDR_IO_4" SITE "AN27"; +LOCATE COMP "HDR_IO_5" SITE "AM27"; +LOCATE COMP "HDR_IO_6" SITE "AL27"; +LOCATE COMP "HDR_IO_7" SITE "AH26"; +LOCATE COMP "HDR_IO_8" SITE "AG26"; +LOCATE COMP "HDR_IO_9" SITE "AM28"; +LOCATE COMP "HDR_IO_10" SITE "AL28"; +DEFINE PORT GROUP "HDR_group" "HDR*" ; +IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + +################################################################# +# KEL Connector +################################################################# +# # LOCATE COMP "KEL1_N" SITE "AP6"; +# # LOCATE COMP "KEL2_N" SITE "AP3"; +# # LOCATE COMP "KEL3_N" SITE "AN2"; +# # LOCATE COMP "KEL4_N" SITE "AM3"; +# # LOCATE COMP "KEL5_N" SITE "AM5"; +# # LOCATE COMP "KEL6_N" SITE "AN6"; +# # LOCATE COMP "KEL7_N" SITE "AM4"; +# # LOCATE COMP "KEL8_N" SITE "AJ6"; +# # LOCATE COMP "KEL9_N" SITE "AJ3"; +# # LOCATE COMP "KEL10_N" SITE "AK3"; +# # LOCATE COMP "KEL11_N" SITE "AD8"; +# # LOCATE COMP "KEL12_N" SITE "AK4"; +# # LOCATE COMP "KEL13_N" SITE "V3"; +# # LOCATE COMP "KEL14_N" SITE "W5"; +# # LOCATE COMP "KEL15_N" SITE "T8"; +# # LOCATE COMP "KEL16_N" SITE "T1"; +# # LOCATE COMP "KEL17_N" SITE "P6"; +# # LOCATE COMP "KEL18_N" SITE "T7"; +# # LOCATE COMP "KEL19_N" SITE "R1"; +# # LOCATE COMP "KEL20_N" SITE "P10"; +# # LOCATE COMP "KEL21_N" SITE "AP30"; +# # LOCATE COMP "KEL22_N" SITE "AP32"; +# # LOCATE COMP "KEL23_N" SITE "AN33"; +# # LOCATE COMP "KEL24_N" SITE "AN31"; +# # LOCATE COMP "KEL25_N" SITE "AM32"; +# # LOCATE COMP "KEL26_N" SITE "AN29"; +# # LOCATE COMP "KEL27_N" SITE "AM31"; +# # LOCATE COMP "KEL28_N" SITE "AM30"; +# # LOCATE COMP "KEL29_N" SITE "AL33"; +# # LOCATE COMP "KEL30_N" SITE "AK31"; +# # LOCATE COMP "KEL31_N" SITE "AJ33"; +# # LOCATE COMP "KEL32_N" SITE "AK32"; +# # LOCATE COMP "KEL33_N" SITE "AF31"; +# # LOCATE COMP "KEL34_N" SITE "AE31"; +# # LOCATE COMP "KEL35_N" SITE "AE29"; +# # LOCATE COMP "KEL36_N" SITE "AD25"; +# # LOCATE COMP "KEL37_N" SITE "L30"; +# # LOCATE COMP "KEL38_N" SITE "AB27"; +# # LOCATE COMP "KEL39_N" SITE "M33"; +# # LOCATE COMP "KEL40_N" SITE "M28"; +LOCATE COMP "KEL_1" SITE "AP5"; +LOCATE COMP "KEL_2" SITE "AP2"; +LOCATE COMP "KEL_3" SITE "AN1"; +LOCATE COMP "KEL_4" SITE "AN3"; +LOCATE COMP "KEL_5" SITE "AL5"; +LOCATE COMP "KEL_6" SITE "AM6"; +LOCATE COMP "KEL_7" SITE "AL4"; +LOCATE COMP "KEL_8" SITE "AJ5"; +LOCATE COMP "KEL_9" SITE "AJ2"; +LOCATE COMP "KEL_10" SITE "AL3"; +LOCATE COMP "KEL_11" SITE "AD9"; +LOCATE COMP "KEL_12" SITE "AJ4"; +LOCATE COMP "KEL_13" SITE "V4"; +LOCATE COMP "KEL_14" SITE "V5"; +LOCATE COMP "KEL_15" SITE "T9"; +LOCATE COMP "KEL_16" SITE "T2"; +LOCATE COMP "KEL_17" SITE "P7"; +LOCATE COMP "KEL_18" SITE "R8"; +LOCATE COMP "KEL_19" SITE "R2"; +LOCATE COMP "KEL_20" SITE "P9"; +LOCATE COMP "KEL_21" SITE "AP29"; +LOCATE COMP "KEL_22" SITE "AP33"; +LOCATE COMP "KEL_23" SITE "AN34"; +LOCATE COMP "KEL_24" SITE "AP31"; +LOCATE COMP "KEL_25" SITE "AN32"; +LOCATE COMP "KEL_26" SITE "AM29"; +LOCATE COMP "KEL_27" SITE "AL31"; +LOCATE COMP "KEL_28" SITE "AL30"; +LOCATE COMP "KEL_29" SITE "AL34"; +LOCATE COMP "KEL_30" SITE "AJ31"; +LOCATE COMP "KEL_31" SITE "AH33"; +LOCATE COMP "KEL_32" SITE "AL32"; +LOCATE COMP "KEL_33" SITE "AF32"; +LOCATE COMP "KEL_34" SITE "AE32"; +LOCATE COMP "KEL_35" SITE "AE30"; +LOCATE COMP "KEL_36" SITE "AD26"; +LOCATE COMP "KEL_37" SITE "M29"; +LOCATE COMP "KEL_38" SITE "AC28"; +LOCATE COMP "KEL_39" SITE "M34"; +LOCATE COMP "KEL_40" SITE "L28"; +DEFINE PORT GROUP "KEL_group" "KEL*" ; +IOBUF GROUP "KEL_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +################################################################# +# Many LED +################################################################# +LOCATE COMP "LED_RJ_GREEN_0" SITE "C25"; +LOCATE COMP "LED_RJ_RED_0" SITE "D25"; +LOCATE COMP "LED_GREEN" SITE "D24"; +LOCATE COMP "LED_ORANGE" SITE "E24"; +LOCATE COMP "LED_RED" SITE "K23"; +LOCATE COMP "LED_RJ_GREEN_1" SITE "G26"; +LOCATE COMP "LED_RJ_RED_1" SITE "G25"; +LOCATE COMP "LED_YELLOW" SITE "K24"; +IOBUF PORT "LED_RJ_GREEN_0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_GREEN" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_ORANGE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RED" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_GREEN_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_YELLOW" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "LED_SFP_GREEN_0" SITE "B4"; +LOCATE COMP "LED_SFP_GREEN_1" SITE "A6"; +LOCATE COMP "LED_SFP_RED_0" SITE "A3"; +LOCATE COMP "LED_SFP_RED_1" SITE "A8"; +DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ; +IOBUF GROUP "LED_SFP_group" IO_TYPE=LVTTL33 ; + +LOCATE COMP "LED_WHITE_0" SITE "A32"; +LOCATE COMP "LED_WHITE_1" SITE "A33"; +DEFINE PORT GROUP "LED_WHITE_group" "LED_WHITE*" ; +IOBUF GROUP "LED_WHITE_group" IO_TYPE=LVTTL33 ; + +################################################################# +# SFP Control Signals +################################################################# +LOCATE COMP "SFP_LOS_0" SITE "B6"; +LOCATE COMP "SFP_LOS_1" SITE "C9"; +LOCATE COMP "SFP_MOD0_0" SITE "A5"; +LOCATE COMP "SFP_MOD0_1" SITE "K11"; +LOCATE COMP "SFP_MOD1_0" SITE "B7"; +LOCATE COMP "SFP_MOD1_1" SITE "J11"; +LOCATE COMP "SFP_MOD2_0" SITE "A7"; +LOCATE COMP "SFP_MOD2_1" SITE "D9"; +# LOCATE COMP "SFP_RATE_SEL_0" SITE "A4"; +# LOCATE COMP "SFP_RATE_SEL_1" SITE "C8"; +LOCATE COMP "SFP_TX_DIS_0" SITE "D6"; +LOCATE COMP "SFP_TX_DIS_1" SITE "A9"; +# LOCATE COMP "SFP_TX_FAULT_0" SITE "C5"; +# LOCATE COMP "SFP_TX_FAULT_1" SITE "B8"; +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVTTL33 ; + + + +################################################################# +# Serdes Output Switch +################################################################# +LOCATE COMP "PCSSW_ENSMB" SITE "B3"; +LOCATE COMP "PCSSW_EQ_0" SITE "B1"; +LOCATE COMP "PCSSW_EQ_1" SITE "B2"; +LOCATE COMP "PCSSW_EQ_2" SITE "E4"; +LOCATE COMP "PCSSW_EQ_3" SITE "D4"; +LOCATE COMP "PCSSW_PE_0" SITE "C3"; +LOCATE COMP "PCSSW_PE_1" SITE "C4"; +LOCATE COMP "PCSSW_PE_2" SITE "D3"; +LOCATE COMP "PCSSW_PE_3" SITE "C2"; +LOCATE COMP "PCSSW_1" SITE "D5"; +LOCATE COMP "PCSSW_0" SITE "A2"; +LOCATE COMP "PCSSW_2" SITE "E13"; +LOCATE COMP "PCSSW_3" SITE "F13"; +LOCATE COMP "PCSSW_4" SITE "G13"; +LOCATE COMP "PCSSW_5" SITE "H14"; +LOCATE COMP "PCSSW_6" SITE "A13"; +LOCATE COMP "PCSSW_7" SITE "B13"; +DEFINE PORT GROUP "PCSSW_group" "PCSSW*" ; +IOBUF GROUP "PCSSW_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; + + +################################################################# +# ADC +################################################################# +LOCATE COMP "ADC_CLK" SITE "A14"; +LOCATE COMP "ADC_CS" SITE "B14"; +LOCATE COMP "ADC_DIN" SITE "G17"; +LOCATE COMP "ADC_DOUT" SITE "G16"; +IOBUF PORT "ADC_CLK" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_CS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_DIN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_DOUT" IO_TYPE=LVTTL33 PULLMODE=UP ; + + + +################################################################# +# RJ-45 connectors +################################################################# +LOCATE COMP "RJ_IO_0" SITE "R28"; +LOCATE COMP "RJ_IO_1" SITE "R31"; +LOCATE COMP "RJ_IO_2" SITE "R26"; +LOCATE COMP "RJ_IO_3" SITE "R34"; +#LOCATE COMP "RJ_IO_1_N" SITE "R27"; +#LOCATE COMP "RJ_IO_2_N" SITE "R30"; +#LOCATE COMP "RJ_IO_3_N" SITE "R25"; +#LOCATE COMP "RJ_IO_4_N" SITE "R33"; +IOBUF PORT "RJ_IO_0" IO_TYPE=LVDS25 ; +IOBUF PORT "RJ_IO_1" IO_TYPE=LVDS25 ; +IOBUF PORT "RJ_IO_2" IO_TYPE=LVDS25E ; +IOBUF PORT "RJ_IO_3" IO_TYPE=LVDS25E ; + + +LOCATE COMP "SPARE_IN_0" SITE "K31"; +LOCATE COMP "SPARE_IN_1" SITE "R4"; +#LOCATE COMP "SPARE_IN0_N" SITE "K32"; +#LOCATE COMP "SPARE_IN1_N" SITE "R3"; +IOBUF PORT "SPARE_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; +IOBUF PORT "SPARE_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; + + + +################################################################# +# Flash ROM and Reboot +################################################################# +LOCATE COMP "FLASH_CLK" SITE "F34"; #was "SPI_CLK" +LOCATE COMP "FLASH_CS" SITE "D34"; #was "SPI_CS" +LOCATE COMP "FLASH_IN" SITE "F33"; #was "SPI_IN" +LOCATE COMP "FLASH_OUT" SITE "F32"; #was "SPI_OUT" +LOCATE COMP "PROGRAMN" SITE "C31"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + +LOCATE COMP "ENPIRION_CLOCK" SITE "H23"; +IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "J13"; #was TEMP_OWB +IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Trigger I/O +################################################################# +LOCATE COMP "TEST_LINE_0" SITE "A19"; +LOCATE COMP "TEST_LINE_1" SITE "B19"; +LOCATE COMP "TEST_LINE_2" SITE "K20"; +LOCATE COMP "TEST_LINE_3" SITE "L19"; +LOCATE COMP "TEST_LINE_4" SITE "C19"; +LOCATE COMP "TEST_LINE_5" SITE "D19"; +LOCATE COMP "TEST_LINE_6" SITE "J19"; +LOCATE COMP "TEST_LINE_7" SITE "K19"; +LOCATE COMP "TEST_LINE_8" SITE "A20"; +LOCATE COMP "TEST_LINE_9" SITE "B20"; +LOCATE COMP "TEST_LINE_10" SITE "G20"; +LOCATE COMP "TEST_LINE_11" SITE "G21"; +LOCATE COMP "TEST_LINE_12" SITE "C20"; +LOCATE COMP "TEST_LINE_13" SITE "D20"; +LOCATE COMP "TEST_LINE_14" SITE "F21"; +LOCATE COMP "TEST_LINE_15" SITE "F22"; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; diff --git a/richSensors/code/magnetBoardParser.vhd b/richSensors/code/magnetBoardParser.vhd new file mode 100644 index 0000000..fd0d86b --- /dev/null +++ b/richSensors/code/magnetBoardParser.vhd @@ -0,0 +1,135 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity magnetBoardParser is + port( + INPUT : in std_logic_vector(7 downto 0); + CLK : in std_logic; + READY : in std_logic; + + SERIAL_NUMBER : out std_logic_vector(6 downto 0); + SENSOR_NUMBER : out std_logic_vector(1 downto 0); + AXIS_NUMBER : out std_logic_vector(1 downto 0); -- coding: 0 = T, 1 = X, 2 = Y, 3 = Z + VALUE : out unsigned(30 downto 0) + ); +end entity; + +architecture behavioral of magnetBoardParser is + type state_type is (idle, readInitSerialNumber, readSerialNumber, readSensorNumber, readAxis, readValue); + signal currentState : state_type := idle; + signal serialNumber : std_logic_vector(6 downto 0) := "0000000"; + signal serialNumber_tmp : std_logic_vector(13 downto 0) := "00000000000000"; + signal sensorNumber : std_logic_vector(1 downto 0) := "00"; + signal axis : std_logic_vector(1 downto 0) := "00"; -- 0 = T, 1 = X, 2 = Y, 3 = Z + signal sign : std_logic := '0'; + signal valueIntern : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal valueIntern_tmp: unsigned(61 downto 0) := b"00_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000"; + signal output_ID : std_logic_vector(31 downto 0) := x"00000000"; + signal output_value : std_logic_vector(31 downto 0) := x"00000000"; +begin + +-- process incoming string. It has the form M_03_2_X 123.456\r +PROC_PARSER : process begin + wait until rising_edge(CLK); + serialNumber <= serialNumber_tmp(6 downto 0); -- need temp value, because of size for multiplication + valueIntern <= valueIntern_tmp(30 downto 0); -- need temp value, because of size for multiplication + + if READY = '1' then -- only read when READY == 1 + case currentState is + when idle => + -- set all values back to 0 + serialNumber <= (others=>'0'); + sensorNumber <= (others=>'0'); + axis <= (others=>'0'); + valueIntern <= (others=>'0'); + sign <= '0'; + serialNumber_tmp <= (others=>'0'); + valueIntern_tmp <= (others=>'0'); + if INPUT = x"4D" then + -- Found char 'M'. Start parsing row and go to next state + currentState <= readInitSerialNumber; + end if; + when readInitSerialNumber => + if INPUT = x"5F" then + -- Found char '_'. + currentState <= readSerialNumber; + else + currentState <= idle; + end if; + when readSerialNumber => + if INPUT = x"5F" then + -- Found char '_'. Serial number is complete + currentState <= readSensorNumber; + elsif INPUT >= x"30" and INPUT <= x"39" then + -- Found figure (0-9). This is part of the serial number. + serialNumber_tmp <= std_logic_vector(unsigned(serialNumber) * 10 + unsigned(INPUT(3 downto 0))); + else + -- all other chars are invalid. go back to idle + currentState <= idle; + end if; + when readSensorNumber => + if INPUT = x"5F" then + -- Found char "_". Sensor number is complete. + currentState <= readAxis; + elsif INPUT >= x"30" and INPUT <= x"39" then + -- Found figure (0-9). This is part of the serial number. + sensorNumber <= INPUT(1 downto 0); + else + -- all other chars are invalid. go back to idle + currentState <= idle; + end if; + when readAxis => + if INPUT = x"20" then + -- Found char " ". Axis is complete. + currentState <= readValue; + elsif INPUT = x"54" then + -- Found char "T". + axis <= "00"; + elsif INPUT = x"58" then + -- Found char "X". + axis <= "01"; + elsif INPUT = x"59" then + -- Found char "Y". + axis <= "10"; + elsif INPUT = x"5A" then + -- Found char "Z". + axis <= "11"; + else + -- all other chars are invalid. go back to idle + currentState <= idle; + end if; + when readValue => + if INPUT = x"0D" or INPUT = x"0A" then + -- Found char "\r" or "\n". Value and complete line are complete. + currentState <= idle; -- back to idle + -- build complete value from sensor number, axis and value + output_value(31 downto 30) <= sensorNumber; + output_value(29 downto 28) <= axis; + output_value(27) <= sign; + output_value(26 downto 0) <= std_logic_vector(valueIntern(26 downto 0)); + output_ID(26 downto 20) <= serialNumber; + output_ID(9 downto 8) <= sensorNumber; + output_ID(1 downto 0) <= axis; + elsif INPUT >= x"30" and INPUT <= x"39" then + -- Found figure (0-9). This is part of the serial number. + valueIntern_tmp <= valueIntern * 10 + unsigned(INPUT(3 downto 0)); + elsif INPUT = x"2E" then + -- Found char "." ignore this char. + elsif INPUT = x"2D" then + -- Found char "-". save sign to variable + sign <= '1'; + else + -- all other chars are invalid. go back to idle. + currentState <= idle; + end if; + end case; + end if; +end process; + +SERIAL_NUMBER <= output_ID(26 downto 20); +SENSOR_NUMBER <= output_ID(9 downto 8); +AXIS_NUMBER <= output_ID(1 downto 0); +VALUE(27 downto 0) <= output_value(27 downto 0); + +end architecture behavioral; diff --git a/richSensors/code/magnetBoardParserHandler.vhd b/richSensors/code/magnetBoardParserHandler.vhd new file mode 100644 index 0000000..d5c2614 --- /dev/null +++ b/richSensors/code/magnetBoardParserHandler.vhd @@ -0,0 +1,140 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity magnetBoardParserHandler is + port( + INPUT : in std_logic_vector(7 downto 0); + CLK : in std_logic; + READY : in std_logic; + + SERIAL_NUMBER : out std_logic_vector(6 downto 0); + -- S for sensor (4 sensons on each board; bit-coded) + -- A for axis (Temperature, X, Y, Z; bit-coded) + VALUE_S00_A00 : out std_logic_vector(30 downto 0); + VALUE_S00_A01 : out std_logic_vector(30 downto 0); + VALUE_S00_A10 : out std_logic_vector(30 downto 0); + VALUE_S00_A11 : out std_logic_vector(30 downto 0); + VALUE_S01_A00 : out std_logic_vector(30 downto 0); + VALUE_S01_A01 : out std_logic_vector(30 downto 0); + VALUE_S01_A10 : out std_logic_vector(30 downto 0); + VALUE_S01_A11 : out std_logic_vector(30 downto 0); + VALUE_S10_A00 : out std_logic_vector(30 downto 0); + VALUE_S10_A01 : out std_logic_vector(30 downto 0); + VALUE_S10_A10 : out std_logic_vector(30 downto 0); + VALUE_S10_A11 : out std_logic_vector(30 downto 0); + VALUE_S11_A00 : out std_logic_vector(30 downto 0); + VALUE_S11_A01 : out std_logic_vector(30 downto 0); + VALUE_S11_A10 : out std_logic_vector(30 downto 0); + VALUE_S11_A11 : out std_logic_vector(30 downto 0); + ERROR_NO_DATA : out std_logic + ); +end entity; + +architecture behavioral of magnetBoardParserHandler is + -- signals for THE_MAGBOARD_PARSER + signal serialNumber : std_logic_vector(6 downto 0) := "0000000"; + signal sensorNumber : std_logic_vector(1 downto 0) := "00"; + signal axis : std_logic_vector(1 downto 0) := "00"; + signal value : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + -- signals for output result from THE_MAGBOARD_PARSER + -- sensor0 + signal value_00_00 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_00_01 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_00_10 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_00_11 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + -- sensor1 + signal value_01_00 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_01_01 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_01_10 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_01_11 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + -- sensor2 + signal value_10_00 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_10_01 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_10_10 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_10_11 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + -- sensor3 + signal value_11_00 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_11_01 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_11_10 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_11_11 : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + + -- signals for PROC_CHECK_ERROR + signal error : std_logic := '0'; + signal counter : unsigned(28 downto 0); + +begin + +-- do parsing in external file +THE_MAGBOARD_PARSER : entity work.magnetBoardParser + port map( + --in + INPUT => INPUT, + CLK => CLK, + READY => READY, + --out + SERIAL_NUMBER => serialNumber, + SENSOR_NUMBER => sensorNumber, + AXIS_NUMBER => axis, + VALUE => value + ); + +-- check if there is data to parse +PROC_CHECK_ERROR : process begin + wait until rising_edge(CLK); + if READY = '0' then + counter <= counter + 1; + else + error <= '0'; + counter <= (others => '0'); + end if; + if counter = 200000000 then + error <= '1'; + counter <= (others => '0'); + end if; +end process; + +--sort THE_MAGBOARD_PARSER values to signals, so they can be used in output +--sensor0 +value_00_00 <= value when sensorNumber = "00" and axis = "00"; +value_00_01 <= value when sensorNumber = "00" and axis = "01"; +value_00_10 <= value when sensorNumber = "00" and axis = "10"; +value_00_11 <= value when sensorNumber = "00" and axis = "11"; +--sensor1 +value_01_00 <= value when sensorNumber = "01" and axis = "00"; +value_01_01 <= value when sensorNumber = "01" and axis = "01"; +value_01_10 <= value when sensorNumber = "01" and axis = "10"; +value_01_11 <= value when sensorNumber = "01" and axis = "11"; +--sensor2 +value_10_00 <= value when sensorNumber = "10" and axis = "00"; +value_10_01 <= value when sensorNumber = "10" and axis = "01"; +value_10_10 <= value when sensorNumber = "10" and axis = "10"; +value_10_11 <= value when sensorNumber = "10" and axis = "11"; +--sensor3 +value_11_00 <= value when sensorNumber = "11" and axis = "00"; +value_11_01 <= value when sensorNumber = "11" and axis = "01"; +value_11_10 <= value when sensorNumber = "11" and axis = "10"; +value_11_11 <= value when sensorNumber = "11" and axis = "11"; + + +-- write signals to output pins. +SERIAL_NUMBER <= serialNumber; +VALUE_S00_A00 <= std_logic_vector(value_00_00); +VALUE_S00_A01 <= std_logic_vector(value_00_01); +VALUE_S00_A10 <= std_logic_vector(value_00_10); +VALUE_S00_A11 <= std_logic_vector(value_00_11); +VALUE_S01_A00 <= std_logic_vector(value_01_00); +VALUE_S01_A01 <= std_logic_vector(value_01_01); +VALUE_S01_A10 <= std_logic_vector(value_01_10); +VALUE_S01_A11 <= std_logic_vector(value_01_11); +VALUE_S10_A00 <= std_logic_vector(value_10_00); +VALUE_S10_A01 <= std_logic_vector(value_10_01); +VALUE_S10_A10 <= std_logic_vector(value_10_10); +VALUE_S10_A11 <= std_logic_vector(value_10_11); +VALUE_S11_A00 <= std_logic_vector(value_11_00); +VALUE_S11_A01 <= std_logic_vector(value_11_01); +VALUE_S11_A10 <= std_logic_vector(value_11_10); +VALUE_S11_A11 <= std_logic_vector(value_11_11); +ERROR_NO_DATA <= error; + +end architecture behavioral; diff --git a/richSensors/code/onewire_multi.vhd b/richSensors/code/onewire_multi.vhd new file mode 100644 index 0000000..51155ec --- /dev/null +++ b/richSensors/code/onewire_multi.vhd @@ -0,0 +1,561 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +USE IEEE.NUMERIC_STD.all; + + +library work; +use work.trb_net_std.all; + + +entity onewire_multi is + generic( + USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; + PARASITIC_MODE : integer range 0 to 1 := c_NO; + N_SENSORS : integer := 10; -- Number of connected sensors + CLK_PERIOD : integer := 10; --clk period in ns + ROM_ADR_0 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADR_1 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADR_2 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADR_3 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADR_4 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADR_5 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADR_6 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADR_7 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADR_8 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADR_9 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADR_10 : std_logic_vector(63 downto 0) := x"0000000000000000" + + ); + port( + CLK : in std_logic; + RESET : in std_logic; + READOUT_ENABLE_IN : in std_logic := '1'; + --connection to 1-wire interface + ONEWIRE : inout std_logic; + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT : out std_logic_vector(15 downto 0); + --ADDR_OUT : out std_logic_vector(2 downto 0); + --WRITE_OUT: out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + TEMP_OUT_1 : out std_logic_vector(11 downto 0) := "111111111111"; + TEMP_OUT_2 : out std_logic_vector(11 downto 0) := "111111111111"; + TEMP_OUT_3 : out std_logic_vector(11 downto 0) := "111111111111"; + TEMP_OUT_4 : out std_logic_vector(11 downto 0) := "111111111111"; + TEMP_OUT_5 : out std_logic_vector(11 downto 0) := "111111111111"; + TEMP_OUT_6 : out std_logic_vector(11 downto 0) := "111111111111"; + TEMP_OUT_7 : out std_logic_vector(11 downto 0) := "111111111111"; + TEMP_OUT_8 : out std_logic_vector(11 downto 0) := "111111111111"; + TEMP_OUT_9 : out std_logic_vector(11 downto 0) := "111111111111"; + TEMP_OUT_10 : out std_logic_vector(11 downto 0) := "111111111111"; + ID_OUT : out std_logic_vector(63 downto 0); + STAT : out std_logic_vector(31 downto 0); + SENS_CNT : out std_logic_vector( 7 downto 0) + ); +end entity; + + +architecture onewire_multi_arch of onewire_multi is + constant MAX_COUNTER : integer := 2**28-1; + type state_t is (START, IDLE, SEND_RESET, WAIT_AFTER_RESET, SEND_ROM_COMMAND, READ_WAIT, + WRITE_START, WRITE_WAIT, READ_BIT, READ_READ_ROM, SEND_CONV_TEMP, + READ_CONV_TEMP, SEND_READ_TEMP, READ_READ_TEMP,SEND_CURR_ROM); + signal state, next_state : state_t; + signal reset_i : std_logic; + signal state_bits : std_logic_vector(3 downto 0); + signal timecounter : integer range 0 to MAX_COUNTER; + signal bitcounter : integer range 0 to 127; + signal sensor_cnt : integer range 0 to 15; + signal inc_sensor_cnt : std_logic; + signal bitcounter_vector : std_logic_vector(6 downto 0); + signal inc_bitcounter, reset_bitcounter : std_logic; + signal output, next_output : std_logic; + signal input : std_logic; + signal reset_timecounter : std_logic; + signal send_bit, next_send_bit : std_logic; + signal recv_bit,next_recv_bit : std_logic; + signal recv_bit_ready, next_recv_bit_ready : std_logic; + signal output_tmp, next_output_tmp : std_logic; + signal word : std_logic_vector(15 downto 0); + signal ram_addr : std_logic_vector(2 downto 0) := "000"; + signal ram_wr : std_logic; + signal send_match_rom, next_send_match_rom : std_logic; + signal conv_temp, next_conv_temp : std_logic; + signal reading_temp, next_reading_temp : std_logic; + signal skip_rom, next_skip_rom : std_logic; + signal buf_TEMP_OUT : std_logic_vector(11 downto 0); + signal buf_STAT : std_logic; + signal strong_pullup, next_strong_pullup : std_logic; + signal rom_addr : std_logic_vector(63 downto 0); --:= x"52031646cd5fff28";--530416523728FF28 + signal rom_addr_0 : std_logic_vector(63 downto 0) := ROM_ADR_0;--x"530416523728FF28";--530416523728FF28 + signal rom_addr_1 : std_logic_vector(63 downto 0) := ROM_ADR_1;--x"BB04165233BFFF28"; + signal rom_addr_2 : std_logic_vector(63 downto 0) := ROM_ADR_2;--x"52031646CD5FFF28"; + signal rom_addr_3 : std_logic_vector(63 downto 0) := ROM_ADR_3;--x"EC0416525116FF28"; + signal rom_addr_4 : std_logic_vector(63 downto 0) := ROM_ADR_4;--x"050416523379FF28"; + signal rom_addr_5 : std_logic_vector(63 downto 0) := ROM_ADR_5;--x"E2041651AEA5FF28"; + signal rom_addr_6 : std_logic_vector(63 downto 0) := ROM_ADR_6;--x"940000092C3B2F28"; + signal rom_addr_7 : std_logic_vector(63 downto 0) := ROM_ADR_7;--x"4B0000092D22BD28"; + signal rom_addr_8 : std_logic_vector(63 downto 0) := ROM_ADR_8;--x"C30000092B07EA28"; + signal rom_addr_9 : std_logic_vector(63 downto 0) := ROM_ADR_9;--x"780000092A277628"; + signal rom_addr_10 : std_logic_vector(63 downto 0) := ROM_ADR_10; + + signal sending_rom, next_sending_rom : std_logic; +begin + + ONEWIRE <= '0' when output = '0' else '1' when strong_pullup = '1' else 'Z'; + input <= ONEWIRE; + reset_i <= RESET when rising_edge(CLK); + + bitcounter_vector <= conv_std_logic_vector(bitcounter,7); + + process(state, timecounter, bitcounter_vector, input, readout_enable_in, + send_bit, output_tmp, skip_rom, recv_bit, conv_temp, reading_temp) + begin + next_state <= state; + next_output <= '1'; + reset_timecounter <= '0'; + reset_bitcounter <= '0'; + next_output_tmp <= output_tmp; + inc_bitcounter <= '0'; + inc_sensor_cnt <= '0'; + next_send_bit <= send_bit; + next_recv_bit_ready <= '0'; + next_send_match_rom <= send_match_rom; + next_conv_temp <= conv_temp; + next_reading_temp <= reading_temp; + next_recv_bit <= recv_bit; + next_skip_rom <= skip_rom; + next_sending_rom <= sending_rom; + next_strong_pullup <= '0'; + case state is +--reset / presence + when START => + if READOUT_ENABLE_IN = '1' then + next_state <= IDLE; + reset_timecounter <= '1'; + end if; + when IDLE => + if is_time_reached(timecounter,640000,CLK_PERIOD) = '1' then + next_state <= SEND_RESET; + reset_timecounter <= '1'; + end if; + when SEND_RESET => + next_output <= '0'; + if is_time_reached(timecounter,640000,CLK_PERIOD) = '1' then + reset_timecounter <= '1'; + next_state <= WAIT_AFTER_RESET; + end if; + when WAIT_AFTER_RESET => + if is_time_reached(timecounter,640000,CLK_PERIOD) = '1' then --1200 + reset_timecounter <= '1'; + next_state <= SEND_ROM_COMMAND; + end if; + --presence is not checked +--sending rom commands + when SEND_ROM_COMMAND => + next_skip_rom <= not send_match_rom and not bitcounter_vector(3); + inc_bitcounter <= '1'; + next_state <= WRITE_START; + + if send_match_rom = '1' then + next_send_bit <= not bitcounter_vector(0); --this is x55, lsb first + else + next_send_bit <= bitcounter_vector(1); --this is xCC, lsb first + end if; + + if bitcounter_vector(3) = '1' then --send 8 bit + if send_match_rom = '1' then + next_sending_rom <= '1'; + next_state <= SEND_CURR_ROM; --jump to send of current ROM Address + elsif conv_temp = '1' then + next_state <= SEND_CONV_TEMP; + else + next_state <= SEND_READ_TEMP; + end if; + reset_bitcounter <= '1'; + end if; + +--sending of current ROM Address + when SEND_CURR_ROM => + if bitcounter < 64 then + next_send_bit <= rom_addr(bitcounter); + else + next_send_bit <= '0'; + end if; + + inc_bitcounter <= '1'; + if bitcounter_vector(6) = '1' then --send 64 bit + next_state <= SEND_READ_TEMP; + reset_bitcounter <= '1'; + reset_timecounter <= '1'; + next_recv_bit <= '0'; + next_sending_rom <= '0'; + next_send_match_rom <= '0'; --could be erased + next_conv_temp <= '0'; --could be erased + next_reading_temp <= '1'; + else + next_state <= WRITE_START; + end if; + +--sending sensor commands + when SEND_CONV_TEMP => + next_send_bit <= bitcounter_vector(1) and not bitcounter_vector(0); + --this is x44, lsb first + inc_bitcounter <= '1'; + if bitcounter_vector(3) = '1' then --send 8 bit + next_state <= READ_CONV_TEMP; + reset_bitcounter <= '1'; + reset_timecounter <= '1'; + next_recv_bit <= '0'; + else + next_state <= WRITE_START; + end if; + + when SEND_READ_TEMP => + if bitcounter_vector(2 downto 0) = "000" or bitcounter_vector(2 downto 0) = "110" then + next_send_bit <= '0'; --this is xBE, lsb first + else + next_send_bit <= '1'; + end if; + inc_bitcounter <= '1'; + if bitcounter_vector(3) = '1' then --send 8 bit + next_state <= READ_READ_TEMP; + reset_bitcounter <= '1'; + next_recv_bit <= '0'; + else + next_state <= WRITE_START; + end if; + +--reading rom answers + when READ_READ_ROM => + inc_bitcounter <= '1'; + if bitcounter_vector(6) = '1' then --read 64 bit + next_state <= IDLE; + if USE_TEMPERATURE_READOUT = 1 then + next_send_match_rom <= '1'; + next_conv_temp <= '1'; + end if; + reset_bitcounter <= '1'; + else + next_state <= READ_BIT; + end if; + +--reading sensor answers + when READ_CONV_TEMP => --waiting for end of conversion + if PARASITIC_MODE = c_YES then + next_strong_pullup <= '1'; + end if; + if is_time_reached(timecounter,130000000,CLK_PERIOD) = '1' then + next_state <= IDLE; + if USE_TEMPERATURE_READOUT = 1 then + next_conv_temp <= '0'; + --next_reading_temp <= '1'; + next_reading_temp <= '0'; + -- go to single sensor readout + next_send_match_rom <= '1'; + end if; + end if; + + + when READ_READ_TEMP => + inc_bitcounter <= '1'; + if bitcounter_vector(3 downto 2) = "11" then --read 12 bit + next_state <= START;-- when sensor_cnt = N_SENSORS else + --IDLE; + inc_sensor_cnt <= '1'; + if USE_TEMPERATURE_READOUT = 1 then + if sensor_cnt = (N_SENSORS-1) then + next_send_match_rom <= '0'; + next_conv_temp <= '1'; + else + next_send_match_rom <= '1'; + next_conv_temp <= '0'; + end if; + next_reading_temp <= '0'; + end if; + reset_bitcounter <= '1'; + else + next_state <= READ_BIT; + end if; + + +--write cycle + when WRITE_START => + next_output <= output_tmp; + if is_time_reached(timecounter,1200,CLK_PERIOD) = '1' then + next_output_tmp <= send_bit; + end if; + if is_time_reached(timecounter,80000,CLK_PERIOD) = '1' then + next_state <= WRITE_WAIT; + next_output_tmp <= '0'; + reset_timecounter <= '1'; + end if; + when WRITE_WAIT => + if is_time_reached(timecounter,1200,CLK_PERIOD) = '1' then + reset_timecounter <= '1'; + if sending_rom = '1' then + next_state <= SEND_CURR_ROM; + elsif skip_rom = '1' or send_match_rom = '1' then + next_state <= SEND_ROM_COMMAND; + elsif conv_temp = '1' then + next_state <= SEND_CONV_TEMP; + elsif reading_temp = '1' then + next_state <= SEND_READ_TEMP; + end if; + end if; + +--read cycle + when READ_BIT => + next_output <= output_tmp; + if is_time_reached(timecounter,1200,CLK_PERIOD) = '1' then + next_output_tmp <= '1'; + end if; + if is_time_reached(timecounter,10000,CLK_PERIOD) = '1' then + next_recv_bit <= input; + next_recv_bit_ready <= '1'; + next_state <= READ_WAIT; + end if; + when READ_WAIT => + if is_time_reached(timecounter,80000,CLK_PERIOD) = '1' then + reset_timecounter <= '1'; + next_output_tmp <= '0'; + --if send_rom = '1' then --todo + -- next_state <= READ_READ_ROM; + --els + if conv_temp = '1' then + next_state <= READ_CONV_TEMP; + else + next_state <= READ_READ_TEMP; + end if; + end if; + + when others => + next_state <= START; + end case; + end process; + +--counting time and bits + process(CLK) + begin + if rising_edge(CLK) then + if reset_timecounter = '1' then + timecounter <= 0; + else + timecounter <= timecounter + 1; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if reset_bitcounter = '1' then + bitcounter <= 0; + elsif inc_bitcounter = '1' then + bitcounter <= bitcounter + 1; + end if; + end if; + end process; + + + process(CLK) + begin + if rising_edge(CLK) then + if inc_sensor_cnt = '1' then + if sensor_cnt >= (N_SENSORS-1) then + sensor_cnt <= 0; + else + sensor_cnt <= sensor_cnt + 1; + end if; + end if; + + if sensor_cnt = 0 then + rom_addr <= rom_addr_0; + elsif sensor_cnt = 1 then + rom_addr <= rom_addr_1; + elsif sensor_cnt = 2 then + rom_addr <= rom_addr_2; + elsif sensor_cnt = 3 then + rom_addr <= rom_addr_3; + elsif sensor_cnt = 4 then + rom_addr <= rom_addr_4; + elsif sensor_cnt = 5 then + rom_addr <= rom_addr_5; + elsif sensor_cnt = 6 then + rom_addr <= rom_addr_6; + elsif sensor_cnt = 7 then + rom_addr <= rom_addr_7; + elsif sensor_cnt = 8 then + rom_addr <= rom_addr_8; + elsif sensor_cnt = 9 then + rom_addr <= rom_addr_9; + else + rom_addr <= x"0000000000000000"; + end if; + end if; + end process; + +--registers for state machine + process(CLK) + begin + if rising_edge(CLK) then + if reset_i = '1' then + send_bit <= '0'; + output_tmp <= '0'; + recv_bit <= '0'; + strong_pullup <= '0'; + state <= START; + sending_rom <= '0'; + else + recv_bit_ready <= next_recv_bit_ready; + state <= next_state; + send_bit <= next_send_bit; + output <= next_output; + output_tmp <= next_output_tmp; + recv_bit <= next_recv_bit; + strong_pullup <= next_strong_pullup; + sending_rom <= next_sending_rom; + end if; + end if; + end process; + +--save current kind of operation + gen_stat_sig : if USE_TEMPERATURE_READOUT = 1 generate + process(CLK) + begin + if rising_edge(CLK) then + if reset_i = '1' then + send_match_rom <= '0'; + conv_temp <= '1'; + reading_temp <= '0'; + skip_rom <= '1'; + else + send_match_rom <= next_send_match_rom; + conv_temp <= next_conv_temp; + reading_temp <= next_reading_temp; + skip_rom <= next_skip_rom; + end if; + end if; + end process; + end generate; + gen_stat_sig_1 : if USE_TEMPERATURE_READOUT = 0 generate + send_match_rom <= '0'; + conv_temp <= '0'; + reading_temp <= '0'; + skip_rom <= '0'; + end generate; + + +--saving received data + process(CLK) + begin + if rising_edge(CLK) then + if reset_i = '1' then + buf_TEMP_OUT <= (others => '0'); + ram_addr <= (others => '0'); + buf_STAT <= '0'; + word <= (others => '0'); + else + -- debug + ram_wr <= '0'; + -- END debug + if (recv_bit_ready = '1') and (reading_temp = '1') then + buf_STAT <= not buf_STAT; + -- debug + ram_addr(1 downto 0) <= (bitcounter_vector(5 downto 4))-1; + ram_addr(2) <= '0'; + -- END debug + word(14 downto 0) <= word(15 downto 1); + word(15) <= recv_bit; + -- debug + if bitcounter_vector(3 downto 0) = "0000" and send_match_rom = '1' then + ram_wr <= '1'; + end if; + -- END debug + if bitcounter_vector(3 downto 0) = "1100" and reading_temp = '1' then + buf_TEMP_OUT <= recv_bit & word(15 downto 5); --todo + if sensor_cnt = 0 then + TEMP_OUT <= recv_bit & word(15 downto 5); + elsif sensor_cnt = 1 then + TEMP_OUT_1 <= recv_bit & word(15 downto 5); + elsif sensor_cnt = 2 then + TEMP_OUT_2 <= recv_bit & word(15 downto 5); + elsif sensor_cnt = 3 then + TEMP_OUT_3 <= recv_bit & word(15 downto 5); + elsif sensor_cnt = 4 then + TEMP_OUT_4 <= recv_bit & word(15 downto 5); + elsif sensor_cnt = 5 then + TEMP_OUT_5 <= recv_bit & word(15 downto 5); + elsif sensor_cnt = 6 then + TEMP_OUT_6 <= recv_bit & word(15 downto 5); + elsif sensor_cnt = 7 then + TEMP_OUT_7 <= recv_bit & word(15 downto 5); + elsif sensor_cnt = 8 then + TEMP_OUT_8 <= recv_bit & word(15 downto 5); + elsif sensor_cnt = 9 then + TEMP_OUT_9 <= recv_bit & word(15 downto 5); + else + TEMP_OUT_10 <= recv_bit & word(15 downto 5); + end if; + + end if; + end if; + end if; + end if; + end process; + + --ADDR_OUT <= ram_addr; + DATA_OUT <= word; + --WRITE_OUT <= ram_wr; + + THE_TMP_OUT : process begin + wait until rising_edge(CLK); + + end process; + + PROC_STORE_ID : process begin + wait until rising_edge(CLK); + if ram_wr = '1' then + case ram_addr is + when "000" => ID_OUT(15 downto 0) <= word; + when "001" => ID_OUT(31 downto 16) <= word; + when "010" => ID_OUT(47 downto 32) <= word; + when "011" => ID_OUT(63 downto 48) <= word; + when others => null; + end case; + end if; + end process; + + state_bits <= x"0" when state = START else + x"1" when state = IDLE else + x"2" when state = SEND_RESET else + x"3" when state = WAIT_AFTER_RESET else + x"4" when state = SEND_ROM_COMMAND else + x"5" when state = READ_WAIT else + x"6" when state = WRITE_START else + x"7" when state = WRITE_WAIT else + x"8" when state = READ_BIT else + x"9" when state = SEND_CURR_ROM else + x"a" when state = SEND_CONV_TEMP else + x"b" when state = READ_CONV_TEMP else + x"c" when state = SEND_READ_TEMP else + x"d" when state = READ_READ_TEMP else + x"F"; + + + STAT(0) <= '0'; + STAT(1) <= '0' when input = '0' else '1'; + STAT(2) <= output; + STAT(3) <= send_match_rom; + STAT(4) <= skip_rom; + STAT(5) <= conv_temp; + STAT(6) <= reading_temp; + STAT(7) <= buf_STAT; + STAT(11 downto 8) <= bitcounter_vector(3 downto 0); + STAT(15 downto 12)<= state_bits; + STAT(16)<= next_strong_pullup; + STAT(31 downto 17) <= (others => '0'); + + SENS_CNT <= std_logic_vector(to_unsigned(sensor_cnt,8)); +end architecture; diff --git a/richSensors/code/onewire_record.vhd b/richSensors/code/onewire_record.vhd new file mode 100644 index 0000000..b85b692 --- /dev/null +++ b/richSensors/code/onewire_record.vhd @@ -0,0 +1,262 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + + +entity onewire_record is + generic( + N_SENSORS : integer := 10; -- Number of connected sensors + ROM_ADDR_0 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADDR_1 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADDR_2 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADDR_3 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADDR_4 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADDR_5 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADDR_6 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADDR_7 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADDR_8 : std_logic_vector(63 downto 0) := x"0000000000000000"; + ROM_ADDR_9 : std_logic_vector(63 downto 0) := x"0000000000000000" + ); + port( + CLK : in std_logic; + RESET : in std_logic; + READOUT_ENABLE_IN : in std_logic := '1'; + --connection to 1-wire interface + ONEWIRE : inout std_logic; + --Interlock + INTERLOCK_FLAG : out std_logic :='0'; + INTERLOCK_LIMIT : in std_logic_vector(31 downto 0) := x"000001F0"; + -- SLOW CONTROL + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); +end entity; + + +architecture onewire_record_arch of onewire_record is + +signal data : std_logic_vector(15 downto 0); +signal temperature_0, temperature_1, temperature_2, temperature_3, temperature_4, temperature_5, temperature_6, temperature_7, temperature_8, temperature_9, temperature_10 : std_logic_vector(11 downto 0) := "111111111111"; +signal ID_debug : std_logic_vector(63 downto 0); +signal statistic : std_logic_vector(31 downto 0); +signal sens_cnt : std_logic_vector(7 downto 0); + +signal interlock_flag_or_i : std_logic := '0'; +signal intlck_flag_i : std_logic_vector(10 downto 0) := b"00000000000"; +begin + + +THE_ONEWIRE : entity work.onewire_multi + generic map( + USE_TEMPERATURE_READOUT => 1, + PARASITIC_MODE => c_NO, + N_SENSORS => N_SENSORS, + CLK_PERIOD => 10, + ROM_ADR_0 => ROM_ADDR_0, + ROM_ADR_1 => ROM_ADDR_1, + ROM_ADR_2 => ROM_ADDR_2, + ROM_ADR_3 => ROM_ADDR_3, + ROM_ADR_4 => ROM_ADDR_4, + ROM_ADR_5 => ROM_ADDR_5, + ROM_ADR_6 => ROM_ADDR_6, + ROM_ADR_7 => ROM_ADDR_7, + ROM_ADR_8 => ROM_ADDR_8, + ROM_ADR_9 => ROM_ADDR_9 + ) + port map( + CLK => CLK, + RESET => RESET, + READOUT_ENABLE_IN => '1', + ONEWIRE => ONEWIRE, + DATA_OUT => data, + + TEMP_OUT => temperature_0, + TEMP_OUT_1 => temperature_1, + TEMP_OUT_2 => temperature_2, + TEMP_OUT_3 => temperature_3, + TEMP_OUT_4 => temperature_4, + TEMP_OUT_5 => temperature_5, + TEMP_OUT_6 => temperature_6, + TEMP_OUT_7 => temperature_7, + TEMP_OUT_8 => temperature_8, + TEMP_OUT_9 => temperature_9, + TEMP_OUT_10 => open, + ID_OUT => ID_debug, + STAT => statistic, + SENS_CNT => sens_cnt + ); + +--onewire_interface : entity work.trb_net_onewire +-- generic map( +-- USE_TEMPERATURE_READOUT => c_YES, +-- CLK_PERIOD => 10 +-- ) +-- port map( +-- CLK => CLK, +-- RESET => RESET, +-- --connection to 1-wire interface +-- ONEWIRE => ONEWIRE, +-- MONITOR_OUT => open, +-- --connection to id ram, according to memory map in TrbNetRegIO +-- DATA_OUT => data, +-- ADDR_OUT => open, +-- WRITE_OUT=> open, +-- TEMP_OUT => temperature, +-- ID_OUT => ID_debug, +-- STAT => statistic +-- ); + +THE_PROC_Handler : process begin + + wait until rising_edge(CLK); + BUS_TX.unknown <= '0'; + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.data <= (others => '0'); + + if BUS_RX.write = '1' then + if BUS_RX.addr(3 downto 0) = x"0" then + --clk_div <= to_integer(unsigned(BUS_RX.data)); + BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + elsif BUS_RX.read = '1' then + if BUS_RX.addr(3 downto 0) = x"0" then + BUS_TX.data(11 downto 0) <= temperature_0; + BUS_TX.data(31 downto 12) <= (others => '0'); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"1" then + BUS_TX.data(11 downto 0) <= temperature_1; + BUS_TX.data(31 downto 12) <= (others => '0'); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"2" then + BUS_TX.data(11 downto 0) <= temperature_2; + BUS_TX.data(31 downto 12) <= (others => '0'); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"3" then + BUS_TX.data(11 downto 0) <= temperature_3; + BUS_TX.data(31 downto 12) <= (others => '0'); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"4" then + BUS_TX.data(11 downto 0) <= temperature_4; + BUS_TX.data(31 downto 12) <= (others => '0'); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"5" then + BUS_TX.data(11 downto 0) <= temperature_5; + BUS_TX.data(31 downto 12) <= (others => '0'); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"6" then + BUS_TX.data(11 downto 0) <= temperature_6; + BUS_TX.data(31 downto 12) <= (others => '0'); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"7" then + BUS_TX.data(11 downto 0) <= temperature_7; + BUS_TX.data(31 downto 12) <= (others => '0'); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"8" then + BUS_TX.data(11 downto 0) <= temperature_8; + BUS_TX.data(31 downto 12) <= (others => '0'); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"9" then + BUS_TX.data(11 downto 0) <= temperature_9; + BUS_TX.data(31 downto 12) <= (others => '0'); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"A" then + BUS_TX.data <= ID_debug(63 downto 32); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"B" then + BUS_TX.data <= statistic; + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"C" then + BUS_TX.data(7 downto 0) <= sens_cnt; + BUS_TX.data(31 downto 8) <= (others => '0'); + BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + end if; + +end process; + + THE_INTERLOCK_HANDLER: process begin + + wait until rising_edge(CLK); + -- Interlock fires, if Sensor is connected, has power and is higher than the limit + if ((temperature_0 >= INTERLOCK_LIMIT) and (temperature_0(11 downto 0) /= x"FFF") and (temperature_0(11 downto 0) /= x"000") and (N_SENSORS >= 1)) then + intlck_flag_i(0) <= '1'; + else + intlck_flag_i(0) <= '0'; + end if; + + if ((temperature_1 >= INTERLOCK_LIMIT) and (temperature_1(11 downto 0) /= x"FFF") and (temperature_1(11 downto 0) /= x"000") and (N_SENSORS >= 2)) then + intlck_flag_i(1) <= '1'; + else + intlck_flag_i(1) <= '0'; + end if; + + if ((temperature_2 >= INTERLOCK_LIMIT) and (temperature_2(11 downto 0) /= x"FFF") and (temperature_2(11 downto 0) /= x"000") and (N_SENSORS >= 3)) then + intlck_flag_i(2) <= '1'; + else + intlck_flag_i(2) <= '0'; + end if; + + if ((temperature_3 >= INTERLOCK_LIMIT) and (temperature_3(11 downto 0) /= x"FFF") and (temperature_3(11 downto 0) /= x"000") and (N_SENSORS >= 4)) then + intlck_flag_i(3) <= '1'; + else + intlck_flag_i(3) <= '0'; + end if; + + if ((temperature_4 >= INTERLOCK_LIMIT) and (temperature_4(11 downto 0) /= x"FFF") and (temperature_4(11 downto 0) /= x"000") and (N_SENSORS >= 5)) then + intlck_flag_i(4) <= '1'; + else + intlck_flag_i(4) <= '0'; + end if; + + if ((temperature_5 >= INTERLOCK_LIMIT) and (temperature_5(11 downto 0) /= x"FFF") and (temperature_5(11 downto 0) /= x"000") and (N_SENSORS >= 6)) then + intlck_flag_i(5) <= '1'; + else + intlck_flag_i(5) <= '0'; + end if; + + if ((temperature_6 >= INTERLOCK_LIMIT) and (temperature_6(11 downto 0) /= x"FFF") and (temperature_6(11 downto 0) /= x"000") and (N_SENSORS >= 7)) then + intlck_flag_i(6) <= '1'; + else + intlck_flag_i(6) <= '0'; + end if; + + if ((temperature_7 >= INTERLOCK_LIMIT) and (temperature_7(11 downto 0) /= x"FFF") and (temperature_7(11 downto 0) /= x"000") and (N_SENSORS >= 8)) then + intlck_flag_i(7) <= '1'; + else + intlck_flag_i(7) <= '0'; + end if; + + if ((temperature_8 >= INTERLOCK_LIMIT) and (temperature_8(11 downto 0) /= x"FFF") and (temperature_8(11 downto 0) /= x"000") and (N_SENSORS >= 9)) then + intlck_flag_i(8) <= '1'; + else + intlck_flag_i(8) <= '0'; + end if; + + if ((temperature_9 >= INTERLOCK_LIMIT) and (temperature_9(11 downto 0) /= x"FFF") and (temperature_9(11 downto 0) /= x"000") and (N_SENSORS >= 10)) then + intlck_flag_i(9) <= '1'; + else + intlck_flag_i(9) <= '0'; + end if; + + if ((temperature_10 >= INTERLOCK_LIMIT) and (temperature_10(11 downto 0) /= x"FFF") and (temperature_10(11 downto 0) /= x"000") and (N_SENSORS >= 11)) then + intlck_flag_i(10) <= '1'; + else + intlck_flag_i(10) <= '0'; + end if; + + interlock_flag_or_i <= or_all(intlck_flag_i(N_SENSORS-1 downto 0)); + + +end process; + + INTERLOCK_FLAG <= interlock_flag_or_i; --high: INTERLOCK Active low: INTERLOCK Unactive +end architecture; \ No newline at end of file diff --git a/richSensors/code/uart.vhd_old b/richSensors/code/uart.vhd_old new file mode 100644 index 0000000..8acbc63 --- /dev/null +++ b/richSensors/code/uart.vhd_old @@ -0,0 +1,193 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.version.all; + +library machxo2; +use machxo2.all; + + +entity uart is + generic( + OUTPUTS : integer := 1 + ); + port( + CLK : in std_logic; + RESET : in std_logic; + UART_RX : in std_logic_vector(OUTPUTS-1 downto 0); + UART_TX : out std_logic_vector(OUTPUTS-1 downto 0); + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); +end entity; + + +architecture uart_arch of uart is + +signal rx_data : std_logic_vector(7 downto 0); +signal rx_ready : std_logic; +signal tx_send : std_logic; +signal tx_ready : std_logic; +signal out_sel : integer range 0 to OUTPUTS-1 := 0; +signal uart_sel_rx : std_logic; +signal uart_sel_tx : std_logic; + +signal clk_div : integer := 100000000/57600; + +signal tx_fifo_out : std_logic_vector(8 downto 0); +signal rx_fifo_out : std_logic_vector(8 downto 0); +signal tx_fifo_empty : std_logic; +signal tx_fifo_full : std_logic; +signal rx_fifo_empty : std_logic; +signal rx_fifo_full : std_logic; +signal rx_fifo_read : std_logic; +signal tx_fifo_read : std_logic; +signal tx_fifo_write : std_logic; + +signal next2_tx_send, next_tx_send : std_logic; +signal last2_rx_read, last_rx_read : std_logic; + +signal rx_debug : std_logic_vector(3 downto 0); +signal tx_debug : std_logic_vector(3 downto 0); + +begin + + +THE_RX : entity work.uart_rec + port map( + CLK_DIV => clk_div, + CLK => CLK, + RST => RESET, + RX => uart_sel_rx, + DATA_OUT => rx_data, + DATA_WAITING => rx_ready, + DEBUG => rx_debug + ); + +THE_TX : entity work.uart_trans + port map( + CLK_DIV => clk_div, + CLK => CLK, + RST => RESET, + DATA_IN => tx_fifo_out(7 downto 0), + SEND => tx_send, + READY => tx_ready, + TX => uart_sel_tx, + DEBUG => tx_debug + ); + + +THE_RX_FIFO : entity work.fifo_9x2k_oreg + port map( + Clock => CLK, + Data(7 downto 0) => rx_data, + Data(8) => '0', + WrEn => rx_ready, + RdEn => rx_fifo_read, + Reset => RESET, + Q => rx_fifo_out, + Empty => rx_fifo_empty, + Full => rx_fifo_full + ); + +THE_TX_FIFO : entity work.fifo_9x2k_oreg + port map( + Clock => CLK, + Data => BUS_RX.data(8 downto 0), + WrEn => tx_fifo_write, + RdEn => tx_fifo_read, + Reset => RESET, + Q => tx_fifo_out, + Empty => tx_fifo_empty, + Full => tx_fifo_full + ); + +PROC_REGS : process begin + wait until rising_edge(CLK); + BUS_TX.unknown <= '0'; + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.data <= (others => '0'); + + tx_fifo_write <= '0'; + rx_fifo_read <= '0'; + last_rx_read <= rx_fifo_read; + last2_rx_read <= last_rx_read; + + if last2_rx_read = '1' then + BUS_TX.data(8 downto 0) <= rx_fifo_out; + BUS_TX.ack <= '1'; + elsif BUS_RX.write = '1' then + if BUS_RX.addr(3 downto 0) = x"0" then + tx_fifo_write <= not tx_fifo_full; + BUS_TX.ack <= not tx_fifo_full; + BUS_TX.nack <= tx_fifo_full; + elsif BUS_RX.addr(3 downto 0) = x"1" then + clk_div <= to_integer(unsigned(BUS_RX.data)); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"2" then + out_sel <= to_integer(unsigned(BUS_RX.data(3 downto 0))); + BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + + elsif BUS_RX.read = '1' then + if BUS_RX.addr(3 downto 0) = x"0" then + rx_fifo_read <= not rx_fifo_empty; + BUS_TX.nack <= rx_fifo_empty; + elsif BUS_RX.addr(3 downto 0) = x"1" then + BUS_TX.data <= std_logic_vector(to_unsigned(clk_div,32)); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"2" then + BUS_TX.data(3 downto 0) <= std_logic_vector(to_unsigned(out_sel,4)); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"3" then + BUS_TX.data(0) <= rx_fifo_full; + BUS_TX.data(1) <= rx_fifo_empty; + BUS_TX.data(2) <= tx_fifo_full; + BUS_TX.data(3) <= tx_fifo_empty; + BUS_TX.data(7 downto 4) <= rx_debug; + BUS_TX.data(11 downto 8) <= tx_debug; + BUS_TX.data(12) <= next_tx_send; + BUS_TX.data(13) <= tx_fifo_read; + BUS_TX.data(14) <= uart_sel_tx; + BUS_TX.data(15) <= uart_sel_rx; + + BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + end if; + +end process; + +PROC_SEND : process begin + wait until rising_edge(CLK); + tx_fifo_read <= '0'; + next_tx_send <= '0'; + next2_tx_send <= next_tx_send; + tx_send <= next2_tx_send; + + if tx_fifo_empty = '0' and tx_ready = '1' and next_tx_send = '0' and next2_tx_send = '0' then + next_tx_send <= '1'; + tx_fifo_read <= '1'; + end if; + +end process; + +proc_io : process begin + wait until rising_edge(CLK); + UART_TX <= (others => '1'); + UART_TX(out_sel) <= uart_sel_tx; + uart_sel_rx <= UART_RX(out_sel); +end process; + + +end architecture; + + diff --git a/richSensors/code/uart_andre.vhd b/richSensors/code/uart_andre.vhd new file mode 100644 index 0000000..3496cb4 --- /dev/null +++ b/richSensors/code/uart_andre.vhd @@ -0,0 +1,313 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.version.all; + +library machxo2; +use machxo2.all; + + +entity uart is + generic( + OUTPUTS : integer := 1; + BAUD : integer := 19200--; + -- GENOPT : std_logic_vector(1 downto 0) := "01" --01: only RX, 10: only TX, 11 : RX and TX, 00: nothing + ); + port( + CLK : in std_logic; + RESET : in std_logic; -- reset all values + UART_RX : in std_logic_vector(OUTPUTS-1 downto 0); -- incoming data which needs to be processed + UART_TX : out std_logic_vector(OUTPUTS-1 downto 0); -- send data to board + + BUS_RX : in CTRLBUS_RX; -- what user is sending to FPGA + BUS_TX : out CTRLBUS_TX -- what FPGA is sending to user + ); +end entity; + + +architecture uart_arch of uart is + +type parserValue_array is array (OUTPUTS - 1 downto 0) of std_logic_vector(30 downto 0); +type serialNumber_array is array (OUTPUTS - 1 downto 0) of std_logic_vector(6 downto 0); +type rxData_array is array (OUTPUTS - 1 downto 0) of std_logic_vector(7 downto 0); + +signal rx_data : rxData_array; +signal rx_ready : std_logic_vector(OUTPUTS - 1 downto 0); +signal tx_send : std_logic; +signal tx_ready : std_logic; +signal out_sel : integer range 0 to OUTPUTS-1 := 0; +signal uart_sel_rx : std_logic; +signal uart_sel_tx : std_logic; + +signal clk_div : integer := 100000000/BAUD; + +--signal rx_fifo_out : std_logic_vector(8 downto 0); +--signal rx_fifo_empty : std_logic; +--signal rx_fifo_full : std_logic; +--signal rx_fifo_read : std_logic; +signal tx_fifo_out : std_logic_vector(8 downto 0); +signal tx_fifo_empty : std_logic; +signal tx_fifo_full : std_logic; +signal tx_fifo_read : std_logic; +signal tx_fifo_write : std_logic; + +signal next2_tx_send, next_tx_send : std_logic; +signal last2_rx_read, last_rx_read : std_logic; + +signal rx_debug : std_logic_vector(3 downto 0); +signal tx_debug : std_logic_vector(3 downto 0); + + +-- signals for output result from THE_PARSER_HANDLER +signal serialNumbers : serialNumber_array; +-- sensor0 +signal values_00_00 : parserValue_array; +signal values_00_01 : parserValue_array; +signal values_00_10 : parserValue_array; +signal values_00_11 : parserValue_array; +-- sensor1 +signal values_01_00 : parserValue_array; +signal values_01_01 : parserValue_array; +signal values_01_10 : parserValue_array; +signal values_01_11 : parserValue_array; +-- sensor2 +signal values_10_00 : parserValue_array; +signal values_10_01 : parserValue_array; +signal values_10_10 : parserValue_array; +signal values_10_11 : parserValue_array; +-- sensor3 +signal values_11_00 : parserValue_array; +signal values_11_01 : parserValue_array; +signal values_11_10 : parserValue_array; +signal values_11_11 : parserValue_array; + +begin + +--GEN_THE_PARSER_HANDLER_SEL: +--if GENOPT(0)="1" generate + GEN_THE_PARSER_HANDLER: + for i in 0 to OUTPUTS - 1 generate + THE_PARSER_HANDLER : entity work.magnetBoardParserHandler + port map( + --in + INPUT => rx_data(i), + CLK => CLK, + READY => rx_ready(i), + --out + SERIAL_NUMBER => serialNumbers(i), + VALUE_S00_A00 => values_00_00(i), + VALUE_S00_A01 => values_00_01(i), + VALUE_S00_A10 => values_00_10(i), + VALUE_S00_A11 => values_00_11(i), + VALUE_S01_A00 => values_01_00(i), + VALUE_S01_A01 => values_01_01(i), + VALUE_S01_A10 => values_01_10(i), + VALUE_S01_A11 => values_01_11(i), + VALUE_S10_A00 => values_10_00(i), + VALUE_S10_A01 => values_10_01(i), + VALUE_S10_A10 => values_10_10(i), + VALUE_S10_A11 => values_10_11(i), + VALUE_S11_A00 => values_11_00(i), + VALUE_S11_A01 => values_11_01(i), + VALUE_S11_A10 => values_11_10(i), + VALUE_S11_A11 => values_11_11(i) + ); + end generate GEN_THE_PARSER_HANDLER; +--end generate GEN_THE_PARSER_HANDLER_SEL; + + +THE_TX_FIFO : entity work.fifo_9x2k_oreg + port map( + Clock => CLK, + Data => BUS_RX.data(8 downto 0), + WrEn => tx_fifo_write, + RdEn => tx_fifo_read, + Reset => RESET, + Q => tx_fifo_out, + Empty => tx_fifo_empty, + Full => tx_fifo_full + ); + +GEN_THE_RX: +for i in 0 to OUTPUTS - 1 generate +-- transfer incoming signal (uart_sel_rx) in 8bit vector. +THE_RX : entity work.uart_rec + port map( + CLK_DIV => clk_div, + CLK => CLK, + RST => RESET, + RX => UART_RX(i), -- pass signale to sub entity (blackbox) + DATA_OUT => rx_data(i), -- return value + DATA_WAITING => rx_ready(i), -- return value + DEBUG => rx_debug -- return value + ); +end generate GEN_THE_RX; + +THE_TX : entity work.uart_trans + port map( + CLK_DIV => clk_div, + CLK => CLK, + RST => RESET, + DATA_IN => tx_fifo_out(7 downto 0), + SEND => tx_send, + READY => tx_ready, + TX => uart_sel_tx, + DEBUG => tx_debug + ); + + +PROC_REGS : process begin + wait until rising_edge(CLK); + BUS_TX.unknown <= '0'; + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.data <= (others => '0'); + + tx_fifo_write <= '0'; + --rx_fifo_read <= '0'; + --last_rx_read <= rx_fifo_read; + --last2_rx_read <= last_rx_read; + + --if last2_rx_read = '1' then + --BUS_TX.data(8 downto 0) <= rx_fifo_out; + --BUS_TX.ack <= '1'; + --els + if BUS_RX.write = '1' then + if BUS_RX.addr(3 downto 0) = x"0" then + tx_fifo_write <= not tx_fifo_full; + BUS_TX.ack <= not tx_fifo_full; + BUS_TX.nack <= tx_fifo_full; + elsif BUS_RX.addr(3 downto 0) = x"1" then + clk_div <= to_integer(unsigned(BUS_RX.data)); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"2" then + out_sel <= to_integer(unsigned(BUS_RX.data(3 downto 0))); + BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + + elsif BUS_RX.read = '1' then + --if BUS_RX.addr(3 downto 0) = x"0" then + --BUS_TX.data <= x"00000001"; + --rx_fifo_read <= not rx_fifo_empty; + --BUS_TX.nack <= rx_fifo_empty; + --els + for i in 0 to OUTPUTS - 1 loop + if BUS_RX.addr(7 downto 0) = x"00" then --clock + BUS_TX.data <= std_logic_vector(to_unsigned(clk_div,32)); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"01" then --serial number + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned(i + 1,8)) then --serial number + BUS_TX.data(6 downto 0) <= serialNumbers(i); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"10" then --sensor0, T Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16,8)) then --sensor0, T Value + BUS_TX.data(27 downto 0) <= values_00_00(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"11" then --sensor0, X Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 1,8)) then --sensor0, X Value + BUS_TX.data(27 downto 0) <= values_00_01(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"12" then --sensor0, Y Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 2,8)) then --sensor0, Y Value + BUS_TX.data(27 downto 0) <= values_00_10(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"13" then --sensor0, Z Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 3,8)) then --sensor0, Z Value + BUS_TX.data(27 downto 0) <= values_00_11(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"14" then --sensor1, T Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 4,8)) then --sensor1, T Value + BUS_TX.data(27 downto 0) <= values_01_00(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"15" then --sensor1, X Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 5,8)) then --sensor1, X Value + BUS_TX.data(27 downto 0) <= values_01_01(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"16" then --sensor1, Y Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 6,8)) then --sensor1, Y Value + BUS_TX.data(27 downto 0) <= values_01_10(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"17" then --sensor1, Z Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 7,8)) then --sensor1, Z Value + BUS_TX.data(27 downto 0) <= values_01_11(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"18" then --sensor2, T Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 8,8)) then --sensor2, T Value + BUS_TX.data(27 downto 0) <= values_10_00(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"19" then --sensor2, X Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 9,8)) then --sensor2, X Value + BUS_TX.data(27 downto 0) <= values_10_01(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"1A" then --sensor2, Y Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 10,8)) then --sensor2, Y Value + BUS_TX.data(27 downto 0) <= values_10_10(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"1B" then --sensor2, Z Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 11,8)) then --sensor2, Z Value + BUS_TX.data(27 downto 0) <= values_10_11(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"1C" then --sensor3, T Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 12,8)) then --sensor3, T Value + BUS_TX.data(27 downto 0) <= values_11_00(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"1D" then --sensor3, X Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 13,8)) then --sensor3, X Value + BUS_TX.data(27 downto 0) <= values_11_01(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"1E" then --sensor3, Y Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 14,8)) then --sensor3, Y Value + BUS_TX.data(27 downto 0) <= values_11_10(i)(27 downto 0); + BUS_TX.ack <= '1'; + --elsif BUS_RX.addr(7 downto 0) = x"1F" then --sensor3, Z Value + elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned((i + 1)*16 + 15,8)) then --sensor3, Z Value + BUS_TX.data(27 downto 0) <= values_11_11(i)(27 downto 0); + BUS_TX.ack <= '1'; + -- elsif BUS_RX.addr(3 downto 0) = x"5" then + -- BUS_TX.data(0) <= '0';--rx_fifo_full; + -- BUS_TX.data(1) <= '0';--rx_fifo_empty; + -- BUS_TX.data(2) <= tx_fifo_full; + -- BUS_TX.data(3) <= tx_fifo_empty; + -- BUS_TX.data(7 downto 4) <= rx_debug; + -- BUS_TX.data(11 downto 8) <= tx_debug; + -- BUS_TX.data(12) <= next_tx_send; + -- BUS_TX.data(13) <= tx_fifo_read; + -- BUS_TX.data(14) <= uart_sel_tx; + -- BUS_TX.data(15) <= uart_sel_rx; + + -- BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + end loop; + end if; +end process; + +PROC_SEND : process begin + wait until rising_edge(CLK); + tx_fifo_read <= '0'; + next_tx_send <= '0'; + next2_tx_send <= next_tx_send; + tx_send <= next2_tx_send; + + if tx_fifo_empty = '0' and tx_ready = '1' and next_tx_send = '0' and next2_tx_send = '0' then + next_tx_send <= '1'; + tx_fifo_read <= '1'; + end if; +end process; + +proc_io : process begin + wait until rising_edge(CLK); + UART_TX(0) <= '1';--(others => '1'); + --UART_TX(out_sel) <= uart_sel_tx; + --uart_sel_rx <= UART_RX(out_sel); +end process; + + +end architecture; + diff --git a/richSensors/code/uart_mag.vhd b/richSensors/code/uart_mag.vhd new file mode 100644 index 0000000..f516375 --- /dev/null +++ b/richSensors/code/uart_mag.vhd @@ -0,0 +1,367 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.version.all; + +library machxo2; +use machxo2.all; + + +entity uart_mag is + generic( + OUTPUTS : integer := 1; + BAUD : integer := 19200 + ); + port( + CLK : in std_logic; + RESET : in std_logic; -- reset all values + UART_RX : in std_logic_vector(OUTPUTS-1 downto 0); -- incoming data which needs to be processed + UART_TX : out std_logic_vector(OUTPUTS-1 downto 0); -- send data to board + + BUS_RX : in CTRLBUS_RX; -- what user is sending to FPGA + BUS_TX : out CTRLBUS_TX -- what FPGA is sending to user + ); +end entity; + + +architecture uart_arch of uart_mag is + +type parserValue_array is array (OUTPUTS - 1 downto 0) of std_logic_vector(30 downto 0); +type serialNumber_array is array (OUTPUTS - 1 downto 0) of std_logic_vector(6 downto 0); +type rxData_array is array (OUTPUTS - 1 downto 0) of std_logic_vector(7 downto 0); + +signal rx_data : rxData_array; +signal rx_ready : std_logic_vector(OUTPUTS - 1 downto 0); +signal tx_send : std_logic; +signal tx_ready : std_logic; +signal out_sel : integer range 0 to OUTPUTS - 1 := 0; +signal uart_sel_rx : std_logic; +signal uart_sel_tx : std_logic; + +signal clk_div : integer := 100000000/BAUD; + +signal tx_fifo_out : std_logic_vector(8 downto 0); +signal tx_fifo_empty : std_logic; +signal tx_fifo_full : std_logic; +signal tx_fifo_read : std_logic; +signal tx_fifo_write : std_logic; + +signal next2_tx_send, next_tx_send : std_logic; +signal last2_rx_read, last_rx_read : std_logic; + +signal rx_debug : std_logic_vector(3 downto 0); +signal tx_debug : std_logic_vector(3 downto 0); + + +-- signals for output result from THE_PARSER_HANDLER +signal parser_error : std_logic_vector(OUTPUTS- 1 downto 0); +signal serialNumbers : serialNumber_array; +-- sensor0 +signal values_00_00 : parserValue_array; +signal values_00_01 : parserValue_array; +signal values_00_10 : parserValue_array; +signal values_00_11 : parserValue_array; +-- sensor1 +signal values_01_00 : parserValue_array; +signal values_01_01 : parserValue_array; +signal values_01_10 : parserValue_array; +signal values_01_11 : parserValue_array; +-- sensor2 +signal values_10_00 : parserValue_array; +signal values_10_01 : parserValue_array; +signal values_10_10 : parserValue_array; +signal values_10_11 : parserValue_array; +-- sensor3 +signal values_11_00 : parserValue_array; +signal values_11_01 : parserValue_array; +signal values_11_10 : parserValue_array; +signal values_11_11 : parserValue_array; + +--signal i,j : integer; + +begin + +GEN_THE_PARSER_HANDLER: +for i in 0 to OUTPUTS - 1 generate +THE_PARSER_HANDLER : entity work.magnetBoardParserHandler + port map( + --in + INPUT => rx_data(i), + CLK => CLK, + READY => rx_ready(i), + --out + SERIAL_NUMBER => serialNumbers(i), + VALUE_S00_A00 => values_00_00(i), + VALUE_S00_A01 => values_00_01(i), + VALUE_S00_A10 => values_00_10(i), + VALUE_S00_A11 => values_00_11(i), + VALUE_S01_A00 => values_01_00(i), + VALUE_S01_A01 => values_01_01(i), + VALUE_S01_A10 => values_01_10(i), + VALUE_S01_A11 => values_01_11(i), + VALUE_S10_A00 => values_10_00(i), + VALUE_S10_A01 => values_10_01(i), + VALUE_S10_A10 => values_10_10(i), + VALUE_S10_A11 => values_10_11(i), + VALUE_S11_A00 => values_11_00(i), + VALUE_S11_A01 => values_11_01(i), + VALUE_S11_A10 => values_11_10(i), + VALUE_S11_A11 => values_11_11(i), + ERROR_NO_DATA => parser_error(i) + ); +end generate GEN_THE_PARSER_HANDLER; + + + +THE_TX_FIFO : entity work.fifo_9x2k_oreg + port map( + Clock => CLK, + Data => BUS_RX.data(8 downto 0), + WrEn => tx_fifo_write, + RdEn => tx_fifo_read, + Reset => RESET, + Q => tx_fifo_out, + Empty => tx_fifo_empty, + Full => tx_fifo_full + ); + +GEN_THE_RX: +for i in 0 to OUTPUTS - 1 generate +-- transfer incoming signal (uart_sel_rx) in 8bit vector. +THE_RX : entity work.uart_rec + port map( + CLK_DIV => clk_div, + CLK => CLK, + RST => RESET, + RX => UART_RX(i), -- pass signale to sub entity (blackbox) + DATA_OUT => rx_data(i), -- return value + DATA_WAITING => rx_ready(i), -- return value + DEBUG => rx_debug -- return value + ); +end generate GEN_THE_RX; + +THE_TX : entity work.uart_trans + port map( + CLK_DIV => clk_div, + CLK => CLK, + RST => RESET, + DATA_IN => tx_fifo_out(7 downto 0), + SEND => tx_send, + READY => tx_ready, + TX => uart_sel_tx, + DEBUG => tx_debug + ); + + +PROC_REGS : process + variable i,j : integer := 0; +begin + wait until rising_edge(CLK); + BUS_TX.unknown <= '0'; + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.data <= (others => '0'); + + tx_fifo_write <= '0'; + --rx_fifo_read <= '0'; + --last_rx_read <= rx_fifo_read; + --last2_rx_read <= last_rx_read; + + --if last2_rx_read = '1' then + --BUS_TX.data(8 downto 0) <= rx_fifo_out; + --BUS_TX.ack <= '1'; + --els + if BUS_RX.write = '1' then + if BUS_RX.addr(3 downto 0) = x"0" then + tx_fifo_write <= not tx_fifo_full; + BUS_TX.ack <= not tx_fifo_full; + BUS_TX.nack <= tx_fifo_full; + elsif BUS_RX.addr(3 downto 0) = x"1" then + clk_div <= to_integer(unsigned(BUS_RX.data)); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"2" then + out_sel <= to_integer(unsigned(BUS_RX.data(3 downto 0))); + BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + + elsif BUS_RX.read = '1' then + + i := to_integer(unsigned(BUS_RX.addr(7 downto 4))); + j := to_integer(unsigned(BUS_RX.addr(3 downto 0))); + if i <= OUTPUTS then + BUS_TX.unknown <= '0'; + BUS_TX.ack <= '1'; + if i = 0 then + if j = 0 then + --clock + BUS_TX.data <= std_logic_vector(to_unsigned(clk_div,32)); + elsif j <= OUTPUTS then + --serial number of boards and potential error + BUS_TX.data(6 downto 0) <= serialNumbers(j - 1); + BUS_TX.data(8) <= parser_error(j - 1); + else + BUS_TX.unknown <= '1'; BUS_TX.ack <= '0'; + end if; + else + case BUS_RX.addr(3 downto 0) is + -- sensor0: T, X, Y, Z + when x"0" => BUS_TX.data(27 downto 0) <= values_00_00(i-1)(27 downto 0); + when x"1" => BUS_TX.data(27 downto 0) <= values_00_01(i-1)(27 downto 0); + when x"2" => BUS_TX.data(27 downto 0) <= values_00_10(i-1)(27 downto 0); + when x"3" => BUS_TX.data(27 downto 0) <= values_00_11(i-1)(27 downto 0); + -- sensor1: T, X, Y, Z + when x"4" => BUS_TX.data(27 downto 0) <= values_01_00(i-1)(27 downto 0); + when x"5" => BUS_TX.data(27 downto 0) <= values_01_01(i-1)(27 downto 0); + when x"6" => BUS_TX.data(27 downto 0) <= values_01_10(i-1)(27 downto 0); + when x"7" => BUS_TX.data(27 downto 0) <= values_01_11(i-1)(27 downto 0); + -- sensor2: T, X, Y, Z + when x"8" => BUS_TX.data(27 downto 0) <= values_10_00(i-1)(27 downto 0); + when x"9" => BUS_TX.data(27 downto 0) <= values_10_01(i-1)(27 downto 0); + when x"A" => BUS_TX.data(27 downto 0) <= values_10_10(i-1)(27 downto 0); + when x"B" => BUS_TX.data(27 downto 0) <= values_10_11(i-1)(27 downto 0); + -- sensor3: T, X, Y, Z + when x"C" => BUS_TX.data(27 downto 0) <= values_11_00(i-1)(27 downto 0); + when x"D" => BUS_TX.data(27 downto 0) <= values_11_01(i-1)(27 downto 0); + when x"E" => BUS_TX.data(27 downto 0) <= values_11_10(i-1)(27 downto 0); + when x"F" => BUS_TX.data(27 downto 0) <= values_11_11(i-1)(27 downto 0); + + when others => BUS_TX.unknown <= '1'; BUS_TX.ack <= '0'; + end case; + end if; + else + BUS_TX.unknown <= '1'; + end if; + end if; +end process; + + +-- elsif BUS_RX.read = '1' then +-- --if BUS_RX.addr(3 downto 0) = x"0" then +-- --BUS_TX.data <= x"00000001"; +-- --rx_fifo_read <= not rx_fifo_empty; +-- --BUS_TX.nack <= rx_fifo_empty; +-- --els +-- for i in 0 to OUTPUTS - 1 loop +-- if BUS_RX.addr(7 downto 0) = x"00" then --clock +-- BUS_TX.data <= std_logic_vector(to_unsigned(clk_div,32)); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 0) = std_logic_vector(to_unsigned(i + 1,8)) then +-- --serial number on port x"0i" +-- BUS_TX.data(8) <= parser_error(i); +-- BUS_TX.data(6 downto 0) <= serialNumbers(i); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"0" then +-- --sensor0, T Value on port x"i0" +-- BUS_TX.data(27 downto 0) <= values_00_00(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"1" then +-- --sensor0, X Value on port x"i1" +-- BUS_TX.data(27 downto 0) <= values_00_01(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"2" then +-- --sensor0, Y Value on port x"i2" +-- BUS_TX.data(27 downto 0) <= values_00_10(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"3" then +-- --sensor0, Z Value on port x"i3" +-- BUS_TX.data(27 downto 0) <= values_00_11(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"4" then +-- --sensor1, T Value on port x"i4" +-- BUS_TX.data(27 downto 0) <= values_01_00(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"5" then +-- --sensor1, X Value on port x"i5" +-- BUS_TX.data(27 downto 0) <= values_01_01(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"6" then +-- --sensor1, Y Value on port x"i6" +-- BUS_TX.data(27 downto 0) <= values_01_10(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"7" then +-- --sensor1, Z Value on port x"i7" +-- BUS_TX.data(27 downto 0) <= values_01_11(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"8" then +-- --sensor2, T Value on port x"i8" +-- BUS_TX.data(27 downto 0) <= values_10_00(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"9" then +-- --sensor2, X Value on port x"i9" +-- BUS_TX.data(27 downto 0) <= values_10_01(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"A" then +-- --sensor2, Y Value on port x"iA" +-- BUS_TX.data(27 downto 0) <= values_10_10(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"B" then +-- --sensor2, Z Value on port x"iB" +-- BUS_TX.data(27 downto 0) <= values_10_11(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"C" then +-- --sensor3, T Value on port x"iC" +-- BUS_TX.data(27 downto 0) <= values_11_00(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"D" then +-- --sensor3, X Value on port x"iD" +-- BUS_TX.data(27 downto 0) <= values_11_01(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"E" then +-- --sensor3, Y Value on port x"iE" +-- BUS_TX.data(27 downto 0) <= values_11_10(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- elsif BUS_RX.addr(7 downto 4) = std_logic_vector(to_unsigned((i + 1),4)) +-- and BUS_RX.addr(3 downto 0) = x"F" then +-- --sensor3, Z Value on port x"iF" +-- BUS_TX.data(27 downto 0) <= values_11_11(i)(27 downto 0); +-- BUS_TX.ack <= '1'; +-- else +-- BUS_TX.unknown <= '1'; +-- end if; +-- end loop; +-- end if; +-- end process; + +PROC_SEND : process begin + wait until rising_edge(CLK); + tx_fifo_read <= '0'; + next_tx_send <= '0'; + next2_tx_send <= next_tx_send; + tx_send <= next2_tx_send; + + if tx_fifo_empty = '0' and tx_ready = '1' and next_tx_send = '0' and next2_tx_send = '0' then + next_tx_send <= '1'; + tx_fifo_read <= '1'; + end if; +end process; + +proc_io : process begin + wait until rising_edge(CLK); + UART_TX(0) <= '1';--(others => '1'); + --UART_TX(out_sel) <= uart_sel_tx; + --uart_sel_rx <= UART_RX(out_sel); +end process; + + +end architecture; + diff --git a/richSensors/code/uart_orig.vhd b/richSensors/code/uart_orig.vhd new file mode 100644 index 0000000..0953117 --- /dev/null +++ b/richSensors/code/uart_orig.vhd @@ -0,0 +1,238 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.version.all; + +library machxo2; +use machxo2.all; + + +entity uart is + generic( + OUTPUTS : integer := 1 + ); + port( + CLK : in std_logic; + RESET : in std_logic; -- Setze alle Werte zurück + UART_RX : in std_logic_vector(OUTPUTS-1 downto 0); -- Daten die ankommen und bearbeitet werden müssen + UART_TX : out std_logic_vector(OUTPUTS-1 downto 0); -- Daten an Board schicken + + BUS_RX : in CTRLBUS_RX; -- Was User an FPGA schickt + BUS_TX : out CTRLBUS_TX -- Was FPGA an User schickt + ); +end entity; + + +architecture uart_arch of uart is + +signal rx_data : std_logic_vector(7 downto 0); +signal rx_ready : std_logic; +signal tx_send : std_logic; +signal tx_ready : std_logic; +signal out_sel : integer range 0 to OUTPUTS-1 := 0; +signal uart_sel_rx : std_logic; +signal uart_sel_tx : std_logic; + +signal clk_div : integer := 100000000/19200; + +--signal rx_fifo_out : std_logic_vector(8 downto 0); +--signal rx_fifo_empty : std_logic; +--signal rx_fifo_full : std_logic; +--signal rx_fifo_read : std_logic; +signal tx_fifo_out : std_logic_vector(8 downto 0); +signal tx_fifo_empty : std_logic; +signal tx_fifo_full : std_logic; +signal tx_fifo_read : std_logic; +signal tx_fifo_write : std_logic; + +signal next2_tx_send, next_tx_send : std_logic; +signal last2_rx_read, last_rx_read : std_logic; + +signal rx_debug : std_logic_vector(3 downto 0); +signal tx_debug : std_logic_vector(3 downto 0); + +-- Signale für Parser +type state_type is (lookForStart, readInitSerialNumber, readSerialNumber, readSensorNumber, readAxis, readValue); +signal currentState : state_type := lookForStart; +signal serialNumber : std_logic_vector(6 downto 0) := "0000000"; +signal serialNumber_tmp : std_logic_vector(13 downto 0) := "00000000000000"; +signal sensorNumber : std_logic_vector(3 downto 0) := "0000"; +signal sensorNumber_tmp : std_logic_vector(7 downto 0) := x"00"; +signal axis : std_logic_vector(1 downto 0) := "00"; -- 0 = T, 1 = X, 2 = Y, 3 = Z +signal value : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; +signal value_tmp : unsigned(61 downto 0); +signal output_ID : std_logic_vector(31 downto 0) := x"00000000"; +signal output_value : std_logic_vector(31 downto 0) := x"00000000"; +signal sign : std_logic; + +signal rx_ready_cnt : unsigned(31 downto 0) := x"00000001"; +signal rx_data_debug : std_logic_vector(7 downto 0); + +signal switch_cnt : unsigned( 4 downto 0) := "00000"; +signal tx_fifo_in : std_logic_vector(8 downto 0); +signal switch_pwr : std_logic_vector(11 downto 0):= x"000"; +signal switch_use : std_logic := '0'; + +signal manual_send : std_logic_vector(7 downto 0); +signal manual_tx_fifo_write,tx_fifo_write_FIFO : std_logic; +signal debug_sig : std_logic_vector(39 downto 0):=x"0000000000"; + +begin + + +THE_TX_FIFO : entity work.fifo_9x2k_oreg + port map( + Clock => CLK, + Data => tx_fifo_in,--BUS_RX.data(8 downto 0), + WrEn => tx_fifo_write_FIFO,--tx_fifo_write, + RdEn => tx_fifo_read, + Reset => RESET, + Q => tx_fifo_out, + Empty => tx_fifo_empty, + Full => tx_fifo_full + ); + +THE_TX : entity work.uart_trans + port map( + CLK_DIV => clk_div, + CLK => CLK, + RST => RESET, + DATA_IN => tx_fifo_out(7 downto 0), + SEND => tx_send, + READY => tx_ready, + TX => UART_TX(0),--uart_sel_tx, + DEBUG => tx_debug + ); + + +PROC_SWITCH_PWR : process begin + wait until rising_edge(CLK); + + tx_fifo_in(8) <= '0'; + --tx_fifo_in(7 downto 0) <= x"00"; + tx_fifo_write <= '0'; + tx_fifo_write_FIFO <= tx_fifo_write; + if manual_tx_fifo_write = '1' then + tx_fifo_in(7 downto 0) <= manual_send;--BUS_RX.data(7 downto 0); + tx_fifo_write <= '1'; + else + if switch_use = '1' and switch_cnt = 0 then + switch_cnt <= 1; + else + if switch_cnt > 0 then + case switch_cnt is + when 1 => tx_fifo_in(7 downto 0) <= x"53"; -- S + tx_fifo_write <= '1'; + switch_cnt <= switch_cnt + 1; + debug_sig(39 downto 32) <= x"53"; + + when 2 => tx_fifo_in(7 downto 0) <= x"30"; --& switch_pwr(11 downto 8); -- ch_0 + tx_fifo_write <= '1'; + switch_cnt <= switch_cnt + 1; + debug_sig(31 downto 24) <= x"30"; + + when 3 => tx_fifo_in(7 downto 0) <= x"33";-- & switch_pwr(7 downto 4); -- ch_1 + tx_fifo_write <= '1'; + switch_cnt <= switch_cnt + 1; + debug_sig(23 downto 16) <= x"33"; + + when 4 => tx_fifo_in(7 downto 0) <= x"31";-- & switch_pwr(3 downto 0); -- off|on|toggle + tx_fifo_write <= '1'; + switch_cnt <= switch_cnt + 1; + debug_sig(15 downto 8) <= x"31"; + + when 5 => tx_fifo_in(7 downto 0) <= x"0A"; -- \n + tx_fifo_write <= '1'; + switch_cnt <= 0; + debug_sig(7 downto 0) <= x"0A"; + + end case; + + end if; + end if; + end if; +end process; + + +PROC_REGS : process begin + wait until rising_edge(CLK); + BUS_TX.unknown <= '0'; + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.data <= (others => '0'); + switch_use <= '0'; + manual_tx_fifo_write <= '0'; + + if BUS_RX.write = '1' then + if BUS_RX.addr(3 downto 0) = x"0" then + --tx_fifo_write <= not tx_fifo_full; + --BUS_TX.ack <= not tx_fifo_full; + --BUS_TX.nack <= tx_fifo_full; + manual_send <= BUS_RX.data(7 downto 0); + manual_tx_fifo_write <= not tx_fifo_full; + BUS_TX.ack <= not tx_fifo_full; + BUS_TX.nack <= tx_fifo_full; + elsif BUS_RX.addr(3 downto 0) = x"1" then + clk_div <= to_integer(unsigned(BUS_RX.data)); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"2" then + out_sel <= to_integer(unsigned(BUS_RX.data(3 downto 0))); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"3" then + switch_pwr <= BUS_RX.data(11 downto 0); + switch_use <= '1'; + BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + + elsif BUS_RX.read = '1' then + --if BUS_RX.addr(3 downto 0) = x"0" then + --BUS_TX.data <= x"00000001"; + --rx_fifo_read <= not rx_fifo_empty; + --BUS_TX.nack <= rx_fifo_empty; + --els + if BUS_RX.addr(3 downto 0) = x"0" then + BUS_TX.data <= std_logic_vector(to_unsigned(clk_div,32)); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"1" then + BUS_TX.data(31 downto 0) <= std_logic_vector(rx_ready_cnt); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"2" then + BUS_TX.data <= debug_sig(31 downto 0); --Wert von 31-0 + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"3" then + BUS_TX.data(7 downto 0) <= debug_sig(39 downto 32); --Wert von 31-0 + BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + end if; + +end process; + +PROC_SEND : process begin + wait until rising_edge(CLK); + tx_fifo_read <= '0'; + next_tx_send <= '0'; + next2_tx_send <= next_tx_send; + tx_send <= next2_tx_send; + + if tx_fifo_empty = '0' and tx_ready = '1' and next_tx_send = '0' and next2_tx_send = '0' then + next_tx_send <= '1'; + tx_fifo_read <= '1'; + end if; + +end process; + + + +end architecture; + + + + + diff --git a/richSensors/code/uart_relais.vhd b/richSensors/code/uart_relais.vhd new file mode 100644 index 0000000..bc92ca1 --- /dev/null +++ b/richSensors/code/uart_relais.vhd @@ -0,0 +1,230 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.version.all; + +library machxo2; +use machxo2.all; + + +entity uart_relais is + generic( + OUTPUTS : integer := 1; + BAUD : integer := 19200 + ); + port( + CLK : in std_logic; + RESET : in std_logic; -- Setze alle Werte zurück + UART_TX : out std_logic_vector(OUTPUTS-1 downto 0); -- Daten an Board schicken + + BUS_RX : in CTRLBUS_RX; -- Was User an FPGA schickt + BUS_TX : out CTRLBUS_TX -- Was FPGA an User schickt + ); +end entity; + + +architecture uart_arch of uart_relais is + +signal rx_data : std_logic_vector(7 downto 0); +signal rx_ready : std_logic; +signal tx_send : std_logic; +signal tx_ready : std_logic; +signal out_sel : integer range 0 to OUTPUTS-1 := 0; +signal uart_sel_rx : std_logic; +signal uart_sel_tx : std_logic; + +signal clk_div : integer := 100000000/BAUD; + +--signal rx_fifo_out : std_logic_vector(8 downto 0); +--signal rx_fifo_empty : std_logic; +--signal rx_fifo_full : std_logic; +--signal rx_fifo_read : std_logic; +signal tx_fifo_out : std_logic_vector(8 downto 0); +signal tx_fifo_empty : std_logic; +signal tx_fifo_full : std_logic; +signal tx_fifo_read : std_logic; +signal tx_fifo_write : std_logic; + +signal next2_tx_send, next_tx_send : std_logic; +signal last2_rx_read, last_rx_read : std_logic; +signal tx_debug : std_logic_vector(3 downto 0); + +signal switch_cnt : unsigned( 4 downto 0) := "00000"; +signal tx_fifo_in : std_logic_vector(8 downto 0); +signal switch_pwr : std_logic_vector(11 downto 0):= x"000"; +signal switch_use : std_logic := '0'; + +signal manual_send : std_logic_vector(7 downto 0); +signal manual_tx_fifo_write,tx_fifo_write_FIFO : std_logic; +signal debug_sig : std_logic_vector(39 downto 0):=x"0000000000"; +signal time_cnt : unsigned(3 downto 0); + +begin + + +THE_TX_FIFO : entity work.fifo_9x2k_oreg + port map( + Clock => CLK, + Data => tx_fifo_in,--BUS_RX.data(8 downto 0), + WrEn => tx_fifo_write_FIFO,--tx_fifo_write, + RdEn => tx_fifo_read, + Reset => RESET, + Q => tx_fifo_out, + Empty => tx_fifo_empty, + Full => tx_fifo_full + ); + +THE_TX : entity work.uart_trans + port map( + CLK_DIV => clk_div, + CLK => CLK, + RST => RESET, + DATA_IN => tx_fifo_out(7 downto 0), + SEND => tx_send, + READY => tx_ready, + TX => UART_TX(0),--uart_sel_tx, + DEBUG => tx_debug + ); + + +PROC_SWITCH_PWR : process begin + wait until rising_edge(CLK); + + tx_fifo_in(8) <= '0'; + --tx_fifo_in(7 downto 0) <= x"00"; + tx_fifo_write <= '0'; + tx_fifo_write_FIFO <= tx_fifo_write; + if manual_tx_fifo_write = '1' then + tx_fifo_in(7 downto 0) <= manual_send;--BUS_RX.data(7 downto 0); + tx_fifo_write <= '1'; + else + if switch_use = '1' and switch_cnt = 0 then + switch_cnt <= 1; + else + if switch_cnt > 0 then + case switch_cnt is + when 1 => tx_fifo_in(7 downto 0) <= x"53"; -- S + if time_cnt = 3 then tx_fifo_write <= '1'; end if; + if time_cnt = 7 then switch_cnt <= switch_cnt + 1; end if; + debug_sig(39 downto 32) <= x"53"; + + when 2 => tx_fifo_in(7 downto 0) <= x"30"; --& switch_pwr(11 downto 8); -- ch_0 + if time_cnt = 3 then tx_fifo_write <= '1'; end if; + if time_cnt = 7 then switch_cnt <= switch_cnt + 1; end if; + debug_sig(31 downto 24) <= x"30"; + + when 3 => tx_fifo_in(7 downto 0) <= x"33";-- & switch_pwr(7 downto 4); -- ch_1 + if time_cnt = 3 then tx_fifo_write <= '1'; end if; + if time_cnt = 7 then switch_cnt <= switch_cnt + 1; end if; + debug_sig(23 downto 16) <= x"33"; + + when 4 => tx_fifo_in(7 downto 0) <= x"31";-- & switch_pwr(3 downto 0); -- off|on|toggle + if time_cnt = 3 then tx_fifo_write <= '1'; end if; + if time_cnt = 7 then switch_cnt <= switch_cnt + 1; end if; + debug_sig(15 downto 8) <= x"31"; + + when 5 => tx_fifo_in(7 downto 0) <= x"0A"; -- \n + if time_cnt = 3 then tx_fifo_write <= '1'; end if; + if time_cnt = 7 then switch_cnt <= 0; end if; + debug_sig(7 downto 0) <= x"0A"; + + when others => tx_fifo_write <= '0'; + switch_cnt <= 0; + + end case; + + end if; + end if; + end if; +end process; + + +PROC_REGS : process begin + wait until rising_edge(CLK); + BUS_TX.unknown <= '0'; + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.data <= (others => '0'); + switch_use <= '0'; + manual_tx_fifo_write <= '0'; + + if BUS_RX.write = '1' then + if BUS_RX.addr(3 downto 0) = x"0" then + --tx_fifo_write <= not tx_fifo_full; + --BUS_TX.ack <= not tx_fifo_full; + --BUS_TX.nack <= tx_fifo_full; + manual_send <= BUS_RX.data(7 downto 0); + manual_tx_fifo_write <= not tx_fifo_full; + BUS_TX.ack <= not tx_fifo_full; + BUS_TX.nack <= tx_fifo_full; + elsif BUS_RX.addr(3 downto 0) = x"1" then + clk_div <= to_integer(unsigned(BUS_RX.data)); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"2" then + out_sel <= to_integer(unsigned(BUS_RX.data(3 downto 0))); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"3" then + switch_pwr <= BUS_RX.data(11 downto 0); + switch_use <= '1'; + BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + + elsif BUS_RX.read = '1' then + --if BUS_RX.addr(3 downto 0) = x"0" then + --BUS_TX.data <= x"00000001"; + --rx_fifo_read <= not rx_fifo_empty; + --BUS_TX.nack <= rx_fifo_empty; + --els + if BUS_RX.addr(3 downto 0) = x"0" then + BUS_TX.data <= std_logic_vector(to_unsigned(clk_div,32)); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"1" then + BUS_TX.data <= debug_sig(31 downto 0); --Wert von 31-0 + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(3 downto 0) = x"2" then + BUS_TX.data(7 downto 0) <= debug_sig(39 downto 32); --Wert von 31-0 + BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + end if; + +end process; + +PROC_SEND : process begin + wait until rising_edge(CLK); + tx_fifo_read <= '0'; + next_tx_send <= '0'; + next2_tx_send <= next_tx_send; + tx_send <= next2_tx_send; + + if tx_fifo_empty = '0' and tx_ready = '1' and next_tx_send = '0' and next2_tx_send = '0' then + next_tx_send <= '1'; + tx_fifo_read <= '1'; + end if; + +end process; + + +PROC_CNT : process begin + wait until rising_edge(CLk); + if time_cnt = 7 then + time_cnt <= 0; + else + time_cnt <= time_cnt + 1; + end if; + +end process; + + +end architecture; + + + + + diff --git a/richSensors/compile.pl b/richSensors/compile.pl new file mode 120000 index 0000000..4456748 --- /dev/null +++ b/richSensors/compile.pl @@ -0,0 +1 @@ +../scripts/compile.pl \ No newline at end of file diff --git a/richSensors/config.vhd b/richSensors/config.vhd new file mode 100644 index 0000000..ddd5981 --- /dev/null +++ b/richSensors/config.vhd @@ -0,0 +1,110 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 + + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + constant USE_200MHZOSCILLATOR : integer := c_YES; + constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3D0"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"60"; + +--set to 0 for backplane serdes, set to 3 for front SFP serdes + constant SERDES_NUM : integer := 3; + + constant INCLUDE_UART : integer := c_NO; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_LCD : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 2; + constant MONITOR_INPUT_NUM : integer := 32; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := ( + x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch + x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + + x"54", x"72", x"62", x"33", x"73", x"63", x"0a", + x"0a", + x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a", + x"55", x"49", x"44", x"20", x"20", x"89", x"88", x"87", x"86", x"0a", + x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", + x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", + x"54", x"65", x"6d", x"70", x"65", x"72", x"61", x"74", x"75", x"72", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"85", x"0a", + others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"95000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 + t(28 downto 28) := std_logic_vector(to_unsigned(3-SERDES_NUM,1)); + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/richSensors/config_compile_frankfurt.pl b/richSensors/config_compile_frankfurt.pl new file mode 100644 index 0000000..9de99d5 --- /dev/null +++ b/richSensors/config_compile_frankfurt.pl @@ -0,0 +1,20 @@ +TOPNAME => "trb3sc_basic", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/d/jspc29/lattice/diamond/3.8_x64', +synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/', +#synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", +# synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", + +nodelist_file => 'nodelist_frankfurt.txt', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, + diff --git a/richSensors/config_compile_gsi.pl b/richSensors/config_compile_gsi.pl new file mode 100644 index 0000000..f907498 --- /dev/null +++ b/richSensors/config_compile_gsi.pl @@ -0,0 +1,14 @@ +TOPNAME => "trb3sc_richSensor", +lm_license_file_for_synplify => "27000\@lxcad03.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.4_x64/', +synplify_path => '/opt/synplicity/J-2014.09-SP2', +#synplify_command => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options", +synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", + +nodelist_file => 'nodes_gsi_template.txt', + +firefox_open => 0, + + +pinout_file => 'trb3sc_richSensor', diff --git a/richSensors/par.p2t b/richSensors/par.p2t new file mode 100644 index 0000000..cb0ad8d --- /dev/null +++ b/richSensors/par.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 26 +-c 1 +-e 2 +#-g guidefile.ncd +#-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 diff --git a/richSensors/synplify.fdc b/richSensors/synplify.fdc new file mode 100644 index 0000000..1a8f9d8 --- /dev/null +++ b/richSensors/synplify.fdc @@ -0,0 +1,51 @@ +###==== BEGIN Header + +# Synopsys, Inc. constraint file +# /d/jspc22/trb/git/trb3sc/template/synplify.fdc +# Written on Thu Jun 18 11:51:05 2015 +# by Synplify Pro, I-2014.03L-SP1 FDC Constraint Editor + +# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. +# These sections are generated from SCOPE spreadsheet tabs. + +###==== END Header + +###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit) +###==== END Collections + +###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) +create_clock -name {clk240} {p:CLK_CORE_PCLK} -period {4.16} +create_clock -name {clksys} {n:THE_CLOCK_RESET.SYS_CLK_OUT} -period {10} +create_clock -name {clktxfull} {n:THE_MEDIA_INTERFACE.gen_pcs3\.THE_SERDES.tx_full_clk_ch3} -period {5} +create_clock -name {clkrxfull} {n:THE_MEDIA_INTERFACE.gen_pcs3\.THE_SERDES.rx_full_clk_ch3} -period {5} +create_clock -name {clkintfull} {n:THE_CLOCK_RESET.gen_norecov_clock\.gen_200\.THE_INT_PLL.CLKOP} -period {5} + +###==== END Clocks + +###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) +###==== END "Generated Clocks" + +###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit) +###==== END Inputs/Outputs + + +###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) +###==== END "Delay Paths" + +###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) +###==== END Attributes + +###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit) +###==== END "I/O Standards" + +###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit) +###==== END "Compile Points" + + + + + + + + + diff --git a/richSensors/trb3sc_richSensor.lpf b/richSensors/trb3sc_richSensor.lpf new file mode 100644 index 0000000..82eb127 --- /dev/null +++ b/richSensors/trb3sc_richSensor.lpf @@ -0,0 +1,7 @@ + +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CLKNET clk_sys 5x; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CELL "THE_TDC/*Channe*/Channel200/RingBuffer*FIFO/*" 5x; + +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x; +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x; + diff --git a/richSensors/trb3sc_richSensor.prj b/richSensors/trb3sc_richSensor.prj new file mode 100644 index 0000000..50a2c49 --- /dev/null +++ b/richSensors/trb3sc_richSensor.prj @@ -0,0 +1,197 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN1156C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3sc_richSensor" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3sc_richSensor.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd" +add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd" +add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "./code/uart_mag.vhd" + +add_file -vhdl -lib work "code/uart_relais.vhd" +add_file -vhdl -lib work "code/magnetBoardParser.vhd" +add_file -vhdl -lib work "code/magnetBoardParserHandler.vhd" +add_file -vhdl -lib work "code/onewire_multi.vhd" +add_file -vhdl -lib work "code/onewire_record.vhd" + + +add_file -vhdl -lib work "./trb3sc_richSensor.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/richSensors/trb3sc_richSensor.vhd b/richSensors/trb3sc_richSensor.vhd new file mode 100644 index 0000000..d5d9a82 --- /dev/null +++ b/richSensors/trb3sc_richSensor.vhd @@ -0,0 +1,666 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.trb_net16_hub_func.all; +use work.version.all; +use work.trb_net_gbe_components.all; +use work.med_sync_define.all; + +entity trb3sc_richSensor is + port( + CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE + CLK_CORE_PCLK : in std_logic; --Main Oscillator + CLK_EXT_PLL_LEFT : in std_logic; --External Clock + --CLK_SUPPL_PLL_LEFT : in std_logic; --not used + --CLK_SUPPL_PLL_RIGHT : in std_logic; --not used + --CLK_CORE_PLL_LEFT : in std_logic; --not used + --CLK_CORE_PLL_RIGHT : in std_logic; --not used + --CLK_EXT_PCLK : in std_logic; --not used + --CLK_EXT_PLL_RIGHT : in std_logic; --not used + + TRIG_LEFT : in std_logic; --Trigger Input + --TRIG_PLL : in std_logic; --not used + --TRIG_RIGHT : in std_logic; --not used + + --Backplane, all lines +-- BACK_GPIO : inout std_logic_vector(15 downto 0); + BACK_LVDS : inout std_logic_vector( 1 downto 0); + BACK_3V3 : inout std_logic_vector( 3 downto 0); + --Backplane for slaves on trbv3scbp1 + BACK_GPIO : inout std_logic_vector(3 downto 0); + + --AddOn Connector + --to be added + INP : in std_logic_vector(7 downto 0); + OUTP : out std_logic_vector(1 downto 0); + ONEWIRE : inout std_logic_vector(1 downto 0); + + --KEL Connector + KEL : inout std_logic_vector(40 downto 1); + + --Additional IO + HDR_IO : inout std_logic_vector(10 downto 1); + RJ_IO : inout std_logic_vector( 3 downto 0); + SPARE_IN : in std_logic_vector( 1 downto 0); + + --LED + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector( 1 downto 0); + LED_RJ_RED : out std_logic_vector( 1 downto 0); + LED_WHITE : out std_logic_vector( 1 downto 0); + LED_SFP_GREEN : out std_logic_vector( 1 downto 0); + LED_SFP_RED : out std_logic_vector( 1 downto 0); + + --SFP + SFP_LOS : in std_logic_vector( 1 downto 0); + SFP_MOD0 : in std_logic_vector( 1 downto 0); + SFP_MOD1 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0'); + + --Serdes switch + PCSSW_ENSMB : out std_logic; + PCSSW_EQ : out std_logic_vector( 3 downto 0); + PCSSW_PE : out std_logic_vector( 3 downto 0); + PCSSW : out std_logic_vector( 7 downto 0); + + --ADC + ADC_CLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; + + --Flash, 1-wire, Reload + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + PROGRAMN : out std_logic; + ENPIRION_CLOCK : out std_logic; + TEMPSENS : inout std_logic; + + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0); + + --INTERLOCK + INTERLOCK_OUT : out std_logic; + INTERLOCK_GND_OUT : out std_logic + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + + attribute syn_useioff of INP : signal is false; + attribute syn_useioff of OUTP : signal is false; + attribute syn_useioff of ONEWIRE : signal is false; + + + --Serdes: Backplane + --Backplane A2,A3,A0,A1 Slave 3,4,1,2, A0: TrbNet from backplane + --AddOn C2,C3,C0,C1,B0,B1,B2,D1(B3) Slave --,--,5,9,8,7,6,-- + --SFP D0,B3(D1) D0: GbE, B3: TrbNet + + +end entity; + +architecture trb3sc_arch of trb3sc_richSensor is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + + signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal led : std_logic_vector(1 downto 0); + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + + --READOUT + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, busrdo_rx, bus_master_out, busparser_rx, busrelais_rx, businterlock_rx : CTRLBUS_RX; + signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, busrdo_tx, bus_master_in , busparser_tx, busrelais_tx, businterlock_tx : CTRLBUS_TX; + + signal busonewire_rx : ctrlbus_rx_array_t(1 downto 0); + signal busonewire_tx : ctrlbus_tx_array_t(1 downto 0); + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + + signal timer : TIMERS; + signal lcd_data : std_logic_vector(511 downto 0); + + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + type a_t is array(1 to 16) of std_logic_vector(6000 downto 0); + signal c : a_t; + attribute syn_keep of c : signal is true; + attribute syn_preserve of c : signal is true; + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + attribute syn_keep of bussci_rx : signal is true; + attribute syn_preserve of bussci_rx : signal is true; + attribute syn_keep of bustools_rx : signal is true; + attribute syn_preserve of bustools_rx : signal is true; + attribute syn_keep of bustc_rx : signal is true; + attribute syn_preserve of bustc_rx : signal is true; + + type state_t is (IDLE, WRITE, FINISH, BUSYEND); + signal state : state_t; + signal data_counter, data_amount : unsigned(15 downto 0) := (others => '0'); + + signal interlock_flag_i : std_logic_vector(1 downto 0) := "00"; + signal interlock_output : std_logic; + signal interlock_limit_i : std_logic_vector(31 downto 0):= x"000001F0"; + +begin + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- +THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + INT_CLK_IN => CLK_CORE_PCLK, + EXT_CLK_IN => CLK_EXT_PLL_LEFT, + NET_CLK_FULL_IN => med2int(0).clk_full, + NET_CLK_HALF_IN => med2int(0).clk_half, + RESET_FROM_NET => med2int(0).stat_op(13), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + FULL_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + REF_CLK_OUT => clk_full_osc, + + ENPIRION_CLOCK => ENPIRION_CLOCK, + LED_RED_OUT => LED_RJ_RED, + LED_GREEN_OUT => LED_RJ_GREEN, + DEBUG_OUT => debug_clock_reset + ); + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync + generic map( + SERDES_NUM => SERDES_NUM, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + SFP_TX_DIS(0) <= '1'; + gen_sfp_con : if SERDES_NUM = 3 generate + sfp_los_i <= SFP_LOS(1); + sfp_prsnt_i <= SFP_MOD0(1); + SFP_TX_DIS(1) <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- +THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**8 + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => TRIG_LEFT, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => TEMPSENS, + --Timing registers + TIMERS_OUT => timer + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 9, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"e100", 5 => x"e110", 6 => x"e000", 7 => x"e200", 8 => x"e120", others => x"0000"), + PORT_ADDR_MASK => (0 => 12 , 1 => 9 , 2 => 1 , 3 => 12 , 4 => 4 , 5 => 4 , 6 => 8 , 7 => 4 , 8 => 4 , others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busrdo_rx, --User config + BUS_RX(4) => busonewire_rx(0), + BUS_RX(5) => busonewire_rx(1), + BUS_RX(6) => busparser_rx, + BUS_RX(7) => busrelais_rx, + BUS_RX(8) => businterlock_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busrdo_tx, + BUS_TX(4) => busonewire_tx(0), + BUS_TX(5) => busonewire_tx(1), + BUS_TX(6) => busparser_tx, + BUS_TX(7) => busrelais_tx, + BUS_TX(8) => businterlock_tx, + + STAT_DEBUG => open + ); + + +--------------------------------------------------------------------------- +-- OneWire TempSensor DS18b20 +--------------------------------------------------------------------------- + THE_ONEWIRE : entity work.onewire_record + generic map( + N_SENSORS => 10, -- Number of connected sensors + ROM_ADDR_0 => x"530416523728FF28", + ROM_ADDR_1 => x"BB04165233BFFF28", + ROM_ADDR_2 => x"52031646CD5FFF28", + ROM_ADDR_3 => x"EC0416525116FF28", + ROM_ADDR_4 => x"050416523379FF28", + ROM_ADDR_5 => x"E2041651AEA5FF28", + ROM_ADDR_6 => x"940000092C3B2F28", + ROM_ADDR_7 => x"4B0000092D22BD28", + ROM_ADDR_8 => x"C30000092B07EA28", + ROM_ADDR_9 => x"780000092A277628" + ) + port map( + CLK => clk_sys, + RESET => reset_i, + READOUT_ENABLE_IN => '1', + --connection to 1-wire interface + ONEWIRE => ONEWIRE(0), + --INTERLOCK + INTERLOCK_FLAG => interlock_flag_i(0), + INTERLOCK_LIMIT => interlock_limit_i, + -- SLOW CONTROL + BUS_RX => busonewire_rx(0), + BUS_TX => busonewire_tx(0) + ); + + THE_ONEWIRE_1 : entity work.onewire_record + generic map( + N_SENSORS => 8, -- Number of connected sensors + ROM_ADDR_0 => x"3B0000092C430228", + ROM_ADDR_1 => x"BB0000092A30D028", + ROM_ADDR_2 => x"B60000092D9D3C28", + ROM_ADDR_3 => x"0E0000092C30AF28", + ROM_ADDR_4 => x"E40000092D682028", + ROM_ADDR_5 => x"E70000092C430628", + ROM_ADDR_6 => x"800000092AE74728", + ROM_ADDR_7 => x"6E0000092AF8EF28" + ) + port map( + CLK => clk_sys, + RESET => reset_i, + READOUT_ENABLE_IN => '1', + --connection to 1-wire interface + ONEWIRE => ONEWIRE(1), + --INTERLOCK + INTERLOCK_FLAG => interlock_flag_i(1), + INTERLOCK_LIMIT => interlock_limit_i, + -- SLOW CONTROL + BUS_RX => busonewire_rx(1), + BUS_TX => busonewire_tx(1) + ); + + interlock_output <= not or_all(interlock_flag_i); + INTERLOCK_OUT <= interlock_output; + INTERLOCK_GND_OUT <= '0'; + + THE_UART : entity work.uart_mag + generic map( + OUTPUTS => 6--, + --BAUD => 56200 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + UART_RX(0) => INP(0),--uart_rx, + UART_RX(1) => INP(1),--uart_rx, + UART_RX(2) => INP(2),--uart_rx, + UART_RX(3) => INP(3),--uart_rx, + UART_RX(4) => INP(4),--uart_rx, + UART_RX(5) => INP(5),--uart_rx, + UART_TX(0) => open,--uart_tx, + BUS_RX => busparser_rx, + BUS_TX => busparser_tx + ); + + THE_UART_relais : entity work.uart_relais + generic map( + OUTPUTS => 1, + BAUD => 57600 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + UART_TX(0) => OUTP(0),--uart_tx, + BUS_RX => busrelais_rx, + BUS_TX => busrelais_tx + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS: entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_OUT, + FLASH_OUT => FLASH_IN, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT=> spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => HDR_IO, + --LCD + LCD_DATA_IN => lcd_data, + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_CLK, + --Trigger & Monitor + MONITOR_INPUTS => KEL(32 downto 1),--(others => '0'), + TRIG_GEN_INPUTS => KEL(32 downto 1),--(others => '0'), + TRIG_GEN_OUTPUTS => BACK_GPIO(3 downto 2),--open, + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + +--------------------------------------------------------------------------- +-- Switches +--------------------------------------------------------------------------- +--Serdes Select + PCSSW_ENSMB <= '0'; + PCSSW_EQ <= x"0"; + PCSSW_PE <= x"F"; + PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + + RJ_IO <= "0000"; + +-- BACK_GPIO <= (others => 'Z'); + BACK_LVDS <= (others => '0'); + BACK_3V3 <= (others => 'Z'); + + +--------------------------------------------------------------------------- +-- LCD Data to display +--------------------------------------------------------------------------- + lcd_data(15 downto 0) <= timer.network_address; + lcd_data(47 downto 16) <= timer.microsecond; + lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)); + lcd_data(91 downto 80) <= timer.temperature; + lcd_data(95 downto 92) <= x"0"; + lcd_data(159 downto 96) <= timer.uid; + lcd_data(511 downto 160) <= (others => '0'); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) + LED_GREEN <= debug_clock_reset(0); + LED_ORANGE <= debug_clock_reset(1); + LED_RED <= not sed_error_i; + LED_YELLOW <= debug_clock_reset(2); + LED_WHITE(0) <= time_counter(26) and time_counter(19); + LED_WHITE(1) <= time_counter(20); + LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX + +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process begin + wait until rising_edge(clk_sys); + time_counter <= time_counter + 1; + if reset_i = '1' then + time_counter <= (others => '0'); + end if; + end process; + +-- TEST_LINE <= med_stat_debug(15 downto 0); +-- TEST_LINE(15 downto 0) <= debug_clock_reset(15 downto 14) & med2int(0).stat_op(13) & clear_i & reset_i & debug_clock_reset(10 downto 0); + TEST_LINE(0) <= med2int(0).stat_op(13); + TEST_LINE(1) <= med2int(0).stat_op(15); + TEST_LINE(2) <= clear_i; + TEST_LINE(3) <= reset_i; + TEST_LINE(4) <= med2int(0).dataready; + TEST_LINE(5) <= int2med(0).dataready; + TEST_LINE(6) <= sfp_txdis_i; + TEST_LINE(7) <= med2int(0).stat_op(9); +-- readout_tx(0).data_finished <= '1'; +-- readout_tx(0).data_write <= '0'; +-- readout_tx(0).busy_release <= '1'; +-- + +-- gen_chains : for i in 1 to 16 generate +-- process begin +-- wait until rising_edge(clk_full); +-- c(i)(5000 downto 1) <= c(i)(4999 downto 0); +-- c(i)(0) <= not c(i)(0) or KEL(i); +-- BACK_GPIO(i-1) <= c(i)(5000); +-- if reset_i = '1' then +-- c(i)(5000 downto 0) <= (others => '0'); +-- end if; +-- end process; +-- +-- end generate; + + +THE_RDO_STAT : process begin + wait until rising_edge(clk_sys); + busrdo_tx.ack <= '0'; + busrdo_tx.nack <= '0'; + busrdo_tx.unknown <= '0'; + + if busrdo_rx.write = '1' then + if busrdo_rx.addr = x"0000" then + busrdo_tx.ack <= '1'; + data_amount <= unsigned(busrdo_rx.data(15 downto 0)); + else + busrdo_tx.unknown <= '1'; + end if; + elsif busrdo_rx.read = '1' then + if busrdo_rx.addr = x"0000" then + busrdo_tx.ack <= '1'; + busrdo_tx.data(15 downto 0) <= std_logic_vector(data_amount); + else + busrdo_tx.unknown <= '1'; + end if; + end if; +end process; + +THE_RDO : process begin + wait until rising_edge(clk_sys); + readout_tx(0).busy_release <= '0'; + readout_tx(0).data_write <= '0'; + readout_tx(0).data_finished <= '0'; + + case state is + when IDLE => + if readout_rx.valid_timing_trg = '1' or readout_rx.valid_notiming_trg = '1' then + state <= WRITE; + end if; + if readout_rx.invalid_trg = '1' then + state <= FINISH; + end if; + data_counter <= 0; + when WRITE => + readout_tx(0).data <= timer.microsecond; + readout_tx(0).data_write <= '1'; + data_counter <= data_counter + 1; + if data_counter = data_amount then + state <= FINISH; + end if; + when FINISH => + state <= BUSYEND; + readout_tx(0).data_finished <= '1'; + when BUSYEND => + state <= IDLE; + readout_tx(0).busy_release <= '1'; + end case; +end process; + +THE_INTERLOCK : process begin + +wait until rising_edge(clk_sys); + + businterlock_tx.unknown <= '0'; + businterlock_tx.ack <= '0'; + businterlock_tx.nack <= '0'; + businterlock_tx.data <= (others => '0'); + + if businterlock_rx.write = '1' then + if businterlock_rx.addr(3 downto 0) = x"0" then + interlock_limit_i <= businterlock_rx.data; + businterlock_tx.ack <= '1'; + else + businterlock_tx.unknown <= '1'; + end if; + elsif businterlock_rx.read = '1' then + if businterlock_rx.addr(3 downto 0) = x"0" then + businterlock_tx.data <= interlock_limit_i; + businterlock_tx.ack <= '1'; + elsif businterlock_rx.addr(3 downto 0) = x"1" then + businterlock_tx.data(0) <= interlock_output; + businterlock_tx.data(31 downto 1) <= (others => '0'); + businterlock_tx.ack <= '1'; + else + businterlock_tx.unknown <= '1'; + end if; + end if; + +end process; + +end architecture; + + +