From: Ludwig Maier Date: Sun, 2 Jun 2013 22:42:28 +0000 (+0200) Subject: adc-timestamp sync found X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1a91cd91ff44d6c5d2242cd08ef1c091b0744fd8;p=trb3.git adc-timestamp sync found --- diff --git a/base/trb3_periph_nxyter.lpf b/base/trb3_periph_nxyter.lpf index c02b52e..beb1c3a 100644 --- a/base/trb3_periph_nxyter.lpf +++ b/base/trb3_periph_nxyter.lpf @@ -111,7 +111,7 @@ LOCATE COMP "NX1_ADC_NX_IN" SITE "C3"; #DQUL0_4 #82 LOCATE COMP "NX1_ADC_DCLK_IN" SITE "G5"; #DQSUL0_T #86 LOCATE COMP "NX1_ADC_B_IN" SITE "E3"; #DQUL0_6 #90 LOCATE COMP "NX1_ADC_FCLK_IN" SITE "H6"; #DQUL0_8 #94 -LOCATE COMP "NX1_ADC_SC_CLK32_OUT" SITE "H5"; #DQUL1_6 #89 +LOCATE COMP "NX1_ADC_SAMPLE_CLK_OUT" SITE "H5"; #DQUL1_6 #89 LOCATE COMP "NX1_SPI_SDIO_INOUT" SITE "G2"; #DQUL1_0 #73 LOCATE COMP "NX1_SPI_SCLK_OUT" SITE "F2"; #DQUL1_2 #77 @@ -146,7 +146,7 @@ IOBUF PORT "NX1_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX1_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX1_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX1_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; -IOBUF PORT "NX1_ADC_SC_CLK32_OUT" IO_TYPE=LVDS25; +IOBUF PORT "NX1_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25; IOBUF PORT "NX1_CLK128_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX1_TESTPULSE_OUT" IO_TYPE=LVDS25; @@ -166,7 +166,7 @@ IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP; # nXyter 2 -LOCATE COMP "NX2_ADC_SC_CLK32_OUT" SITE "Y19"; #DQLR0_2 #133 +LOCATE COMP "NX2_SAMPLE_CLK_OUT" SITE "Y19"; #DQLR0_2 #133 LOCATE COMP "NX2_RESET_OUT" SITE "W23"; #DQLR1_0 #169 LOCATE COMP "NX2_CLK256A_OUT" SITE "AA26"; #DQLR1_4 #177 LOCATE COMP "NX2_TESTPULSE_OUT" SITE "AA24"; #DQLR1_6 #185 @@ -219,7 +219,7 @@ IOBUF PORT "NX2_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX2_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX2_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX2_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; -IOBUF PORT "NX2_ADC_SC_CLK32_OUT" IO_TYPE=LVDS25; +IOBUF PORT "NX2_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25; IOBUF PORT "NX2_CLK128_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX2_TESTPULSE_OUT" IO_TYPE=LVDS25; diff --git a/nxyter/.gitignore b/nxyter/.gitignore new file mode 100644 index 0000000..8507be3 --- /dev/null +++ b/nxyter/.gitignore @@ -0,0 +1 @@ +version.vhd diff --git a/nxyter/compile_munich.sh b/nxyter/compile_munich.sh index ed1ab06..f5574ea 100755 --- a/nxyter/compile_munich.sh +++ b/nxyter/compile_munich.sh @@ -1,5 +1,5 @@ #!/bin/sh -. /usr/local/opt/lattice_diamond/diamond/new/bin/lin/diamond_env +. /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env exec ./compile_munich2.pl diff --git a/nxyter/compile_munich2.pl b/nxyter/compile_munich2.pl index a67b487..c5c2b62 100755 --- a/nxyter/compile_munich2.pl +++ b/nxyter/compile_munich2.pl @@ -9,7 +9,7 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph"; #Name of top-level entity -my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/2.0'; +my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/2.1'; my $synplify_path = '/usr/local/opt/synplify/F-2012.03-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; @@ -95,43 +95,43 @@ foreach (@a) $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; - -$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +$c=qq| $lattice_path/ispfpga/bin/lin64/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +$c=qq|$lattice_path/ispfpga/bin/lin64/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +$c=qq|$lattice_path/ispfpga/bin/lin64/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; execute($c); my $tpmap = $TOPNAME . "_map" ; -$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +$c=qq|$lattice_path/ispfpga/bin/lin64/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; execute($c); system("rm $TOPNAME.ncd"); -$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +#$c=qq|$lattice_path/ispfpga/bin/lin64/par "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/bin/lin64/mpartrce -p "../$TOPNAME.p2t" -f "$TOPNAME.p3t" -tf "$TOPNAME.pt" "$tpmap.ncd" "$TOPNAME.ncd"|; execute($c); # IOR IO Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin64/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); # TWR Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin64/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin64/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +$c=qq|$lattice_path/ispfpga/bin/lin64/ltxt2ptxt $TOPNAME.ncd|; execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; -# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; +# $c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); chdir ".."; diff --git a/nxyter/cores/fifo_32to32_dc.ipx b/nxyter/cores/fifo_32to32_dc.ipx deleted file mode 100644 index ad3a7ac..0000000 --- a/nxyter/cores/fifo_32to32_dc.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/nxyter/cores/fifo_ts_32to32_dc.ipx b/nxyter/cores/fifo_ts_32to32_dc.ipx new file mode 100644 index 0000000..a05b4f1 --- /dev/null +++ b/nxyter/cores/fifo_ts_32to32_dc.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/nxyter/cores/fifo_32to32_dc.lpc b/nxyter/cores/fifo_ts_32to32_dc.lpc similarity index 89% rename from nxyter/cores/fifo_32to32_dc.lpc rename to nxyter/cores/fifo_ts_32to32_dc.lpc index ad53e9e..996fcfb 100644 --- a/nxyter/cores/fifo_32to32_dc.lpc +++ b/nxyter/cores/fifo_ts_32to32_dc.lpc @@ -13,11 +13,11 @@ CoreType=LPM CoreStatus=Demo CoreName=FIFO_DC CoreRevision=5.4 -ModuleName=fifo_32to32_dc +ModuleName=fifo_ts_32to32_dc SourceFormat=VHDL ParameterFileVersion=1.0 -Date=04/07/2013 -Time=20:23:08 +Date=06/02/2013 +Time=03:59:31 [Parameters] Verilog=0 @@ -28,9 +28,9 @@ Expression=BusA(0 to 7) Order=Big Endian [MSB:LSB] IO=0 FIFOImp=EBR Based -Depth=64 +Depth=32 Width=32 -RDepth=64 +RDepth=32 RWidth=32 regout=1 CtrlByRdEn=1 diff --git a/nxyter/cores/fifo_32to32_dc.vhd b/nxyter/cores/fifo_ts_32to32_dc.vhd similarity index 82% rename from nxyter/cores/fifo_32to32_dc.vhd rename to nxyter/cores/fifo_ts_32to32_dc.vhd index a52318a..8a4c217 100644 --- a/nxyter/cores/fifo_32to32_dc.vhd +++ b/nxyter/cores/fifo_ts_32to32_dc.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) -- Module Version: 5.4 ---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 32 -depth 64 -rdata_width 32 -regout -pe 0 -pf -1 -e +--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32 -width 32 -depth 32 -rdata_width 32 -regout -pe 0 -pf -1 -e --- Sun Apr 7 20:23:08 2013 +-- Sun Jun 2 03:59:31 2013 library IEEE; use IEEE.std_logic_1164.all; @@ -11,7 +11,7 @@ library ecp3; use ecp3.components.all; -- synopsys translate_on -entity fifo_32to32_dc is +entity fifo_ts_32to32_dc is port ( Data: in std_logic_vector(31 downto 0); WrClock: in std_logic; @@ -20,45 +20,41 @@ entity fifo_32to32_dc is RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(5 downto 0); + AmEmptyThresh: in std_logic_vector(4 downto 0); Q: out std_logic_vector(31 downto 0); Empty: out std_logic; Full: out std_logic; AlmostEmpty: out std_logic); -end fifo_32to32_dc; +end fifo_ts_32to32_dc; -architecture Structure of fifo_32to32_dc is +architecture Structure of fifo_ts_32to32_dc is -- internal signal declarations signal invout_1: std_logic; signal invout_0: std_logic; - signal rcnt_reg_5_inv: std_logic; + signal rcnt_reg_4_inv: std_logic; signal w_gdata_0: std_logic; signal w_gdata_1: std_logic; signal w_gdata_2: std_logic; signal w_gdata_3: std_logic; signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; signal wptr_0: std_logic; signal wptr_1: std_logic; signal wptr_2: std_logic; signal wptr_3: std_logic; signal wptr_4: std_logic; signal wptr_5: std_logic; - signal wptr_6: std_logic; signal r_gdata_0: std_logic; signal r_gdata_1: std_logic; signal r_gdata_2: std_logic; signal r_gdata_3: std_logic; signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; signal rptr_0: std_logic; signal rptr_1: std_logic; signal rptr_2: std_logic; signal rptr_3: std_logic; signal rptr_4: std_logic; signal rptr_5: std_logic; - signal rptr_6: std_logic; signal ffidata_0: std_logic; signal ffidata_1: std_logic; signal ffidata_2: std_logic; @@ -97,14 +93,12 @@ architecture Structure of fifo_32to32_dc is signal w_gcount_3: std_logic; signal w_gcount_4: std_logic; signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; signal r_gcount_0: std_logic; signal r_gcount_1: std_logic; signal r_gcount_2: std_logic; signal r_gcount_3: std_logic; signal r_gcount_4: std_logic; signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; signal w_gcount_r20: std_logic; signal w_gcount_r0: std_logic; signal w_gcount_r21: std_logic; @@ -117,8 +111,6 @@ architecture Structure of fifo_32to32_dc is signal w_gcount_r4: std_logic; signal w_gcount_r25: std_logic; signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; signal r_gcount_w20: std_logic; signal r_gcount_w0: std_logic; signal r_gcount_w21: std_logic; @@ -131,9 +123,7 @@ architecture Structure of fifo_32to32_dc is signal r_gcount_w4: std_logic; signal r_gcount_w25: std_logic; signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal rcnt_reg_6: std_logic; + signal rcnt_reg_5: std_logic; signal empty_i: std_logic; signal full_i: std_logic; signal rRst: std_logic; @@ -145,11 +135,9 @@ architecture Structure of fifo_32to32_dc is signal co0: std_logic; signal iwcount_4: std_logic; signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal co3: std_logic; - signal wcount_6: std_logic; signal co2: std_logic; + signal wcount_5: std_logic; + signal co1: std_logic; signal ircount_0: std_logic; signal ircount_1: std_logic; signal r_gctr_ci: std_logic; @@ -158,11 +146,9 @@ architecture Structure of fifo_32to32_dc is signal co0_1: std_logic; signal ircount_4: std_logic; signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal co3_1: std_logic; - signal rcount_6: std_logic; signal co2_1: std_logic; + signal rcount_5: std_logic; + signal co1_1: std_logic; signal rcnt_sub_0: std_logic; signal scuba_vhi: std_logic; signal rcnt_sub_1: std_logic; @@ -172,28 +158,22 @@ architecture Structure of fifo_32to32_dc is signal rcnt_sub_4: std_logic; signal co1_2: std_logic; signal rcnt_sub_5: std_logic; - signal rcnt_sub_6: std_logic; signal co2_2: std_logic; signal rcnt_sub_msb: std_logic; - signal co3_2d: std_logic; - signal co3_2: std_logic; signal cmp_ci: std_logic; signal wcount_r0: std_logic; signal wcount_r1: std_logic; signal rcount_0: std_logic; signal rcount_1: std_logic; signal co0_3: std_logic; - signal wcount_r2: std_logic; signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r3: std_logic; signal rcount_2: std_logic; signal rcount_3: std_logic; signal co1_3: std_logic; signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_3: std_logic; signal empty_cmp_clr: std_logic; + signal rcount_4: std_logic; signal empty_cmp_set: std_logic; signal empty_d: std_logic; signal empty_d_c: std_logic; @@ -204,17 +184,14 @@ architecture Structure of fifo_32to32_dc is signal wcount_0: std_logic; signal wcount_1: std_logic; signal co0_4: std_logic; - signal rcount_w2: std_logic; signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w3: std_logic; signal wcount_2: std_logic; signal wcount_3: std_logic; signal co1_4: std_logic; signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_4: std_logic; signal full_cmp_clr: std_logic; + signal wcount_4: std_logic; signal full_cmp_set: std_logic; signal full_d: std_logic; signal full_d_c: std_logic; @@ -227,8 +204,6 @@ architecture Structure of fifo_32to32_dc is signal rcnt_reg_3: std_logic; signal co1_5: std_logic; signal rcnt_reg_4: std_logic; - signal rcnt_reg_5: std_logic; - signal co2_5: std_logic; signal ae_clrsig: std_logic; signal ae_setsig: std_logic; signal ae_d: std_logic; @@ -353,20 +328,9 @@ architecture Structure of fifo_32to32_dc is attribute MEM_INIT_FILE : string; attribute RESETMODE : string; attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_32to32_dc.lpc"; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_ts_32to32_dc.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; attribute GSR of FF_100 : label is "ENABLED"; attribute GSR of FF_99 : label is "ENABLED"; attribute GSR of FF_98 : label is "ENABLED"; @@ -469,111 +433,97 @@ architecture Structure of fifo_32to32_dc is attribute GSR of FF_1 : label is "ENABLED"; attribute GSR of FF_0 : label is "ENABLED"; attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; begin -- component instantiation statements - AND2_t17: AND2 + AND2_t15: AND2 port map (A=>WrEn, B=>invout_1, Z=>wren_i); INV_2: INV port map (A=>full_i, Z=>invout_1); - AND2_t16: AND2 + AND2_t14: AND2 port map (A=>RdEn, B=>invout_0, Z=>rden_i); INV_1: INV port map (A=>empty_i, Z=>invout_0); - OR2_t15: OR2 + OR2_t13: OR2 port map (A=>Reset, B=>RPReset, Z=>rRst); - XOR2_t14: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t13: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - XOR2_t12: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); XOR2_t11: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); XOR2_t10: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); XOR2_t9: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); XOR2_t8: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); XOR2_t7: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); XOR2_t6: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); XOR2_t5: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); XOR2_t4: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); XOR2_t3: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_gcount_r26, - DO0=>w_g2b_xor_cluster_0); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r5); + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); LUT4_13: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r4); + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, + DO0=>w_g2b_xor_cluster_0); LUT4_12: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>wcount_r5, DO0=>wcount_r2); + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r4); LUT4_11: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1); + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>wcount_r3); LUT4_10: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r0); + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1); LUT4_9: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_gcount_w26, - DO0=>r_g2b_xor_cluster_0); + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0); LUT4_8: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w5); + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>r_gcount_w25, + DO0=>r_g2b_xor_cluster_0); LUT4_7: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w4); + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w4); LUT4_6: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>rcount_w5, DO0=>rcount_w2); + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>rcount_w3); LUT4_5: ROM16X1A generic map (initval=> X"6996") @@ -583,39 +533,39 @@ begin LUT4_4: ROM16X1A generic map (initval=> X"6996") port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w0); + AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0); XOR2_t2: XOR2 - port map (A=>w_gcount_r26, B=>rcount_6, Z=>rcnt_sub_msb); + port map (A=>w_gcount_r25, B=>rcount_5, Z=>rcnt_sub_msb); LUT4_3: ROM16X1A generic map (initval=> X"0410") - port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r26, + port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>empty_cmp_set); LUT4_2: ROM16X1A generic map (initval=> X"1004") - port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r26, + port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>empty_cmp_clr); LUT4_1: ROM16X1A generic map (initval=> X"0140") - port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w26, + port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>full_cmp_set); LUT4_0: ROM16X1A generic map (initval=> X"4001") - port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w26, + port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>full_cmp_clr); INV_0: INV - port map (A=>rcnt_reg_5, Z=>rcnt_reg_5_inv); + port map (A=>rcnt_reg_4, Z=>rcnt_reg_4_inv); AND2_t1: AND2 - port map (A=>rcnt_reg_6, B=>rcnt_reg_5_inv, Z=>ae_clrsig); + port map (A=>rcnt_reg_5, B=>rcnt_reg_4_inv, Z=>ae_clrsig); AND2_t0: AND2 - port map (A=>rcnt_reg_6, B=>rcnt_reg_5, Z=>ae_setsig); + port map (A=>rcnt_reg_5, B=>rcnt_reg_4, Z=>ae_setsig); pdp_ram_0_0_0: PDPW16KC generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", @@ -632,15 +582,16 @@ begin DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, - ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>scuba_vlo, ADW7=>scuba_vlo, - ADW8=>scuba_vlo, BE0=>scuba_vhi, BE1=>scuba_vhi, - BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, - CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, - ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, - ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, - ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, - ADR11=>scuba_vlo, ADR12=>scuba_vlo, ADR13=>scuba_vlo, - CER=>rden_i, CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, + ADW4=>wptr_4, ADW5=>scuba_vlo, ADW6=>scuba_vlo, + ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi, + BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, + CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, + CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, + ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, + ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3, + ADR9=>rptr_4, ADR10=>scuba_vlo, ADR11=>scuba_vlo, + ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>rden_i, + CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>ffidata_18, DO1=>ffidata_19, DO2=>ffidata_20, DO3=>ffidata_21, DO4=>ffidata_22, DO5=>ffidata_23, DO6=>ffidata_24, @@ -655,403 +606,363 @@ begin DO32=>ffidata_14, DO33=>ffidata_15, DO34=>ffidata_16, DO35=>ffidata_17); - FF_111: FD1P3BX + FF_100: FD1P3BX port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, Q=>wcount_0); - FF_110: FD1P3DX + FF_99: FD1P3DX port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_1); - FF_109: FD1P3DX + FF_98: FD1P3DX port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_2); - FF_108: FD1P3DX + FF_97: FD1P3DX port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_3); - FF_107: FD1P3DX + FF_96: FD1P3DX port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_4); - FF_106: FD1P3DX + FF_95: FD1P3DX port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_5); - FF_105: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_104: FD1P3DX + FF_94: FD1P3DX port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_0); - FF_103: FD1P3DX + FF_93: FD1P3DX port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_1); - FF_102: FD1P3DX + FF_92: FD1P3DX port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_2); - FF_101: FD1P3DX + FF_91: FD1P3DX port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_3); - FF_100: FD1P3DX + FF_90: FD1P3DX port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_4); - FF_99: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + FF_89: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_5); - FF_98: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_97: FD1P3DX + FF_88: FD1P3DX port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_0); - FF_96: FD1P3DX + FF_87: FD1P3DX port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_1); - FF_95: FD1P3DX + FF_86: FD1P3DX port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_2); - FF_94: FD1P3DX + FF_85: FD1P3DX port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_3); - FF_93: FD1P3DX + FF_84: FD1P3DX port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_4); - FF_92: FD1P3DX + FF_83: FD1P3DX port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_5); - FF_91: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_90: FD1P3BX + FF_82: FD1P3BX port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, Q=>rcount_0); - FF_89: FD1P3DX + FF_81: FD1P3DX port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_1); - FF_88: FD1P3DX + FF_80: FD1P3DX port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_2); - FF_87: FD1P3DX + FF_79: FD1P3DX port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_3); - FF_86: FD1P3DX + FF_78: FD1P3DX port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_4); - FF_85: FD1P3DX + FF_77: FD1P3DX port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_5); - FF_84: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_83: FD1P3DX + FF_76: FD1P3DX port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_0); - FF_82: FD1P3DX + FF_75: FD1P3DX port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_1); - FF_81: FD1P3DX + FF_74: FD1P3DX port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_2); - FF_80: FD1P3DX + FF_73: FD1P3DX port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_3); - FF_79: FD1P3DX + FF_72: FD1P3DX port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_4); - FF_78: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + FF_71: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_5); - FF_77: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_76: FD1P3DX + FF_70: FD1P3DX port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_0); - FF_75: FD1P3DX + FF_69: FD1P3DX port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_1); - FF_74: FD1P3DX + FF_68: FD1P3DX port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_2); - FF_73: FD1P3DX + FF_67: FD1P3DX port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_3); - FF_72: FD1P3DX + FF_66: FD1P3DX port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_4); - FF_71: FD1P3DX + FF_65: FD1P3DX port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_5); - FF_70: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_69: FD1P3DX + FF_64: FD1P3DX port map (D=>ffidata_0, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(0)); - FF_68: FD1P3DX + FF_63: FD1P3DX port map (D=>ffidata_1, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(1)); - FF_67: FD1P3DX + FF_62: FD1P3DX port map (D=>ffidata_2, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(2)); - FF_66: FD1P3DX + FF_61: FD1P3DX port map (D=>ffidata_3, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(3)); - FF_65: FD1P3DX + FF_60: FD1P3DX port map (D=>ffidata_4, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(4)); - FF_64: FD1P3DX + FF_59: FD1P3DX port map (D=>ffidata_5, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(5)); - FF_63: FD1P3DX + FF_58: FD1P3DX port map (D=>ffidata_6, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(6)); - FF_62: FD1P3DX + FF_57: FD1P3DX port map (D=>ffidata_7, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(7)); - FF_61: FD1P3DX + FF_56: FD1P3DX port map (D=>ffidata_8, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(8)); - FF_60: FD1P3DX + FF_55: FD1P3DX port map (D=>ffidata_9, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(9)); - FF_59: FD1P3DX + FF_54: FD1P3DX port map (D=>ffidata_10, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(10)); - FF_58: FD1P3DX + FF_53: FD1P3DX port map (D=>ffidata_11, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(11)); - FF_57: FD1P3DX + FF_52: FD1P3DX port map (D=>ffidata_12, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(12)); - FF_56: FD1P3DX + FF_51: FD1P3DX port map (D=>ffidata_13, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(13)); - FF_55: FD1P3DX + FF_50: FD1P3DX port map (D=>ffidata_14, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(14)); - FF_54: FD1P3DX + FF_49: FD1P3DX port map (D=>ffidata_15, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(15)); - FF_53: FD1P3DX + FF_48: FD1P3DX port map (D=>ffidata_16, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(16)); - FF_52: FD1P3DX + FF_47: FD1P3DX port map (D=>ffidata_17, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(17)); - FF_51: FD1P3DX + FF_46: FD1P3DX port map (D=>ffidata_18, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(18)); - FF_50: FD1P3DX + FF_45: FD1P3DX port map (D=>ffidata_19, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(19)); - FF_49: FD1P3DX + FF_44: FD1P3DX port map (D=>ffidata_20, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(20)); - FF_48: FD1P3DX + FF_43: FD1P3DX port map (D=>ffidata_21, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(21)); - FF_47: FD1P3DX + FF_42: FD1P3DX port map (D=>ffidata_22, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(22)); - FF_46: FD1P3DX + FF_41: FD1P3DX port map (D=>ffidata_23, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(23)); - FF_45: FD1P3DX + FF_40: FD1P3DX port map (D=>ffidata_24, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(24)); - FF_44: FD1P3DX + FF_39: FD1P3DX port map (D=>ffidata_25, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(25)); - FF_43: FD1P3DX + FF_38: FD1P3DX port map (D=>ffidata_26, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(26)); - FF_42: FD1P3DX + FF_37: FD1P3DX port map (D=>ffidata_27, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(27)); - FF_41: FD1P3DX + FF_36: FD1P3DX port map (D=>ffidata_28, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(28)); - FF_40: FD1P3DX + FF_35: FD1P3DX port map (D=>ffidata_29, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(29)); - FF_39: FD1P3DX + FF_34: FD1P3DX port map (D=>ffidata_30, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(30)); - FF_38: FD1P3DX + FF_33: FD1P3DX port map (D=>ffidata_31, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(31)); - FF_37: FD1S3DX + FF_32: FD1S3DX port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - FF_36: FD1S3DX + FF_31: FD1S3DX port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - FF_35: FD1S3DX + FF_30: FD1S3DX port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - FF_34: FD1S3DX + FF_29: FD1S3DX port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - FF_33: FD1S3DX + FF_28: FD1S3DX port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - FF_32: FD1S3DX + FF_27: FD1S3DX port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - FF_31: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_30: FD1S3DX + FF_26: FD1S3DX port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - FF_29: FD1S3DX + FF_25: FD1S3DX port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - FF_28: FD1S3DX + FF_24: FD1S3DX port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - FF_27: FD1S3DX + FF_23: FD1S3DX port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - FF_26: FD1S3DX + FF_22: FD1S3DX port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - FF_25: FD1S3DX + FF_21: FD1S3DX port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - FF_24: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_23: FD1S3DX + FF_20: FD1S3DX port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r20); - FF_22: FD1S3DX + FF_19: FD1S3DX port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r21); - FF_21: FD1S3DX + FF_18: FD1S3DX port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r22); - FF_20: FD1S3DX + FF_17: FD1S3DX port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r23); - FF_19: FD1S3DX + FF_16: FD1S3DX port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r24); - FF_18: FD1S3DX + FF_15: FD1S3DX port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r25); - FF_17: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_16: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_15: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - FF_14: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); FF_13: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); FF_12: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); FF_11: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); FF_10: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); FF_9: FD1S3DX - port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); FF_8: FD1S3DX - port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); + port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); FF_7: FD1S3DX - port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); + port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); FF_6: FD1S3DX - port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); + port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); FF_5: FD1S3DX - port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); + port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); FF_4: FD1S3DX - port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); + port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); FF_3: FD1S3DX - port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); + port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); FF_2: FD1S3BX port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); @@ -1079,10 +990,6 @@ begin port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, NC0=>iwcount_4, NC1=>iwcount_5); - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>scuba_vlo, CO=>co3, - NC0=>iwcount_6, NC1=>open); - r_gctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, @@ -1100,10 +1007,6 @@ begin port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, NC0=>ircount_4, NC1=>ircount_5); - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>scuba_vlo, CO=>co3_1, - NC0=>ircount_6, NC1=>open); - scuba_vhi_inst: VHI port map (Z=>scuba_vhi); @@ -1113,23 +1016,19 @@ begin S1=>rcnt_sub_0); rcnt_1: FSUB2B - port map (A0=>wcount_r1, A1=>wcount_r2, B0=>rcount_1, + port map (A0=>wcount_r1, A1=>w_g2b_xor_cluster_0, B0=>rcount_1, B1=>rcount_2, BI=>co0_2, BOUT=>co1_2, S0=>rcnt_sub_1, S1=>rcnt_sub_2); rcnt_2: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r4, B0=>rcount_3, + port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rcount_3, B1=>rcount_4, BI=>co1_2, BOUT=>co2_2, S0=>rcnt_sub_3, S1=>rcnt_sub_4); rcnt_3: FSUB2B - port map (A0=>wcount_r5, A1=>rcnt_sub_msb, B0=>rcount_5, - B1=>scuba_vlo, BI=>co2_2, BOUT=>co3_2, S0=>rcnt_sub_5, - S1=>rcnt_sub_6); - - rcntd: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co3_2, COUT=>open, S0=>co3_2d, S1=>open); + port map (A0=>rcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co2_2, BOUT=>open, S0=>rcnt_sub_5, + S1=>open); empty_cmp_ci_a: FADD2B port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, @@ -1140,16 +1039,12 @@ begin B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3); empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>w_g2b_xor_cluster_0, CI=>co0_3, GE=>co1_3); + port map (A0=>rcount_2, A1=>rcount_3, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r3, CI=>co0_3, GE=>co1_3); empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_3, GE=>co2_3); - - empty_cmp_3: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co2_3, GE=>empty_d_c); + port map (A0=>rcount_4, A1=>empty_cmp_set, B0=>wcount_r4, + B1=>empty_cmp_clr, CI=>co1_3, GE=>empty_d_c); a0: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, @@ -1165,16 +1060,12 @@ begin B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4); full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>r_g2b_xor_cluster_0, CI=>co0_4, GE=>co1_4); + port map (A0=>wcount_2, A1=>wcount_3, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w3, CI=>co0_4, GE=>co1_4); full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_4, GE=>co2_4); - - full_cmp_3: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co2_4, GE=>full_d_c); + port map (A0=>wcount_4, A1=>full_cmp_set, B0=>rcount_w4, + B1=>full_cmp_clr, CI=>co1_4, GE=>full_d_c); a1: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, @@ -1194,12 +1085,8 @@ begin B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_5, GE=>co1_5); ae_cmp_2: AGEB2 - port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), - B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_5, GE=>co2_5); - - ae_cmp_3: AGEB2 - port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, - B1=>scuba_vlo, CI=>co2_5, GE=>ae_d_c); + port map (A0=>AmEmptyThresh(4), A1=>ae_setsig, B0=>rcnt_reg_4, + B1=>ae_clrsig, CI=>co1_5, GE=>ae_d_c); scuba_vlo_inst: VLO port map (Z=>scuba_vlo); @@ -1214,7 +1101,7 @@ end Structure; -- synopsys translate_off library ecp3; -configuration Structure_CON of fifo_32to32_dc is +configuration Structure_CON of fifo_ts_32to32_dc is for Structure for all:AGEB2 use entity ecp3.AGEB2(V); end for; for all:AND2 use entity ecp3.AND2(V); end for; diff --git a/nxyter/source/adc_receiver.vhd b/nxyter/source/adc_receiver.vhd deleted file mode 100644 index ccde877..0000000 --- a/nxyter/source/adc_receiver.vhd +++ /dev/null @@ -1,133 +0,0 @@ ----------------------------------------------------------------------------- --- ADC Pulse height Handler ------------------------------------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.nxyter_components.all; - -entity adc_receiver is - - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - CLK_ADC_IN : in std_logic; - - ADC_FCLK_IN : in std_logic_vector(1 downto 0); - ADC_DCLK_IN : in std_logic_vector(1 downto 0); - ADC_SC_CLK32_OUT : out std_logic; - ADC_A_IN : in std_logic_vector(1 downto 0); - ADC_B_IN : in std_logic_vector(1 downto 0); - ADC_NX_IN : in std_logic_vector(1 downto 0); - ADC_D_IN : in std_logic_vector(1 downto 0); - - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end entity; - - -architecture Behavioral of adc_receiver is - - signal even_bit_reg : std_logic; - signal even_bit_ctr : unsigned(2 downto 0); - signal even_bits : std_logic_vector(5 downto 0); - signal even_word : std_logic_vector(5 downto 0); - signal new_even_word : std_logic; - - signal odd_bit_reg : std_logic; - signal odd_bit_ctr : unsigned(2 downto 0); - signal odd_bits : std_logic_vector(5 downto 0); - signal odd_word : std_logic_vector(5 downto 0); - signal new_odd_word : std_logic; - - signal adc_recv_clk : std_logic; - signal adc_recv_bits : std_logic_vector(3 downto 0); - - -- ADC PLLs - signal pll_32MHz : std_logic; - signal pll_lock_32MHz : std_logic; - - signal pll_192MHz : std_logic; - signal pll_lock_192MHz : std_logic; - -begin - - -- Debug - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= pll_lock_32MHz; - DEBUG_OUT(2) <= pll_lock_192MHz; - -- DEBUG_OUT(3) <= '0';--pll_32MHz; - -- DEBUG_OUT(4) <= '0';--pll_192MHz; - -- - -- DEBUG_OUT(15 downto 5) <= (others => '0'); - - ----------------------------------------------------------------------------- - -- ADC PLLs - ----------------------------------------------------------------------------- - - pll_adc_clk192_1: pll_adc_clk192 - port map ( - CLK => CLK_ADC_IN, - CLKOP => pll_192MHz, - LOCK => pll_lock_192MHz - ); - - pll_adc_clk32_1: entity work.pll_adc_clk32 - port map ( - CLK => CLK_ADC_IN, - CLKOP => pll_32MHz, - LOCK => pll_lock_32MHz - ); - - ----------------------------------------------------------------------------- - -- ADC - ----------------------------------------------------------------------------- - - adc_ad9222_1: entity work.adc_ad9222 - generic map ( - CHANNELS => 4, - DEVICES => 2, - RESOLUTION => 12 - ) - port map ( - CLK => CLK_IN, - CLK_ADCREF => pll_32MHz, - CLK_ADCDAT => pll_192MHz, - RESTART_IN => '0', - ADCCLK_OUT => ADC_SC_CLK32_OUT, - - ADC_DATA(0) => ADC_NX_IN(0), - ADC_DATA(1) => ADC_A_IN(0), - ADC_DATA(2) => ADC_B_IN(0), - ADC_DATA(3) => ADC_D_IN(0), - - ADC_DATA(4) => ADC_NX_IN(1), - ADC_DATA(5) => ADC_A_IN(1), - ADC_DATA(6) => ADC_B_IN(1), - ADC_DATA(7) => ADC_D_IN(1), - - ADC_DCO => ADC_DCLK_IN, - ADC_FCO => ADC_FCLK_IN, - - DATA_OUT(11 downto 0) => DEBUG_OUT(15 downto 4), - DATA_OUT(95 downto 12) => open, - - FCO_OUT => open, - DATA_VALID_OUT(0) => DEBUG_OUT(3), - DATA_VALID_OUT(1) => open, - DEBUG => open - ); - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - ADC_SC_CLK32_OUT <= pll_32MHz; -- adc_sc_clk32_o; - - -end Behavioral; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd new file mode 100644 index 0000000..eb646da --- /dev/null +++ b/nxyter/source/nx_data_receiver.vhd @@ -0,0 +1,945 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.nxyter_components.all; + +entity nx_data_receiver is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + -- nXyter Ports + NX_TIMESTAMP_CLK_IN : in std_logic; + NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); + + -- ADC Ports + ADC_CLK_DAT_SRC_IN : in std_logic; + ADC_FCLK_IN : in std_logic_vector(1 downto 0); + ADC_DCLK_IN : in std_logic_vector(1 downto 0); + ADC_SAMPLE_CLK_OUT : out std_logic; + ADC_A_IN : in std_logic_vector(1 downto 0); + ADC_B_IN : in std_logic_vector(1 downto 0); + ADC_NX_IN : in std_logic_vector(1 downto 0); + ADC_D_IN : in std_logic_vector(1 downto 0); + + -- Outputs + NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0); + ADC_DATA_OUT : out std_logic_vector(11 downto 0); + NEW_DATA_OUT : out std_logic; + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture Behavioral of nx_data_receiver is + + ----------------------------------------------------------------------------- + -- NX_TIMESTAMP_CLK Domain + ----------------------------------------------------------------------------- + + -- FIFO DC Input Handler + signal nx_timestamp_reg_t : std_logic_vector(7 downto 0); + signal nx_timestamp_reg : std_logic_vector(7 downto 0); + signal nx_fifo_full : std_logic; + signal nx_fifo_reset : std_logic; + + -- NX_TIMESTAMP_IN Process + signal frame_byte_ctr : unsigned(1 downto 0); + signal nx_frame_word : std_logic_vector(31 downto 0); + signal nx_new_frame : std_logic; + + -- Frame Sync Process + signal frame_byte_pos : unsigned(1 downto 0); + + -- RS Sync FlipFlop + signal nx_frame_synced : std_logic; + signal rs_sync_set : std_logic; + signal rs_sync_reset : std_logic; + + -- Parity Check + signal parity_error : std_logic; + + -- Write to FIFO Handler + signal nx_fifo_data_input : std_logic_vector(31 downto 0); + signal nx_fifo_write_enable : std_logic; + + -- NX Clock Active + signal nx_clk_active_ff_0 : std_logic; + signal nx_clk_active_ff_1 : std_logic; + signal nx_clk_active_ff_2 : std_logic; + + -- ADC Ckl Generator + signal adc_clk_skip : std_logic; + signal adc_sample_clk : std_logic; + signal johnson_ff_0 : std_logic; + signal johnson_ff_1 : std_logic; + signal adc_clk_inv : std_logic; + signal adc_clk_delay : std_logic_vector(2 downto 0); + + ----------------------------------------------------------------------------- + -- CLK_IN Domain + ----------------------------------------------------------------------------- + + -- NX FIFO_READ + signal nx_timestamp_t : std_logic_vector(31 downto 0); + signal nx_new_timestamp : std_logic; + signal nx_new_timestamp_ctr : unsigned(3 downto 0); + + signal nx_fifo_delay_r : std_logic_vector(4 downto 0); + signal nx_fifo_almost_empty : std_logic; + + -- NX FIFO Output Handler + signal nx_fifo_data : std_logic_vector(31 downto 0); + signal nx_fifo_empty : std_logic; + signal nx_fifo_read_enable : std_logic; + signal nx_fifo_data_valid_t : std_logic; + signal nx_fifo_data_valid : std_logic; + signal nx_read_enable_pause : std_logic; + + -- Resync Counter Process + signal resync_counter : unsigned(11 downto 0); + signal resync_ctr_inc : std_logic; + signal nx_clk_active : std_logic; + + -- Parity Error Counter Process + signal parity_error_counter : unsigned(11 downto 0); + signal parity_error_ctr_inc : std_logic; + + signal reg_nx_frame_synced_t : std_logic; + signal reg_nx_frame_synced : std_logic; + + ----------------------------------------------------------------------------- + -- ADC Data Handler + ----------------------------------------------------------------------------- + + -- ADC Handler + signal adc_dat_clk : std_logic; + signal adc_dat_clk_lock : std_logic; + signal adc_reset_r : std_logic; + signal adc_reset : std_logic; + + signal adc_data : std_logic_vector(11 downto 0); + signal adc_data_valid : std_logic; + + -- ADC FIFO Handler +-- signal adc_fifo_reset : std_logic; +-- signal adc_fifo_next_word : std_logic_vector(11 downto 0); +-- signal adc_fifo_almost_empty : std_logic; +-- signal adc_fifo_full : std_logic; +-- signal adc_fifo_empty : std_logic; +-- signal adc_fifo_read_enable : std_logic; +-- signal adc_fifo_write_enable : std_logic; +-- signal adc_read_enable_pause : std_logic; +-- +-- signal adc_fifo_data_valid_t : std_logic; +-- signal adc_fifo_data_valid : std_logic; +-- signal adc_fifo_data : std_logic_vector(11 downto 0); + + signal adc_data_t : std_logic_vector(11 downto 0); + signal adc_new_data : std_logic; + signal adc_new_data_ctr : unsigned(3 downto 0); + + -- Data Output Handler + type STATES is (IDLE, + WAIT_ADC, + WAIT_TIMESTAMP + ); + signal STATE : STATES; + signal STATE_d : std_logic_vector(1 downto 0); + + signal nx_timestamp_o : std_logic_vector(31 downto 0); + signal adc_data_o : std_logic_vector(11 downto 0); + signal new_data_o : std_logic; + + -- Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + + signal reset_resync_ctr : std_logic; + signal reset_parity_error_ctr : std_logic; + signal adc_fifo_delay_r : std_logic_vector(5 downto 0); + signal fifo_reset_r : std_logic; + + signal valid_data_d : std_logic; + +begin + + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(2 downto 1) <= STATE_d; + DEBUG_OUT(3) <= nx_new_timestamp; + DEBUG_OUT(4) <= adc_new_data; + DEBUG_OUT(5) <= new_data_o; + DEBUG_OUT(6) <= nx_fifo_data_valid; + --DEBUG_OUT(7) <= adc_fifo_data_valid; + DEBUG_OUT(7) <= valid_data_d;--(others => '0'); + DEBUG_OUT(15 downto 8) <= nx_timestamp_reg; + --DEBUG_OUT(15 downto 8) <= (others => '0'); + + PROC_DEBUG: process(NX_TIMESTAMP_CLK_IN) + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if( RESET_IN = '1' ) then + valid_data_d <= '0'; + else + if ((nx_timestamp_reg /= x"7f") and + (nx_timestamp_reg /= x"06")) then + valid_data_d <= '1'; + else + valid_data_d <= '0'; + end if; + end if; + end if; + end process PROC_DEBUG; + + ----------------------------------------------------------------------------- + -- ADC CLK DOMAIN + ----------------------------------------------------------------------------- + + pll_adc_clk192_1: pll_adc_clk192 + port map ( + CLK => ADC_CLK_DAT_SRC_IN, + CLKOP => adc_dat_clk, + LOCK => adc_dat_clk_lock + ); + + adc_ad9222_1: entity work.adc_ad9222 + generic map ( + CHANNELS => 4, + DEVICES => 2, + RESOLUTION => 12 + ) + port map ( + CLK => CLK_IN, + CLK_ADCREF => adc_sample_clk, + CLK_ADCDAT => adc_dat_clk, + RESTART_IN => adc_reset, + ADCCLK_OUT => ADC_SAMPLE_CLK_OUT, + + ADC_DATA(0) => ADC_NX_IN(0), + ADC_DATA(1) => ADC_A_IN(0), + ADC_DATA(2) => ADC_B_IN(0), + ADC_DATA(3) => ADC_D_IN(0), + + ADC_DATA(4) => ADC_NX_IN(1), + ADC_DATA(5) => ADC_A_IN(1), + ADC_DATA(6) => ADC_B_IN(1), + ADC_DATA(7) => ADC_D_IN(1), + + ADC_DCO => ADC_DCLK_IN, + ADC_FCO => ADC_FCLK_IN, + + DATA_OUT(11 downto 0) => adc_data, + DATA_OUT(95 downto 12) => open, + + FCO_OUT => open, + DATA_VALID_OUT(0) => adc_data_valid, + DATA_VALID_OUT(1) => open, + DEBUG => open + ); + +-- pulse_to_level_1: pulse_to_level +-- generic map ( +-- NUM_CYCLES => "10000" +-- ) +-- port map ( +-- CLK_IN => CLK_IN, +-- RESET_IN => RESET_IN, +-- PULSE_IN => adc_reset_r, +-- LEVEL_OUT => adc_reset +-- ); + + adc_reset <= adc_reset_r; + +-- PROC_ADC_RESET: proc(CLK_IN) +-- begin +-- if( rising_edge(CLK_IN) ) then +-- if (RESET_IN = '1' or reset_parity_error_ctr = '1') then +-- adc_reset <= '0'; +-- else +-- if (adc_reset_start = '1') then +-- adc_reset <= '1'; +-- +-- end generate (adc_reset_start = '1'); +-- adc_reset +-- end if; +-- end if; +-- end if; + + ----------------------------------------------------------------------------- + -- NX_TIMESTAMP_CLK_IN Domain + ----------------------------------------------------------------------------- + + nx_timestamp_reg <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN); + + -- Transfer 8 to 32Bit + PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN) + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if( RESET_IN = '1' ) then + frame_byte_ctr <= (others => '0'); + nx_frame_word <= (others => '0'); + nx_new_frame <= '0'; + else + nx_new_frame <= '0'; + + case frame_byte_pos is + when "11" => nx_frame_word(31 downto 24) <= nx_timestamp_reg; + frame_byte_ctr <= frame_byte_ctr + 1; + + when "10" => nx_frame_word(23 downto 16) <= nx_timestamp_reg; + frame_byte_ctr <= frame_byte_ctr + 1; + + when "01" => nx_frame_word(15 downto 8) <= nx_timestamp_reg; + frame_byte_ctr <= frame_byte_ctr + 1; + + when "00" => nx_frame_word( 7 downto 0) <= nx_timestamp_reg; + if (frame_byte_ctr = "11") then + nx_new_frame <= '1'; + end if; + frame_byte_ctr <= (others => '0'); + end case; + end if; + end if; + end process PROC_8_TO_32_BIT; + + -- Frame Sync process + PROC_SYNC_TO_NX_FRAME: process(NX_TIMESTAMP_CLK_IN) + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if( RESET_IN = '1' ) then + frame_byte_pos <= "11"; + rs_sync_set <= '0'; + rs_sync_reset <= '0'; + else + rs_sync_set <= '0'; + rs_sync_reset <= '0'; + if (nx_new_frame = '1') then + case nx_frame_word is + when x"7f7f7f06" => + rs_sync_set <= '1'; + frame_byte_pos <= frame_byte_pos - 1; + + when x"7f7f067f" => + rs_sync_reset <= '1'; + frame_byte_pos <= frame_byte_pos - 2; + + when x"7f067f7f" => + rs_sync_reset <= '1'; + frame_byte_pos <= frame_byte_pos - 3; + + when x"067f7f7f" => + rs_sync_reset <= '1'; + frame_byte_pos <= frame_byte_pos - 4; + + when others => + frame_byte_pos <= frame_byte_pos - 1; + end case; + else + frame_byte_pos <= frame_byte_pos - 1; + end if; + end if; + end if; + end process PROC_SYNC_TO_NX_FRAME; + + -- RS FlipFlop to hold Sync Status + PROC_RS_FRAME_SYNCED: process(NX_TIMESTAMP_CLK_IN) + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (RESET_IN = '1' or rs_sync_reset = '1') then + nx_frame_synced <= '0'; + elsif (rs_sync_set = '1') then + nx_frame_synced <= '1'; + end if; + end if; + end process PROC_RS_FRAME_SYNCED; + + -- Check Parity + PROC_PARITY_CHECK: process(NX_TIMESTAMP_CLK_IN) + variable parity_bits : std_logic_vector(22 downto 0); + variable parity : std_logic; + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (RESET_IN = '1') then + parity_error <= '0'; + else + parity_error <= '0'; + if (nx_new_frame = '1' and nx_frame_synced = '1') then + -- Timestamp Bit #6 is excluded (funny nxyter-bug) + parity_bits := nx_frame_word(31) & + nx_frame_word(30 downto 24) & + nx_frame_word(21 downto 16) & + nx_frame_word(14 downto 8) & + nx_frame_word( 2 downto 1); + parity := xor_all(parity_bits); + + if (parity /= nx_frame_word(0)) then + parity_error <= '1'; + end if; + end if; + end if; + end if; + end process PROC_PARITY_CHECK; + + -- Write to FIFO + PROC_WRITE_TO_FIFO: process(NX_TIMESTAMP_CLK_IN) + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (RESET_IN = '1') then + nx_fifo_data_input <= (others => '0'); + nx_fifo_write_enable <= '0'; + else + nx_fifo_data_input <= x"deadbeef"; + nx_fifo_write_enable <= '0'; + if (nx_new_frame = '1' and nx_frame_synced = '1') then + nx_fifo_data_input <= nx_frame_word; + nx_fifo_write_enable <= '1'; + end if; + end if; + end if; + end process PROC_WRITE_TO_FIFO; + + fifo_ts_32to32_dc_1: fifo_ts_32to32_dc + port map ( + Data => nx_fifo_data_input, + WrClock => NX_TIMESTAMP_CLK_IN, + RdClock => CLK_IN, + WrEn => nx_fifo_write_enable, + RdEn => nx_fifo_read_enable, + Reset => nx_fifo_reset, + RPReset => nx_fifo_reset, + AmEmptyThresh => nx_fifo_delay_r, + Q => nx_fifo_data, + Empty => nx_fifo_empty, + Full => nx_fifo_full, + AlmostEmpty => nx_fifo_almost_empty + ); + + nx_fifo_reset <= RESET_IN or fifo_reset_r; + +-- fifo_12_adc_1: fifo_12_adc +-- port map ( +-- Data => adc_fifo_next_word, +-- Clock => CLK_IN, +-- WrEn => adc_fifo_write_enable, +-- RdEn => adc_fifo_read_enable, +-- Reset => adc_fifo_reset, +-- AmEmptyThresh => adc_fifo_delay_r, +-- Q => adc_fifo_data, +-- Empty => adc_fifo_empty, +-- Full => adc_fifo_full, +-- AlmostEmpty => adc_fifo_almost_empty +-- ); +-- +-- adc_fifo_reset <= RESET_IN; + + +-- -- Reset NX_TIMESTAMP_CLK Domain +-- PROC_NX_CLK_DOMAIN_RESET: process(CLK_IN) +-- begin +-- if( rising_edge(CLK_IN) ) then +-- if( RESET_IN = '1' ) then +-- reset_nx_domain_ctr <= (others => '0'); +-- reset_nx_domain <= '1'; +-- else +-- if (nx_clk_pulse = '1') then +-- nx_clk_pulse_ctr <= nx_clk_pulse_ctr + 1; +-- end if; +-- +-- end if; +-- +-- end if; +-- end process PROC_NX_CLK_DOMAIN_RESET; + + PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN) + begin + if(rising_edge(NX_TIMESTAMP_CLK_IN)) then + if(RESET_IN = '1' ) then + nx_clk_active_ff_0 <= '0'; + nx_clk_active_ff_1 <= '0'; + nx_clk_active_ff_2 <= '0'; + else + nx_clk_active_ff_0 <= not nx_clk_active_ff_2; + nx_clk_active_ff_1 <= nx_clk_active_ff_0; + nx_clk_active_ff_2 <= nx_clk_active_ff_1; + end if; + end if; + end process PROC_NX_CLK_ACT; + + -- Johnson Counter + PROC_ADC_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN) + begin + if(rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (RESET_IN = '1') then + johnson_ff_0 <= '0'; + johnson_ff_1 <= '0'; + else + if (adc_clk_skip = '0') then + johnson_ff_0 <= not johnson_ff_1; + johnson_ff_1 <= johnson_ff_0; + end if; + end if; + end if; + end process PROC_ADC_CLK_GENERATOR; + + PROC_ADC_CLK_DELAY_4NS: process(NX_TIMESTAMP_CLK_IN) + begin + if(falling_edge(NX_TIMESTAMP_CLK_IN)) then + if (RESET_IN = '1') then + adc_clk_inv <= '0'; + else + adc_clk_inv <= johnson_ff_0; + end if; + end if; + end process PROC_ADC_CLK_DELAY_4NS; + + adc_sample_clk <= adc_clk_inv when adc_clk_delay(0) = '1' else johnson_ff_0; + + PROC_ADC_CLK_DELAY: process(NX_TIMESTAMP_CLK_IN) + variable adc_clk_state : std_logic_vector(1 downto 0); + begin + if(rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (RESET_IN = '1') then + adc_clk_skip <= '0'; + else + adc_clk_state := johnson_ff_1 & johnson_ff_0; + adc_clk_skip <= '0'; + + if (nx_new_frame = '1') then + if (adc_clk_state /= adc_clk_delay(2 downto 1)) then + adc_clk_skip <= '1'; + end if; + end if; + end if; + end if; + end process PROC_ADC_CLK_DELAY; + + ----------------------------------------------------------------------------- + -- NX CLK_IN Domain + ----------------------------------------------------------------------------- + + -- FIFO Read Handler + PROC_NX_FIFO_READ_ENABLE: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' or fifo_reset_r = '1') then + nx_fifo_read_enable <= '0'; + nx_read_enable_pause <= '0'; + nx_fifo_data_valid_t <= '0'; + nx_fifo_data_valid <= '0'; + else + if (nx_fifo_almost_empty = '0' and nx_read_enable_pause = '0') then + nx_fifo_read_enable <= '1'; + nx_read_enable_pause <= '1'; + else + nx_fifo_read_enable <= '0'; + nx_read_enable_pause <= '0'; + end if; + + -- Delay read signal by one CLK + nx_fifo_data_valid_t <= nx_fifo_read_enable; + nx_fifo_data_valid <= nx_fifo_data_valid_t; + + end if; + end if; + end process PROC_NX_FIFO_READ_ENABLE; + + PROC_NX_FIFO_READ: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or fifo_reset_r = '1') then + nx_timestamp_t <= (others => '0'); + nx_new_timestamp <= '0'; + nx_new_timestamp_ctr <= (others => '0'); + else + if (nx_fifo_data_valid = '1') then + nx_timestamp_t <= nx_fifo_data; + nx_new_timestamp <= '1'; + nx_new_timestamp_ctr <= nx_new_timestamp_ctr + 1; + else + nx_timestamp_t <= x"deadbeef"; + nx_new_timestamp <= '0'; + end if; + end if; + end if; + end process PROC_NX_FIFO_READ; + + ----------------------------------------------------------------------------- + -- Status Counters + ----------------------------------------------------------------------------- + + -- Domain Transfers + pulse_sync_1: pulse_sync + port map ( + CLK_A_IN => NX_TIMESTAMP_CLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => rs_sync_reset, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => resync_ctr_inc + ); + + pulse_sync_2: pulse_sync + port map ( + CLK_A_IN => NX_TIMESTAMP_CLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => parity_error, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => parity_error_ctr_inc + ); + + PROC_SYNC_FRAME_SYNC: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if(RESET_IN = '1' ) then + reg_nx_frame_synced_t <= '0'; + reg_nx_frame_synced <= '0'; + else + reg_nx_frame_synced_t <= nx_frame_synced; + reg_nx_frame_synced <= reg_nx_frame_synced_t; + end if; + end if; + end process PROC_SYNC_FRAME_SYNC; + + -- Counters + PROC_RESYNC_COUNTER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or reset_resync_ctr = '1') then + resync_counter <= (others => '0'); + else + if (resync_ctr_inc = '1') then + resync_counter <= resync_counter + 1; + end if; + end if; + end if; + end process PROC_RESYNC_COUNTER; + + PROC_PARITY_ERROR_COUNTER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or reset_parity_error_ctr = '1') then + parity_error_counter <= (others => '0'); + else + if (parity_error_ctr_inc = '1') then + parity_error_counter <= parity_error_counter + 1; + end if; + end if; + end if; + end process PROC_PARITY_ERROR_COUNTER; + + + ----------------------------------------------------------------------------- + -- ADC Fifo Handler + ----------------------------------------------------------------------------- + PROC_ADC_DATA_READ: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or fifo_reset_r = '1') then + adc_data_t <= (others => '0'); + adc_new_data <= '0'; + adc_new_data_ctr <= (others => '0'); + else + if (adc_data_valid = '1') then + adc_data_t <= adc_data; + adc_new_data <= '1'; + adc_new_data_ctr <= adc_new_data_ctr + 1; + else + adc_data_t <= x"aff"; + adc_new_data <= '0'; + end if; + end if; + end if; + end process PROC_ADC_DATA_READ; + + -- ADC FIFO Write Handler +-- PROC_ADC_FIFO_WRITE_ENABLE: process(CLK_IN) +-- begin +-- if( rising_edge(CLK_IN) ) then +-- if( RESET_IN = '1' ) then +-- adc_fifo_next_word <= x"bee"; +-- adc_fifo_write_enable <= '0'; +-- else +-- if (adc_data_valid = '1' and adc_fifo_full = '0') then +-- adc_fifo_next_word <= adc_data; +-- adc_fifo_write_enable <= '1'; +-- else +-- adc_fifo_next_word <= x"bee"; +-- adc_fifo_write_enable <= '0'; +-- end if; +-- end if; +-- end if; +-- end process PROC_ADC_FIFO_WRITE_ENABLE; +-- +-- -- ADC FIFO Read Handler +-- PROC_ADC_FIFO_READ_ENABLE: process(CLK_IN) +-- begin +-- if( rising_edge(CLK_IN) ) then +-- if( RESET_IN = '1' or fifo_reset_r = '1') then +-- adc_fifo_read_enable <= '0'; +-- adc_read_enable_pause <= '0'; +-- adc_fifo_data_valid_t <= '0'; +-- adc_fifo_data_valid <= '0'; +-- else +-- if (adc_fifo_almost_empty = '0' and adc_read_enable_pause = '0') then +-- adc_fifo_read_enable <= '1'; +-- adc_read_enable_pause <= '1'; +-- else +-- adc_fifo_read_enable <= '0'; +-- adc_read_enable_pause <= '0'; +-- end if; +-- +-- -- Delay read signal by one CLK +-- adc_fifo_data_valid_t <= adc_fifo_read_enable; +-- adc_fifo_data_valid <= adc_fifo_data_valid_t; +-- +-- end if; +-- end if; +-- end process PROC_ADC_FIFO_READ_ENABLE; + +-- PROC_ADC_FIFO_READ: process(CLK_IN) +-- begin +-- if( rising_edge(CLK_IN) ) then +-- if (RESET_IN = '1' or fifo_reset_r = '1') then +-- adc_data_t <= (others => '0'); +-- adc_new_data <= '0'; +-- adc_new_data_ctr <= (others => '0'); +-- else +-- if (adc_fifo_data_valid = '1') then +-- adc_data_t <= adc_fifo_data; +-- adc_new_data <= '1'; +-- adc_new_data_ctr <= adc_new_data_ctr + 1; +-- else +-- adc_data_t <= x"aff"; +-- adc_new_data <= '0'; +-- end if; +-- end if; +-- end if; +-- end process PROC_ADC_FIFO_READ; + + ----------------------------------------------------------------------------- + -- Output handler + ----------------------------------------------------------------------------- + PROC_OUTPUT_HANDLER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or fifo_reset_r = '1') then + nx_timestamp_o <= (others => '0'); + adc_data_o <= (others => '0'); + new_data_o <= '0'; + STATE <= IDLE; + else + case STATE is + + when IDLE => + STATE_d <= "00"; + if (nx_new_timestamp = '1' and adc_new_data = '1') then + nx_timestamp_o <= nx_timestamp_t; + adc_data_o <= adc_data_t; + new_data_o <= '1'; + STATE <= IDLE; + elsif (nx_new_timestamp = '1') then + nx_timestamp_o <= nx_timestamp_t; + adc_data_o <= (others => '0'); + new_data_o <= '0'; + STATE <= WAIT_ADC; + elsif (adc_new_data = '1') then + adc_data_o <= adc_data_t; + nx_timestamp_o <= (others => '0'); + new_data_o <= '0'; + STATE <= WAIT_TIMESTAMP; + else + nx_timestamp_o <= (others => '0'); + adc_data_o <= (others => '0'); + new_data_o <= '0'; + STATE <= IDLE; + end if; + + when WAIT_ADC => + STATE_d <= "01"; + if (adc_new_data = '1') then + adc_data_o <= adc_data_t; + new_data_o <= '1'; + STATE <= IDLE; + else + new_data_o <= '0'; + STATE <= WAIT_ADC; + end if; + + when WAIT_TIMESTAMP => + STATE_d <= "10"; + if (nx_new_timestamp = '1') then + nx_timestamp_o <= nx_timestamp_t; + new_data_o <= '1'; + STATE <= IDLE; + else + new_data_o <= '0'; + STATE <= WAIT_TIMESTAMP; + end if; + + end case; + end if; + end if; + end process PROC_OUTPUT_HANDLER; + + ----------------------------------------------------------------------------- + -- TRBNet Slave Bus + ----------------------------------------------------------------------------- + + -- Give status info to the TRB Slow Control Channel + PROC_FIFO_REGISTERS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_ack_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + reset_resync_ctr <= '0'; + reset_parity_error_ctr <= '0'; + nx_fifo_delay_r <= "01000"; + adc_fifo_delay_r <= "000010"; + fifo_reset_r <= '0'; + adc_clk_delay <= "111"; + adc_reset_r <= '0'; + else + slv_data_out_o <= (others => '0'); + slv_ack_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + reset_resync_ctr <= '0'; + reset_parity_error_ctr <= '0'; + fifo_reset_r <= '0'; + adc_reset_r <= '0'; + + if (SLV_READ_IN = '1') then + case SLV_ADDR_IN is + when x"0000" => + slv_data_out_o <= nx_timestamp_t; + slv_ack_o <= '1'; + + when x"0001" => + slv_data_out_o(0) <= nx_fifo_full; + slv_data_out_o(1) <= nx_fifo_empty; + slv_data_out_o(2) <= '0'; --adc_fifo_full; + slv_data_out_o(3) <= '0'; -- adc_fifo_empty; + slv_data_out_o(4) <= nx_fifo_data_valid; + slv_data_out_o(5) <= adc_new_data; --adc_fifo_data_valid; + slv_data_out_o(29 downto 5) <= (others => '0'); + slv_data_out_o(30) <= '0'; + slv_data_out_o(31) <= reg_nx_frame_synced; + slv_ack_o <= '1'; + + when x"0002" => + slv_data_out_o(11 downto 0) <= resync_counter; + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0003" => + slv_data_out_o(11 downto 0) <= parity_error_counter; + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0004" => + slv_data_out_o( 4 downto 0) <= nx_fifo_delay_r; + slv_data_out_o(31 downto 5) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0005" => + case adc_clk_delay is + when "010" => slv_data_out_o(2 downto 0) <= "000"; + when "011" => slv_data_out_o(2 downto 0) <= "001"; + when "000" => slv_data_out_o(2 downto 0) <= "010"; + when "001" => slv_data_out_o(2 downto 0) <= "011"; + when "100" => slv_data_out_o(2 downto 0) <= "100"; + when "101" => slv_data_out_o(2 downto 0) <= "101"; + when "110" => slv_data_out_o(2 downto 0) <= "110"; + when "111" => slv_data_out_o(2 downto 0) <= "111"; + end case; + + slv_data_out_o(31 downto 3) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0006" => + slv_data_out_o(11 downto 0) <= adc_data_t; + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + end case; + + elsif (SLV_WRITE_IN = '1') then + case SLV_ADDR_IN is + when x"0001" => + adc_reset_r <= '1'; + slv_ack_o <= '1'; + + when x"0002" => + reset_resync_ctr <= '1'; + slv_ack_o <= '1'; + + when x"0003" => + reset_parity_error_ctr <= '1'; + slv_ack_o <= '1'; + + when x"0004" => + if (SLV_DATA_IN < x"0000_001c" and + SLV_DATA_IN > x"0000_0001") then + nx_fifo_delay_r <= SLV_DATA_IN(4 downto 0); + fifo_reset_r <= '1'; + end if; + slv_ack_o <= '1'; + + when x"0005" => + if (SLV_DATA_IN < x"0000_0008") then + case SLV_DATA_IN(2 downto 0) is + when "000" => adc_clk_delay <= "010"; + when "001" => adc_clk_delay <= "011"; + when "010" => adc_clk_delay <= "000"; + when "011" => adc_clk_delay <= "001"; + when "100" => adc_clk_delay <= "100"; + when "101" => adc_clk_delay <= "101"; + when "110" => adc_clk_delay <= "110"; + when "111" => adc_clk_delay <= "111"; + end case; + end if; + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + end case; + end if; + end if; + end if; + end process PROC_FIFO_REGISTERS; + + -- Output Signals + + NX_TIMESTAMP_OUT <= nx_timestamp_o; + ADC_DATA_OUT <= adc_data_o; + NEW_DATA_OUT <= new_data_o; + + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + +end Behavioral; diff --git a/nxyter/source/nx_timestamp_decode.vhd b/nxyter/source/nx_data_validate.vhd similarity index 79% rename from nxyter/source/nx_timestamp_decode.vhd rename to nxyter/source/nx_data_validate.vhd index 9ab9b7e..3082bf6 100644 --- a/nxyter/source/nx_timestamp_decode.vhd +++ b/nxyter/source/nx_data_validate.vhd @@ -6,20 +6,23 @@ library work; use work.trb_net_std.all; use work.nxyter_components.all; -entity nx_timestamp_decode is +entity nx_data_validate is port ( CLK_IN : in std_logic; RESET_IN : in std_logic; -- Inputs - NX_NEW_TIMESTAMP_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector(31 downto 0); + ADC_DATA_IN : in std_logic_vector(11 downto 0); + NEW_DATA_IN : in std_logic; -- Outputs - TIMESTAMP_OUT : out unsigned(13 downto 0); - CHANNEL_OUT : out unsigned(6 downto 0); - TIMESTAMP_STATUS_OUT : out std_logic_vector(1 downto 0); - TIMESTAMP_VALID_OUT : out std_logic; + TIMESTAMP_OUT : out std_logic_vector(13 downto 0); + CHANNEL_OUT : out std_logic_vector(6 downto 0); + TIMESTAMP_STATUS_OUT : out std_logic_vector(2 downto 0); + ADC_DATA_OUT : out std_logic_vector(11 downto 0); + DATA_VALID_OUT : out std_logic; + NX_TOKEN_RETURN_OUT : out std_logic; NX_NOMORE_DATA_OUT : out std_logic; @@ -38,25 +41,26 @@ entity nx_timestamp_decode is end entity; -architecture Behavioral of nx_timestamp_decode is +architecture Behavioral of nx_data_validate is -- Gray Decoder signal nx_timestamp : std_logic_vector(13 downto 0); signal nx_channel_id : std_logic_vector( 6 downto 0); - + -- TIMESTAMP_BITS signal new_timestamp : std_logic; signal valid_frame_bits : std_logic_vector(3 downto 0); signal status_bits : std_logic_vector(1 downto 0); signal parity_bit : std_logic; signal parity : std_logic; - signal timstamp_raw : std_logic_vector(31 downto 0); + signal adc_data : std_logic_vector(11 downto 0); -- Validate Timestamp - signal timestamp_o : unsigned(13 downto 0); - signal channel_o : unsigned(6 downto 0); - signal timestamp_status_o : std_logic_vector(1 downto 0); - signal timestamp_valid_o : std_logic; + signal timestamp_o : std_logic_vector(13 downto 0); + signal channel_o : std_logic_vector(6 downto 0); + signal timestamp_status_o : std_logic_vector(2 downto 0); + signal adc_data_o : std_logic_vector(11 downto 0); + signal data_valid_o : std_logic; signal nx_notempty_ctr : unsigned (1 downto 0); signal nx_token_return_o : std_logic; @@ -80,19 +84,22 @@ architecture Behavioral of nx_timestamp_decode is signal clear_counters : std_logic; signal nx_trigger_rate : unsigned(19 downto 0); + signal invalid_adc : std_logic; + begin -- Debug Line - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= NX_NEW_TIMESTAMP_IN; - DEBUG_OUT(2) <= timestamp_valid_o; - DEBUG_OUT(3) <= '0'; - DEBUG_OUT(5 downto 4) <= status_bits; - DEBUG_OUT(6) <= parity; - DEBUG_OUT(7) <= nx_token_return_o; - DEBUG_OUT(8) <= nx_nomore_data_o; +-- DEBUG_OUT(0) <= CLK_IN; +-- DEBUG_OUT(1) <= new_timestamp; +-- DEBUG_OUT(2) <= nx_token_return_o;-- new_timestamp; + DEBUG_OUT(0) <= data_valid_o; + DEBUG_OUT(3 downto 1) <= channel_o(2 downto 0); + DEBUG_OUT(15 downto 4) <= adc_data; + --DEBUG_OUT(6 downto 4) <= timestamp_status_o; + --DEBUG_OUT(7) <= nx_token_return_o; + --DEBUG_OUT(8) <= invalid_adc;--nx_nomore_data_o; - DEBUG_OUT(15 downto 9) <= nx_channel_id; + --DEBUG_OUT(15 downto 9) <= channel_o; ----------------------------------------------------------------------------- -- Gray Decoder for Timestamp and Chgannel Id @@ -132,7 +139,7 @@ begin parity_bit <= '0'; parity <= '0'; new_timestamp <= '0'; - timstamp_raw <= (others => '0'); + adc_data <= (others => '0'); else -- Timestamp Bit #6 is excluded (funny nxyter-bug) parity_bits := NX_TIMESTAMP_IN(31 downto 24) & @@ -144,9 +151,9 @@ begin parity_bit <= '0'; parity <= '0'; new_timestamp <= '0'; - timstamp_raw <= (others => '0'); + adc_data <= (others => '0'); - if (NX_NEW_TIMESTAMP_IN = '1') then + if (NEW_DATA_IN = '1') then valid_frame_bits(3) <= NX_TIMESTAMP_IN(31); valid_frame_bits(2) <= NX_TIMESTAMP_IN(23); valid_frame_bits(1) <= NX_TIMESTAMP_IN(15); @@ -154,7 +161,7 @@ begin status_bits <= NX_TIMESTAMP_IN(2 downto 1); parity_bit <= NX_TIMESTAMP_IN(0); parity <= xor_all(parity_bits); - timstamp_raw <= NX_TIMESTAMP_IN; + adc_data <= ADC_DATA_IN; new_timestamp <= '1'; end if; end if; @@ -172,7 +179,8 @@ begin timestamp_o <= (others => '0'); channel_o <= (others => '0'); timestamp_status_o <= (others => '0'); - timestamp_valid_o <= '0'; + adc_data_o <= (others => '0'); + data_valid_o <= '0'; nx_notempty_ctr <= (others => '0'); nx_token_return_o <= '0'; nx_nomore_data_o <= '1'; @@ -188,10 +196,13 @@ begin timestamp_o <= (others => '0'); channel_o <= (others => '0'); timestamp_status_o <= (others => '0'); - timestamp_valid_o <= '0'; + adc_data_o <= (others => '0'); + data_valid_o <= '0'; nx_token_return_o <= '0'; nx_nomore_data_o <= '0'; - + + invalid_adc <= '0'; + if (new_timestamp = '1') then case valid_frame_bits is when "1000" => @@ -202,7 +213,8 @@ begin ---- Check Parity if ((parity_bit /= parity) and (clear_counters = '0')) then - parity_error_ctr <= parity_error_ctr + 1; + timestamp_status_o(0) <= '1'; + parity_error_ctr <= parity_error_ctr + 1; end if; -- Check PileUp @@ -211,18 +223,23 @@ begin end if; -- Take Timestamp - timestamp_o <= unsigned(nx_timestamp); - channel_o <= unsigned(nx_channel_id); - timestamp_status_o <= status_bits; - timestamp_valid_o <= '1'; + timestamp_o <= nx_timestamp; + channel_o <= nx_channel_id; + timestamp_status_o(2 downto 1) <= status_bits; + adc_data_o <= adc_data; + data_valid_o <= '1'; - nx_notempty_ctr <= (others => '0'); + nx_notempty_ctr <= (others => '0'); -- Rate Counter if (nx_rate_timer < x"186a0") then nx_valid_ctr <= nx_valid_ctr + 1; end if; - + + if (adc_data = x"aff") then + invalid_adc <= '1'; + end if; + when "0000" => case nx_notempty_ctr is when "00" => @@ -232,7 +249,7 @@ begin when "01" => nx_nomore_data_o <= '1'; nx_notempty_ctr <= nx_notempty_ctr + 1; - + when others => null; end case; @@ -347,7 +364,8 @@ begin TIMESTAMP_OUT <= timestamp_o; CHANNEL_OUT <= channel_o; TIMESTAMP_STATUS_OUT <= timestamp_status_o; - TIMESTAMP_VALID_OUT <= timestamp_valid_o; + ADC_DATA_OUT <= adc_data_o; + DATA_VALID_OUT <= data_valid_o; NX_TOKEN_RETURN_OUT <= nx_token_return_o; NX_NOMORE_DATA_OUT <= nx_nomore_data_o; diff --git a/nxyter/source/nx_timestamp_fifo_read.vhd b/nxyter/source/nx_timestamp_fifo_read.vhd deleted file mode 100644 index af82fd8..0000000 --- a/nxyter/source/nx_timestamp_fifo_read.vhd +++ /dev/null @@ -1,535 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.nxyter_components.all; - -entity nx_timestamp_fifo_read is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - -- nXyter Timestamp Ports - NX_TIMESTAMP_CLK_IN : in std_logic; - NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); - NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0); - NX_NEW_TIMESTAMP_OUT : out std_logic; - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end entity; - -architecture Behavioral of nx_timestamp_fifo_read is - - ----------------------------------------------------------------------------- - -- NX_TIMESTAMP_CLK Domain - ----------------------------------------------------------------------------- - - -- FIFO Input Handler - signal nx_timestamp_reg_t : std_logic_vector(7 downto 0); - signal nx_timestamp_reg : std_logic_vector(7 downto 0); - signal fifo_full : std_logic; - signal fifo_reset : std_logic; - - -- NX_TIMESTAMP_IN Process - signal frame_byte_ctr : unsigned(1 downto 0); - signal fifo_32bit_word : std_logic_vector(31 downto 0); - signal nx_new_frame : std_logic; - - -- Frame Sync Process - signal frame_byte_pos : unsigned(1 downto 0); - - -- RS Sync FlipFlop - signal nx_frame_synced : std_logic; - signal rs_sync_set : std_logic; - signal rs_sync_reset : std_logic; - - -- Parity Check - signal parity_error : std_logic; - - -- Write to FIFO Handler - signal fifo_data_input : std_logic_vector(31 downto 0); - signal fifo_write_enable : std_logic; - - ----------------------------------------------------------------------------- - -- CLK_IN Domain - ----------------------------------------------------------------------------- - - -- PROC FIFO_READ - signal nx_new_timestamp_o : std_logic; - signal register_fifo_data : std_logic_vector(31 downto 0); - - signal fifo_almost_empty_tt : std_logic; - signal fifo_almost_empty_t : std_logic; - - - -- FIFO Output Handler - signal fifo_out : std_logic_vector(31 downto 0); - signal fifo_empty : std_logic; - signal fifo_almost_empty : std_logic; - signal fifo_read_enable : std_logic; - signal fifo_data_valid_t : std_logic; - signal fifo_data_valid : std_logic; - signal read_enable_pause : std_logic; - - -- Resync Counter Process - signal resync_counter : unsigned(11 downto 0); - signal resync_ctr_inc : std_logic; - signal nx_clk_active : std_logic; - - -- Parity Error Counter Process - signal parity_error_counter : unsigned(11 downto 0); - signal parity_error_ctr_inc : std_logic; - - signal reg_nx_frame_synced_t : std_logic; - signal reg_nx_frame_synced : std_logic; - - -- Slave Bus - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - - signal reset_resync_ctr : std_logic; - signal reset_parity_error_ctr : std_logic; - signal fifo_delay_r : std_logic_vector(5 downto 0); - signal fifo_reset_r : std_logic; - -begin - - DEBUG_OUT(0) <= CLK_IN; --NX_TIMESTAMP_CLK_IN; - DEBUG_OUT(1) <= parity_error; - DEBUG_OUT(2) <= nx_new_frame; - DEBUG_OUT(3) <= rs_sync_set; - DEBUG_OUT(4) <= rs_sync_reset; - DEBUG_OUT(5) <= nx_frame_synced; - DEBUG_OUT(7 downto 6) <= frame_byte_pos; - - DEBUG_OUT(8) <= fifo_write_enable; - DEBUG_OUT(9) <= fifo_read_enable; - DEBUG_OUT(10) <= nx_new_timestamp_o; - DEBUG_OUT(11) <= fifo_data_valid; - DEBUG_OUT(12) <= nx_clk_active; - DEBUG_OUT(13) <= resync_ctr_inc; - DEBUG_OUT(14) <= parity_error_ctr_inc; - DEBUG_OUT(15) <= reg_nx_frame_synced; - - - ---DEBUG_OUT(15 downto 8) <= fifo_32bit_word(15 downto 8); - - --- DEBUG_OUT(6) <= nx_new_timestamp_o; --- DEBUG_OUT(7) <= fifo_almost_empty; --- DEBUG_OUT(8) <= nx_frame_synced; --- DEBUG_OUT(9) <= rs_sync_reset; --- DEBUG_OUT(11 downto 10) <= frame_tag_pos; --- DEBUG_OUT(12) <= fifo_full; --- DEBUG_OUT(15 downto 13) <= (others => '0'); - - - --DEBUG_OUT(8 downto 1) <= fifo_out(7 downto 0); --nx_timestamp_reg_t when rising_edge(NX_TIMESTAMP_CLK_IN) ; - - ----------------------------------------------------------------------------- - -- NX_TIMESTAMP_CLK_IN Domain - ----------------------------------------------------------------------------- - - nx_timestamp_reg <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN); - - -- Transfer 8 to 32Bit - PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN) - begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if( RESET_IN = '1' ) then - frame_byte_ctr <= (others => '0'); - fifo_32bit_word <= (others => '0'); - nx_new_frame <= '0'; - else - nx_new_frame <= '0'; - - case frame_byte_pos is - when "11" => fifo_32bit_word(31 downto 24) <= nx_timestamp_reg; - frame_byte_ctr <= frame_byte_ctr + 1; - - when "10" => fifo_32bit_word(23 downto 16) <= nx_timestamp_reg; - frame_byte_ctr <= frame_byte_ctr + 1; - - when "01" => fifo_32bit_word(15 downto 8) <= nx_timestamp_reg; - frame_byte_ctr <= frame_byte_ctr + 1; - - when "00" => fifo_32bit_word( 7 downto 0) <= nx_timestamp_reg; - if (frame_byte_ctr = "11") then - nx_new_frame <= '1'; - end if; - frame_byte_ctr <= (others => '0'); - end case; - end if; - end if; - end process PROC_8_TO_32_BIT; - - -- Frame Sync process - PROC_SYNC_TO_NX_FRAME: process(NX_TIMESTAMP_CLK_IN) - begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if( RESET_IN = '1' ) then - frame_byte_pos <= "11"; - rs_sync_set <= '0'; - rs_sync_reset <= '0'; - else - rs_sync_set <= '0'; - rs_sync_reset <= '0'; - if (nx_new_frame = '1') then - case fifo_32bit_word is - when x"7f7f7f06" => - rs_sync_set <= '1'; - frame_byte_pos <= frame_byte_pos - 1; - - when x"7f7f067f" => - rs_sync_reset <= '1'; - frame_byte_pos <= frame_byte_pos - 2; - - when x"7f067f7f" => - rs_sync_reset <= '1'; - frame_byte_pos <= frame_byte_pos - 3; - - when x"067f7f7f" => - rs_sync_reset <= '1'; - frame_byte_pos <= frame_byte_pos - 4; - - when others => - frame_byte_pos <= frame_byte_pos - 1; - end case; - else - frame_byte_pos <= frame_byte_pos - 1; - end if; - end if; - end if; - end process PROC_SYNC_TO_NX_FRAME; - - -- RS FlipFlop to hold Sync Status - PROC_RS_FRAME_SYNCED: process(NX_TIMESTAMP_CLK_IN) - begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if (RESET_IN = '1' or rs_sync_reset = '1') then - nx_frame_synced <= '0'; - elsif (rs_sync_set = '1') then - nx_frame_synced <= '1'; - end if; - end if; - end process PROC_RS_FRAME_SYNCED; - - -- Check Parity - PROC_PARITY_CHECK: process(NX_TIMESTAMP_CLK_IN) - variable parity_bits : std_logic_vector(22 downto 0); - variable parity : std_logic; - begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if (RESET_IN = '1') then - parity_error <= '0'; - else - parity_error <= '0'; - if (nx_new_frame = '1' and nx_frame_synced = '1') then - -- Timestamp Bit #6 is excluded (funny nxyter-bug) - parity_bits := fifo_32bit_word(31) & - fifo_32bit_word(30 downto 24) & - fifo_32bit_word(21 downto 16) & - fifo_32bit_word(14 downto 8) & - fifo_32bit_word( 2 downto 1); - parity := xor_all(parity_bits); - - if (parity /= fifo_32bit_word(0)) then - parity_error <= '1'; - end if; - end if; - end if; - end if; - end process PROC_PARITY_CHECK; - - -- Write to FIFO - PROC_WRITE_TO_FIFO: process(NX_TIMESTAMP_CLK_IN) - begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if (RESET_IN = '1') then - fifo_data_input <= (others => '0'); - fifo_write_enable <= '0'; - else - fifo_data_input <= x"deadbeef"; - fifo_write_enable <= '0'; - if (nx_new_frame = '1' and nx_frame_synced = '1') then - fifo_data_input <= fifo_32bit_word; - fifo_write_enable <= '1'; - end if; - end if; - end if; - end process PROC_WRITE_TO_FIFO; - - fifo_32to32_dc_1: fifo_32to32_dc - port map ( - Data => fifo_data_input, - WrClock => NX_TIMESTAMP_CLK_IN, - RdClock => CLK_IN, - WrEn => fifo_write_enable, - RdEn => fifo_read_enable, - Reset => fifo_reset, - RPReset => fifo_reset, - AmEmptyThresh => fifo_delay_r, - Q => fifo_out, - Empty => fifo_empty, - Full => fifo_full, - AlmostEmpty => fifo_almost_empty - ); - - fifo_reset <= (RESET_IN or fifo_reset_r); - --- -- Reset NX_TIMESTAMP_CLK Domain --- PROC_NX_CLK_DOMAIN_RESET: process(CLK_IN) --- begin --- if( rising_edge(CLK_IN) ) then --- if( RESET_IN = '1' ) then --- reset_nx_domain_ctr <= (others => '0'); --- reset_nx_domain <= '1'; --- else --- if (nx_clk_pulse = '1') then --- nx_clk_pulse_ctr <= nx_clk_pulse_ctr + 1; --- end if; --- --- end if; --- --- end if; --- end process PROC_NX_CLK_DOMAIN_RESET; - - PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN) - begin - if(rising_edge(NX_TIMESTAMP_CLK_IN)) then - if(RESET_IN = '1' ) then - nx_clk_active <= '0'; - else - nx_clk_active <= not nx_clk_active; - end if; - end if; - end process PROC_NX_CLK_ACT; - - ----------------------------------------------------------------------------- - -- CLK_IN Domain - ----------------------------------------------------------------------------- - - -- FIFO Read Handler - PROC_FIFO_READ_ENABLE: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - fifo_read_enable <= '0'; - read_enable_pause <= '0'; - fifo_data_valid_t <= '0'; - fifo_data_valid <= '0'; - else - if (fifo_almost_empty = '0' and read_enable_pause = '0') then - fifo_read_enable <= '1'; - read_enable_pause <= '1'; - else - fifo_read_enable <= '0'; - read_enable_pause <= '0'; - end if; - - -- Delay read signal by one CLK - fifo_data_valid_t <= fifo_read_enable; - fifo_data_valid <= fifo_data_valid_t; - - end if; - end if; - end process PROC_FIFO_READ_ENABLE; - - PROC_FIFO_READ: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1') then - nx_new_timestamp_o <= '0'; - register_fifo_data <= (others => '0'); - else - nx_new_timestamp_o <= '0'; - register_fifo_data <= x"affebabe"; - - if (fifo_data_valid = '1') then - register_fifo_data <= fifo_out; - nx_new_timestamp_o <= '1'; - end if; - end if; - end if; - end process PROC_FIFO_READ; - - ----------------------------------------------------------------------------- - -- Status Counters - ----------------------------------------------------------------------------- - - -- Domain Transfers - pulse_sync_1: pulse_sync - port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_IN, - PULSE_A_IN => rs_sync_reset, - CLK_B_IN => CLK_IN, - RESET_B_IN => RESET_IN, - PULSE_B_OUT => resync_ctr_inc - ); - - pulse_sync_2: pulse_sync - port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_IN, - PULSE_A_IN => parity_error, - CLK_B_IN => CLK_IN, - RESET_B_IN => RESET_IN, - PULSE_B_OUT => parity_error_ctr_inc - ); - - PROC_SYNC_FRAME_SYNC: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if(RESET_IN = '1' ) then - reg_nx_frame_synced_t <= '0'; - reg_nx_frame_synced <= '0'; - else - reg_nx_frame_synced_t <= nx_frame_synced; - reg_nx_frame_synced <= reg_nx_frame_synced_t; - end if; - end if; - end process PROC_SYNC_FRAME_SYNC; - - -- Counters - PROC_RESYNC_COUNTER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1' or reset_resync_ctr = '1') then - resync_counter <= (others => '0'); - else - if (resync_ctr_inc = '1') then - resync_counter <= resync_counter + 1; - end if; - end if; - end if; - end process PROC_RESYNC_COUNTER; - - PROC_PARITY_ERROR_COUNTER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1' or reset_parity_error_ctr = '1') then - parity_error_counter <= (others => '0'); - else - if (parity_error_ctr_inc = '1') then - parity_error_counter <= parity_error_counter + 1; - end if; - end if; - end if; - end process PROC_PARITY_ERROR_COUNTER; - - ----------------------------------------------------------------------------- - -- TRBNet Slave Bus - ----------------------------------------------------------------------------- - - -- Give status info to the TRB Slow Control Channel - PROC_FIFO_REGISTERS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - slv_data_out_o <= (others => '0'); - slv_ack_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - reset_resync_ctr <= '0'; - reset_parity_error_ctr <= '0'; - fifo_delay_r <= "000010"; - fifo_reset_r <= '0'; - else - slv_data_out_o <= (others => '0'); - slv_ack_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - reset_resync_ctr <= '0'; - reset_parity_error_ctr <= '0'; - fifo_reset_r <= '0'; - - if (SLV_READ_IN = '1') then - case SLV_ADDR_IN is - when x"0000" => - slv_data_out_o <= register_fifo_data; - slv_ack_o <= '1'; - - when x"0001" => - slv_data_out_o(0) <= fifo_full; - slv_data_out_o(1) <= fifo_empty; - slv_data_out_o(2) <= fifo_almost_empty; - slv_data_out_o(3) <= '0'; - slv_data_out_o(4) <= fifo_data_valid; - slv_data_out_o(29 downto 5) <= (others => '0'); - slv_data_out_o(30) <= '0'; - slv_data_out_o(31) <= reg_nx_frame_synced; - slv_ack_o <= '1'; - - when x"0002" => - slv_data_out_o(11 downto 0) <= resync_counter; - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; - - when x"0003" => - slv_data_out_o(11 downto 0) <= parity_error_counter; - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; - - when x"0004" => - slv_data_out_o( 5 downto 0) <= fifo_delay_r; - slv_data_out_o(31 downto 6) <= (others => '0'); - slv_ack_o <= '1'; - - when others => - slv_unknown_addr_o <= '1'; - end case; - - elsif (SLV_WRITE_IN = '1') then - case SLV_ADDR_IN is - when x"0002" => - reset_resync_ctr <= '1'; - slv_ack_o <= '1'; - - when x"0003" => - reset_parity_error_ctr <= '1'; - slv_ack_o <= '1'; - - when x"0004" => - if (SLV_DATA_IN < x"0000003c" and - SLV_DATA_IN > x"00000001") then - fifo_delay_r <= SLV_DATA_IN(5 downto 0); - fifo_reset_r <= '1'; - end if; - slv_ack_o <= '1'; - - when others => - slv_unknown_addr_o <= '1'; - end case; - end if; - end if; - end if; - end process PROC_FIFO_REGISTERS; - - -- Output Signals - NX_TIMESTAMP_OUT <= register_fifo_data; - NX_NEW_TIMESTAMP_OUT <= nx_new_timestamp_o; - - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; - -end Behavioral; diff --git a/nxyter/source/nx_trigger_generator.vhd b/nxyter/source/nx_trigger_generator.vhd index 70f4179..d556817 100644 --- a/nxyter/source/nx_trigger_generator.vhd +++ b/nxyter/source/nx_trigger_generator.vhd @@ -61,11 +61,12 @@ begin -- Debug Line DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= TRIGGER_OUT; + DEBUG_OUT(1) <= trigger_o; DEBUG_OUT(2) <= start_cycle; DEBUG_OUT(3) <= wait_timer_done; DEBUG_OUT(4) <= ts_reset_o; - DEBUG_OUT(7 downto 5) <= (others => '0'); + DEBUG_OUT(5) <= testpulse_o; + DEBUG_OUT(7 downto 6) <= (others => '0'); DEBUG_OUT(15 downto 8) <= trigger_cycle_ctr; -- Timer diff --git a/nxyter/source/nx_timestamp_process.vhd b/nxyter/source/nx_trigger_validate.vhd similarity index 93% rename from nxyter/source/nx_timestamp_process.vhd rename to nxyter/source/nx_trigger_validate.vhd index c4c0b89..b2d56f9 100644 --- a/nxyter/source/nx_timestamp_process.vhd +++ b/nxyter/source/nx_trigger_validate.vhd @@ -6,18 +6,20 @@ library work; use work.trb_net_std.all; use work.nxyter_components.all; -entity nx_timestamp_process is +entity nx_trigger_validate is port ( CLK_IN : in std_logic; RESET_IN : in std_logic; -- Inputs - TIMESTAMP_CLK_IN : in std_logic; + DATA_CLK_IN : in std_logic; + TIMESTAMP_IN : in std_logic_vector(13 downto 0); + CHANNEL_IN : in std_logic_vector(6 downto 0); + TIMESTAMP_STATUS_IN : in std_logic_vector(2 downto 0); + ADC_DATA_IN : in std_logic_vector(11 downto 0); NX_TOKEN_RETURN_IN : in std_logic; NX_NOMORE_DATA_IN : in std_logic; - TIMESTAMP_IN : in unsigned(13 downto 0); - CHANNEL_IN : in unsigned(6 downto 0); - TIMESTAMP_STATUS_IN : in std_logic_vector(1 downto 0); + TIMESTAMP_REF_IN : in unsigned(11 downto 0); TRIGGER_IN : in std_logic; @@ -42,7 +44,7 @@ entity nx_timestamp_process is end entity; -architecture Behavioral of nx_timestamp_process is +architecture Behavioral of nx_trigger_validate is -- Sync Ref signal timestamp_ref_x : unsigned(11 downto 0); @@ -167,16 +169,16 @@ begin out_of_window_h <= '0'; ch_status_cmd_pr <= CS_NONE; - if (store_to_fifo = '1' and TIMESTAMP_CLK_IN = '1') then + if (store_to_fifo = '1' and DATA_CLK_IN = '1') then ts_ref := timestamp_ref - x"010"; window_lower_thr := trigger_window_delay; window_upper_thr := window_lower_thr + trigger_window_width; - deltaT := TIMESTAMP_IN(13 downto 2) - ts_ref; + deltaT := unsigned(TIMESTAMP_IN(13 downto 2)) - ts_ref; case readout_mode is when x"0" => -- RefValue + valid and window filter - if (TIMESTAMP_STATUS_IN(0) = '0') then + if (TIMESTAMP_STATUS_IN(1) = '0') then if (deltaT < window_lower_thr) then out_of_window_l <= '1'; data_clk_o <= '0'; @@ -191,12 +193,14 @@ begin ch_status_cmd_pr <= CS_SET_DONE; else --data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0); - data_o(11 downto 0) <= deltaT; - data_o(15 downto 12) <= (others => '0'); - data_o(22 downto 16) <= CHANNEL_IN; - data_o(27 downto 23) <= (others => '0'); - data_o(29 downto 28) <= TIMESTAMP_STATUS_IN; - data_o(31 downto 30) <= (others => '0'); + data_o(11 downto 0) <= deltaT; + data_o(15 downto 12) <= (others => '0'); + --data_o(22 downto 16) <= CHANNEL_IN; + --data_o(27 downto 23) <= (others => '0'); + --data_o(30 downto 28) <= TIMESTAMP_STATUS_IN; + --data_o(31) <= '0'; + data_o(27 downto 16) <= ADC_DATA_IN; + data_o(31 downto 28) <= (others => '0'); data_clk_o <= '1'; -- IN LUT-Data bit setzten. channel_index <= CHANNEL_IN; @@ -205,44 +209,52 @@ begin end if; when x"1" => -- RefValue + valid filter - if (TIMESTAMP_STATUS_IN(0) = '0') then + if (TIMESTAMP_STATUS_IN(1) = '0') then --data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0); data_o(11 downto 0) <= deltaT; data_o(15 downto 12) <= (others => '0'); - data_o(22 downto 16) <= CHANNEL_IN; - data_o(27 downto 23) <= (others => '0'); - data_o(29 downto 28) <= TIMESTAMP_STATUS_IN; - data_o(31 downto 30) <= (others => '0'); + -- data_o(22 downto 16) <= CHANNEL_IN; + -- data_o(27 downto 23) <= (others => '0'); + -- data_o(30 downto 28) <= TIMESTAMP_STATUS_IN; + -- data_o(31) <= '0'; + data_o(27 downto 16) <= ADC_DATA_IN; + data_o(31 downto 28) <= (others => '0'); data_clk_o <= '1'; end if; when x"3" => -- RefValue + valid filter - if (TIMESTAMP_STATUS_IN(0) = '0') then + if (TIMESTAMP_STATUS_IN(1) = '0') then data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2); data_o(13 downto 12) <= (others => '0'); data_o(15 downto 14) <= (others => '0'); - data_o(27 downto 16) <= ts_ref; - data_o(31 downto 28) <= (others => '0'); + -- data_o(27 downto 16) <= ts_ref; + -- data_o(31) <= '0'; + data_o(27 downto 16) <= ADC_DATA_IN; + data_o(31 downto 28) <= (others => '0'); data_clk_o <= '1'; end if; when x"4" => -- RawValue data_o(13 downto 0) <= TIMESTAMP_IN; data_o(15 downto 14) <= (others => '0'); - data_o(22 downto 16) <= CHANNEL_IN; - data_o(27 downto 23) <= (others => '0'); - data_o(29 downto 28) <= TIMESTAMP_STATUS_IN; - data_o(31 downto 30) <= (others => '0'); + --data_o(22 downto 16) <= CHANNEL_IN; + --data_o(27 downto 23) <= (others => '0'); + --data_o(30 downto 28) <= TIMESTAMP_STATUS_IN; + --data_o(31) <= '0'; + data_o(27 downto 16) <= ADC_DATA_IN; + data_o(31 downto 28) <= (others => '0'); data_clk_o <= '1'; when x"5" => -- RawValue + valid filter - if (TIMESTAMP_STATUS_IN(0) = '0') then + if (TIMESTAMP_STATUS_IN(1) = '0') then data_o(13 downto 0) <= TIMESTAMP_IN; data_o(15 downto 14) <= (others => '0'); - data_o(22 downto 16) <= CHANNEL_IN; - data_o(27 downto 23) <= (others => '0'); - data_o(29 downto 28) <= TIMESTAMP_STATUS_IN; - data_o(31 downto 30) <= (others => '0'); + --data_o(22 downto 16) <= CHANNEL_IN; + --data_o(27 downto 23) <= (others => '0'); + --data_o(30 downto 28) <= TIMESTAMP_STATUS_IN; + --data_o(31) <= '0'; + data_o(27 downto 16) <= ADC_DATA_IN; + data_o(31 downto 28) <= (others => '0'); data_clk_o <= '1'; end if; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 05424f4..f2bbd96 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -30,7 +30,7 @@ component nXyter_FEE_board ADC_FCLK_IN : in std_logic_vector(1 downto 0); ADC_DCLK_IN : in std_logic_vector(1 downto 0); - ADC_SC_CLK32_OUT : out std_logic; + ADC_SAMPLE_CLK_OUT : out std_logic; ADC_A_IN : in std_logic_vector(1 downto 0); ADC_B_IN : in std_logic_vector(1 downto 0); ADC_NX_IN : in std_logic_vector(1 downto 0); @@ -249,7 +249,7 @@ component clock10MHz ); end component; -component fifo_32to32_dc +component fifo_ts_32to32_dc port ( Data : in std_logic_vector(31 downto 0); WrClock : in std_logic; @@ -258,28 +258,11 @@ component fifo_32to32_dc RdEn : in std_logic; Reset : in std_logic; RPReset : in std_logic; - AmEmptyThresh : in std_logic_vector(5 downto 0); + AmEmptyThresh : in std_logic_vector(4 downto 0); Q : out std_logic_vector(31 downto 0); Empty : out std_logic; Full : out std_logic; - AlmostEmpty : out std_logic - ); -end component; - -component fifo_6to6_dc - port ( - Data : in std_logic_vector(5 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - AmEmptyThresh : in std_logic_vector(5 downto 0); - Q : out std_logic_vector(5 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic + AlmostEmpty : out std_logic ); end component; @@ -296,16 +279,23 @@ component fifo_32_data ); end component; -component nx_timestamp_fifo_read +component nx_data_receiver port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - NX_TIMESTAMP_CLK_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); + ADC_CLK_DAT_SRC_IN : in std_logic; + ADC_FCLK_IN : in std_logic_vector(1 downto 0); + ADC_DCLK_IN : in std_logic_vector(1 downto 0); + ADC_SAMPLE_CLK_OUT : out std_logic; + ADC_A_IN : in std_logic_vector(1 downto 0); + ADC_B_IN : in std_logic_vector(1 downto 0); + ADC_NX_IN : in std_logic_vector(1 downto 0); + ADC_D_IN : in std_logic_vector(1 downto 0); NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0); - NX_NEW_TIMESTAMP_OUT : out std_logic; - + ADC_DATA_OUT : out std_logic_vector(11 downto 0); + NEW_DATA_OUT : out std_logic; SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -314,21 +304,47 @@ component nx_timestamp_fifo_read SLV_ACK_OUT : out std_logic; SLV_NO_MORE_DATA_OUT : out std_logic; SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end component; +component nx_data_validate + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + NX_TIMESTAMP_IN : in std_logic_vector(31 downto 0); + ADC_DATA_IN : in std_logic_vector(11 downto 0); + NEW_DATA_IN : in std_logic; + TIMESTAMP_OUT : out std_logic_vector(13 downto 0); + CHANNEL_OUT : out std_logic_vector(6 downto 0); + TIMESTAMP_STATUS_OUT : out std_logic_vector(2 downto 0); + ADC_DATA_OUT : out std_logic_vector(11 downto 0); + DATA_VALID_OUT : out std_logic; + NX_TOKEN_RETURN_OUT : out std_logic; + NX_NOMORE_DATA_OUT : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; DEBUG_OUT : out std_logic_vector(15 downto 0) ); end component; -component nx_timestamp_process +component nx_trigger_validate port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - TIMESTAMP_CLK_IN : in std_logic; + DATA_CLK_IN : in std_logic; + TIMESTAMP_IN : in std_logic_vector(13 downto 0); + CHANNEL_IN : in std_logic_vector(6 downto 0); + TIMESTAMP_STATUS_IN : in std_logic_vector(2 downto 0); + ADC_DATA_IN : in std_logic_vector(11 downto 0); NX_TOKEN_RETURN_IN : in std_logic; NX_NOMORE_DATA_IN : in std_logic; - TIMESTAMP_IN : in unsigned(13 downto 0); - CHANNEL_IN : in unsigned(6 downto 0); - TIMESTAMP_STATUS_IN : in std_logic_vector(1 downto 0); TIMESTAMP_REF_IN : in unsigned(11 downto 0); TRIGGER_IN : in std_logic; PROCESS_BUSY_OUT : out std_logic; @@ -343,7 +359,8 @@ component nx_timestamp_process SLV_ACK_OUT : out std_logic; SLV_NO_MORE_DATA_OUT : out std_logic; SLV_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0)); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); end component; component level_to_pulse @@ -355,6 +372,18 @@ component level_to_pulse ); end component; +component pulse_to_level + generic ( + NUM_CYCLES : unsigned(4 downto 0) := "11111" + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + PULSE_IN : in std_logic; + LEVEL_OUT : out std_logic + ); +end component; + component Gray_Decoder generic ( WIDTH : integer @@ -367,7 +396,6 @@ component Gray_Decoder ); end component; - component Gray_Encoder generic ( WIDTH : integer @@ -399,27 +427,13 @@ component nx_data_buffer ); end component; -component nx_timestamp_decode +component pll_125_hub port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - NX_NEW_TIMESTAMP_IN : in std_logic; - NX_TIMESTAMP_IN : in std_logic_vector(31 downto 0); - TIMESTAMP_OUT : out unsigned(13 downto 0); - CHANNEL_OUT : out unsigned(6 downto 0); - TIMESTAMP_STATUS_OUT : out std_logic_vector(1 downto 0); - TIMESTAMP_VALID_OUT : out std_logic; - NX_TOKEN_RETURN_OUT : out std_logic; - NX_NOMORE_DATA_OUT : out std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0)); + CLK : in std_logic; + CLKOP : out std_logic; + CLKOK : out std_logic; + LOCK : out std_logic + ); end component; component pll_nx_clk256 @@ -540,7 +554,10 @@ component adc_receiver port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - CLK_ADC_IN : in std_logic; + RESTART_IN : in std_logic; + SAMPLE_CLK_IN : in std_logic; + DATA_CLK_SRC_IN : in std_logic; + ADC_FCLK_IN : in std_logic_vector(1 downto 0); ADC_DCLK_IN : in std_logic_vector(1 downto 0); ADC_SC_CLK32_OUT : out std_logic; @@ -548,6 +565,10 @@ component adc_receiver ADC_B_IN : in std_logic_vector(1 downto 0); ADC_NX_IN : in std_logic_vector(1 downto 0); ADC_D_IN : in std_logic_vector(1 downto 0); + + DATA_OUT : out std_logic_vector(11 downto 0); + DATA_VALID_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) ); end component; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index 75bf3cc..7b3c539 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -40,7 +40,7 @@ entity nXyter_FEE_board is -- ADC nXyter Pulse Hight Ports ADC_FCLK_IN : in std_logic_vector(1 downto 0); ADC_DCLK_IN : in std_logic_vector(1 downto 0); - ADC_SC_CLK32_OUT : out std_logic; + ADC_SAMPLE_CLK_OUT : out std_logic; ADC_A_IN : in std_logic_vector(1 downto 0); ADC_B_IN : in std_logic_vector(1 downto 0); ADC_NX_IN : in std_logic_vector(1 downto 0); @@ -94,17 +94,20 @@ architecture Behavioral of nXyter_FEE_board is signal spi_sdi : std_logic; signal spi_sdo : std_logic; - -- Timestamp FIFO Read - signal nx_timestamp : std_logic_vector(31 downto 0); - signal nx_new_timestamp : std_logic; - signal adc_clk_o : std_logic; - - -- Timestamp Decode Handlers - signal timestamp_data : std_logic_vector(31 downto 0); - signal timestamp : unsigned(13 downto 0); - signal timestamp_channel_id : unsigned(6 downto 0); - signal timestamp_status : std_logic_vector(1 downto 0); - signal timestamp_valid : std_logic; + -- Data Receiver + signal adc_data_valid : std_logic; + signal adc_new_data : std_logic; + + signal new_timestamp : std_logic_vector(31 downto 0); + signal new_adc_data : std_logic_vector(11 downto 0); + signal new_data : std_logic; + + -- Data Validate + signal timestamp : std_logic_vector(13 downto 0); + signal timestamp_channel_id : std_logic_vector(6 downto 0); + signal timestamp_status : std_logic_vector(2 downto 0); + signal adc_data : std_logic_vector(11 downto 0); + signal data_valid : std_logic; signal nx_token_return : std_logic; signal nx_nomore_data : std_logic; @@ -146,9 +149,8 @@ architecture Behavioral of nXyter_FEE_board is -- -- signal adc_dat_clk : std_logic; -- signal adc_restart : std_logic; --- signal adc_clk_o : std_logic; +-- signal adc_clk : std_logic; -- --- signal adc_data_i : std_logic_vector(7 downto 0); -- signal adc_dat_clk_i : std_logic_vector(1 downto 0); -- signal adc_fco_clk_i : std_logic_vector(1 downto 0); -- @@ -161,10 +163,11 @@ begin ------------------------------------------------------------------------------- -- DEBUG ------------------------------------------------------------------------------- --- DEBUG_LINE_OUT(0) <= CLK_IN; --- DEBUG_LINE_OUT(1) <= trigger_ack; --- DEBUG_LINE_OUT(2) <= nx_ts_reset_o; --- DEBUG_LINE_OUT(3) <= nx_testpulse_o; +-- DEBUG_LINE_OUT(0) <= CLK_IN; +-- DEBUG_LINE_OUT(1) <= NX_CLK128_IN; +-- DEBUG_LINE_OUT(2) <= ADC_SAMPLE_CLK_OUT; +-- DEBUG_LINE_OUT(7 downto 3) <= (others => '0'); +-- DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN; -- DEBUG_LINE_OUT(4) <= nx_new_timestamp; -- DEBUG_LINE_OUT(5) <= timestamp_valid; -- DEBUG_LINE_OUT(6) <= timestamp_hold; @@ -217,22 +220,22 @@ begin PORT_ADDRESSES => ( 0 => x"0100", -- Control Register Handler 1 => x"0040", -- I2C Master - 2 => x"0500", -- Timestamp Fifo + 2 => x"0500", -- Data Receiver 3 => x"0600", -- Data Buffer 4 => x"0060", -- SPI Master 5 => x"0140", -- Trigger Generator - 6 => x"0120", -- Timestamp Decode + 6 => x"0120", -- Data Validate 7 => x"0160", -- Trigger Handler 8 => x"0180", -- Timestamp Process others => x"0000"), PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler 1 => 0, -- I2C master - 2 => 3, -- Timestamp Fifo + 2 => 3, -- Data Receiver 3 => 1, -- Data Buffer 4 => 0, -- SPI Master 5 => 3, -- Trigger Generator - 6 => 4, -- Timestamp Decode + 6 => 4, -- Data Validate 7 => 1, -- Trigger Handler 8 => 4, -- Timestamp Process others => 0) @@ -276,7 +279,7 @@ begin BUS_NO_MORE_DATA_IN(1) => slv_no_more_data(1), BUS_UNKNOWN_ADDR_IN(1) => slv_unknown_addr(1), - -- Timestamp Fifo + -- Data Receiver BUS_READ_ENABLE_OUT(2) => slv_read(2), BUS_WRITE_ENABLE_OUT(2) => slv_write(2), BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32), @@ -327,7 +330,7 @@ begin BUS_NO_MORE_DATA_IN(5) => slv_no_more_data(5), BUS_UNKNOWN_ADDR_IN(5) => slv_unknown_addr(5), - -- Timestamp Decode + -- Data Validate BUS_READ_ENABLE_OUT(6) => slv_read(6), BUS_WRITE_ENABLE_OUT(6) => slv_write(6), BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32), @@ -510,54 +513,66 @@ begin SLV_ACK_OUT => slv_ack(5), SLV_NO_MORE_DATA_OUT => slv_no_more_data(5), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5), - -- DEBUG_OUT => DEBUG_LINE_OUT + --DEBUG_OUT => DEBUG_LINE_OUT DEBUG_OUT => open ); - ------------------------------------------------------------------------------- --- nXyter TimeStamp Read +-- nXyter Data Receiver ------------------------------------------------------------------------------- - nx_timestamp_fifo_read_1: nx_timestamp_fifo_read + nx_data_receiver_1: nx_data_receiver port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, - + NX_TIMESTAMP_CLK_IN => NX_CLK128_IN, NX_TIMESTAMP_IN => NX_TIMESTAMP_IN, - NX_TIMESTAMP_OUT => nx_timestamp, - NX_NEW_TIMESTAMP_OUT => nx_new_timestamp, - - SLV_READ_IN => slv_read(2), - SLV_WRITE_IN => slv_write(2), - SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32), - SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32), - SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16), - SLV_ACK_OUT => slv_ack(2), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2), + ADC_CLK_DAT_SRC_IN => CLK_ADC_IN, + ADC_FCLK_IN => ADC_FCLK_IN, + ADC_DCLK_IN => ADC_DCLK_IN, + ADC_SAMPLE_CLK_OUT => ADC_SAMPLE_CLK_OUT, + ADC_A_IN => ADC_A_IN, + ADC_B_IN => ADC_B_IN, + ADC_NX_IN => ADC_NX_IN, + ADC_D_IN => ADC_D_IN, + + NX_TIMESTAMP_OUT => new_timestamp, + ADC_DATA_OUT => new_adc_data, + NEW_DATA_OUT => new_data, + + SLV_READ_IN => slv_read(2), + SLV_WRITE_IN => slv_write(2), + SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32), + SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32), + SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16), + SLV_ACK_OUT => slv_ack(2), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2), --DEBUG_OUT => DEBUG_LINE_OUT DEBUG_OUT => open ); - - + ------------------------------------------------------------------------------- -- Timestamp Decoder and Valid Data Filter ------------------------------------------------------------------------------- - nx_timestamp_decode_1: nx_timestamp_decode + nx_data_validate_1: nx_data_validate port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, - NX_NEW_TIMESTAMP_IN => nx_new_timestamp, - NX_TIMESTAMP_IN => nx_timestamp, + + NX_TIMESTAMP_IN => new_timestamp, + ADC_DATA_IN => new_adc_data, + NEW_DATA_IN => new_data, TIMESTAMP_OUT => timestamp, CHANNEL_OUT => timestamp_channel_id, TIMESTAMP_STATUS_OUT => timestamp_status, - TIMESTAMP_VALID_OUT => timestamp_valid, + ADC_DATA_OUT => adc_data, + DATA_VALID_OUT => data_valid, + NX_TOKEN_RETURN_OUT => nx_token_return, NX_NOMORE_DATA_OUT => nx_nomore_data, @@ -569,25 +584,27 @@ begin SLV_ACK_OUT => slv_ack(6), SLV_NO_MORE_DATA_OUT => slv_no_more_data(6), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6), - -- DEBUG_OUT => DEBUG_LINE_OUT - DEBUG_OUT => open + DEBUG_OUT => DEBUG_LINE_OUT + --DEBUG_OUT => open ); ------------------------------------------------------------------------------- -- NX Timestamp Process ------------------------------------------------------------------------------- - nx_timestamp_process_1: nx_timestamp_process + nx_trigger_validate_1: nx_trigger_validate port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, - TIMESTAMP_CLK_IN => timestamp_valid, - NX_TOKEN_RETURN_IN => nx_token_return, - NX_NOMORE_DATA_IN => nx_nomore_data, + DATA_CLK_IN => data_valid, TIMESTAMP_IN => timestamp, CHANNEL_IN => timestamp_channel_id, TIMESTAMP_STATUS_IN => timestamp_status, + ADC_DATA_IN => adc_data, + NX_TOKEN_RETURN_IN => nx_token_return, + NX_NOMORE_DATA_IN => nx_nomore_data, + TIMESTAMP_REF_IN => timestamp_trigger, TRIGGER_IN => trigger_ack, @@ -635,66 +652,6 @@ begin data_buffer_reset <= RESET_IN or data_fifo_reset; -------------------------------------------------------------------------------- --- ADC 9228 Handler -------------------------------------------------------------------------------- - --- adc_ad9222_1: entity work.adc_ad9222 --- generic map ( --- CHANNELS => 4, --- DEVICES => 1, --- RESOLUTION => 12 --- ) --- port map ( --- CLK => CLK_IN, --- CLK_ADCREF => adc_clk, -- adc_ref_clk, --- CLK_ADCDAT => adc_clk, -- adc_dat_clk, --- RESTART_IN => '0', -- adc_restart, --- ADCCLK_OUT => ADC_SC_CLK32_OUT, -- adc_sc_clk32_o, --- ADC_DATA(0) => ADC_A_IN, -- adc_data_i, --- ADC_DATA(1) => ADC_B_IN, -- adc_data_i, --- ADC_DATA(2) => ADC_NX_IN, -- adc_data_i, --- ADC_DATA(3) => ADC_D_IN, -- adc_data_i, --- ADC_FCO(0) => ADC_FCLK_IN, -- adc_fco_clk_i, --- DATA_OUT(0) => DEBUG_LINE_OUT(0), -- adc_data_word, --- FCO_OUT(0) => DEBUG_LINE_OUT(1), -- adc_fco, --- DATA_VALID_OUT(0) => DEBUG_LINE_OUT(2), -- adc_data_valid, --- DEBUG => open --- ); - - adc_receiver_1: adc_receiver - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - CLK_ADC_IN => CLK_ADC_IN, - - ADC_FCLK_IN => ADC_FCLK_IN, - ADC_DCLK_IN => ADC_DCLK_IN, - ADC_SC_CLK32_OUT => ADC_SC_CLK32_OUT, - ADC_A_IN => ADC_A_IN, - ADC_B_IN => ADC_B_IN, - ADC_NX_IN => ADC_NX_IN, - ADC_D_IN => ADC_D_IN, - - --DEBUG_OUT => open, - DEBUG_OUT => DEBUG_LINE_OUT - ); - --- adc_ad9228_1: adc_ad9228 --- port map ( --- CLK_IN => CLK_IN, --- RESET_IN => RESET_IN, --- ADC_FCLK_IN => ADC_FCLK_IN, --- ADC_DCLK_IN => ADC_DCLK_IN, --- ADC_SC_CLK32_OUT => ADC_SC_CLK32_OUT, --- ADC_A_IN => ADC_A_IN, --- ADC_B_IN => ADC_B_IN, --- ADC_NX_IN => ADC_NX_IN, --- ADC_D_IN => ADC_D_IN, --- --DEBUG_OUT => open, --- DEBUG_OUT => DEBUG_LINE_OUT --- ); - ------------------------------------------------------------------------------- -- nXyter Signals ------------------------------------------------------------------------------- diff --git a/nxyter/source/pulse_to_level.vhd b/nxyter/source/pulse_to_level.vhd new file mode 100644 index 0000000..8e9f6db --- /dev/null +++ b/nxyter/source/pulse_to_level.vhd @@ -0,0 +1,84 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use nxyter_components.all; + +entity pulse_to_level is + generic ( + NUM_CYCLES : unsigned(4 downto 0) := "11111" + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + PULSE_IN : in std_logic; + LEVEL_OUT : out std_logic + ); + +end pulse_to_level; + +architecture Behavioral of pulse_to_level is + + signal start_timer : unsigned(4 downto 0); + signal timer_done : std_logic; + signal level_o : std_logic; + + type STATES is (IDLE, + WAIT_TIMER + ); + signal STATE : STATES; + +begin + + nx_timer_1: nx_timer + generic map ( + CTR_WIDTH => 5 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => start_timer, + TIMER_DONE_OUT => timer_done + ); + + PROC_CONVERT: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + start_timer <= (others => '0'); + level_o <= '0'; + STATE <= IDLE; + else + level_o <= '0'; + start_timer <= (others => '0'); + + case STATE is + + when IDLE => + if (PULSE_IN = '1') then + level_o <= '1'; + start_timer <= NUM_CYCLES; + STATE <= WAIT_TIMER; + else + STATE <= IDLE; + end if; + + when WAIT_TIMER => + level_o <= '1'; + if (timer_done = '1') then + STATE <= IDLE; + else + STATE <= WAIT_TIMER; + end if; + + when others => null; + + end case; + end if; + end if; + end process PROC_CONVERT; + + LEVEL_OUT <= level_o; + +end Behavioral; diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index 8a73412..6ffe69f 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -3,14 +3,14 @@ 0x8101 : r/w w: reset I2C all Register r: reset ctr 0x8102 : r/w w: Reset and Sync Timestamps (nXyter and FPGA) r: reset ctr --- Timestamp Decode +-- NX Data Validate 0x8120 : rw Invalid Frame Counter (16 bit) / w: clear all counters 0x8121 : r Overflow Counter (16 bit) 0x8122 : r Pileup Counter (16 bit) 0x8123 : r Parity Error Counter (16 bit) 0x8124 : r Trigger Rate (in kHz) --- Timestamp Process +-- NX Trigger Validate 0x8180 : r/w Readout Mode (0:Ref + valid + window, 1: Ref + Valid 3: Raw and TimeStamp + valid, 4: Raw, 5: Raw + Valid ) @@ -34,8 +34,8 @@ -- Trigger Handler 0x8160 : r/w Bit 15-0 : Delay Trigger in Timestamp Hold --- Timestamp Fifo -0x8500 : r current FIFO value +-- NX Data Receiver +0x8500 : r current Timestamp FIFO value 0x8501 : r/w r: FIFO Status 0: fifo_full 1: fifo_empty @@ -47,17 +47,24 @@ w: clear Resync Counter 0x8503 : r/w r: Parity Error Counter (12bit) w: clear Parity Error Counter -0x8504 : r/w FIFO Delay, i.e. Trigger Delay (6bit, in 3.1ns, range 2 .. 60) +0x8504 : r/w FIFO Delay, i.e. Trigger Delay (6Bit, in 31.25ns, range 2..60) default: 8 +0x8505 : r/w ADC CLK Delay 4ns steps (3Bit: range 0..7) + 0: 4ns after frame_valid + 1: 8ns -------"--------- + ...... -------"--------- + 6: 28ns -------"--------- + 7: 32ns -------"--------- <= this shoud be correct i.e. 2ns before new frame clock +0x8506 : r current ADC FIFO value --- Data Buffer +-- Event Data Buffer 0x8600 : r read FIFO buffer 0x8601 : r/w r: read FIFO status w: enable/disable FIFO write -- I2C Master -0x8040 : Access to I2C Interface +0x8040 : Access to I2C Interface -- SPI Master -0x8060 : Access to SPI Interface +0x8060 : Access to SPI Interface diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index d835980..2975b74 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -139,32 +139,37 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" + +# nXyter Files + +add_file -vhdl -lib "work" "cores/pll_125_hub.vhd" add_file -vhdl -lib "work" "cores/pll_nx_clk256.vhd" add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd" add_file -vhdl -lib "work" "cores/pll_adc_clk32.vhd" add_file -vhdl -lib "work" "cores/pll_adc_clk192.vhd" -add_file -vhdl -lib "work" "cores/fifo_32to32_dc.vhd" +#add_file -vhdl -lib "work" "cores/fifo_32to32_dc.vhd" +add_file -vhdl -lib "work" "cores/fifo_ts_32to32_dc.vhd" +add_file -vhdl -lib "work" "cores/fifo_12_adc.vhd" add_file -vhdl -lib "work" "cores/fifo_32_data.vhd" -add_file -vhdl -lib "work" "cores/fifo_6to6_dc.vhd" add_file -vhdl -lib "work" "trb3_periph.vhd" -# nXyter Files add_file -vhdl -lib "work" "source/nxyter_components.vhd" - -add_file -vhdl -lib "work" "source/nxyter_fee_board.vhd" -add_file -vhdl -lib "work" "source/nxyter_data_handler.vhd" -add_file -vhdl -lib "work" "source/nxyter_registers.vhd" -add_file -vhdl -lib "work" "source/nx_timestamp_fifo_read.vhd" add_file -vhdl -lib "work" "source/level_to_pulse.vhd" +add_file -vhdl -lib "work" "source/pulse_to_level.vhd" add_file -vhdl -lib "work" "source/gray_decoder.vhd" add_file -vhdl -lib "work" "source/gray_encoder.vhd" -add_file -vhdl -lib "work" "source/nx_data_buffer.vhd" add_file -vhdl -lib "work" "source/nx_timer.vhd" -add_file -vhdl -lib "work" "source/nx_timestamp_decode.vhd" -add_file -vhdl -lib "work" "source/nx_timestamp_process.vhd" +add_file -vhdl -lib "work" "source/nxyter_fee_board.vhd" +add_file -vhdl -lib "work" "source/nx_data_receiver.vhd" +add_file -vhdl -lib "work" "source/nx_data_validate.vhd" +add_file -vhdl -lib "work" "source/nx_trigger_validate.vhd" +add_file -vhdl -lib "work" "source/nx_data_buffer.vhd" + +add_file -vhdl -lib "work" "source/nxyter_data_handler.vhd" +add_file -vhdl -lib "work" "source/nxyter_registers.vhd" add_file -vhdl -lib "work" "source/nx_i2c_master.vhd" add_file -vhdl -lib "work" "source/nx_i2c_startstop.vhd" @@ -180,9 +185,6 @@ add_file -vhdl -lib "work" "source/nx_trigger_generator.vhd" add_file -vhdl -lib "work" "source/nx_trigger_handler.vhd" add_file -vhdl -lib "work" "source/nx_timestamp_sim.vhd" -add_file -vhdl -lib "work" "source/adc_ad9228.vhd" -add_file -vhdl -lib "work" "source/adc_receiver.vhd" - # Needed by ADC9222 Entity add_file -vhdl -lib "work" "../base/cores/dqsinput.vhd" add_file -vhdl -lib "work" "../base/cores/dqsinput1x4.vhd" diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd index 51eadbe..119c977 100644 --- a/nxyter/trb3_periph.vhd +++ b/nxyter/trb3_periph.vhd @@ -54,7 +54,7 @@ entity trb3_periph is NX1_TESTPULSE_OUT : out std_logic; NX1_ADC_FCLK_IN : in std_logic; NX1_ADC_DCLK_IN : in std_logic; - NX1_ADC_SC_CLK32_OUT : out std_logic; + NX1_ADC_SAMPLE_CLK_OUT : out std_logic; NX1_ADC_A_IN : in std_logic; NX1_ADC_B_IN : in std_logic; NX1_ADC_NX_IN : in std_logic; @@ -83,7 +83,7 @@ entity trb3_periph is NX2_TESTPULSE_OUT : out std_logic; NX2_ADC_FCLK_IN : in std_logic; NX2_ADC_DCLK_IN : in std_logic; - NX2_ADC_SC_CLK32_OUT : out std_logic; + NX2_ADC_SAMPLE_CLK_OUT : out std_logic; NX2_ADC_A_IN : in std_logic; NX2_ADC_B_IN : in std_logic; NX2_ADC_NX_IN : in std_logic; @@ -153,8 +153,8 @@ architecture trb3_periph_arch of trb3_periph is attribute syn_preserve : boolean; -- For 250MHz PLL nxyter clock, THE_256M_ODDR_1 - -- attribute ODDRAPPS : string; - -- attribute ODDRAPPS of THE_256M_ODDR_1 : label is "SCLK_ALIGNED"; + --attribute ODDRAPPS : string; + --attribute ODDRAPPS of THE_256M_ODDR_1 : label is "SCLK_ALIGNED"; --Clock / Reset @@ -304,9 +304,6 @@ architecture trb3_periph_arch of trb3_periph is signal nx2_clk256_o : std_logic; - - signal pll_192MHz : std_logic; - begin --------------------------------------------------------------------------- -- Reset Generation @@ -507,13 +504,6 @@ begin -- AddOn --------------------------------------------------------------------------- - pll_adc_clk192_1: pll_adc_clk192 - port map ( - CLK => CLK_PCLK_LEFT, - CLKOP => pll_192MHz, - LOCK => open - ); - --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- @@ -741,7 +731,7 @@ begin ADC_FCLK_IN(1) => NX1B_ADC_FCLK_IN, ADC_DCLK_IN(0) => NX1_ADC_DCLK_IN, ADC_DCLK_IN(1) => NX1B_ADC_DCLK_IN, - ADC_SC_CLK32_OUT => NX1_ADC_SC_CLK32_OUT, + ADC_SAMPLE_CLK_OUT => NX1_ADC_SAMPLE_CLK_OUT, ADC_A_IN(0) => NX1_ADC_A_IN, ADC_A_IN(1) => NX1B_ADC_A_IN, ADC_B_IN(0) => NX1_ADC_B_IN, @@ -769,25 +759,37 @@ begin pll_nx_clk256_1: entity work.pll_nx_clk256 port map ( CLK => clk_100_i, - CLKOP => NX1_CLK256A_OUT, + CLKOP => nx1_clk256_o, LOCK => pll_lock_clk256 ); + + NX1_CLK256A_OUT <= nx1_clk256_o; + + + -- 250MHz Clock to nXyters + --pll_nx_clk250_1: entity work.pll_nx_clk250 + -- port map ( + -- CLK => CLK_GPLL_LEFT, + -- CLKOP => nx1_clk256_o, + -- LOCK => open + -- ); + + --pll_125_hub_1: pll_125_hub + -- port map ( + -- CLK => CLK_GPLL_LEFT, + -- CLKOP => open, + -- CLKOK => nx1_clk256_o, + -- LOCK => open + -- ); + -- NX1_CLK256A_OUT <= CLK_PCLK_RIGHT; --- -- 250MHz Clock to nXyters --- pll_nx_clk250_1: entity work.pll_nx_clk250 --- port map ( --- CLK => CLK_GPLL_LEFT, --- CLKOP => NX1_CLK256A_OUT, -- nx1_clk256_o, --- LOCK => open --- ); - --- THE_256M_ODDR_1: ODDRXD1 --- port map( --- SCLK => nx1_clk256_o, --- DA => '1', --- DB => '0', --- Q => open --NX1_CLK256A_OUT --- ); + --THE_256M_ODDR_1: ODDRXD1 + -- port map( + -- SCLK => nx1_clk256_o, + -- DA => '1', + -- DB => '0', + -- Q => NX1_CLK256A_OUT + -- ); ------------------------------------------------------------------------------- diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index a4a117a..3501d2c 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -28,8 +28,8 @@ USE PRIMARY NET "CLK_PCLK_LEFT"; USE PRIMARY NET "CLK_PCLK_LEFT_c"; - # USE PRIMARY NET "CLK_GPLL_RIGHT"; - # USE PRIMARY NET "CLK_GPLL_RIGHT_c"; + USE PRIMARY2EDGE NET "THE_MAIN_PLL/PLLInst_0"; + USE PRIMARY NET "THE_MAIN_PLL/PLLInst_0"; USE PRIMARY NET "NX1_ADC_SC_CLK32_OUT"; USE PRIMARY NET "NX1_ADC_SC_CLK32_OUT_c"; @@ -42,8 +42,6 @@ GSR_NET NET "GSR_N"; - - ################################################################# # Locate Serdes and media interfaces ################################################################# @@ -77,12 +75,6 @@ INPUT_SETUP GROUP "NX_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN" ; MULTICYCLE FROM CLKNET "NX1_CLK256A_OUT_c_c" 50 ns; - - - - - - #PROHIBIT PRIMARY NET "NX1_ADC_DCLK_IN_c"; #PROHIBIT SECONDARY NET "NX1_ADC_DCLK_IN_c"; diff --git a/nxyter/version.vhd b/nxyter/version.vhd deleted file mode 100644 index 5aac2a7..0000000 --- a/nxyter/version.vhd +++ /dev/null @@ -1,13 +0,0 @@ - ---## attention, automatically generated. Don't change by hand. -library ieee; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use ieee.numeric_std.all; - -package version is - - constant VERSION_NUMBER_TIME : integer := 1366059697; - -end package version;