From: Jan Michel Date: Mon, 24 Apr 2017 09:31:12 +0000 (+0200) Subject: Update Dirich design with new SPI port and option to disable PWM X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1aa44e687df1036da716ce91cd19ca59c132415b;p=dirich.git Update Dirich design with new SPI port and option to disable PWM --- diff --git a/dirich/config.vhd b/dirich/config.vhd index 222661e..813c7b0 100644 --- a/dirich/config.vhd +++ b/dirich/config.vhd @@ -9,10 +9,13 @@ package config is ------------------------------------------------------------------------------ --Begin of design configuration ------------------------------------------------------------------------------ + + constant DIRICH_VERSION : integer := 2; --1 or 2. + --TDC settings constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 3; -- number of tdc channels per module - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 16; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, @@ -21,7 +24,7 @@ package config is constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size -- mode: 0, 1, 2, 3, 7 -- size: 32, 64, 96, 128, dyn - constant TDC_DATA_FORMAT : integer range 0 to 3 := 15; --type of data format for the TDC + constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC -- 0: Single fine time as the sum of the two transitions -- 1: Double fine time, individual transitions -- 14: Debug - single fine time and the ROM addresses for the two transitions @@ -41,13 +44,13 @@ package config is constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"51"; constant INCLUDE_UART : integer := c_NO; --300 slices - constant INCLUDE_SPI : integer := c_YES; --300 slices + constant INCLUDE_SPI : integer := c_YES; --300 slices --needed for Dirich2 constant INCLUDE_LCD : integer := c_NO; --800 slices constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; --300 slices --input monitor and trigger generation logic constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; --400 slices @32->2 - constant INCLUDE_STATISTICS : integer := c_YES; --1300 slices, 1 RAM @32 + constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 constant TRIG_GEN_INPUT_NUM : integer := 32; constant TRIG_GEN_OUTPUT_NUM : integer := 2; constant MONITOR_INPUT_NUM : integer := 32; diff --git a/dirich/config_compile_frankfurt.pl b/dirich/config_compile_frankfurt.pl index 6d1188d..19df01d 100644 --- a/dirich/config_compile_frankfurt.pl +++ b/dirich/config_compile_frankfurt.pl @@ -7,8 +7,8 @@ Speedgrade => '8', TOPNAME => "dirich", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@jspc29", -lattice_path => '/d/jspc29/lattice/diamond/3.7_x64', -synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', +lattice_path => '/d/jspc29/lattice/diamond/3.9_x64', +synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/', # synplify_command => "/d/jspc29/lattice/diamond/3.7_x64/bin/lin64/synpwrap -fg -options", # synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", # synplify_command => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #", diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd index 29151c5..51cfbd4 100644 --- a/dirich/dirich.vhd +++ b/dirich/dirich.vhd @@ -41,6 +41,11 @@ entity dirich is FLASH_WP : out std_logic; PROGRAMN : out std_logic; TEMP_LINE : inout std_logic; + + MISO_IN : in std_logic_vector(1 downto 0); + MOSI_OUT : out std_logic_vector(1 downto 0); + SCLK_OUT : out std_logic_vector(1 downto 0); + CS_OUT : out std_logic_vector(1 downto 0); --Test Connectors TEST_LINE : inout std_logic_vector(14 downto 1) @@ -299,10 +304,10 @@ begin PROGRAMN => PROGRAMN, REBOOT_IN => common_ctrl_reg(15), --SPI - SPI_CS_OUT => open, - SPI_MOSI_OUT => open, - SPI_MISO_IN => open, - SPI_CLK_OUT => open, + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, --Header HEADER_IO => hdr_io, ADDITIONAL_REG(0) => led_off, @@ -338,7 +343,7 @@ begin --------------------------------------------------------------------------- -- PWM / Thresh --------------------------------------------------------------------------- - +gen_pwm: if DIRICH_VERSION = 1 generate THE_PWM_GEN : entity work.pwm_generator port map( CLK => clk_sys, @@ -350,16 +355,25 @@ begin ); PWM <= pwm_i; +end generate; + +gen_DAC : if DIRICH_VERSION = 2 generate + MOSI_OUT <= spi_mosi(1 downto 0); + SCLK_OUT <= spi_clk(1 downto 0); + CS_OUT <= spi_cs(1 downto 0); + spi_miso(1 downto 0) <= MISO_IN; +end generate; --------------------------------------------------------------------------- -- I/O --------------------------------------------------------------------------- - TEST_LINE(8 downto 1) <= hdr_io(7 downto 0); - hdr_io(8) <= TEST_LINE(9); - TEST_LINE(10) <= hdr_io(9); - TEST_LINE(14 downto 11) <= time_counter(31 downto 28); --- TEST_LINE(14 downto 1) <= med2int(0).stat_op(13) & clear_i & reset_i & med_stat_debug(18 downto 8); +-- TEST_LINE(8 downto 1) <= hdr_io(7 downto 0); +-- hdr_io(8) <= TEST_LINE(9); +-- TEST_LINE(10) <= hdr_io(9); +-- TEST_LINE(14 downto 11) <= time_counter(31 downto 28); +-- TEST_LINE(14 downto 1) <= med2int(0).stat_op(13) & clear_i & reset_i & debug_clock_reset(10 downto 0); + --& med_stat_debug(18 downto 8); --------------------------------------------------------------------------- -- LCD Data to display @@ -425,11 +439,11 @@ begin ); -- For single edge measurements - --gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate - -- hit_in_i <= INPUT; - --end generate; - hit_in_i(1) <= INPUT(31); - hit_in_i(2) <= INPUT(32); + gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + hit_in_i <= INPUT; + end generate; +-- hit_in_i(1) <= INPUT(31); +-- hit_in_i(2) <= INPUT(32); -- For ToT Measurements gen_double : if DOUBLE_EDGE_TYPE = 2 generate @@ -440,6 +454,10 @@ begin end generate; +-- readout_tx(0).data_finished <= '1'; +-- readout_tx(0).data_write <= '0'; +-- readout_tx(0).busy_release <= '1'; + end architecture;