From: hadeshyp <hadeshyp>
Date: Fri, 17 Apr 2009 11:52:33 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~460
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1ae79bb391d5cf2703b0882f819e0dfd05366027;p=trbnet.git

*** empty log message ***
---

diff --git a/media_interfaces/trb_net16_med_ecp_sfp.vhd b/media_interfaces/trb_net16_med_ecp_sfp.vhd
index 00e4ea6..1115a19 100644
--- a/media_interfaces/trb_net16_med_ecp_sfp.vhd
+++ b/media_interfaces/trb_net16_med_ecp_sfp.vhd
@@ -49,7 +49,7 @@ end entity;
 
 architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
 
-  component serdes_0
+  component serdes_sfp_0
     port(
      core_txrefclk : in std_logic;
      core_rxrefclk : in std_logic;
@@ -94,12 +94,10 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
       );
   end component;
 
-  component serdes_1
+  component serdes_sfp_1
     port(
       core_txrefclk : in std_logic;
       core_rxrefclk : in std_logic;
-      refclkp : IN std_logic;
-      refclkn : IN std_logic;
       hdinp1 : in std_logic;
       hdinn1 : in std_logic;
       ff_rxiclk_ch1 : in std_logic;
@@ -142,7 +140,7 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
   end component;
 
 
-  component serdes_2
+  component serdes_sfp_2
     port(
       core_txrefclk : in std_logic;
       core_rxrefclk : in std_logic;
@@ -187,7 +185,7 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
       );
   end component;
 
-  component serdes_3
+  component serdes_sfp_3
     port(
       core_txrefclk : in std_logic;
       core_rxrefclk : in std_logic;
@@ -455,7 +453,7 @@ REFCLK2CORE_OUT <= refck2core;
 
 -- Instantiation of serdes module
   gen_serdes_0 : if SERDES_NUM = 0 generate
-    THE_SERDES: serdes_0
+    THE_SERDES: serdes_sfp_0
       port map(
              core_txrefclk          => clk,
              core_rxrefclk          => clk,
@@ -500,12 +498,10 @@ REFCLK2CORE_OUT <= refck2core;
             );
   end generate;
   gen_serdes_1 : if SERDES_NUM = 1 generate
-    THE_SERDES: serdes_1
+    THE_SERDES: serdes_sfp_1
       port map(
               core_txrefclk          => clk,
               core_rxrefclk          => clk,
-              refclkp                => SD_REFCLK_P_IN,
-              refclkn                => SD_REFCLK_N_IN,
               hdinp1                 => sd_rxd_p_in,
               hdinn1                 => sd_rxd_n_in,
               ff_rxiclk_ch1          => ff_rxhalfclk,
@@ -547,7 +543,7 @@ REFCLK2CORE_OUT <= refck2core;
             );
   end generate;
   gen_serdes_2 : if SERDES_NUM = 2 generate
-    THE_SERDES: serdes_2
+    THE_SERDES: serdes_sfp_2
       port map(
               core_txrefclk          => clk,
               core_rxrefclk          => clk,
@@ -592,7 +588,7 @@ REFCLK2CORE_OUT <= refck2core;
             );
   end generate;
   gen_serdes_3 : if SERDES_NUM = 3 generate
-    THE_SERDES: serdes_3
+    THE_SERDES: serdes_sfp_3
       port map(
               core_txrefclk          => clk,
               core_rxrefclk          => clk,