From: Jan Michel Date: Wed, 11 Aug 2021 09:16:02 +0000 (+0200) Subject: add missing PCS file X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1af9d281f761e2b394b5c9cb4686d3849406fc29;p=trbnet.git add missing PCS file --- diff --git a/media_interfaces/ecp5/pcs2.vhd b/media_interfaces/ecp5/pcs2.vhd new file mode 100644 index 0000000..8edc15b --- /dev/null +++ b/media_interfaces/ecp5/pcs2.vhd @@ -0,0 +1,161 @@ + + +-- +-- Verific VHDL Description of module pcs +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity pcs2 is + port (serdes_sync_0_rx_cv_err: out std_logic_vector(0 downto 0); + serdes_sync_0_rx_disp_err: out std_logic_vector(0 downto 0); + serdes_sync_0_rx_k: out std_logic_vector(0 downto 0); + serdes_sync_0_rxdata: out std_logic_vector(7 downto 0); + serdes_sync_0_sci_addr: in std_logic_vector(5 downto 0); + serdes_sync_0_sci_rddata: out std_logic_vector(7 downto 0); + serdes_sync_0_sci_wrdata: in std_logic_vector(7 downto 0); + serdes_sync_0_tx_disp_sel: in std_logic_vector(0 downto 0); + serdes_sync_0_tx_force_disp: in std_logic_vector(0 downto 0); + serdes_sync_0_tx_k: in std_logic_vector(0 downto 0); + serdes_sync_0_txdata: in std_logic_vector(7 downto 0); + serdes_sync_0_cyawstn: in std_logic; + serdes_sync_0_hdinn: in std_logic; + serdes_sync_0_hdinp: in std_logic; + serdes_sync_0_hdoutn: out std_logic; + serdes_sync_0_hdoutp: out std_logic; + serdes_sync_0_lsm_status_s: out std_logic; + serdes_sync_0_pll_lol: out std_logic; + serdes_sync_0_pll_refclki: in std_logic; + serdes_sync_0_rsl_disable: in std_logic; + serdes_sync_0_rsl_rst: in std_logic; + serdes_sync_0_rsl_rx_rdy: out std_logic; + serdes_sync_0_rsl_tx_rdy: out std_logic; + serdes_sync_0_rst_dual_c: in std_logic; + serdes_sync_0_rx_cdr_lol_s: out std_logic; + serdes_sync_0_rx_los_low_s: out std_logic; + serdes_sync_0_rx_pclk: out std_logic; + serdes_sync_0_rx_pcs_rst_c: in std_logic; + serdes_sync_0_rx_pwrup_c: in std_logic; + serdes_sync_0_rx_serdes_rst_c: in std_logic; + serdes_sync_0_rxrefclk: in std_logic; + serdes_sync_0_sci_en: in std_logic; + serdes_sync_0_sci_en_dual: in std_logic; + serdes_sync_0_sci_int: out std_logic; + serdes_sync_0_sci_rd: in std_logic; + serdes_sync_0_sci_sel: in std_logic; + serdes_sync_0_sci_sel_dual: in std_logic; + serdes_sync_0_sci_wrn: in std_logic; + serdes_sync_0_serdes_pdb: in std_logic; + serdes_sync_0_serdes_rst_dual_c: in std_logic; + serdes_sync_0_signal_detect_c: in std_logic; + serdes_sync_0_tx_idle_c: in std_logic; + serdes_sync_0_tx_pclk: out std_logic; + serdes_sync_0_tx_pcs_rst_c: in std_logic; + serdes_sync_0_tx_pwrup_c: in std_logic; + serdes_sync_0_tx_serdes_rst_c: in std_logic + ); + +end entity pcs2; -- sbp_module=true + +architecture pcs2 of pcs2 is + component serdes_sync_2 is + port (rx_cv_err: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_wrdata: in std_logic_vector(7 downto 0); + tx_disp_sel: in std_logic_vector(0 downto 0); + tx_force_disp: in std_logic_vector(0 downto 0); + tx_k: in std_logic_vector(0 downto 0); + txdata: in std_logic_vector(7 downto 0); + cyawstn: in std_logic; + hdinn: in std_logic; + hdinp: in std_logic; + hdoutn: out std_logic; + hdoutp: out std_logic; + lsm_status_s: out std_logic; + pll_lol: out std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + rsl_rx_rdy: out std_logic; + rsl_tx_rdy: out std_logic; + rst_dual_c: in std_logic; + rx_cdr_lol_s: out std_logic; + rx_los_low_s: out std_logic; + rx_pclk: out std_logic; + rx_pcs_rst_c: in std_logic; + rx_pwrup_c: in std_logic; + rx_serdes_rst_c: in std_logic; + rxrefclk: in std_logic; + sci_en: in std_logic; + sci_en_dual: in std_logic; + sci_int: out std_logic; + sci_rd: in std_logic; + sci_sel: in std_logic; + sci_sel_dual: in std_logic; + sci_wrn: in std_logic; + serdes_pdb: in std_logic; + serdes_rst_dual_c: in std_logic; + signal_detect_c: in std_logic; + sli_rst: in std_logic; + tx_idle_c: in std_logic; + tx_pclk: out std_logic; + tx_pcs_rst_c: in std_logic; + tx_pwrup_c: in std_logic; + tx_serdes_rst_c: in std_logic + ); + + end component serdes_sync_2; -- not_need_bbox=true + + + signal sli_rst_wire0,gnd : std_logic; +begin + sli_rst_wire0 <= serdes_sync_0_serdes_rst_dual_c OR serdes_sync_0_tx_serdes_rst_c OR (NOT serdes_sync_0_serdes_pdb) OR (NOT serdes_sync_0_tx_pwrup_c); + serdes_sync_0_inst: component serdes_sync_2 port map (rx_cv_err(0)=>serdes_sync_0_rx_cv_err(0), + rx_disp_err(0)=>serdes_sync_0_rx_disp_err(0),rx_k(0)=>serdes_sync_0_rx_k(0), + rxdata(7)=>serdes_sync_0_rxdata(7),rxdata(6)=>serdes_sync_0_rxdata(6), + rxdata(5)=>serdes_sync_0_rxdata(5),rxdata(4)=>serdes_sync_0_rxdata(4), + rxdata(3)=>serdes_sync_0_rxdata(3),rxdata(2)=>serdes_sync_0_rxdata(2), + rxdata(1)=>serdes_sync_0_rxdata(1),rxdata(0)=>serdes_sync_0_rxdata(0), + sci_addr(5)=>serdes_sync_0_sci_addr(5),sci_addr(4)=>serdes_sync_0_sci_addr(4), + sci_addr(3)=>serdes_sync_0_sci_addr(3),sci_addr(2)=>serdes_sync_0_sci_addr(2), + sci_addr(1)=>serdes_sync_0_sci_addr(1),sci_addr(0)=>serdes_sync_0_sci_addr(0), + sci_rddata(7)=>serdes_sync_0_sci_rddata(7),sci_rddata(6)=>serdes_sync_0_sci_rddata(6), + sci_rddata(5)=>serdes_sync_0_sci_rddata(5),sci_rddata(4)=>serdes_sync_0_sci_rddata(4), + sci_rddata(3)=>serdes_sync_0_sci_rddata(3),sci_rddata(2)=>serdes_sync_0_sci_rddata(2), + sci_rddata(1)=>serdes_sync_0_sci_rddata(1),sci_rddata(0)=>serdes_sync_0_sci_rddata(0), + sci_wrdata(7)=>serdes_sync_0_sci_wrdata(7),sci_wrdata(6)=>serdes_sync_0_sci_wrdata(6), + sci_wrdata(5)=>serdes_sync_0_sci_wrdata(5),sci_wrdata(4)=>serdes_sync_0_sci_wrdata(4), + sci_wrdata(3)=>serdes_sync_0_sci_wrdata(3),sci_wrdata(2)=>serdes_sync_0_sci_wrdata(2), + sci_wrdata(1)=>serdes_sync_0_sci_wrdata(1),sci_wrdata(0)=>serdes_sync_0_sci_wrdata(0), + tx_disp_sel(0)=>serdes_sync_0_tx_disp_sel(0),tx_force_disp(0)=>serdes_sync_0_tx_force_disp(0), + tx_k(0)=>serdes_sync_0_tx_k(0),txdata(7)=>serdes_sync_0_txdata(7), + txdata(6)=>serdes_sync_0_txdata(6),txdata(5)=>serdes_sync_0_txdata(5), + txdata(4)=>serdes_sync_0_txdata(4),txdata(3)=>serdes_sync_0_txdata(3), + txdata(2)=>serdes_sync_0_txdata(2),txdata(1)=>serdes_sync_0_txdata(1), + txdata(0)=>serdes_sync_0_txdata(0),cyawstn=>serdes_sync_0_cyawstn, + hdinn=>serdes_sync_0_hdinn,hdinp=>serdes_sync_0_hdinp,hdoutn=>serdes_sync_0_hdoutn, + hdoutp=>serdes_sync_0_hdoutp,lsm_status_s=>serdes_sync_0_lsm_status_s, + pll_lol=>serdes_sync_0_pll_lol,pll_refclki=>serdes_sync_0_pll_refclki, + rsl_disable=>serdes_sync_0_rsl_disable,rsl_rst=>serdes_sync_0_rsl_rst, + rsl_rx_rdy=>serdes_sync_0_rsl_rx_rdy,rsl_tx_rdy=>serdes_sync_0_rsl_tx_rdy, + rst_dual_c=>serdes_sync_0_rst_dual_c,rx_cdr_lol_s=>serdes_sync_0_rx_cdr_lol_s, + rx_los_low_s=>serdes_sync_0_rx_los_low_s,rx_pclk=>serdes_sync_0_rx_pclk, + rx_pcs_rst_c=>serdes_sync_0_rx_pcs_rst_c,rx_pwrup_c=>serdes_sync_0_rx_pwrup_c, + rx_serdes_rst_c=>serdes_sync_0_rx_serdes_rst_c,rxrefclk=>serdes_sync_0_rxrefclk, + sci_en=>serdes_sync_0_sci_en,sci_en_dual=>serdes_sync_0_sci_en_dual, + sci_int=>serdes_sync_0_sci_int,sci_rd=>serdes_sync_0_sci_rd,sci_sel=>serdes_sync_0_sci_sel, + sci_sel_dual=>serdes_sync_0_sci_sel_dual,sci_wrn=>serdes_sync_0_sci_wrn, + serdes_pdb=>serdes_sync_0_serdes_pdb,serdes_rst_dual_c=>serdes_sync_0_serdes_rst_dual_c, + signal_detect_c=>serdes_sync_0_signal_detect_c,sli_rst=>sli_rst_wire0, + tx_idle_c=>serdes_sync_0_tx_idle_c,tx_pclk=>serdes_sync_0_tx_pclk, + tx_pcs_rst_c=>serdes_sync_0_tx_pcs_rst_c,tx_pwrup_c=>serdes_sync_0_tx_pwrup_c, + tx_serdes_rst_c=>serdes_sync_0_tx_serdes_rst_c); + gnd <= '0' ; + +end architecture pcs2; -- sbp_module=true +