From: Jan Michel Date: Mon, 23 Jan 2017 15:49:11 +0000 (+0100) Subject: some updates to placement of trb3s tdc X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1b534745551e74f37d6c534ddf7b103826463a53;p=trb3sc.git some updates to placement of trb3s tdc --- diff --git a/pinout/basic_constraints.lpf b/pinout/basic_constraints.lpf index 033e461..4fe5665 100644 --- a/pinout/basic_constraints.lpf +++ b/pinout/basic_constraints.lpf @@ -50,7 +50,8 @@ FREQUENCY NET "THE_MEDIA_INT*/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps #main serdes is PCSB for stand-along or PCSA for crate operation LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ; LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB" ; -REGION "MEDIA_UPLINK" "R96C107D" 19 24; +#REGION "MEDIA_UPLINK" "R96C107D" 19 24; +REGION "MEDIA_UPLINK" "R96C55D" 19 24; LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA_UPLINK" ; #more space for media interface on backplane master diff --git a/tdctemplate/config.vhd b/tdctemplate/config.vhd index 731053a..b9df684 100644 --- a/tdctemplate/config.vhd +++ b/tdctemplate/config.vhd @@ -13,14 +13,15 @@ package config is --TDC settings constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement constant NUM_TDC_CHANNELS : integer range 1 to 65 := 41; -- number of tdc channels per module - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons - constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 1; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, -- 2: alternating channels, -- 3: same channel with stretcher constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file --ring buffer size: 32,64,96,128,dyn + constant TDC_DATA_FORMAT : integer := 0; constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 @@ -37,10 +38,12 @@ package config is constant INIT_ADDRESS : std_logic_vector := x"F3CF"; constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"62"; - - constant INCLUDE_UART : integer := c_YES; - constant INCLUDE_SPI : integer := c_YES; - constant INCLUDE_LCD : integer := c_YES; +--set to 0 for backplane serdes, set to 3 for front SFP serdes + constant SERDES_NUM : integer := 3; + + constant INCLUDE_UART : integer := c_NO; + constant INCLUDE_SPI : integer := c_NO; + constant INCLUDE_LCD : integer := c_NO; constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; --input monitor and trigger generation logic diff --git a/tdctemplate/par.p2t b/tdctemplate/par.p2t index e202e18..c203493 100644 --- a/tdctemplate/par.p2t +++ b/tdctemplate/par.p2t @@ -1,21 +1,21 @@ +#-w +#-i 15 +#-l 5 +#-y +#-s 12 +#-t 6 +#-c 1 +#-e 2 +##-g guidefile.ncd +##-m nodelist.txt +#-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 + -w --i 15 -l 5 -#-n 1 --y --s 12 --t 8 --c 1 --e 2 -#-g guidefile.ncd -#-m nodelist.txt -# -w -# -i 6 -# -l 5 -# -n 1 -# -t 1 -# -s 1 -# -c 0 -# -e 0 -# --exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 +-i 6 +-n 1 +-t 1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF:parHold=0 diff --git a/tdctemplate/synplify.fdc b/tdctemplate/synplify.fdc index 1a8f9d8..4132d21 100644 --- a/tdctemplate/synplify.fdc +++ b/tdctemplate/synplify.fdc @@ -14,7 +14,7 @@ ###==== END Collections ###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) -create_clock -name {clk240} {p:CLK_CORE_PCLK} -period {4.16} +create_clock -name {clk240} {p:CLK_CORE_PCLK} -period {4.166666} create_clock -name {clksys} {n:THE_CLOCK_RESET.SYS_CLK_OUT} -period {10} create_clock -name {clktxfull} {n:THE_MEDIA_INTERFACE.gen_pcs3\.THE_SERDES.tx_full_clk_ch3} -period {5} create_clock -name {clkrxfull} {n:THE_MEDIA_INTERFACE.gen_pcs3\.THE_SERDES.rx_full_clk_ch3} -period {5} diff --git a/tdctemplate/trb3sc_tdctemplate.lpf b/tdctemplate/trb3sc_tdctemplate.lpf index 6286407..f7752d4 100644 --- a/tdctemplate/trb3sc_tdctemplate.lpf +++ b/tdctemplate/trb3sc_tdctemplate.lpf @@ -5,4 +5,5 @@ MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CELL "THE_TDC/*Channe*/Channel200/RingBuffer*FIFO/*" 5x; MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x; +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x; diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj index 3cdfea3..2af62b3 100644 --- a/tdctemplate/trb3sc_tdctemplate.prj +++ b/tdctemplate/trb3sc_tdctemplate.prj @@ -93,6 +93,7 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x8k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index 9180ee5..577390a 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -143,7 +143,8 @@ architecture trb3sc_arch of trb3sc_tdctemplate is signal timer : TIMERS; signal lcd_data : std_logic_vector(511 downto 0); signal trig_gen_out_i : std_logic_vector(3 downto 0); - + + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; --TDC signal hit_in_i : std_logic_vector(64 downto 1); signal logic_analyser_i : std_logic_vector(15 downto 0); @@ -175,7 +176,7 @@ begin RESET_OUT => reset_i, CLEAR_OUT => clear_i, - GSR_OUT => open, + GSR_OUT => GSR_N, FULL_CLK_OUT => clk_full, SYS_CLK_OUT => clk_sys, @@ -193,7 +194,7 @@ begin CLKOP => clk_cal, LOCK => open); -GSR_N <= reset_i; +-- GSR_N <= reset_i; --------------------------------------------------------------------------- -- TrbNet Uplink @@ -201,7 +202,7 @@ GSR_N <= reset_i; THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync generic map( - SERDES_NUM => 3, + SERDES_NUM => SERDES_NUM, IS_SYNC_SLAVE => c_YES ) port map( @@ -221,9 +222,9 @@ GSR_N <= reset_i; TX_DLM_WORD => open, --SFP Connection - SD_PRSNT_N_IN => SFP_MOD0(1), - SD_LOS_IN => SFP_LOS(1), - SD_TXDIS_OUT => SFP_TX_DIS(1), + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, --Control Interface BUS_RX => bussci_rx, BUS_TX => bussci_tx, @@ -233,7 +234,17 @@ GSR_N <= reset_i; ); SFP_TX_DIS(0) <= '1'; - + gen_sfp_con : if SERDES_NUM = 3 generate + sfp_los_i <= SFP_LOS(1); + sfp_prsnt_i <= SFP_MOD0(1); + SFP_TX_DIS(1) <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + --------------------------------------------------------------------------- -- Endpoint ---------------------------------------------------------------------------