From: hadeshyp Date: Thu, 19 Feb 2009 14:06:57 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~481 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1b8474ccfb66bccc0f4f0b7fe064366abb268d60;p=trbnet.git *** empty log message *** --- diff --git a/trb_net16_med_16_CC.vhd b/trb_net16_med_16_CC.vhd index fe009bf..1c9d847 100644 --- a/trb_net16_med_16_CC.vhd +++ b/trb_net16_med_16_CC.vhd @@ -265,6 +265,7 @@ begin resync_counter <= resync_counter + "1"; if resync_counter = x"F" then resync <= '0'; + resync_counter <= (others => '0'); link_state <= RESYNC_WAIT; end if; diff --git a/trb_net16_med_ecp_sfp.vhd b/trb_net16_med_ecp_sfp.vhd index 02daf45..39b96ea 100644 --- a/trb_net16_med_ecp_sfp.vhd +++ b/trb_net16_med_ecp_sfp.vhd @@ -111,21 +111,6 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is ); end component; - component dcs is --- synthesis translate_off - generic ( DCSMODE : string := "POS" ); --- synthesis translate_on - port( CLK0 : in std_logic; - CLK1 : in std_logic; - SEL : in std_logic; - DCSOUT : out std_logic - ); - end component; - - -- taken from HB1003.pdf, DCS section page 10-34 - attribute DCSMODE : string; - attribute DCSMODE of THE_DCS : label is "POS"; - component signal_sync is generic( WIDTH : integer := 1; -- @@ -140,12 +125,6 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is ); end component; - signal dcs_clk : std_logic; -- DCS output - signal dcs_clk_0 : std_logic; - signal dcs_clk_1 : std_logic; - signal dcs_select : std_logic; - signal flip_flop : std_logic; - signal refck2core : std_logic; --reset signals signal ffc_quad_rst : std_logic; @@ -241,9 +220,6 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is signal led_counter : std_logic_vector(17 downto 0); signal rx_led, tx_led : std_logic; - signal comb_rx_k : std_logic_vector(1 downto 0); - signal comb_rx_data : std_logic_vector(15 downto 0); - begin -------------------------------------------------------------------------- @@ -282,20 +258,7 @@ THE_RX_K_SYNC: signal_sync D_OUT => rx_k_q ); -THE_RX_SYNC: signal_sync - generic map( - DEPTH => 2, - WIDTH => 18 - ) - port map( - RESET => RESET, - D_IN(15 downto 0) => comb_rx_data, - D_IN(17 downto 16) => comb_rx_k, - CLK0 => ff_rxhalfclk, - CLK1 => ff_rxhalfclk, - D_OUT(17 downto 16)=> rx_k, - D_OUT(15 downto 0) => rx_data - ); + -- "Swap Bytes" indicator @@ -528,93 +491,68 @@ refclk2core_out <= refck2core; -- Instantiation of serdes module THE_SERDES: serdes -port map( core_txrefclk => clock, - core_rxrefclk => dcs_clk, --clk_in, - hdinp2 => sd_rxd_p_in, - hdinn2 => sd_rxd_n_in, - ff_rxiclk_ch2 => ff_rxhalfclk, - ff_txiclk_ch2 => ff_txhalfclk, - ff_ebrd_clk_2 => ff_rxhalfclk, -- not used, just for completeness - ff_txdata_ch2 => tx_data, - ff_tx_k_cntrl_ch2 => tx_k, - ff_force_disp_ch2 => "00", - ff_disp_sel_ch2 => "00", - ff_correct_disp_ch2 => "00", - ffc_rrst_ch2 => '0', - ffc_signal_detect_ch2 => '1', - ffc_enable_cgalign_ch2 => resync, --'1', - ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst_ch2, - ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst_ch2, - ffc_txpwdnb_ch2 => '1', - ffc_rxpwdnb_ch2 => '1', - ffc_macro_rst => '0', - ffc_quad_rst => ffc_quad_rst, - ffc_trst => '0', - hdoutp2 => sd_txd_p_out, - hdoutn2 => sd_txd_n_out, - ff_rxdata_ch2 => comb_rx_data, - ff_rx_k_cntrl_ch2 => comb_rx_k, - ff_rxfullclk_ch2 => open, - ff_rxhalfclk_ch2 => ff_rxhalfclk, - ff_disp_err_ch2 => open, - ff_cv_ch2 => link_error(7 downto 6), - ffs_rlos_lo_ch2 => link_error(8), - ffs_ls_sync_status_ch2 => link_ok(0), - ffs_cc_underrun_ch2 => link_error(0), - ffs_cc_overrun_ch2 => link_error(1), - ffs_txfbfifo_error_ch2 => link_error(2), - ffs_rxfbfifo_error_ch2 => link_error(3), - ffs_rlol_ch2 => link_error(4), - oob_out_ch2 => open, - ff_txfullclk => open, - ff_txhalfclk => ff_txhalfclk, - refck2core => refck2core, - ffs_plol => link_error(5) - ); + port map( + core_txrefclk => clk, + core_rxrefclk => clk, + hdinp2 => sd_rxd_p_in, + hdinn2 => sd_rxd_n_in, + ff_rxiclk_ch2 => ff_rxhalfclk, + ff_txiclk_ch2 => ff_txhalfclk, + ff_ebrd_clk_2 => ff_rxhalfclk, -- not used, just for completeness + ff_txdata_ch2 => tx_data, + ff_tx_k_cntrl_ch2 => tx_k, + ff_force_disp_ch2 => "00", + ff_disp_sel_ch2 => "00", + ff_correct_disp_ch2 => "00", + ffc_rrst_ch2 => '0', + ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst_ch2, + ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst_ch2, + ffc_txpwdnb_ch2 => '1', + ffc_rxpwdnb_ch2 => '1', + ffc_macro_rst => '0', + ffc_quad_rst => ffc_quad_rst, + ffc_trst => '0', + hdoutp2 => sd_txd_p_out, + hdoutn2 => sd_txd_n_out, + ff_rxdata_ch2 => rx_data, --comb_rx_data, + ff_rx_k_cntrl_ch2 => rx_k, --comb_rx_k, + ff_rxfullclk_ch2 => open, + ff_rxhalfclk_ch2 => ff_rxhalfclk, + ff_disp_err_ch2 => open, + ff_cv_ch2 => link_error(7 downto 6), + ffs_rlos_lo_ch2 => link_error(8), + ffs_ls_sync_status_ch2 => link_ok(0), + ffs_cc_underrun_ch2 => link_error(0), + ffs_cc_overrun_ch2 => link_error(1), + ffs_txfbfifo_error_ch2 => link_error(2), + ffs_rxfbfifo_error_ch2 => link_error(3), + ffs_rlol_ch2 => link_error(4), + oob_out_ch2 => open, + ff_txfullclk => open, + ff_txhalfclk => ff_txhalfclk, + refck2core => refck2core, + ffs_plol => link_error(5) + ); link_error(9) <= '0'; -- unused ----- Implement the TN1171 bugfix -dcs_select <= link_error(4); -dcs_clk_0 <= flip_flop xor ff_rxhalfclk; -dcs_clk_1 <= clock; - --- Flipflop for phase shifting in case of repeated loss of lock -THE_FLIP_FLOP_PROC: process( dcs_select, ffc_quad_rst ) -begin - if ( ffc_quad_rst = '1' ) then - flip_flop <= '0'; - elsif( rising_edge(dcs_select) ) then - flip_flop <= not flip_flop; - end if; -end process THE_FLIP_FLOP_PROC; - -THE_DCS: dcs --- synthesis translate_off -generic map ( DCSMODE => "POS" ) --- synthesis translate_on -port map( SEL => dcs_select, - CLK0 => dcs_clk_0, - CLK1 => dcs_clk_1, - DCSOUT => dcs_clk - ); - ------------------------------------------------------------------------- -- RX Fifo & Data output ------------------------------------------------------------------------- THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport -generic map( - USE_STATUS_FLAGS => c_NO - ) -port map( read_clock_in => clock, - write_clock_in => ff_rxhalfclk, - read_enable_in => fifo_rx_rd_en, - write_enable_in => fifo_rx_wr_en, - fifo_gsr_in => fifo_rx_reset, - write_data_in => fifo_rx_din, - read_data_out => fifo_rx_dout, - full_out => fifo_rx_full, - empty_out => fifo_rx_empty + generic map( + USE_STATUS_FLAGS => c_NO + ) + port map( + read_clock_in => clock, + write_clock_in => ff_rxhalfclk, + read_enable_in => fifo_rx_rd_en, + write_enable_in => fifo_rx_wr_en, + fifo_gsr_in => fifo_rx_reset, + write_data_in => fifo_rx_din, + read_data_out => fifo_rx_dout, + full_out => fifo_rx_full, + empty_out => fifo_rx_empty ); fifo_rx_reset <= RESET; diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index 6e829e8..fc5db99 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -134,6 +134,9 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is signal led_counter : std_logic_vector(18 downto 0); signal rx_led, tx_led, link_led : std_logic; + signal comb_fifo_wr_en_a : std_logic; + signal comb_fifo_din_a : std_logic_vector(17 downto 0); + begin TLK_ENABLE <= not RESET; @@ -169,8 +172,9 @@ begin almost_full_out => fifo_almost_full_a ); - fifo_wr_en_a <= ((reg_RX_DV and not reg_RX_ER) ) and rx_allow; fifo_rd_en_a <= rx_allow; + comb_fifo_wr_en_a <= ((reg_RX_DV and not reg_RX_ER) ) and rx_allow; + comb_fifo_din_a <= reg_RX_ER & reg_RX_DV & reg_RXD; -- fifo_wr_en_a <= ((reg_RX_DV and not reg_RX_ER) or fifo_almost_empty_a) and rx_allow; @@ -179,7 +183,15 @@ begin buf_MED_DATAREADY_OUT <= fifo_valid_read_a and fifo_dout_a(16) and not fifo_dout_a(17) and rx_allow; fifo_reset <= internal_reset; - fifo_din_a <= reg_RX_ER & reg_RX_DV & reg_RXD; + + + process(TLK_RX_CLK) + begin + if rising_edge(TLK_RX_CLK) then + fifo_wr_en_a <= comb_fifo_wr_en_a; + fifo_din_a <= comb_fifo_din_a; + end if; + end process; --STAT_OP & LED --------------- @@ -267,7 +279,11 @@ begin STAT_MONITOR(20) <= fifo_almost_empty_m; STAT_MONITOR(21) <= fifo_almost_empty_a; STAT_MONITOR(37 downto 22) <= CTRL_OP; - STAT_MONITOR(100 downto 38) <= (others => '0'); + STAT_MONITOR(46 downto 38) <= (others => '0'); + STAT_MONITOR(47) <= reg_TX_EN; + STAT_MONITOR(63 downto 48) <= reg_TXD; + STAT_MONITOR(81 downto 64) <= fifo_din_a; -- RX_ER & RX_DV & RX_DATA + STAT_MONITOR(100 downto 82) <= (others => '0'); process(TLK_RX_CLK) begin @@ -406,8 +422,14 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); ); TLK_TX_ER <= '0'; - TLK_TX_EN <= reg_TX_EN; - TLK_TXD <= reg_TXD; + + process(TLK_CLK_neg) + begin + if rising_edge(TLK_CLK_neg) then + TLK_TX_EN <= reg_TX_EN; + TLK_TXD <= reg_TXD; + end if; + end process; process(CLK) begin