From: Thomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Date: Fri, 12 Feb 2021 15:56:12 +0000 (+0100)
Subject: hub_test: Downlink TX clocks to 240 MHz TXPROGDIV
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1b9d1342938498c0e0a44a665268653585c83f3b;p=cri.git

hub_test: Downlink TX clocks to 240 MHz TXPROGDIV
---

diff --git a/hub_test/hub_test.xpr b/hub_test/hub_test.xpr
index 58c7252..afc3254 100644
--- a/hub_test/hub_test.xpr
+++ b/hub_test/hub_test.xpr
@@ -67,21 +67,14 @@
   <FileSets Version="1" Minor="31">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
       <Filter Type="Srcs"/>
-      <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xci">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xci">
+      <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gth_xcku_2gbps4_120mhz_txprogdiv240_txbufbypass/gth_xcku_2gbps4_120mhz_txprogdiv240_txbufbypass.xci">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xci">
+      <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gth_xcku_2gbps4_120mhz_txprogdiv240/gth_xcku_2gbps4_120mhz_txprogdiv240.xci">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
@@ -95,42 +88,21 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xci">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xci">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xci">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/ip/vio_0/vio_0.xci">
+      <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gtwizard_ultrascale_v1_7_bit_sync.v">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/ip/clk_wiz_0/clk_wiz_0.xci">
+      <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/ip/clk_wiz_1/clk_wiz_1.xci">
+      <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gtwizard_ultrascale_v1_7_reset_inv_sync.v">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
@@ -511,6 +483,69 @@
           <Attr Name="IsVisible" Val="1"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/ip/clk_wiz_0/clk_wiz_0.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/ip/clk_wiz_1/clk_wiz_1.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/ip/vio_0/vio_0.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="hub_test"/>
diff --git a/hub_test/src/hub_test.vhd b/hub_test/src/hub_test.vhd
index 01e2108..c834291 100644
--- a/hub_test/src/hub_test.vhd
+++ b/hub_test/src/hub_test.vhd
@@ -12,6 +12,9 @@ use work.trb_net16_hub_func.all;
 use work.version.all;
 
 entity hub_test is
+    generic (
+        BYPASS_TXBUF : integer range 0 to 1 := 0
+    );
     port (
         CLK_200_P             : in    std_logic;
         CLK_200_N             : in    std_logic;
@@ -84,6 +87,43 @@ architecture behavioral of hub_test is
         );
     end component;
 
+    component gtwizard_ultrascale_v1_7_8_gtwiz_buffbypass_tx is
+        generic (
+            P_BUFFER_BYPASS_MODE       : integer;
+            P_TOTAL_NUMBER_OF_CHANNELS : integer;
+            P_MASTER_CHANNEL_POINTER   : integer
+        );
+        port (
+            gtwiz_buffbypass_tx_clk_in        : in  std_logic;
+            gtwiz_buffbypass_tx_reset_in      : in  std_logic;
+            gtwiz_buffbypass_tx_start_user_in : in  std_logic;
+            gtwiz_buffbypass_tx_resetdone_in  : in  std_logic;
+            gtwiz_buffbypass_tx_done_out      : out std_logic;
+            gtwiz_buffbypass_tx_error_out     : out std_logic;
+            txphaligndone_in                  : in  std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txphinitdone_in                   : in  std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txdlysresetdone_in                : in  std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txsyncout_in                      : in  std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txsyncdone_in                     : in  std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txphdlyreset_out                  : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txphalign_out                     : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txphalignen_out                   : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txphdlypd_out                     : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txphinit_out                      : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txphovrden_out                    : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txdlysreset_out                   : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txdlybypass_out                   : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txdlyen_out                       : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txdlyovrden_out                   : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txphdlytstclk_out                 : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txdlyhold_out                     : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txdlyupdown_out                   : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txsyncmode_out                    : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txsyncallin_out                   : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
+            txsyncin_out                      : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0)
+        );
+    end component gtwizard_ultrascale_v1_7_8_gtwiz_buffbypass_tx;
+
     signal clk_200_ibuf : std_logic;
     signal baseclk_100 : std_logic;
     signal mb_ext_resets_n : std_logic_vector(7 downto 0);
@@ -97,6 +137,7 @@ architecture behavioral of hub_test is
     signal sysclk_120 : std_logic;
     signal sysclk_240 : std_logic;
     signal sysclk_locked : std_logic;
+    signal not_sysclk_locked : std_logic;
 
     signal mgtrefclk_downlink : std_logic;
     signal mgtrefclk_downlink_hrow : std_logic;
@@ -107,6 +148,11 @@ architecture behavioral of hub_test is
     signal mgtrefclk_uplink_bufg : std_logic;
     signal mgtrefclk_uplink_bufg_half : std_logic;
 
+    signal downlink_usrclk : std_logic;
+    signal downlink_usrclk_double : std_logic;
+    signal downlink_usrclk_active : std_logic;
+    signal not_downlink_usrclk_active : std_logic;
+
     signal initial_clear_timer : unsigned(27 downto 0) := (others => '0');
     signal initial_clear_n : std_logic := '0';
 
@@ -124,6 +170,36 @@ architecture behavioral of hub_test is
     signal med2int_i : med2int_array_t(0 to 10);
     signal int2med_i : int2med_array_t(0 to 10);
 
+    signal txoutclk : std_logic_vector(0 to INTERFACE_NUM - 2);
+    signal txprgdivresetdone : std_logic_vector(0 to INTERFACE_NUM - 2);
+
+    signal txresetdone : std_logic_vector(0 to INTERFACE_NUM - 2);
+
+    signal txdlybypass : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txdlyen : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txdlyhold : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txdlyovrden : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txdlysreset : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txdlyupdown : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txphalign : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txphalignen : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txphdlypd : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txphdlyreset : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txphdlytstclk : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txphinit : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txphovrden : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txsyncallin : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txsyncin : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txsyncmode : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txdlysresetdone : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txphaligndone : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txphinitdone : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txsyncdone : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal txsyncout : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+    signal buffbypass_tx_start_user : std_logic := '0';
+    signal buffbypass_tx_done : std_logic;
+    signal buffbypass_tx_error : std_logic;
+
     signal ctrlbus_rx_i : CTRLBUS_RX;
     signal bussci1_rx : CTRLBUS_RX;
     signal bussci2_rx : CTRLBUS_RX;
@@ -256,6 +332,32 @@ begin
         locked   => sysclk_locked,
         clk_in1  => mgtrefclk_downlink_bufg
     );
+    not_sysclk_locked <= not sysclk_locked;
+
+    downlink_usrclk_active <= txprgdivresetdone(0);
+    not_downlink_usrclk_active <= not downlink_usrclk_active;
+
+    THE_DOWNLINK_USRCLK_DOUBLE : BUFG_GT
+    port map (
+        O       => downlink_usrclk_double,
+        CE      => '1',
+        CEMASK  => '0',
+        CLR     => not_downlink_usrclk_active,
+        CLRMASK => '0',
+        DIV     => "000",
+        I       => txoutclk(0)
+    );
+
+    THE_DOWNLINK_USRCLK : BUFG_GT
+    port map (
+        O       => downlink_usrclk,
+        CE      => '1',
+        CEMASK  => '0',
+        CLR     => not_downlink_usrclk_active,
+        CLRMASK => '0',
+        DIV     => "001",
+        I       => txoutclk(0)
+    );
 
     THE_MGTREFCLK0_232 : IBUFDS_GTE3
     generic map (
@@ -367,7 +469,9 @@ begin
     generic map (
         IS_SYNC_SLAVE  => c_YES,
         LINE_RATE_KBPS => 2000000,
-        REFCLK_FREQ_HZ => 200000000
+        REFCLK_FREQ_HZ => 200000000,
+        USE_TXPROGDIV  => 0,
+        BYPASS_TXBUF   => 0
     )
     port map (
         SYSCLK            => sysclk_120,
@@ -384,6 +488,8 @@ begin
         TXUSRCLK_ACTIVE   => '1', -- TODO: should be GTPOWERGOOD?
         RXPMARESETDONE    => open,
         TXPMARESETDONE    => open,
+        RXRESETDONE       => open,
+        TXRESETDONE       => open,
         RESET             => reset,
         CLEAR             => clear,
         RXN               => RXN(INTERFACE_NUM - 1),
@@ -410,7 +516,9 @@ begin
         generic map (
             IS_SYNC_SLAVE  => c_NO,
             LINE_RATE_KBPS => 2400000,
-            REFCLK_FREQ_HZ => 120000000
+            REFCLK_FREQ_HZ => 120000000,
+            USE_TXPROGDIV  => 1,
+            BYPASS_TXBUF   => BYPASS_TXBUF
         )
         port map (
             SYSCLK            => sysclk_120,
@@ -418,15 +526,17 @@ begin
             GTREFCLK          => mgtrefclk_downlink,
             GTREFCLK_BUFG     => mgtrefclk_downlink_bufg,
             RXOUTCLK          => open,
-            TXOUTCLK          => open,
-            RXUSRCLK          => sysclk_120,
-            RXUSRCLK_DOUBLE   => sysclk_240,
-            TXUSRCLK          => sysclk_120,
-            TXUSRCLK_DOUBLE   => sysclk_240,
-            RXUSRCLK_ACTIVE   => sysclk_locked,
-            TXUSRCLK_ACTIVE   => sysclk_locked,
+            TXOUTCLK          => txoutclk(linknum),
+            RXUSRCLK          => downlink_usrclk,
+            RXUSRCLK_DOUBLE   => downlink_usrclk_double,
+            TXUSRCLK          => downlink_usrclk,
+            TXUSRCLK_DOUBLE   => downlink_usrclk_double,
+            RXUSRCLK_ACTIVE   => downlink_usrclk_active,
+            TXUSRCLK_ACTIVE   => downlink_usrclk_active,
             RXPMARESETDONE    => open,
             TXPMARESETDONE    => open,
+            RXRESETDONE       => open,
+            TXRESETDONE       => txresetdone(linknum),
             RESET             => reset,
             CLEAR             => clear,
             RXN               => RXN(linknum),
@@ -442,10 +552,71 @@ begin
             SD_LOS_IN         => mpod_d_los(linknum + 3),
             SD_TXDIS_OUT      => mpod_d_txdis(linknum + 3),
             STAT_DEBUG        => open,
-            CTRL_DEBUG        => (others => '0')
+            CTRL_DEBUG        => (others => '0'),
+            TXPRGDIVRESETDONE => txprgdivresetdone(linknum),
+            TXDLYBYPASS       => txdlybypass(linknum),
+            TXDLYEN           => txdlyen(linknum),
+            TXDLYHOLD         => txdlyhold(linknum),
+            TXDLYOVRDEN       => txdlyovrden(linknum),
+            TXDLYSRESET       => txdlysreset(linknum),
+            TXDLYUPDOWN       => txdlyupdown(linknum),
+            TXPHALIGN         => txphalign(linknum),
+            TXPHALIGNEN       => txphalignen(linknum),
+            TXPHDLYPD         => txphdlypd(linknum),
+            TXPHDLYRESET      => txphdlyreset(linknum),
+            TXPHDLYTSTCLK     => txphdlytstclk(linknum),
+            TXPHINIT          => txphinit(linknum),
+            TXPHOVRDEN        => txphovrden(linknum),
+            TXSYNCALLIN       => txsyncallin(linknum),
+            TXSYNCIN          => txsyncin(linknum),
+            TXSYNCMODE        => txsyncmode(linknum),
+            TXDLYSRESETDONE   => txdlysresetdone(linknum),
+            TXPHALIGNDONE     => txphaligndone(linknum),
+            TXPHINITDONE      => txphinitdone(linknum),
+            TXSYNCDONE        => txsyncdone(linknum),
+            TXSYNCOUT         => txsyncout(linknum)
         );
     end generate generate_downlinks;
 
+    generate_bypass_txbuf:
+    if BYPASS_TXBUF = 1 generate
+    begin
+        buffbypass_tx_i : gtwizard_ultrascale_v1_7_8_gtwiz_buffbypass_tx
+        generic map (
+            P_BUFFER_BYPASS_MODE       => 0,
+            P_TOTAL_NUMBER_OF_CHANNELS => INTERFACE_NUM - 1,
+            P_MASTER_CHANNEL_POINTER   => 0
+        )
+        port map (
+            gtwiz_buffbypass_tx_clk_in        => sysclk_120,
+            gtwiz_buffbypass_tx_reset_in      => not_sysclk_locked,
+            gtwiz_buffbypass_tx_start_user_in => buffbypass_tx_start_user,
+            gtwiz_buffbypass_tx_resetdone_in  => txresetdone(0), -- TODO: OR of all channels?
+            gtwiz_buffbypass_tx_done_out      => buffbypass_tx_done,
+            gtwiz_buffbypass_tx_error_out     => buffbypass_tx_error,
+            txphaligndone_in                  => txphaligndone,
+            txphinitdone_in                   => txphinitdone,
+            txdlysresetdone_in                => txdlysresetdone,
+            txsyncout_in                      => txsyncout,
+            txsyncdone_in                     => txsyncdone,
+            txphdlyreset_out                  => txphdlyreset,
+            txphalign_out                     => txphalign,
+            txphalignen_out                   => txphalignen,
+            txphdlypd_out                     => txphdlypd,
+            txphinit_out                      => txphinit,
+            txphovrden_out                    => txphovrden,
+            txdlysreset_out                   => txdlysreset,
+            txdlybypass_out                   => txdlybypass,
+            txdlyen_out                       => txdlyen,
+            txdlyovrden_out                   => txdlyovrden,
+            txphdlytstclk_out                 => txphdlytstclk,
+            txdlyhold_out                     => txdlyhold,
+            txdlyupdown_out                   => txdlyupdown,
+            txsyncmode_out                    => txsyncmode,
+            txsyncallin_out                   => txsyncallin,
+            txsyncin_out                      => txsyncin
+        );
+    end generate generate_bypass_txbuf;
 
     -- Create a 100 ns test pulse for debugging of microslice timing
     process (sysclk_240) is