From: Benedikt Gutsche <b.gutsche@gsi.de>
Date: Wed, 10 Jan 2024 12:51:29 +0000 (+0100)
Subject: added testbench stuff for sca simulation
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1beeef2f84b73022854fda441614b3ae0dc3aedc;p=trb5sc.git

added testbench stuff for sca simulation
---

diff --git a/.gitignore b/.gitignore
index 3f6e911..915a1ff 100644
--- a/.gitignore
+++ b/.gitignore
@@ -37,3 +37,4 @@ cores/serdes_sync_0
 cores/pcs.vhd
 archv
 _math_real.vhd
+transcript
diff --git a/vldb/code/Testbench/SCA-model/Auxiliary_i2c_Port.v b/vldb/code/Testbench/SCA-model/Auxiliary_i2c_Port.v
new file mode 100644
index 0000000..08c21f9
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/Auxiliary_i2c_Port.v
@@ -0,0 +1,453 @@
+
+/////////////////////////////////////////////////////////////////////////////
+// Design Name:    GBT_SCA                                                 //
+// Module Name:    Auxiliary_Port(TRI Version)                             //
+// Made by:        Alessandro Caratelli                                    //
+//                                                                         //
+// Description:    Auxiliary serial port to access the SCA                 // 
+//                 for testing or deasy chain running mode                 //
+// Company:        CERN (PH-ESE)                                           //
+// Create Date:    10/jan/2014                                             //
+/////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+module SwitchPort_tri (
+      //global signals 
+      input              clk_1,              clk_2,              clk_3,
+      input              resetB_1,           resetB_2,           resetB_3,
+      //Auxiliary port pad connections
+      input              auxPort_TestEn_1,   auxPort_TestEn_2,   auxPort_TestEn_3,
+      input              auxPort_SCL_1,      auxPort_SCL_2,      auxPort_SCL_3,
+      input              auxPort_SDA_in_1,   auxPort_SDA_in_2,   auxPort_SDA_in_3,      
+      output wire        auxPort_SDA_out_1,  auxPort_SDA_out_2,  auxPort_SDA_out_3,
+      output wire        auxPort_SDA_oEn_1,  auxPort_SDA_oEn_2,  auxPort_SDA_oEn_3,
+      //Network Controller connections
+      output wire        nctrl_tx_dav_1,     nctrl_tx_dav_2,     nctrl_tx_dav_3,
+      input       [15:0] nctrl_tx_dat_1,     nctrl_tx_dat_2,     nctrl_tx_dat_3,  
+      output wire        nctrl_rx_ena_1,     nctrl_rx_ena_2,     nctrl_rx_ena_3,
+      input              nctrl_rx_dav_1,     nctrl_rx_dav_2,     nctrl_rx_dav_3,
+      output wire [15:0] nctrl_rx_dat_1,     nctrl_rx_dat_2,     nctrl_rx_dat_3,
+      input              nctrl_tx_ena_1,     nctrl_tx_ena_2,     nctrl_tx_ena_3,
+      //EPORT signals to Network Controller
+      input              elink_tx_dav_1,     elink_tx_dav_2,     elink_tx_dav_3,
+      output wire [15:0] elink_tx_dat_1,     elink_tx_dat_2,     elink_tx_dat_3,
+      input              elink_rx_ena_1,     elink_rx_ena_2,     elink_rx_ena_3,
+      output wire        elink_rx_dav_1,     elink_rx_dav_2,     elink_rx_dav_3,
+      input       [15:0] elink_rx_dat_1,     elink_rx_dat_2,     elink_rx_dat_3,
+      output wire        elink_tx_ena_1,     elink_tx_ena_2,     elink_tx_ena_3
+      );
+      //Auxiliary I2C port signals to Network Controller
+      wire               aux_tx_dav_1,       aux_tx_dav_2,       aux_tx_dav_3;
+      wire        [15:0] aux_tx_dat_1,       aux_tx_dat_2,       aux_tx_dat_3;
+      wire               aux_rx_ena_1,       aux_rx_ena_2,       aux_rx_ena_3;
+      wire               aux_rx_dav_1,       aux_rx_dav_2,       aux_rx_dav_3;
+      wire        [15:0] aux_rx_dat_1,       aux_rx_dat_2,       aux_rx_dat_3;
+      wire               aux_tx_ena_1,       aux_tx_ena_2,       taux_x_ena_3;
+	wire               clk_g_1,            clk_g_2,            clk_g_3;
+	
+	auxiliary_port aux_port (
+		//global signals
+		.clk_1(clk_g_1),             .clk_2(clk_g_2),             .clk_3(clk_g_3),
+      	.reset_n_1(resetB_1),        .reset_n_2(resetB_2),        .reset_n_3(resetB_3),
+      	//I2C signals
+		.SDAo_1(auxPort_SDA_out_1),  .SDAo_2(auxPort_SDA_out_2),  .SDAo_3(auxPort_SDA_out_3),              
+		.SDAen_1(auxPort_SDA_oEn_1), .SDAen_2(auxPort_SDA_oEn_2), .SDAen_3(auxPort_SDA_oEn_3),             
+		.SDAi_1(auxPort_SDA_in_1),   .SDAi_2(auxPort_SDA_in_2),   .SDAi_3(auxPort_SDA_in_3),   
+		.SCL_1(auxPort_SCL_1),       .SCL_2(auxPort_SCL_2),       .SCL_3(auxPort_SCL_3),           
+		//Atlantic Interface eport signals
+		.rx_dav_1(aux_rx_dav_1),     .rx_dav_2(aux_rx_dav_2),     .rx_dav_3(aux_rx_dav_3),
+		.tx_ena_1(aux_tx_ena_1),     .tx_ena_2(aux_tx_ena_2),     .tx_ena_3(aux_tx_ena_3),
+		.tx_dat_1(aux_tx_dat_1),     .tx_dat_2(aux_tx_dat_2),     .tx_dat_3(aux_tx_dat_3),
+		.rx_ena_1(aux_rx_ena_1),     .rx_ena_2(aux_rx_ena_2),     .rx_ena_3(aux_rx_ena_3),
+		.rx_dat_1(aux_rx_dat_1),     .rx_dat_2(aux_rx_dat_2),     .rx_dat_3(aux_rx_dat_3)  
+	);  
+	
+	clk_gating_tri ckgate(
+		.en_clk_1(auxPort_TestEn_1), .en_clk_2(auxPort_TestEn_2),   .en_clk_3(auxPort_TestEn_3),
+		.clk_1(clk_1),               .clk_2(clk_2),               .clk_3(clk_3),
+		.clk_gated_1(clk_g_1),       .clk_gated_2(clk_g_2),       .clk_gated_3(clk_g_3)
+	);
+	
+	 		
+      assign nctrl_tx_dav_1 = (auxPort_TestEn_1) ? 1'b1 : elink_tx_dav_1;
+      assign nctrl_tx_dav_2 = (auxPort_TestEn_2) ? 1'b1 : elink_tx_dav_2;
+      assign nctrl_tx_dav_3 = (auxPort_TestEn_3) ? 1'b1 : elink_tx_dav_3;
+      
+      assign nctrl_rx_dat_1 = (auxPort_TestEn_1) ? aux_rx_dat_1 : elink_rx_dat_1; 
+      assign nctrl_rx_dat_2 = (auxPort_TestEn_2) ? aux_rx_dat_2 : elink_rx_dat_2;
+      assign nctrl_rx_dat_3 = (auxPort_TestEn_3) ? aux_rx_dat_3 : elink_rx_dat_3;
+      
+      assign nctrl_rx_ena_1 = (auxPort_TestEn_1) ? aux_rx_ena_1 : elink_rx_ena_1;
+      assign nctrl_rx_ena_2 = (auxPort_TestEn_2) ? aux_rx_ena_2 : elink_rx_ena_2;
+      assign nctrl_rx_ena_3 = (auxPort_TestEn_3) ? aux_rx_ena_3 : elink_rx_ena_3;
+      
+      assign elink_tx_dat_1 = nctrl_tx_dat_1; assign aux_tx_dat_1 = nctrl_tx_dat_1;
+      assign elink_tx_dat_2 = nctrl_tx_dat_2; assign aux_tx_dat_2 = nctrl_tx_dat_2;
+      assign elink_tx_dat_3 = nctrl_tx_dat_3; assign aux_tx_dat_3 = nctrl_tx_dat_3;
+      
+      assign elink_rx_dav_1 = nctrl_rx_dav_1; assign aux_rx_dav_1 = nctrl_rx_dav_1;
+      assign elink_rx_dav_2 = nctrl_rx_dav_2; assign aux_rx_dav_2 = nctrl_rx_dav_2;
+      assign elink_rx_dav_3 = nctrl_rx_dav_3; assign aux_rx_dav_3 = nctrl_rx_dav_3;
+       
+      assign elink_tx_ena_1 = nctrl_tx_ena_1; assign aux_tx_ena_1 = nctrl_tx_ena_1;
+      assign elink_tx_ena_2 = nctrl_tx_ena_2; assign aux_tx_ena_2 = nctrl_tx_ena_2;
+      assign elink_tx_ena_3 = nctrl_tx_ena_3; assign aux_tx_ena_3 = nctrl_tx_ena_3;
+ 
+endmodule
+ 
+      
+      
+module clk_gating_tri(
+	input       en_clk_1,    en_clk_2,    en_clk_3,
+	input       clk_1,       clk_2,       clk_3,
+	output wire clk_gated_1, clk_gated_2, clk_gated_3
+	);
+	
+	clk_gating ckgate1(
+		.en_clk(en_clk_1),
+		.clk(clk_1),
+		.clk_gated(clk_gated_1)
+	);
+	clk_gating ckgate2(
+		.en_clk(en_clk_2),
+		.clk(clk_2),
+		.clk_gated(clk_gated_2)
+	);
+	clk_gating ckgate3(
+		.en_clk(en_clk_3),
+		.clk(clk_3),
+		.clk_gated(clk_gated_3)
+	);
+endmodule
+
+module clk_gating(
+	input       en_clk,
+	input       clk,
+	output wire clk_gated
+	);
+	
+	reg en_clk_latched;
+	
+	always @(clk) begin //keep during high period
+		if (~clk) en_clk_latched = en_clk;
+	end
+	
+	assign clk_gated = clk & en_clk_latched;
+	
+endmodule
+
+
+
+
+
+`timescale 1ns / 1ps
+
+module wishbone2atlanticSCA_tri (clk_1, clk_2, clk_3,reset_n_1, reset_n_2, reset_n_3,wb_ack_out_1, wb_ack_out_2, wb_ack_out_3,wb_adr_in_1, wb_adr_in_2, wb_adr_in_3,wb_dat_in_1, wb_dat_in_2, wb_dat_in_3,wb_we_in_1, wb_we_in_2, wb_we_in_3, wb_stb_in_1, wb_stb_in_2, wb_stb_in_3,wb_cyc_in_1, wb_cyc_in_2, wb_cyc_in_3,wb_dat_out_1, wb_dat_out_2, wb_dat_out_3,
+					rx_ena_1, rx_ena_2, rx_ena_3,rx_dav_1, rx_dav_2, rx_dav_3,tx_ena_1, tx_ena_2, tx_ena_3,rx_dat_1, rx_dat_2, rx_dat_3,tx_dat_1, tx_dat_2, tx_dat_3);
+
+	//global signals
+	input         clk_1,        clk_2,        clk_3; 
+	input         reset_n_1,    reset_n_2,    reset_n_3;	
+	//wb interface
+	output        wb_ack_out_1, wb_ack_out_2, wb_ack_out_3;                  
+	input   [3:0] wb_adr_in_1,  wb_adr_in_2,  wb_adr_in_3;         
+	input   [7:0] wb_dat_in_1,  wb_dat_in_2,  wb_dat_in_3;                  
+	input         wb_we_in_1,   wb_we_in_2,   wb_we_in_3;          
+	input         wb_stb_in_1,  wb_stb_in_2,  wb_stb_in_3;      
+	input         wb_cyc_in_1,  wb_cyc_in_2,  wb_cyc_in_3; 
+	output  [7:0] wb_dat_out_1, wb_dat_out_2, wb_dat_out_3;
+	//Atlantic Interface eport signals	
+	output        rx_ena_1,     rx_ena_2,     rx_ena_3;
+      input         rx_dav_1,     rx_dav_2,     rx_dav_3;
+      input         tx_ena_1,     tx_ena_2,     tx_ena_3;
+      output [15:0] rx_dat_1,     rx_dat_2,     rx_dat_3;
+      input  [15:0] tx_dat_1,     tx_dat_2,     tx_dat_3;
+      
+	// triple module redundancy signals
+	wire [1:0] CTRL_1, CTRL_2, CTRL_3;
+	wire [63:0] data_1, data_2, data_3;
+	wire [2:0] count_tx_1, count_tx_2, count_tx_3;
+	wire wb_ack_out_1, wb_ack_out_2, wb_ack_out_3;
+	wire state_rx_1, state_rx_2, state_rx_3;
+	wire [1:0] count_rx_1, count_rx_2, count_rx_3;
+	wire [15:0] rx_dat_1, rx_dat_2, rx_dat_3;
+	wire send_ack_1, send_ack_2, send_ack_3;
+	wire [7:0] wb_dat_out_1, wb_dat_out_2, wb_dat_out_3;
+	wire [1:0] CTRL;
+	wire [63:0] data;
+	wire [2:0] count_tx;
+	wire wb_ack_out;
+	wire state_rx;
+	wire [1:0] count_rx;
+	wire [15:0] rx_dat;
+	wire send_ack;
+	wire [7:0] wb_dat_out;
+	
+	wishbone2atlanticSCA_iostate wishbone2atlanticSCA_iostate_1   (.clk(clk_1),.reset_n(reset_n_1),.wb_ack_out_i(wb_ack_out_1), .wb_ack_out_o(wb_ack_out_2),.wb_adr_in(wb_adr_in_1),.wb_dat_in(wb_dat_in_1),.wb_we_in(wb_we_in_1), .wb_stb_in(wb_stb_in_1),.wb_cyc_in(wb_cyc_in_1),.wb_dat_out_i(wb_dat_out_1), .wb_dat_out_o(wb_dat_out_2),
+					.rx_ena(rx_ena_1),.rx_dav(rx_dav_1),.tx_ena(tx_ena_1),.rx_dat_i(rx_dat_1), .rx_dat_o(rx_dat_2),.tx_dat(tx_dat_1), .CTRL_i(CTRL_1), .CTRL_o(CTRL_2), .data_i(data_1), .data_o(data_2), .count_tx_i(count_tx_1), .count_tx_o(count_tx_2), .state_rx_i(state_rx_1), .state_rx_o(state_rx_2), .count_rx_i(count_rx_1), .count_rx_o(count_rx_2), .send_ack_i(send_ack_1), .send_ack_o(send_ack_2));
+	wishbone2atlanticSCA_iostate wishbone2atlanticSCA_iostate_2   (.clk(clk_2),.reset_n(reset_n_2),.wb_ack_out_i(wb_ack_out_2), .wb_ack_out_o(wb_ack_out_3),.wb_adr_in(wb_adr_in_2),.wb_dat_in(wb_dat_in_2),.wb_we_in(wb_we_in_2), .wb_stb_in(wb_stb_in_2),.wb_cyc_in(wb_cyc_in_2),.wb_dat_out_i(wb_dat_out_2), .wb_dat_out_o(wb_dat_out_3),
+					.rx_ena(rx_ena_2),.rx_dav(rx_dav_2),.tx_ena(tx_ena_2),.rx_dat_i(rx_dat_2), .rx_dat_o(rx_dat_3),.tx_dat(tx_dat_2), .CTRL_i(CTRL_2), .CTRL_o(CTRL_3), .data_i(data_2), .data_o(data_3), .count_tx_i(count_tx_2), .count_tx_o(count_tx_3), .state_rx_i(state_rx_2), .state_rx_o(state_rx_3), .count_rx_i(count_rx_2), .count_rx_o(count_rx_3), .send_ack_i(send_ack_2), .send_ack_o(send_ack_3));
+	wishbone2atlanticSCA_iostate wishbone2atlanticSCA_iostate_3   (.clk(clk_3),.reset_n(reset_n_3),.wb_ack_out_i(wb_ack_out_3), .wb_ack_out_o(wb_ack_out),.wb_adr_in(wb_adr_in_3),.wb_dat_in(wb_dat_in_3),.wb_we_in(wb_we_in_3), .wb_stb_in(wb_stb_in_3),.wb_cyc_in(wb_cyc_in_3),.wb_dat_out_i(wb_dat_out_3), .wb_dat_out_o(wb_dat_out),
+					.rx_ena(rx_ena_3),.rx_dav(rx_dav_3),.tx_ena(tx_ena_3),.rx_dat_i(rx_dat_3), .rx_dat_o(rx_dat),.tx_dat(tx_dat_3), .CTRL_i(CTRL_3), .CTRL_o(CTRL), .data_i(data_3), .data_o(data), .count_tx_i(count_tx_3), .count_tx_o(count_tx), .state_rx_i(state_rx_3), .state_rx_o(state_rx), .count_rx_i(count_rx_3), .count_rx_o(count_rx), .send_ack_i(send_ack_3), .send_ack_o(send_ack));
+
+	majority_voter #(.WIDTH(98)) mv (
+		.in1({CTRL_2, data_2, count_tx_2, wb_ack_out_2, state_rx_2, count_rx_2, rx_dat_2, send_ack_2, wb_dat_out_2}),
+		.in2({CTRL_3, data_3, count_tx_3, wb_ack_out_3, state_rx_3, count_rx_3, rx_dat_3, send_ack_3, wb_dat_out_3}),
+		.in3({CTRL, data, count_tx, wb_ack_out, state_rx, count_rx, rx_dat, send_ack, wb_dat_out}),
+		.out({CTRL_1, data_1, count_tx_1, wb_ack_out_1, state_rx_1, count_rx_1, rx_dat_1, send_ack_1, wb_dat_out_1}),
+		.err()
+	);
+endmodule
+
+
+
+module wishbone2atlanticSCA_iostate (clk,reset_n,wb_ack_out_i, wb_ack_out_o,wb_adr_in,wb_dat_in,wb_we_in, wb_stb_in,wb_cyc_in,wb_dat_out_i, wb_dat_out_o,
+					rx_ena,rx_dav,tx_ena,rx_dat_i, rx_dat_o,tx_dat, CTRL_i, CTRL_o, data_i, data_o, count_tx_i, count_tx_o, state_rx_i, state_rx_o, count_rx_i, count_rx_o, send_ack_i, send_ack_o);	
+	//global signals
+	input         clk; 
+	input         reset_n;
+	//wb interface
+	input   [3:0] wb_adr_in;         
+	input   [7:0] wb_dat_in;                  
+	input         wb_we_in;          
+	input         wb_stb_in;      
+	input         wb_cyc_in; 
+	output  [7:0] wb_dat_out_o;	
+	output        wb_ack_out_o;	
+	//atlantic interface
+	input         rx_dav;  
+      input         tx_ena;
+      input  [15:0] tx_dat;
+ 	output        rx_ena;
+	output [15:0] rx_dat_o;     
+      // triple module redundancy signals
+      input         send_ack_i; 
+      input   [1:0] count_rx_i; 
+      input         state_rx_i;     
+	input   [2:0] count_tx_i;
+      input  [63:0] data_i;
+      input   [1:0] CTRL_i;
+	output        send_ack_o;
+      output  [1:0] count_rx_o;
+	output        state_rx_o;
+	input  [15:0] rx_dat_i;
+      input         wb_ack_out_i;                  
+	output  [2:0] count_tx_o;
+	output [63:0] data_o;
+	output  [1:0] CTRL_o;
+	input   [7:0] wb_dat_out_i;
+      
+	//Atlantic Interface eport signals	
+	reg    [63:0] data_o;
+	reg           state_rx_o, send_ack_o,  wb_ack_out_o; 
+	reg     [2:0] count_tx_o;
+	reg     [1:0] count_rx_o, CTRL_o;
+	reg     [7:0] wb_dat_out_o;
+	
+	wire   [15:0] rx_dat_o;
+      wire          send, rx_ena, SCA_new_pkt_rec;
+      
+      `define inactive    1'b0
+      `define send_packet 1'b1
+      
+      assign rx_ena = state_rx_i;
+      
+	assign rx_dat_o[15:8] = (state_rx_i==`send_packet) ? (data_i[ (16*count_rx_i) +: 8])     : {8{1'b0}};
+	assign rx_dat_o[7:0]  = (state_rx_i==`send_packet) ? (data_i[ ((16*count_rx_i)+8) +: 8]) : {8{1'b0}};
+	
+      assign SCA_new_pkt_rec = ((~tx_ena) && (|(count_tx_i))) ? 1'b1 : 1'b0;
+	
+	
+	//write ctrl register
+	always @(posedge clk or negedge reset_n) begin 
+		if (~reset_n) CTRL_o <=#1 2'h0;
+		else begin
+			if(wb_cyc_in & wb_stb_in & wb_we_in & (wb_adr_in[3:0] == 4'h8)) 
+				CTRL_o <=#1 wb_dat_in[1:0];
+			else begin
+				if(&(count_rx_i)) CTRL_o[0] <=#1 1'b0;
+				else              CTRL_o[0] <=#1 CTRL_i[0];
+				if(SCA_new_pkt_rec) CTRL_o[1] <=#1 1'b1;
+				else                CTRL_o[1] <=#1 CTRL_i[1];
+			end
+		end
+	end
+	assign send = CTRL_i[0];
+
+	// write_data_buffer
+	always @(posedge clk or negedge reset_n) begin 
+		if (~reset_n) data_o <=#1 {64{1'b0}};
+		else begin
+			data_o <=#1 data_i;
+			if(wb_cyc_in & wb_stb_in & wb_we_in & (wb_adr_in[3:0] < 8)) 
+				data_o[ (8 * wb_adr_in[3:0]) +: 8] <=#1 wb_dat_in;
+			else if(tx_ena) begin
+				data_o[(count_tx_i*16) +: 8]     <=#1  tx_dat[15:8];
+				data_o[((count_tx_i*16)+8) +: 8] <=#1  tx_dat[7:0];
+			end
+			else 
+				data_o[63:0] <=#1 data_i[63:0];
+		end
+	end
+	   
+	// transmit_word_counter
+      always @(posedge clk or negedge reset_n) begin 
+      	if(~reset_n) count_tx_o <=#1 3'h0;
+            else begin
+            	if(tx_ena) count_tx_o <=#1 count_tx_i + 1;
+           		else count_tx_o <=#1 3'h0;         		
+           	end
+      end
+  
+      // acknoladge_wb
+	always @(posedge clk or negedge reset_n) begin 
+		if (~reset_n) wb_ack_out_o <=#1 1'b0;
+		else	wb_ack_out_o <=#1 wb_cyc_in & wb_stb_in & ~wb_ack_out_i;
+	end
+	// receive_state_machine    
+      always @(posedge clk or negedge reset_n) begin 
+            if(~reset_n) begin
+                  state_rx_o <=#1 `inactive;
+                  count_rx_o <=#1 2'h0;
+            end
+            else case (state_rx_i) 
+           		`inactive:    begin
+           			count_rx_o <=#1 2'h0;
+           		      if(send) state_rx_o <=#1 `send_packet;
+           		      else state_rx_o <=#1 `inactive;
+           		 end
+           		`send_packet: begin
+           		      if(&(count_rx_i)) begin
+           		      	state_rx_o <=#1 `inactive;
+           		      	count_rx_o <=#1 2'h0;
+           		      end
+           		      else begin
+           		      	state_rx_o <=#1 `send_packet;
+           		      	count_rx_o <=#1 count_rx_i + 2'h1;
+           		      end
+           		 end
+            endcase
+      end
+	
+      // read buf through wb   
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) 
+			wb_dat_out_o <=#1 {8{1'b0}};
+		else begin	
+			if(wb_adr_in[3:0] < 8)
+				wb_dat_out_o <=#1  data_i[ (8 * wb_adr_in[3:0]) +: 8];
+			else if(wb_adr_in[3:0] == 4'h8) 
+				wb_dat_out_o <=#1 CTRL_i;
+			else 
+				wb_dat_out_o <=#1 {8{1'b0}};
+		end
+	end
+  
+endmodule
+
+`include "I2C_slavle_wb.v"
+
+module auxiliary_port (
+	//global signals
+	input             clk_1,        clk_2,        clk_3,
+      input             reset_n_1,    reset_n_2,    reset_n_3,
+      //I2C signals
+	output wire       SDAo_1,       SDAo_2,       SDAo_3,              
+	output wire       SDAen_1,      SDAen_2,      SDAen_3,             
+	input             SDAi_1,       SDAi_2,       SDAi_3,   
+	input             SCL_1,        SCL_2,        SCL_3,           
+	//Atlantic Interface eport signals
+	input             rx_dav_1,     rx_dav_2,     rx_dav_3,
+	input             tx_ena_1,     tx_ena_2,     tx_ena_3,
+	input      [15:0] tx_dat_1,     tx_dat_2,     tx_dat_3,
+	output wire       rx_ena_1,     rx_ena_2,     rx_ena_3,
+	output     [15:0] rx_dat_1,     rx_dat_2,     rx_dat_3
+	);
+		
+	wire              wb_ack_out_1, wb_ack_out_2, wb_ack_out_3;                  
+	wire        [6:0] wb_adr_in_1,  wb_adr_in_2,  wb_adr_in_3;         
+	wire        [7:0] wb_dat_in_1,  wb_dat_in_2,  wb_dat_in_3;                  
+	wire              wb_we_in_1,   wb_we_in_2,   wb_we_in_3;          
+	wire              wb_stb_in_1,  wb_stb_in_2,  wb_stb_in_3;      
+	wire              wb_cyc_in_1,  wb_cyc_in_2,  wb_cyc_in_3; 
+	wire        [7:0] wb_dat_out_1, wb_dat_out_2, wb_dat_out_3;
+	
+	wishbone2atlanticSCA_tri wb2atlantic(
+		.clk_1(clk_1),	             .clk_2(clk_2),	              .clk_3(clk_3),
+		.reset_n_1(reset_n_1),	       .reset_n_2(reset_n_2),	        .reset_n_3(reset_n_3),
+		
+		.wb_ack_out_1(wb_ack_out_1),	 .wb_ack_out_2(wb_ack_out_2),	  .wb_ack_out_3(wb_ack_out_3),
+		.wb_adr_in_1(wb_adr_in_1[3:0]),.wb_adr_in_2(wb_adr_in_2[3:0]),.wb_adr_in_3(wb_adr_in_3[3:0]),
+		.wb_dat_in_1(wb_dat_in_1),	 .wb_dat_in_2(wb_dat_in_2),	  .wb_dat_in_3(wb_dat_in_3),
+		.wb_we_in_1(wb_we_in_1),	 .wb_we_in_2(wb_we_in_2),	  .wb_we_in_3(wb_we_in_3), 
+		.wb_stb_in_1(wb_stb_in_1),	 .wb_stb_in_2(wb_stb_in_2),	  .wb_stb_in_3(wb_stb_in_3),
+		.wb_cyc_in_1(wb_cyc_in_1),	 .wb_cyc_in_2(wb_cyc_in_2),	  .wb_cyc_in_3(wb_cyc_in_3),
+		.wb_dat_out_1(wb_dat_out_1),	 .wb_dat_out_2(wb_dat_out_2),	  .wb_dat_out_3(wb_dat_out_3),
+					
+		.rx_ena_1(rx_ena_1),	       .rx_ena_2(rx_ena_2),	        .rx_ena_3(rx_ena_3),
+		.rx_dav_1(rx_dav_1),	       .rx_dav_2(rx_dav_2),	        .rx_dav_3(rx_dav_3),
+		.tx_ena_1(tx_ena_1),	       .tx_ena_2(tx_ena_2),	        .tx_ena_3(tx_ena_3),
+		.rx_dat_1(rx_dat_1),	       .rx_dat_2(rx_dat_2),	        .rx_dat_3(rx_dat_3),
+		.tx_dat_1(tx_dat_1),	       .tx_dat_2(tx_dat_2),	        .tx_dat_3(tx_dat_3)
+      );
+                
+                
+      i2c_slave I2C_Port (         
+		.SCL1(SCL_1), 
+		.resetB1(reset_n_1), 
+		.clk1(clk_1), 
+		.wb_dat_i1(wb_dat_out_1), 
+		.wb_we1(wb_we_in_1), 
+		.wb_stb1(wb_stb_in_1),  
+		.wb_cyc1(wb_cyc_in_1),
+		.wb_ack1(wb_ack_out_1), 
+		.chip_id1(3'h0), 
+		.ADDR10BIT1(1'b0), 
+		.INCREMENT_ADDR1(1'b1), 
+		.wb_dat_o1(wb_dat_in_1), 
+		.SDAo1(SDAo_1),
+		.SDAen1(SDAen_1), 
+		.wb_adr1(wb_adr_in_1), 
+		.SDAi1(SDAi_1), 
+		
+		 
+		.SCL2(SCL_2), 
+		.resetB2(reset_n_2), 
+		.clk2(clk_2), 
+		.wb_dat_i2(wb_dat_out_2), 
+		.wb_we2(wb_we_in_2),	
+		.wb_stb2(wb_stb_in_2),  
+		.wb_cyc2(wb_cyc_in_2), 
+		.wb_ack2(wb_ack_out_2), 
+		.chip_id2(3'h0), 
+		.ADDR10BIT2(1'b0), 
+		.INCREMENT_ADDR2(1'b1),
+		.wb_dat_o2(wb_dat_in_2), 
+		.SDAo2(SDAo_2), 
+		.SDAen2(SDAen_2), 
+		.wb_adr2(wb_adr_in_2), 
+		.SDAi2(SDAi_2),
+		 
+		.SCL3(SCL_3), 
+		.resetB3(reset_n_3), 
+		.clk3(clk_3),	
+		.wb_dat_i3(wb_dat_out_3), 
+		.wb_we3(wb_we_in_3), 
+		.wb_stb3(wb_stb_in_3),  
+		.wb_cyc3(wb_cyc_in_3), 
+		.wb_ack3(wb_ack_out_3), 
+		.chip_id3(3'h0),
+		.ADDR10BIT3(1'b0), 
+		.INCREMENT_ADDR3(1'b1), 
+		.wb_dat_o3(wb_dat_in_3), 
+		.SDAo3(SDAo_3), 
+		.SDAen3(SDAen_3), 
+		.wb_adr3(wb_adr_in_3),
+		.SDAi3(SDAi_3)
+        );     
+endmodule
+         
+
+
+
diff --git a/vldb/code/Testbench/SCA-model/ClkGate_Reset_channels.v b/vldb/code/Testbench/SCA-model/ClkGate_Reset_channels.v
new file mode 100644
index 0000000..a44c3dc
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/ClkGate_Reset_channels.v
@@ -0,0 +1,181 @@
+
+/////////////////////////////////////////////////////////////////////////////
+// Design Name:    GBT_SCA                                                 //
+// Module Name:    ClkGate_Reset_channels (tri version)                    //
+// Made by:        Alessandro Caratelli                                    //
+//                                                                         //
+// Description:    Generate clock gating and reset for enable/disable      // 
+//                 the specific SCA channell                               //
+// Company:        CERN (PH-ESE)                                           //
+// Create Date:    22/jan/2014                                             //
+/////////////////////////////////////////////////////////////////////////////
+
+
+
+`timescale 1ns / 1ps
+
+module ClkGate_Reset_channels_tri #(
+	parameter n_ch = 22
+	)(
+	input                    clk_1,       clk_2,       clk_3,
+	input                    reset_1,     reset_2,     reset_3,
+	input       [(n_ch-1):0] ch_enable_1, ch_enable_2, ch_enable_3,
+	output      [(n_ch-1):0] ch_clk_1,    ch_clk_2,    ch_clk_3,
+	output      [(n_ch-1):0] ch_res_1,    ch_res_2,    ch_res_3
+	);
+	wire        [(n_ch-1):0] int_res_1,   int_res_2,   int_res_3;
+	genvar i;
+	
+	generate 
+	for(i=0; i<n_ch; i=i+1) begin: inst_ch_clk_gating   
+		ch_gate_clk_tri ch_clk_gating(
+			.clk_1(clk_1),            .clk_2(clk_2),            .clk_3(clk_3),       
+			.resetB_1(~reset_1),      .resetB_2(~reset_2),      .resetB_3(~reset_3),   
+			.ch_en_1(ch_enable_1[i]), .ch_en_2(ch_enable_2[i]), .ch_en_3(ch_enable_3[i]),  
+			.ch_clk_1(ch_clk_1[i]),   .ch_clk_2(ch_clk_2[i]),   .ch_clk_3(ch_clk_3[i]),  
+			.ch_res_1(int_res_1[i]),  .ch_res_2(int_res_2[i]), .ch_res_3(int_res_3[i])
+		);	
+		assign ch_res_1[i] = int_res_1[i] | reset_1;
+		assign ch_res_2[i] = int_res_2[i] | reset_2;
+		assign ch_res_3[i] = int_res_3[i] | reset_3;
+	end
+	endgenerate
+	
+endmodule 
+
+module ch_gate_clk(
+	input             clk,    //global clk
+	input             resetB, //global reset
+	
+	input             ch_en,  //ch enable
+	output            ch_clk, //channel clock gated
+	output reg        ch_res, //channel reset 
+	
+	input             en_clk_voted,
+	output            en_clk,
+	input       [1:0] state_voted,
+	output reg  [1:0] state
+	); 
+	reg               en_clk_latched;  
+	
+	always @(clk, en_clk_voted) begin
+		if (~clk) en_clk_latched =  en_clk_voted;
+	end
+	
+	assign ch_clk = clk & en_clk_latched;      
+	
+	always @(posedge clk or negedge resetB) begin
+		if(~resetB) state <=  2'h0; 
+		else  if(~ch_en) 
+			      state <=  2'h0;
+			else case(state_voted)
+				2'h0: state <=  2'h1;    
+				2'h1: state <=  2'h2;
+				2'h2: state <=  2'h3;
+				2'h3: state <=  2'h3;  
+			endcase
+	end
+	
+	always @(negedge clk or negedge resetB) begin
+		if(~resetB) ch_res <= 1'b1;
+		else ch_res <= ~(state_voted[1] & state_voted[0]);
+	end 
+	
+	assign en_clk = (state_voted[1] | state_voted[0]);
+	
+endmodule
+
+module clkg_voter(
+	input in1, in2, in3,
+	output out
+	);
+	assign out = (in1 != in2) ? in3 : in1;
+	//clkg_voter name (.in1(), .in2(), .in3(), .out());
+endmodule 
+
+module ch_gate_clk_tri(
+	input       clk_1,        clk_2,        clk_3,      //global clk
+	input       resetB_1,     resetB_2,     resetB_3,   //global reset
+	input       ch_en_1,      ch_en_2,      ch_en_3,    //ch enable
+	output      ch_clk_1,     ch_clk_2,     ch_clk_3,   //channel clock gated
+	output      ch_res_1,     ch_res_2,     ch_res_3    //channel reset 
+	); 
+	wire        en_clk_int_1, en_clk_int_2, en_clk_int_3; 
+	wire  [1:0] state_int_1,  state_int_2,  state_int_3;  
+	wire        en_clk_1,     en_clk_2,     en_clk_3;     
+	wire  [1:0] state_1,      state_2,      state_3;  
+	wire        ch_res_int_1, ch_res_int_2, ch_res_int_3;       
+	
+	// the connection are mada in this way in order to avoid unwanted 
+	// optimizations on this chritical module
+	
+	clkg_voter clkg_res_v1(.in1(ch_res_int_1),   .in2(ch_res_int_2),   .in3(ch_res_int_3),   .out(ch_res_1));
+	clkg_voter clkg_en_v1 (.in1(en_clk_int_1),   .in2(en_clk_int_2),   .in3(en_clk_int_3),   .out(en_clk_1));
+	clkg_voter clkg_st0_v1(.in1(state_int_1[0]), .in2(state_int_2[0]), .in3(state_int_3[0]), .out(state_1[0]));
+	clkg_voter clkg_st1_v1(.in1(state_int_1[1]), .in2(state_int_2[1]), .in3(state_int_3[1]), .out(state_1[1]));
+	
+	ch_gate_clk ch_gate_clk_1(
+		.clk(clk_1),    
+		.resetB(resetB_1),
+		.ch_en(ch_en_1),  
+		
+		.ch_clk(ch_clk_1), 
+		.ch_res(ch_res_int_1), 
+		
+		.en_clk_voted(en_clk_1),
+		.en_clk(en_clk_int_1),
+		.state_voted(state_1),
+		.state(state_int_1)
+	); 
+
+	clkg_voter clkg_res_v2(.in2(ch_res_int_1),   .in3(ch_res_int_2),   .in1(ch_res_int_3),   .out(ch_res_2));
+	clkg_voter clkg_en_v2 (.in2(en_clk_int_1),   .in3(en_clk_int_2),   .in1(en_clk_int_3),   .out(en_clk_2));
+	clkg_voter clkg_st0_v2(.in2(state_int_1[0]), .in3(state_int_2[0]), .in1(state_int_3[0]), .out(state_2[0]));
+	clkg_voter clkg_st1_v2(.in2(state_int_1[1]), .in3(state_int_2[1]), .in1(state_int_3[1]), .out(state_2[1]));
+
+	ch_gate_clk ch_gate_clk_2(
+		.clk(clk_2),    
+		.resetB(resetB_2),
+		.ch_en(ch_en_2),  
+		
+		.ch_clk(ch_clk_2), 
+		.ch_res(ch_res_int_2), 
+		
+		.en_clk_voted(en_clk_2),
+		.en_clk(en_clk_int_2),
+		.state_voted(state_2),
+		.state(state_int_2)
+	); 
+
+	clkg_voter clkg_res_v3(.in3(ch_res_int_1),   .in1(ch_res_int_2),   .in2(ch_res_int_3),   .out(ch_res_3));
+	clkg_voter clkg_en_v3 (.in3(en_clk_int_1),   .in1(en_clk_int_2),   .in2(en_clk_int_3),   .out(en_clk_3));
+	clkg_voter clkg_st0_v3(.in3(state_int_1[0]), .in1(state_int_2[0]), .in2(state_int_3[0]), .out(state_3[0]));
+	clkg_voter clkg_st1_v3(.in3(state_int_1[1]), .in1(state_int_2[1]), .in2(state_int_3[1]), .out(state_3[1]));
+
+	ch_gate_clk ch_gate_clk_3(
+		.clk(clk_3),    
+		.resetB(resetB_3),
+		.ch_en(ch_en_3),  
+		
+		.ch_clk(ch_clk_3), 
+		.ch_res(ch_res_int_3), 
+		
+		.en_clk_voted(en_clk_3),
+		.en_clk(en_clk_int_3),
+		.state_voted(state_3),
+		.state(state_int_3)
+	); 
+	
+endmodule	
+	
+
+	
+	
+	
+	
+	
+	
+	
+	
+	
+	
diff --git a/vldb/code/Testbench/SCA-model/DAC_channel.v b/vldb/code/Testbench/SCA-model/DAC_channel.v
new file mode 100644
index 0000000..d820ece
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/DAC_channel.v
@@ -0,0 +1,217 @@
+
+
+/////////////////////////////////////////////////////////////////////////////
+// Design Name:    GBT_SCA                                                 //
+// Module Name:    DAC_wb_interface(TRI Version)                           //
+// Description:    whishbone Interface for DAC module                      //
+// Company:        CERN (PH-ESE)                                           //
+// Made by:        Alessandro Caratelli                                    //
+//                                                                         //
+// Create Date:    18/July/2013 - Created                                  //
+/////////////////////////////////////////////////////////////////////////////
+
+`include "DAC_defines.v"
+`timescale 1ns / 1ps
+module DAC_wb_interf_iostate(
+   wb_clk_in, wb_rst_in ,wb_adr_in ,wb_dat_in ,wb_sel_in ,wb_we_in ,
+   wb_stb_in ,wb_cyc_in ,wb_dat_out_i, wb_dat_out_o ,wb_ack_out_i, wb_ack_out_o ,wb_err_out ,wb_int_out,
+	dac_out_1_i, dac_out_1_o, dac_out_2_i, dac_out_2_o, dac_out_3_i, dac_out_3_o, dac_out_4_i, dac_out_4_o
+   );
+	 
+	//Wishbone signals///////////////////////////////////////////
+	input                         wb_clk_in;         
+	input    [`dac_conv_nbit-1:0] dac_out_4_i;
+	input    [`dac_conv_nbit-1:0] dac_out_3_i;
+	input    [`dac_conv_nbit-1:0] dac_out_2_i;
+	input    [`dac_conv_nbit-1:0] dac_out_1_i;
+
+	input                          wb_ack_out_i;         
+	input                   [31:0] wb_dat_out_i;
+	input                          wb_rst_in;         
+	input                    [4:0] wb_adr_in;         
+	input                   [31:0] wb_dat_in;                  
+	input                    [3:0] wb_sel_in;         
+	input                          wb_we_in;          
+	input                          wb_stb_in;         
+	input                          wb_cyc_in; 
+	output                  [31:0] wb_dat_out_o;
+	output                         wb_err_out;         
+	output                         wb_int_out;
+	
+	output    [`dac_conv_nbit-1:0] dac_out_1_o;
+	output    [`dac_conv_nbit-1:0] dac_out_2_o;
+	output    [`dac_conv_nbit-1:0] dac_out_3_o;
+	output    [`dac_conv_nbit-1:0] dac_out_4_o;
+	output                         wb_ack_out_o;
+	// Output data to DAC
+	//WB data out /////////////////////////////////////////////////
+	reg  [31:0] wb_dat_out_o;
+	reg  [`dac_conv_nbit-1:0] wb_datM;	
+
+	always @(*) begin
+			case (wb_adr_in[`dac_wb_ofset_bits])
+				`dac_out1:       wb_datM = dac_out_1_i[`dac_conv_nbit-1:0];
+				`dac_out2:       wb_datM = dac_out_2_i[`dac_conv_nbit-1:0];
+				`dac_out3:       wb_datM = dac_out_3_i[`dac_conv_nbit-1:0];
+				`dac_out4:       wb_datM = dac_out_4_i[`dac_conv_nbit-1:0];
+				`dac_ctrl:       wb_datM = {`dac_conv_nbit{1'b0}};
+				default:         wb_datM = {`dac_conv_nbit{1'b0}};
+			endcase
+	end
+	
+	always @(posedge wb_clk_in or posedge wb_rst_in) begin
+		if (wb_rst_in)
+			wb_dat_out_o <= #1 {32{1'b0}};
+		else
+			wb_dat_out_o <= #1 {wb_datM[7:0],{24{1'b0}}}; 
+	end
+	
+	
+	//WB Interrupt /////////////////////////////////////////////////
+	assign wb_int_out = 1'b0;
+	
+	//WB ack //////////////////////////////////////////////////////////
+	reg   wb_ack_out_o; 
+	always @(posedge wb_clk_in or posedge wb_rst_in) begin
+		if (wb_rst_in)
+			wb_ack_out_o <= #1 1'b0;
+		else	
+			wb_ack_out_o <= #1 wb_cyc_in & wb_stb_in & ~wb_ack_out_i;
+	end
+	
+	//WB err //////////////////////////////////////////////////////////
+	assign wb_err_out = 1'b0;
+
+	// Analog Outputs /////////////////////////////////////////////////////	
+	
+	reg    [`dac_conv_nbit-1:0] dac_out_1_o;
+	reg    [`dac_conv_nbit-1:0] dac_out_2_o;
+	reg    [`dac_conv_nbit-1:0] dac_out_3_o;
+	reg    [`dac_conv_nbit-1:0] dac_out_4_o;	
+	
+	wire   dac_out1_sel;
+	wire   dac_out2_sel;
+	wire   dac_out3_sel;
+	wire   dac_out4_sel;
+	
+	assign dac_out1_sel   = wb_cyc_in & wb_stb_in & (wb_adr_in[`dac_wb_ofset_bits] == `dac_out1);
+	assign dac_out2_sel   = wb_cyc_in & wb_stb_in & (wb_adr_in[`dac_wb_ofset_bits] == `dac_out2);
+	assign dac_out3_sel   = wb_cyc_in & wb_stb_in & (wb_adr_in[`dac_wb_ofset_bits] == `dac_out3);
+	assign dac_out4_sel   = wb_cyc_in & wb_stb_in & (wb_adr_in[`dac_wb_ofset_bits] == `dac_out4);
+	
+	
+	always @(posedge wb_clk_in or posedge wb_rst_in) begin
+		if (wb_rst_in) 
+			dac_out_1_o <= #1 {`dac_conv_nbit{1'b0}};
+		else begin
+			if(dac_out1_sel &&  wb_we_in && wb_sel_in[3])
+				dac_out_1_o <= #1 wb_dat_in[31:24];
+			else
+				dac_out_1_o <= #1 dac_out_1_i;
+		end
+	end
+	
+	always @(posedge wb_clk_in or posedge wb_rst_in) begin
+		if (wb_rst_in) 
+			dac_out_2_o <= #1 {`dac_conv_nbit{1'b0}};
+		else begin
+			if(dac_out2_sel &&  wb_we_in && wb_sel_in[3])
+				dac_out_2_o <= #1 wb_dat_in[31:24];
+			else
+				dac_out_2_o <= #1 dac_out_2_i;
+		end
+	end
+	
+	always @(posedge wb_clk_in or posedge wb_rst_in) begin
+		if (wb_rst_in) 
+			dac_out_3_o <= #1 {`dac_conv_nbit{1'b0}};
+		else begin
+			if(dac_out3_sel &&  wb_we_in && wb_sel_in[3])
+				dac_out_3_o <= #1 wb_dat_in[31:24];
+			else
+				dac_out_3_o <= #1 dac_out_3_i;
+		end
+	end
+	
+	always @(posedge wb_clk_in or posedge wb_rst_in) begin
+		if (wb_rst_in) 
+			dac_out_4_o <= #1 {`dac_conv_nbit{1'b0}};
+		else begin
+			if(dac_out4_sel &&  wb_we_in && wb_sel_in[3])
+				dac_out_4_o <= #1 wb_dat_in[31:24];
+			else
+				dac_out_4_o <= #1 dac_out_4_i;
+		end
+	end
+	
+
+endmodule
+
+`timescale 1ns / 1ps
+`include "DAC_defines.v"
+module DAC_wb_interf_tri(
+   wb_clk_in_1, wb_clk_in_2, wb_clk_in_3, wb_rst_in_1, wb_rst_in_2, wb_rst_in_3 ,wb_adr_in_1, wb_adr_in_2, wb_adr_in_3 ,wb_dat_in_1, wb_dat_in_2, wb_dat_in_3 ,wb_sel_in_1, wb_sel_in_2, wb_sel_in_3 ,wb_we_in_1, wb_we_in_2, wb_we_in_3 ,
+   wb_stb_in_1, wb_stb_in_2, wb_stb_in_3 ,wb_cyc_in_1, wb_cyc_in_2, wb_cyc_in_3 ,wb_dat_out_1, wb_dat_out_2, wb_dat_out_3 ,wb_ack_out_1, wb_ack_out_2, wb_ack_out_3 ,wb_err_out_1, wb_err_out_2, wb_err_out_3 ,wb_int_out_1, wb_int_out_2, wb_int_out_3,
+	dac_out_1_1, dac_out_1_2, dac_out_1_3, dac_out_2_1, dac_out_2_2, dac_out_2_3, dac_out_3_1, dac_out_3_2, dac_out_3_3, dac_out_4_1, dac_out_4_2, dac_out_4_3
+   );
+
+	//Wishbone signals///////////////////////////////////////////
+	input                           wb_clk_in_1, wb_clk_in_2, wb_clk_in_3;         
+	input                           wb_rst_in_1, wb_rst_in_2, wb_rst_in_3;         
+	input                     [4:0] wb_adr_in_1, wb_adr_in_2, wb_adr_in_3;         
+	input                    [31:0] wb_dat_in_1, wb_dat_in_2, wb_dat_in_3;                  
+	input                     [3:0] wb_sel_in_1, wb_sel_in_2, wb_sel_in_3;         
+	input                           wb_we_in_1, wb_we_in_2, wb_we_in_3;          
+	input                           wb_stb_in_1, wb_stb_in_2, wb_stb_in_3;         
+	input                           wb_cyc_in_1, wb_cyc_in_2, wb_cyc_in_3; 
+	output                   [31:0] wb_dat_out_1, wb_dat_out_2, wb_dat_out_3;
+	output                          wb_ack_out_1, wb_ack_out_2, wb_ack_out_3;         
+	output                          wb_err_out_1, wb_err_out_2, wb_err_out_3;         
+	output                          wb_int_out_1, wb_int_out_2, wb_int_out_3;
+
+	// Output data to DAC
+	output    [`dac_conv_nbit-1:0] dac_out_1_1, dac_out_1_2, dac_out_1_3;
+	output    [`dac_conv_nbit-1:0] dac_out_2_1, dac_out_2_2, dac_out_2_3;
+	output    [`dac_conv_nbit-1:0] dac_out_3_1, dac_out_3_2, dac_out_3_3;
+	output    [`dac_conv_nbit-1:0] dac_out_4_1, dac_out_4_2, dac_out_4_3;
+
+	//WB data out /////////////////////////////////////////////////
+
+	wire [31:0] wb_dat_out_1, wb_dat_out_2, wb_dat_out_3;
+	wire wb_ack_out_1, wb_ack_out_2, wb_ack_out_3;
+	wire [`dac_conv_nbit-1:0] dac_out_1_1, dac_out_1_2, dac_out_1_3;
+	wire [`dac_conv_nbit-1:0] dac_out_2_1, dac_out_2_2, dac_out_2_3;
+	wire [`dac_conv_nbit-1:0] dac_out_3_1, dac_out_3_2, dac_out_3_3;
+	wire [`dac_conv_nbit-1:0] dac_out_4_1, dac_out_4_2, dac_out_4_3;
+	wire [31:0] wb_dat_out;
+	wire wb_ack_out;
+	wire [`dac_conv_nbit-1:0] dac_out_1;
+	wire [`dac_conv_nbit-1:0] dac_out_2;
+	wire [`dac_conv_nbit-1:0] dac_out_3;
+	wire [`dac_conv_nbit-1:0] dac_out_4;
+
+	DAC_wb_interf_iostate DAC_wb_interf_iostate_1  (
+   .wb_clk_in(wb_clk_in_1), .wb_rst_in(wb_rst_in_1),.wb_adr_in(wb_adr_in_1),.wb_dat_in(wb_dat_in_1),.wb_sel_in(wb_sel_in_1),.wb_we_in(wb_we_in_1),
+   .wb_stb_in(wb_stb_in_1),.wb_cyc_in(wb_cyc_in_1),.wb_dat_out_i(wb_dat_out_1), .wb_dat_out_o(wb_dat_out_2),.wb_ack_out_i(wb_ack_out_1), .wb_ack_out_o(wb_ack_out_2),.wb_err_out(wb_err_out_1),.wb_int_out(wb_int_out_1),
+	.dac_out_1_i(dac_out_1_1), .dac_out_1_o(dac_out_1_2), .dac_out_2_i(dac_out_2_1), .dac_out_2_o(dac_out_2_2), .dac_out_3_i(dac_out_3_1), .dac_out_3_o(dac_out_3_2), .dac_out_4_i(dac_out_4_1), .dac_out_4_o(dac_out_4_2));
+
+	DAC_wb_interf_iostate DAC_wb_interf_iostate_2  (
+   .wb_clk_in(wb_clk_in_2), .wb_rst_in(wb_rst_in_2),.wb_adr_in(wb_adr_in_2),.wb_dat_in(wb_dat_in_2),.wb_sel_in(wb_sel_in_2),.wb_we_in(wb_we_in_2),
+   .wb_stb_in(wb_stb_in_2),.wb_cyc_in(wb_cyc_in_2),.wb_dat_out_i(wb_dat_out_2), .wb_dat_out_o(wb_dat_out_3),.wb_ack_out_i(wb_ack_out_2), .wb_ack_out_o(wb_ack_out_3),.wb_err_out(wb_err_out_2),.wb_int_out(wb_int_out_2),
+	.dac_out_1_i(dac_out_1_2), .dac_out_1_o(dac_out_1_3), .dac_out_2_i(dac_out_2_2), .dac_out_2_o(dac_out_2_3), .dac_out_3_i(dac_out_3_2), .dac_out_3_o(dac_out_3_3), .dac_out_4_i(dac_out_4_2), .dac_out_4_o(dac_out_4_3));
+
+	DAC_wb_interf_iostate DAC_wb_interf_iostate_3  (
+   .wb_clk_in(wb_clk_in_3), .wb_rst_in(wb_rst_in_3),.wb_adr_in(wb_adr_in_3),.wb_dat_in(wb_dat_in_3),.wb_sel_in(wb_sel_in_3),.wb_we_in(wb_we_in_3),
+   .wb_stb_in(wb_stb_in_3),.wb_cyc_in(wb_cyc_in_3),.wb_dat_out_i(wb_dat_out_3), .wb_dat_out_o(wb_dat_out),.wb_ack_out_i(wb_ack_out_3), .wb_ack_out_o(wb_ack_out),.wb_err_out(wb_err_out_3),.wb_int_out(wb_int_out_3),
+	.dac_out_1_i(dac_out_1_3), .dac_out_1_o(dac_out_1), .dac_out_2_i(dac_out_2_3), .dac_out_2_o(dac_out_2), .dac_out_3_i(dac_out_3_3), .dac_out_3_o(dac_out_3), .dac_out_4_i(dac_out_4_3), .dac_out_4_o(dac_out_4));
+
+	majority_voter #(.WIDTH(37+`dac_conv_nbit-1+`dac_conv_nbit-1+`dac_conv_nbit-1+`dac_conv_nbit-1)) mv (
+		.in1({wb_dat_out_2, wb_ack_out_2, dac_out_1_2, dac_out_2_2, dac_out_3_2, dac_out_4_2}),
+		.in2({wb_dat_out_3, wb_ack_out_3, dac_out_1_3, dac_out_2_3, dac_out_3_3, dac_out_4_3}),
+		.in3({wb_dat_out, wb_ack_out,  dac_out_1, dac_out_2, dac_out_3, dac_out_4}),
+		.out({wb_dat_out_1, wb_ack_out_1,  dac_out_1_1, dac_out_2_1, dac_out_3_1, dac_out_4_1}),
+		.err()
+	);
+endmodule
+
+
diff --git a/vldb/code/Testbench/SCA-model/DAC_defines.v b/vldb/code/Testbench/SCA-model/DAC_defines.v
new file mode 100644
index 0000000..2e1d8d6
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/DAC_defines.v
@@ -0,0 +1,22 @@
+/////////////////////////////////////////////////////////////////////////////
+// Design Name:    GBT_SCA                                                 //
+// Module Name:    DAC_wb_interface(TRI Version)                           //
+// Description:    whishbone Interface for DAC module                      //
+// Company:        CERN (PH-ESE)                                           //
+// Made by:        Alessandro Caratelli                                    //
+//                                                                         //
+// Create Date:    18/July/2013 - Created                                  //
+/////////////////////////////////////////////////////////////////////////////
+
+`ifndef DAC_DEFINES
+		`define DAC_DEFINES		
+		// Registers address ofset on whishbone bus
+		`define dac_out1                1
+		`define dac_out2                2
+		`define dac_out3                3
+		`define dac_out4                4
+		`define dac_ctrl                0
+		`define dac_wb_ofset_bits     4:2
+		// #bit used in hich register
+		`define dac_conv_nbit           8 //maximum 8
+`endif
diff --git a/vldb/code/Testbench/SCA-model/GPIO_channel.v b/vldb/code/Testbench/SCA-model/GPIO_channel.v
new file mode 100644
index 0000000..a4835c6
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/GPIO_channel.v
@@ -0,0 +1,567 @@
+`include "gpio_defines.v"
+`timescale 1ns / 1ps
+module gpio_top_iostate(
+	wb_clk_in, wb_rst_in, wb_cyc_in, wb_adr_in, wb_dat_in, wb_sel_in, wb_we_in, wb_stb_in,
+	wb_dat_out_i, wb_dat_out_o, wb_ack_out_i, wb_ack_out_o, wb_err_out_i, wb_err_out_o, 
+	wb_inta_out_i, wb_inta_out_o, GPIO_ext_pad_out_i, GPIO_ext_pad_out_o, GPIO_ext_pad_in,
+	//aux_in, //rgpio_aux_i, //rgpio_aux_o, 
+	GPIO_ext_padOE_out, GPIO_clk_pad_in , rgpio_ctrl_i, rgpio_ctrl_o, rgpio_out_i, rgpio_out_o, rgpio_oe_i, 
+	rgpio_oe_o, rgpio_inte_i, rgpio_inte_o, rgpio_ptrig_i, rgpio_ptrig_o, 
+	rgpio_eclk_i, rgpio_eclk_o, rgpio_nec_i, rgpio_nec_o, sync_i, sync_o, GPIO_ext_pad_s_i, GPIO_ext_pad_s_o, 
+	rgpio_in_i, rgpio_in_o, sync_clk_i, sync_clk_o, clk_s_i, clk_s_o, clk_r_i, clk_r_o, 
+	pextc_sampled_i, pextc_sampled_o, rgpio_ints_i, rgpio_ints_o);
+
+
+parameter dw = 32;
+parameter aw = `GPIO_ADDRHH+1;
+parameter gw = `GPIO_IOS;
+
+input            	wb_clk_in;	
+input            	wb_ack_out_i;	
+input            	wb_err_out_i;	
+input	  [gw-1:0]	rgpio_ints_i;	
+//input	  [gw-1:0]  	aux_in;		
+input   [gw-1:0]  	pextc_sampled_i;  
+input                   clk_r_i;
+input 		        clk_s_i;
+input 	      		sync_clk_i;
+input	[gw-1:0]	rgpio_in_i;	
+input [gw-1:0]	GPIO_ext_pad_s_i;
+input [gw-1:0]	sync_i;
+input	[gw-1:0]	rgpio_nec_i;	
+input	[gw-1:0]	rgpio_eclk_i;	
+//input	[gw-1:0]	rgpio_aux_i;	
+input	[gw-1:0]	rgpio_ptrig_i;	
+input	[gw-1:0]	rgpio_inte_i;	
+input	[gw-1:0]	rgpio_oe_i;	
+input	[gw-1:0]	rgpio_out_i;	
+input	[1:0]		rgpio_ctrl_i;	
+input   [gw-1:0] 	GPIO_ext_pad_in;   
+input            	GPIO_clk_pad_in;   
+input            	wb_rst_in;    
+input            	wb_cyc_in;    
+input   [aw-1:0] 	wb_adr_in;	
+input   [dw-1:0] 	wb_dat_in;	
+input	  [3:0]  	wb_sel_in;  
+input           	wb_we_in;     
+input           	wb_stb_in;    
+output  [dw-1:0]	wb_dat_out_o;
+output          	wb_ack_out_o;
+output          	wb_err_out_o;
+output	[gw-1:0]	rgpio_ints_o;
+output            	wb_inta_out_o;
+input            	wb_inta_out_i;	
+input  [dw-1:0]  	wb_dat_out_i;	
+output   [gw-1:0]	pextc_sampled_o;
+output  clk_r_o;
+output  clk_s_o;
+output  sync_clk_o;
+output	[gw-1:0]	rgpio_in_o;
+output   [gw-1:0]       GPIO_ext_pad_s_o;
+output   [gw-1:0]       sync_o;
+output	[gw-1:0]	rgpio_nec_o;
+output	[gw-1:0]	rgpio_eclk_o;
+//output	[gw-1:0]	rgpio_aux_o;
+output	[gw-1:0]	rgpio_ptrig_o;
+output	[gw-1:0]	rgpio_inte_o;
+output	[gw-1:0]	rgpio_oe_o;
+output	[gw-1:0]	rgpio_out_o;
+output	[1:0]		rgpio_ctrl_o;
+output  [gw-1:0]	 GPIO_ext_pad_out_o;
+input  [gw-1:0] 	GPIO_ext_pad_out_i; 
+output  [gw-1:0]	 GPIO_ext_padOE_out;
+	
+reg	[gw-1:0]	rgpio_in_o;
+reg	[gw-1:0]	rgpio_out_o;
+reg	[gw-1:0]	rgpio_oe_o;
+reg	[gw-1:0]	rgpio_inte_o;
+reg	[gw-1:0]	rgpio_ptrig_o;
+//reg	[gw-1:0]	rgpio_aux_o;
+reg	[1:0]		rgpio_ctrl_o;
+reg	[gw-1:0]	rgpio_ints_o;
+reg	[gw-1:0]	rgpio_eclk_o;
+reg	[gw-1:0]	rgpio_nec_o;
+reg   [gw-1:0]          sync_o;
+reg   [gw-1:0]	        GPIO_ext_pad_s_o;
+reg   [dw-1:0]	       wb_dat;   
+reg           	       wb_ack_out_o; 
+reg           	       wb_err_out_o; 
+reg           	       wb_inta_out_o;  
+reg   [dw-1:0]	       wb_dat_out_o;
+reg   [gw-1:0]	       GPIO_ext_pad_out_o; 
+reg   [gw-1:0]	       pextc_sampled_o;
+reg   [gw-1:0]		nextc_sampled; 
+reg  sync_clk_o;
+reg  clk_s_o;
+reg  clk_r_o;
+
+
+
+wire            rgpio_out_sel;  
+wire            rgpio_oe_sel; 
+wire            rgpio_inte_sel; 
+wire            rgpio_ptrig_sel;
+//wire          rgpio_aux_sel;  
+wire            rgpio_ctrl_sel; 
+wire            rgpio_ints_sel; 
+wire            rgpio_eclk_sel ;
+wire            rgpio_nec_sel ;
+wire            full_decoding;  
+wire  [gw-1:0]  in_muxed; 
+wire            wb_ack;   
+wire            wb_err;   
+wire            wb_inta; 
+wire  [gw-1:0]  out_pad; 
+wire  [gw-1:0]  extc_in;  
+wire  [gw-1:0]  pext_clk; 
+
+wire 		pedge;
+wire 		nedge;
+wire [gw-1:0] 	pedge_vec;
+wire [gw-1:0] 	nedge_vec;
+wire [gw-1:0] 	in_lach;
+
+assign pedge =  clk_s_i & !clk_r_i ; 
+assign nedge = !clk_s_i &  clk_r_i ; 
+assign pedge_vec = {gw{pedge}} ;   
+assign nedge_vec = {gw{nedge}} ;   
+assign in_lach = (~rgpio_nec_i & pedge_vec) | (rgpio_nec_i & nedge_vec) ;
+assign extc_in = (in_lach & GPIO_ext_pad_s_i) | (~in_lach & pextc_sampled_i) ;
+ 	
+assign full_decoding = (wb_adr_in[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) & (wb_adr_in[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
+assign rgpio_out_sel = wb_cyc_in & wb_stb_in & (wb_adr_in[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
+assign rgpio_oe_sel = wb_cyc_in & wb_stb_in & (wb_adr_in[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
+assign rgpio_inte_sel = wb_cyc_in & wb_stb_in & (wb_adr_in[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
+assign rgpio_ptrig_sel = wb_cyc_in & wb_stb_in & (wb_adr_in[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
+//assign rgpio_aux_sel = wb_cyc_in & wb_stb_in & (wb_adr_in[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
+assign rgpio_ctrl_sel = wb_cyc_in & wb_stb_in & (wb_adr_in[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
+assign rgpio_ints_sel = wb_cyc_in & wb_stb_in & (wb_adr_in[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
+assign rgpio_eclk_sel = wb_cyc_in & wb_stb_in & (wb_adr_in[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding;
+assign rgpio_nec_sel = wb_cyc_in & wb_stb_in & (wb_adr_in[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding;
+assign wb_ack = wb_cyc_in & wb_stb_in & !wb_err_out_i;
+assign wb_err = wb_cyc_in & wb_stb_in & !full_decoding;
+
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+	if (wb_rst_in)
+		wb_ack_out_o <= #1 1'b0;
+	else
+		wb_ack_out_o <= #1 wb_ack & ~wb_ack_out_i & (!wb_err) ;
+end
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+	if (wb_rst_in)
+		wb_err_out_o <= #1 1'b0;
+	else
+		wb_err_out_o <= #1 wb_err & ~wb_err_out_i;
+end
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+	if (wb_rst_in)
+		rgpio_ctrl_o <= #1 2'b0;
+	else if (rgpio_ctrl_sel && wb_we_in)
+		rgpio_ctrl_o <= #1 wb_dat_in[1:0];
+	else if (rgpio_ctrl_i[`GPIO_RGPIO_CTRL_INTE])
+		rgpio_ctrl_o[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl_i[`GPIO_RGPIO_CTRL_INTS] | wb_inta_out_i;
+	else 
+		rgpio_ctrl_o <= #1 rgpio_ctrl_i;
+end
+
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+	if (wb_rst_in)
+		rgpio_out_o <= #1 {gw{1'b0}};
+	else begin
+	   rgpio_out_o <= #1 rgpio_out_i;
+	   if (rgpio_out_sel && wb_we_in)
+	   begin
+	     if ( wb_sel_in [3] == 1'b1 )
+	       rgpio_out_o [gw-1:24] <= #1 wb_dat_in [gw-1:24] ;
+	     if ( wb_sel_in [2] == 1'b1 )
+	       rgpio_out_o [23:16] <= #1 wb_dat_in [23:16] ;
+	     if ( wb_sel_in [1] == 1'b1 )
+	       rgpio_out_o [15:8] <= #1 wb_dat_in [15:8] ;
+	     if ( wb_sel_in [0] == 1'b1 )
+	       rgpio_out_o [7:0] <= #1 wb_dat_in [7:0] ;
+	   end
+	end 	
+end
+
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+    if (wb_rst_in)
+     	    rgpio_oe_o <= #1 {gw{1'b0}};
+    else begin
+    	rgpio_oe_o <= #1 rgpio_oe_i;
+    	if (rgpio_oe_sel && wb_we_in)
+	begin
+	    if ( wb_sel_in [3] == 1'b1 )
+	      rgpio_oe_o [gw-1:24] <= #1 wb_dat_in [gw-1:24] ;
+	    if ( wb_sel_in [2] == 1'b1 )
+	      rgpio_oe_o [23:16] <= #1 wb_dat_in [23:16] ;
+	    if ( wb_sel_in [1] == 1'b1 )
+	      rgpio_oe_o [15:8] <= #1 wb_dat_in [15:8] ;
+	    if ( wb_sel_in [0] == 1'b1 )
+	      rgpio_oe_o [7:0] <= #1 wb_dat_in [7:0] ;
+  	end
+    end
+end
+
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+	if (wb_rst_in)
+		rgpio_inte_o <= #1 {gw{1'b0}};
+	else begin
+		rgpio_inte_o <= #1 rgpio_inte_i;
+		if (rgpio_inte_sel && wb_we_in)
+   	     	begin
+   	     	     if ( wb_sel_in [3] == 1'b1 )
+   	     	       rgpio_inte_o [gw-1:24] <= #1 wb_dat_in [gw-1:24] ;
+   	     	     if ( wb_sel_in [2] == 1'b1 )
+   	     	       rgpio_inte_o [23:16] <= #1 wb_dat_in [23:16] ;
+   	     	     if ( wb_sel_in [1] == 1'b1 )
+   	     	       rgpio_inte_o [15:8] <= #1 wb_dat_in [15:8] ;
+   	     	     if ( wb_sel_in [0] == 1'b1 )
+   	     	       rgpio_inte_o [7:0] <= #1 wb_dat_in [7:0] ;
+   	     	end
+	end
+end
+
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+	if (wb_rst_in)
+		rgpio_ptrig_o <= #1 {gw{1'b0}};
+	else begin
+	    rgpio_ptrig_o <= #1 rgpio_ptrig_i;
+	    if (rgpio_ptrig_sel && wb_we_in)
+ 	    begin
+ 	       if ( wb_sel_in [3] == 1'b1 )
+ 	    	 rgpio_ptrig_o [gw-1:24] <= #1 wb_dat_in [gw-1:24] ;
+ 	       if ( wb_sel_in [2] == 1'b1 )
+ 	    	 rgpio_ptrig_o [23:16] <= #1 wb_dat_in [23:16] ;
+ 	       if ( wb_sel_in [1] == 1'b1 )
+ 	    	 rgpio_ptrig_o [15:8] <= #1 wb_dat_in [15:8] ;
+ 	       if ( wb_sel_in [0] == 1'b1 )
+ 	    	 rgpio_ptrig_o [7:0] <= #1 wb_dat_in [7:0] ;
+ 	     end
+	end
+end
+
+  
+//always @(posedge wb_clk_in or posedge wb_rst_in) begin
+//	if (wb_rst_in)
+//		rgpio_aux_o <= #1 {gw{1'b0}};
+//	else begin
+//	     rgpio_aux_o <= #1 rgpio_aux_i;
+//	     if (rgpio_aux_sel && wb_we_in)
+//	     begin
+//	     	if ( wb_sel_in [3] == 1'b1 )
+//	     	  rgpio_aux_o [gw-1:24] <= #1 wb_dat_in [gw-1:24] ;
+//	     	if ( wb_sel_in [2] == 1'b1 )
+//	     	  rgpio_aux_o [23:16] <= #1 wb_dat_in [23:16] ;
+//	     	if ( wb_sel_in [1] == 1'b1 )
+//	     	  rgpio_aux_o [15:8] <= #1 wb_dat_in [15:8] ;
+//	     	if ( wb_sel_in [0] == 1'b1 )
+//	     	  rgpio_aux_o [7:0] <= #1 wb_dat_in [7:0] ;
+//	      end
+//	end
+//end
+
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+	if (wb_rst_in)
+		rgpio_eclk_o <= #1 {gw{1'b0}};
+	else begin
+		rgpio_eclk_o <= #1 rgpio_eclk_i;
+	      	if (rgpio_eclk_sel && wb_we_in)
+	      	begin
+	     	 if ( wb_sel_in [3] == 1'b1 )
+	     	   rgpio_eclk_o [gw-1:24] <= #1 wb_dat_in [gw-1:24] ;
+	     	 if ( wb_sel_in [2] == 1'b1 )
+	     	   rgpio_eclk_o [23:16] <= #1 wb_dat_in [23:16] ;
+	     	 if ( wb_sel_in [1] == 1'b1 )
+	     	   rgpio_eclk_o [15:8] <= #1 wb_dat_in [15:8] ;
+	     	 if ( wb_sel_in [0] == 1'b1 )
+	     	   rgpio_eclk_o [7:0] <= #1 wb_dat_in [7:0] ;
+	       end
+	end
+end
+
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+	if (wb_rst_in)
+		rgpio_nec_o <= #1 {gw{1'b0}};
+	else begin
+		rgpio_nec_o <= #1 rgpio_nec_i; 
+		if (rgpio_nec_sel && wb_we_in)
+  		begin
+                     if ( wb_sel_in [3] == 1'b1 )
+                     rgpio_nec_o [gw-1:24] <= #1 wb_dat_in [gw-1:24] ;
+        	     if ( wb_sel_in [2] == 1'b1 )
+                     rgpio_nec_o [23:16] <= #1 wb_dat_in [23:16] ;
+        	     if ( wb_sel_in [1] == 1'b1 )
+                     rgpio_nec_o [15:8] <= #1 wb_dat_in [15:8] ;
+        	     if ( wb_sel_in [0] == 1'b1 )
+                     rgpio_nec_o [7:0] <= #1 wb_dat_in [7:0] ;
+   		end
+	end 
+end
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+  if (wb_rst_in) begin
+    sync_o      <= #1 {gw{1'b0}} ; 
+    GPIO_ext_pad_s_o <= #1 {gw{1'b0}} ; 
+  end 
+  else begin
+    sync_o      <= #1 GPIO_ext_pad_in  ; 
+    GPIO_ext_pad_s_o <= #1 sync_i       ; 
+  end
+end
+  
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+	if (wb_rst_in)
+		rgpio_in_o <= #1 {gw{1'b0}};
+	else
+		rgpio_in_o <= #1 in_muxed;
+end
+
+
+
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+  if (wb_rst_in) begin
+    sync_clk_o <= #1 1'b0 ;
+    clk_s_o    <= #1 1'b0 ;
+    clk_r_o    <= #1 1'b0 ;
+  end 
+  else begin
+    sync_clk_o <= #1 GPIO_clk_pad_in ;
+    clk_s_o    <= #1 sync_clk_i  ;
+    clk_r_o    <= #1 clk_s_i     ;
+  end
+end
+
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+  if (wb_rst_in) begin
+    pextc_sampled_o <= #1 {gw{1'b0}};
+  end else begin
+    pextc_sampled_o <= #1 extc_in ;
+  end
+end
+
+assign in_muxed = (rgpio_eclk_i & pextc_sampled_i) | (~rgpio_eclk_i & GPIO_ext_pad_s_i) ;
+ 
+
+always @(	wb_adr_in or rgpio_in_i or rgpio_out_i or rgpio_oe_i or rgpio_inte_i or 
+		rgpio_ptrig_i /*or rgpio_aux_i*/ or rgpio_ctrl_i or rgpio_ints_i or rgpio_eclk_i or rgpio_nec_i) 
+  begin
+	case (wb_adr_in[`GPIO_OFS_BITS])	
+    	`GPIO_RGPIO_OUT: begin
+			wb_dat[dw-1:0] = rgpio_out_i;
+		end
+  
+  		`GPIO_RGPIO_OE: begin
+			wb_dat[dw-1:0] = rgpio_oe_i;
+		end
+  
+  		`GPIO_RGPIO_INTE: begin
+			wb_dat[dw-1:0] = rgpio_inte_i;
+		end
+  
+  		`GPIO_RGPIO_PTRIG: begin
+			wb_dat[dw-1:0] = rgpio_ptrig_i;   
+		end
+  
+  		`GPIO_RGPIO_NEC: begin
+			wb_dat[dw-1:0] = rgpio_nec_i;
+		end
+  
+  		`GPIO_RGPIO_ECLK: begin
+			wb_dat[dw-1:0] = rgpio_eclk_i;
+		end
+  
+		//`GPIO_RGPIO_AUX: begin
+		//	wb_dat[dw-1:0] = rgpio_aux_i;
+		//end
+  
+  		`GPIO_RGPIO_CTRL: begin
+			wb_dat[1:0] = rgpio_ctrl_i;
+			wb_dat[dw-1:2] = {dw-2{1'b0}};
+		end
+  
+  		`GPIO_RGPIO_INTS: begin
+			wb_dat[dw-1:0] = rgpio_ints_i;
+		end
+  
+		default: begin
+			wb_dat[dw-1:0] = rgpio_in_i; 
+		end
+	endcase
+end
+
+
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+	if (wb_rst_in)
+		wb_dat_out_o <= #1 {dw{1'b0}};
+	else
+		wb_dat_out_o <= #1 wb_dat;
+end
+
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+	if (wb_rst_in)
+		rgpio_ints_o <= #1 {gw{1'b0}};
+	else if (rgpio_ints_sel && wb_we_in)
+		rgpio_ints_o <= #1 wb_dat_in[gw-1:0];
+	else if (rgpio_ctrl_i[`GPIO_RGPIO_CTRL_INTE])
+		rgpio_ints_o <= #1 (rgpio_ints_i | ((in_muxed ^ rgpio_in_i) & ~(in_muxed ^ rgpio_ptrig_i)) & rgpio_inte_i);
+	else 
+		rgpio_ints_o <= #1 rgpio_ints_i;
+end
+
+
+assign wb_inta = |rgpio_ints_i ? rgpio_ctrl_i[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
+
+
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+	if (wb_rst_in)
+		wb_inta_out_o <= #1 1'b0;
+	else
+		wb_inta_out_o <= #1 wb_inta;
+end
+
+
+assign GPIO_ext_padOE_out = rgpio_oe_i;
+//assign out_pad = rgpio_out_i & ~rgpio_aux_i | aux_in & rgpio_aux_i;
+assign out_pad = rgpio_out_i; //new
+
+ 
+always @(posedge wb_clk_in or posedge wb_rst_in) begin
+	if (wb_rst_in)
+		GPIO_ext_pad_out_o <= #1 {gw{1'b0}};
+	else
+		GPIO_ext_pad_out_o <= #1 out_pad;
+end
+
+
+endmodule
+
+
+
+
+
+module gpio_top_tri(
+	wb_clk_i_1, wb_clk_i_2, wb_clk_i_3, wb_rst_i_1, wb_rst_i_2, wb_rst_i_3, wb_cyc_i_1, wb_cyc_i_2, wb_cyc_i_3, 
+	wb_adr_i_1, wb_adr_i_2, wb_adr_i_3, wb_dat_i_1, wb_dat_i_2, wb_dat_i_3, wb_sel_i_1, wb_sel_i_2, wb_sel_i_3, 
+	wb_we_i_1, wb_we_i_2, wb_we_i_3, wb_stb_i_1, wb_stb_i_2, wb_stb_i_3,
+	wb_dat_o_1, wb_dat_o_2, wb_dat_o_3, wb_ack_o_1, wb_ack_o_2, wb_ack_o_3, wb_err_o_1, wb_err_o_2, wb_err_o_3, 
+	wb_inta_o_1, wb_inta_o_2, wb_inta_o_3,
+	//aux_i_1, aux_i_2, aux_i_3,
+	GPIO_ext_pad_i_1, GPIO_ext_pad_i_2, GPIO_ext_pad_i_3, 
+	GPIO_ext_pad_o_1, GPIO_ext_pad_o_2, GPIO_ext_pad_o_3, GPIO_ext_padOE_o_1, GPIO_ext_padOE_o_2, 
+	GPIO_ext_padOE_o_3, GPIO_clk_pad_i_1, GPIO_clk_pad_i_2, GPIO_clk_pad_i_3 
+);
+
+parameter dw = 32;
+parameter aw = `GPIO_ADDRHH+1;
+parameter gw = `GPIO_IOS;
+
+input             wb_clk_i_1, wb_clk_i_2, wb_clk_i_3;	
+input             wb_rst_i_1, wb_rst_i_2, wb_rst_i_3;	
+input             wb_cyc_i_1, wb_cyc_i_2, wb_cyc_i_3;	
+input   [aw-1:0]	wb_adr_i_1, wb_adr_i_2, wb_adr_i_3;	
+input   [dw-1:0]	wb_dat_i_1, wb_dat_i_2, wb_dat_i_3;	
+input	  [3:0]     wb_sel_i_1, wb_sel_i_2, wb_sel_i_3;	
+input             wb_we_i_1, wb_we_i_2, wb_we_i_3;	
+input             wb_stb_i_1, wb_stb_i_2, wb_stb_i_3;	
+output  [dw-1:0]  wb_dat_o_1, wb_dat_o_2, wb_dat_o_3;	
+output            wb_ack_o_1, wb_ack_o_2, wb_ack_o_3;	
+output            wb_err_o_1, wb_err_o_2, wb_err_o_3;	
+output            wb_inta_o_1, wb_inta_o_2, wb_inta_o_3;	
+//input	  [gw-1:0]  aux_i_1, aux_i_2, aux_i_3;		
+input   [gw-1:0]  GPIO_ext_pad_i_1, GPIO_ext_pad_i_2, GPIO_ext_pad_i_3;	
+input             GPIO_clk_pad_i_1, GPIO_clk_pad_i_2, GPIO_clk_pad_i_3;	
+output  [gw-1:0]  GPIO_ext_pad_o_1, GPIO_ext_pad_o_2, GPIO_ext_pad_o_3;	
+output  [gw-1:0]  GPIO_ext_padOE_o_1, GPIO_ext_padOE_o_2, GPIO_ext_padOE_o_3;
+
+	wire wb_ack_o_1, wb_ack_o_2, wb_ack_o_3;
+	wire wb_err_o_1, wb_err_o_2, wb_err_o_3;
+	wire [1:0] rgpio_ctrl_1, rgpio_ctrl_2, rgpio_ctrl_3;
+	wire [gw-1:0] rgpio_o_1, rgpio_o_2, rgpio_o_3;
+	wire [gw-1:0] rgpio_oe_1, rgpio_oe_2, rgpio_oe_3;
+	wire [gw-1:0] rgpio_inte_1, rgpio_inte_2, rgpio_inte_3;
+	wire [gw-1:0] rgpio_ptrig_1, rgpio_ptrig_2, rgpio_ptrig_3;
+	//wire [gw-1:0] rgpio_aux_1, rgpio_aux_2, rgpio_aux_3;
+	wire [gw-1:0] rgpio_eclk_1, rgpio_eclk_2, rgpio_eclk_3;
+	wire [gw-1:0] rgpio_nec_1, rgpio_nec_2, rgpio_nec_3;
+	wire [gw-1:0] sync_1, sync_2, sync_3;
+	wire [gw-1:0] GPIO_ext_pad_s_1, GPIO_ext_pad_s_2, GPIO_ext_pad_s_3;
+	wire [gw-1:0] rgpio_i_1, rgpio_i_2, rgpio_i_3;
+	wire sync_clk_1, sync_clk_2, sync_clk_3;
+	wire clk_s_1, clk_s_2, clk_s_3;
+	wire clk_r_1, clk_r_2, clk_r_3;
+	wire [gw-1:0] pextc_sampled_1, pextc_sampled_2, pextc_sampled_3;
+	wire [dw-1:0] wb_dat_o_1, wb_dat_o_2, wb_dat_o_3;
+	wire [gw-1:0] rgpio_ints_1, rgpio_ints_2, rgpio_ints_3;
+	wire wb_inta_o_1, wb_inta_o_2, wb_inta_o_3;
+	wire [gw-1:0] GPIO_ext_pad_o_1, GPIO_ext_pad_o_2, GPIO_ext_pad_o_3;
+	wire wb_ack_out;
+	wire wb_err_out;
+	wire [1:0] rgpio_ctrl;
+	wire [gw-1:0] rgpio_out;
+	wire [gw-1:0] rgpio_oe;
+	wire [gw-1:0] rgpio_inte;
+	wire [gw-1:0] rgpio_ptrig;
+	//wire [gw-1:0] rgpio_aux;
+	wire [gw-1:0] rgpio_eclk;
+	wire [gw-1:0] rgpio_nec;
+	wire [gw-1:0] sync;
+	wire [gw-1:0] GPIO_ext_pad_s;
+	wire [gw-1:0] rgpio_in;
+	wire sync_clk;
+	wire clk_s;
+	wire clk_r;
+	wire [gw-1:0] pextc_sampled;
+	wire [dw-1:0] wb_dat_out;
+	wire [gw-1:0] rgpio_ints;
+	wire wb_inta_out;
+	wire [gw-1:0] GPIO_ext_pad_out;
+
+	gpio_top_iostate #(.dw(dw), .aw(aw), .gw(gw) ) gpio_top_iostate_1 (
+	.wb_clk_in(wb_clk_i_1), .wb_rst_in(wb_rst_i_1), .wb_cyc_in(wb_cyc_i_1), .wb_adr_in(wb_adr_i_1), .wb_dat_in(wb_dat_i_1), .wb_sel_in(wb_sel_i_1), .wb_we_in(wb_we_i_1), .wb_stb_in(wb_stb_i_1),
+	.wb_dat_out_i(wb_dat_o_1), .wb_dat_out_o(wb_dat_o_2), .wb_ack_out_i(wb_ack_o_1), .wb_ack_out_o(wb_ack_o_2), .wb_err_out_i(wb_err_o_1), .wb_err_out_o(wb_err_o_2), .wb_inta_out_i(wb_inta_o_1), .wb_inta_out_o(wb_inta_o_2),
+	/*.aux_in(aux_i_1),.rgpio_aux_i(rgpio_aux_1), .rgpio_aux_o(rgpio_aux_2),*/
+	.GPIO_ext_pad_in(GPIO_ext_pad_i_1), .GPIO_ext_pad_out_i(GPIO_ext_pad_o_1), .GPIO_ext_pad_out_o(GPIO_ext_pad_o_2), .GPIO_ext_padOE_out(GPIO_ext_padOE_o_1), .GPIO_clk_pad_in(GPIO_clk_pad_i_1), .rgpio_ctrl_i(rgpio_ctrl_1), .rgpio_ctrl_o(rgpio_ctrl_2), .rgpio_out_i(rgpio_o_1), .rgpio_out_o(rgpio_o_2), .rgpio_oe_i(rgpio_oe_1), .rgpio_oe_o(rgpio_oe_2), .rgpio_inte_i(rgpio_inte_1), .rgpio_inte_o(rgpio_inte_2), .rgpio_ptrig_i(rgpio_ptrig_1), .rgpio_ptrig_o(rgpio_ptrig_2), 
+	.rgpio_eclk_i(rgpio_eclk_1), .rgpio_eclk_o(rgpio_eclk_2), .rgpio_nec_i(rgpio_nec_1), .rgpio_nec_o(rgpio_nec_2), .sync_i(sync_1), .sync_o(sync_2), .GPIO_ext_pad_s_i(GPIO_ext_pad_s_1), .GPIO_ext_pad_s_o(GPIO_ext_pad_s_2), .rgpio_in_i(rgpio_i_1), .rgpio_in_o(rgpio_i_2), .sync_clk_i(sync_clk_1), .sync_clk_o(sync_clk_2), .clk_s_i(clk_s_1), .clk_s_o(clk_s_2), .clk_r_i(clk_r_1), .clk_r_o(clk_r_2), .pextc_sampled_i(pextc_sampled_1), .pextc_sampled_o(pextc_sampled_2), .rgpio_ints_i(rgpio_ints_1), .rgpio_ints_o(rgpio_ints_2));
+
+	gpio_top_iostate #(.dw(dw), .aw(aw), .gw(gw) ) gpio_top_iostate_2 (
+	.wb_clk_in(wb_clk_i_2), .wb_rst_in(wb_rst_i_2), .wb_cyc_in(wb_cyc_i_2), .wb_adr_in(wb_adr_i_2), .wb_dat_in(wb_dat_i_2), .wb_sel_in(wb_sel_i_2), .wb_we_in(wb_we_i_2), .wb_stb_in(wb_stb_i_2),
+	.wb_dat_out_i(wb_dat_o_2), .wb_dat_out_o(wb_dat_o_3), .wb_ack_out_i(wb_ack_o_2), .wb_ack_out_o(wb_ack_o_3), .wb_err_out_i(wb_err_o_2), .wb_err_out_o(wb_err_o_3), .wb_inta_out_i(wb_inta_o_2), .wb_inta_out_o(wb_inta_o_3),
+	/*.aux_in(aux_i_2),.rgpio_aux_i(rgpio_aux_2), .rgpio_aux_o(rgpio_aux_3),*/
+	.GPIO_ext_pad_in(GPIO_ext_pad_i_2), .GPIO_ext_pad_out_i(GPIO_ext_pad_o_2), .GPIO_ext_pad_out_o(GPIO_ext_pad_o_3), .GPIO_ext_padOE_out(GPIO_ext_padOE_o_2), .GPIO_clk_pad_in(GPIO_clk_pad_i_2), .rgpio_ctrl_i(rgpio_ctrl_2), .rgpio_ctrl_o(rgpio_ctrl_3), .rgpio_out_i(rgpio_o_2), .rgpio_out_o(rgpio_o_3), .rgpio_oe_i(rgpio_oe_2), .rgpio_oe_o(rgpio_oe_3), .rgpio_inte_i(rgpio_inte_2), .rgpio_inte_o(rgpio_inte_3), .rgpio_ptrig_i(rgpio_ptrig_2), .rgpio_ptrig_o(rgpio_ptrig_3), 
+	.rgpio_eclk_i(rgpio_eclk_2), .rgpio_eclk_o(rgpio_eclk_3), .rgpio_nec_i(rgpio_nec_2), .rgpio_nec_o(rgpio_nec_3), .sync_i(sync_2), .sync_o(sync_3), .GPIO_ext_pad_s_i(GPIO_ext_pad_s_2), .GPIO_ext_pad_s_o(GPIO_ext_pad_s_3), .rgpio_in_i(rgpio_i_2), .rgpio_in_o(rgpio_i_3), .sync_clk_i(sync_clk_2), .sync_clk_o(sync_clk_3), .clk_s_i(clk_s_2), .clk_s_o(clk_s_3), .clk_r_i(clk_r_2), .clk_r_o(clk_r_3), .pextc_sampled_i(pextc_sampled_2), .pextc_sampled_o(pextc_sampled_3), .rgpio_ints_i(rgpio_ints_2), .rgpio_ints_o(rgpio_ints_3));
+
+
+
+
+	gpio_top_iostate #(.dw(dw), .aw(aw), .gw(gw) ) gpio_top_iostate_3 (
+	.wb_clk_in(wb_clk_i_3), .wb_rst_in(wb_rst_i_3), .wb_cyc_in(wb_cyc_i_3), .wb_adr_in(wb_adr_i_3), .wb_dat_in(wb_dat_i_3), .wb_sel_in(wb_sel_i_3), .wb_we_in(wb_we_i_3), .wb_stb_in(wb_stb_i_3),
+	.wb_dat_out_i(wb_dat_o_3), .wb_dat_out_o(wb_dat_out), .wb_ack_out_i(wb_ack_o_3), .wb_ack_out_o(wb_ack_out), .wb_err_out_i(wb_err_o_3), .wb_err_out_o(wb_err_out), .wb_inta_out_i(wb_inta_o_3), .wb_inta_out_o(wb_inta_out),
+	/*.aux_in(aux_i_3),.rgpio_aux_i(rgpio_aux_3), .rgpio_aux_o(rgpio_aux),*/
+	.GPIO_ext_pad_in(GPIO_ext_pad_i_3), .GPIO_ext_pad_out_i(GPIO_ext_pad_o_3), .GPIO_ext_pad_out_o(GPIO_ext_pad_out), .GPIO_ext_padOE_out(GPIO_ext_padOE_o_3), .GPIO_clk_pad_in(GPIO_clk_pad_i_3), .rgpio_ctrl_i(rgpio_ctrl_3), .rgpio_ctrl_o(rgpio_ctrl), .rgpio_out_i(rgpio_o_3), .rgpio_out_o(rgpio_out), .rgpio_oe_i(rgpio_oe_3), .rgpio_oe_o(rgpio_oe), .rgpio_inte_i(rgpio_inte_3), .rgpio_inte_o(rgpio_inte), .rgpio_ptrig_i(rgpio_ptrig_3), .rgpio_ptrig_o(rgpio_ptrig), 
+	.rgpio_eclk_i(rgpio_eclk_3), .rgpio_eclk_o(rgpio_eclk), .rgpio_nec_i(rgpio_nec_3), .rgpio_nec_o(rgpio_nec), .sync_i(sync_3), .sync_o(sync), .GPIO_ext_pad_s_i(GPIO_ext_pad_s_3), .GPIO_ext_pad_s_o(GPIO_ext_pad_s), .rgpio_in_i(rgpio_i_3), .rgpio_in_o(rgpio_in), .sync_clk_i(sync_clk_3), .sync_clk_o(sync_clk), .clk_s_i(clk_s_3), .clk_s_o(clk_s), .clk_r_i(clk_r_3), .clk_r_o(clk_r), .pextc_sampled_i(pextc_sampled_3), .pextc_sampled_o(pextc_sampled), .rgpio_ints_i(rgpio_ints_3), .rgpio_ints_o(rgpio_ints));
+
+
+	majority_voter #(.WIDTH(22+gw-1+gw-1+gw-1+gw-1+gw-1+gw-1+gw-1+gw-1+gw-1+gw-1+gw-1+dw-1+gw-1+gw-1 -gw )) mv (
+		.in1({wb_ack_o_2, wb_err_o_2, rgpio_ctrl_2, rgpio_o_2, rgpio_oe_2, rgpio_inte_2, rgpio_ptrig_2, /*rgpio_aux_2,*/ rgpio_eclk_2, rgpio_nec_2, sync_2, GPIO_ext_pad_s_2, rgpio_i_2, sync_clk_2, clk_s_2, clk_r_2, pextc_sampled_2, wb_dat_o_2, rgpio_ints_2, wb_inta_o_2, GPIO_ext_pad_o_2}),
+		.in2({wb_ack_o_3, wb_err_o_3, rgpio_ctrl_3, rgpio_o_3, rgpio_oe_3, rgpio_inte_3, rgpio_ptrig_3, /*rgpio_aux_3,*/ rgpio_eclk_3, rgpio_nec_3, sync_3, GPIO_ext_pad_s_3, rgpio_i_3, sync_clk_3, clk_s_3, clk_r_3, pextc_sampled_3, wb_dat_o_3, rgpio_ints_3, wb_inta_o_3, GPIO_ext_pad_o_3}),
+		.in3({wb_ack_out, wb_err_out, rgpio_ctrl, rgpio_out, rgpio_oe, rgpio_inte, rgpio_ptrig, /*rgpio_aux,*/ rgpio_eclk, rgpio_nec, sync, GPIO_ext_pad_s, rgpio_in, sync_clk, clk_s, clk_r, pextc_sampled, wb_dat_out, rgpio_ints, wb_inta_out, GPIO_ext_pad_out}),
+		.out({wb_ack_o_1, wb_err_o_1, rgpio_ctrl_1, rgpio_o_1, rgpio_oe_1, rgpio_inte_1, rgpio_ptrig_1, /*rgpio_aux_1,*/ rgpio_eclk_1, rgpio_nec_1, sync_1, GPIO_ext_pad_s_1, rgpio_i_1, sync_clk_1, clk_s_1, clk_r_1, pextc_sampled_1, wb_dat_o_1, rgpio_ints_1, wb_inta_o_1, GPIO_ext_pad_o_1}),
+		.err()
+	);
+
+endmodule
+
+
diff --git a/vldb/code/Testbench/SCA-model/I2C_channel.v b/vldb/code/Testbench/SCA-model/I2C_channel.v
new file mode 100644
index 0000000..ea6a4a4
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/I2C_channel.v
@@ -0,0 +1,3931 @@
+// Modified the 1 October 2015
+// change log:
+// - line  559: added asyncronous reset for i2c_dat_out_o
+// - line 1965: added initialization value for: 
+//              busy_o, scl_o, sda_o, nb_byte_o, le_ec_o, 
+//              address_o, ack_multi_orx_1byte_o, 
+//              nb_bit_o, ack_ok_o, registre_o sda_gnd_o  
+
+
+
+`timescale 1ns / 1ps
+`include "I2C_prog_divider.v"
+`timescale 1ns/1ps
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  wb_i2c
+//      Library Name  :  node_ctrl
+//  
+//      Creation Date :  Mon Jun 24 09:42:12 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  node_ctrl
+//  Unit    Name :  wb_i2c
+//  Unit    Type :  Block Diagram
+//  
+//----------------------------------------------------
+ 
+
+
+module wb_i2c_tri (
+
+output  scl_1,
+output  scl_2,
+output  scl_3,
+output  sclen_1,// added 26 october 2015 
+output  sclen_2,// added 26 october 2015 
+output  sclen_3,// added 26 october 2015 
+output  sda_out_1,
+output  sda_out_2,
+output  sda_out_3,
+output  wb_int_o_1,
+output  wb_int_o_2,
+output  wb_int_o_3,
+output  wb_ack_o_1,
+output  wb_ack_o_2,
+output  wb_ack_o_3,
+output  wb_err_o_1,
+output  wb_err_o_2,
+output  wb_err_o_3,
+output [31:0]  wb_dat_o_1, 
+output [31:0]  wb_dat_o_2, 
+output [31:0]  wb_dat_o_3, 
+input  sda_in_1,
+input  sda_in_2,
+input  sda_in_3,
+input [31:0]  wb_dat_i_1, 
+input [31:0]  wb_dat_i_2, 
+input [31:0]  wb_dat_i_3, 
+input [4:0]  wb_adr_i_1,
+input [4:0]  wb_adr_i_2,
+input [4:0]  wb_adr_i_3,
+input  wb_rst_i_1,
+input  wb_rst_i_2,
+input  wb_rst_i_3,
+input [3:0]  wb_sel_i_1, 
+input [3:0]  wb_sel_i_2, 
+input [3:0]  wb_sel_i_3, 
+input  wb_we_i_1,
+input  wb_we_i_2,
+input  wb_we_i_3,
+input  wb_stb_i_1,
+input  wb_stb_i_2,
+input  wb_stb_i_3,
+input  wb_cyc_i_1,
+input  wb_cyc_i_2,
+input  wb_cyc_i_3,
+input  wb_clk_i_1,
+input  wb_clk_i_2,
+input  wb_clk_i_3
+);
+
+wire [31:0]  i2c_msk_reg_1;
+wire [31:0]  i2c_msk_reg_2;
+wire [31:0]  i2c_msk_reg_3;
+wire [7:0]  SRA_reg_1;
+wire [7:0]  SRA_reg_2;
+wire [7:0]  SRA_reg_3;
+wire  reponse_1;
+wire  reponse_2;
+wire  reponse_3;
+wire  read_nc_1;
+wire  read_nc_2;
+wire  read_nc_3;
+wire [7:0]  i2c_dat_out_1;
+wire [7:0]  i2c_dat_out_2;
+wire [7:0]  i2c_dat_out_3;
+wire  Start_tr_1;
+wire  Start_tr_2;
+wire  Start_tr_3;
+wire [7:0]  Rx_Byte_1;
+wire [7:0]  Rx_Byte_2;
+wire [7:0]  Rx_Byte_3;
+wire  MultiByte_1;
+wire  MultiByte_2;
+wire  MultiByte_3;
+wire [127:0]  rx_1;
+wire [127:0]  rx_2;
+wire [127:0]  rx_3;
+wire [3:0]  data_reg_sel_1;
+wire [3:0]  data_reg_sel_2;
+wire [3:0]  data_reg_sel_3;
+wire  busy_1;
+wire  busy_2;
+wire  busy_3;
+wire  rx_1byte_1;
+wire  rx_1byte_2;
+wire  rx_1byte_3;
+wire [31:0]  i2c_ctrl_reg_1;
+wire [31:0]  i2c_ctrl_reg_2;
+wire [31:0]  i2c_ctrl_reg_3;
+wire [3:0]  blktr_idx_1;
+wire [3:0]  blktr_idx_2;
+wire [3:0]  blktr_idx_3;
+wire [31:0]  r0_out_1;
+wire [31:0]  r0_out_2;
+wire [31:0]  r0_out_3;
+wire [3:0]  O_1;
+wire [3:0]  O_2;
+wire [3:0]  O_3;
+wire  S133_1;
+wire  S133_2;
+wire  S133_3;
+wire  le_ec_1;
+wire  le_ec_2;
+wire  le_ec_3;
+
+// added 26 october 2015 
+	wire outscl_1, outscl_2, outscl_3;
+	wire scl_mode_1 = i2c_ctrl_reg_1[31];
+	wire scl_mode_2 = i2c_ctrl_reg_2[31];
+	wire scl_mode_3 = i2c_ctrl_reg_3[31];
+	assign scl_1    = (scl_mode_1) ? outscl_1 : 1'b0;
+	assign scl_2    = (scl_mode_2) ? outscl_2 : 1'b0;
+	assign scl_3    = (scl_mode_3) ? outscl_3 : 1'b0;
+	assign sclen_1  = (scl_mode_1) ? 1'b1 : ~outscl_1;
+	assign sclen_2  = (scl_mode_2) ? 1'b1 : ~outscl_2;
+	assign sclen_3  = (scl_mode_3) ? 1'b1 : ~outscl_3;
+/////////////////////// 
+
+i2c_multi_reg_tri  I2C_multi (
+     .clk_1(wb_clk_i_1),
+     .rst_1(wb_rst_i_1),
+     .wb_dat_in_1(wb_dat_i_1[31:0]),
+     .i2c_dat_out_1(i2c_dat_out_1[7:0]),
+     .latch_1(O_1[3:0]),
+     .i2c_latch_1(blktr_idx_1[3:0]),
+     .Rx_1byte_1(rx_1byte_1),
+     .rx_1(rx_1[127:0]),
+     .byte_sel_1(wb_sel_i_1[3:0]),
+     .tip_1(busy_1),
+     .le_el_1(le_ec_1),
+     .multi_byte_1(MultiByte_1),
+     .Rx_Byte_in_1(Rx_Byte_1[7:0]),
+		.clk_2(wb_clk_i_2),
+     .rst_2(wb_rst_i_2),
+     .wb_dat_in_2(wb_dat_i_2[31:0]),
+     .i2c_dat_out_2(i2c_dat_out_2[7:0]),
+     .latch_2(O_2[3:0]),
+     .i2c_latch_2(blktr_idx_2[3:0]),
+     .Rx_1byte_2(rx_1byte_2),
+     .rx_2(rx_2[127:0]),
+     .byte_sel_2(wb_sel_i_2[3:0]),
+     .tip_2(busy_2),
+     .le_el_2(le_ec_2),
+     .multi_byte_2(MultiByte_2),
+     .Rx_Byte_in_2(Rx_Byte_2[7:0]),
+		.clk_3(wb_clk_i_3),
+     .rst_3(wb_rst_i_3),
+     .wb_dat_in_3(wb_dat_i_3[31:0]),
+     .i2c_dat_out_3(i2c_dat_out_3[7:0]),
+     .latch_3(O_3[3:0]),
+     .i2c_latch_3(blktr_idx_3[3:0]),
+     .Rx_1byte_3(rx_1byte_3),
+     .rx_3(rx_3[127:0]),
+     .byte_sel_3(wb_sel_i_3[3:0]),
+     .tip_3(busy_3),
+     .le_el_3(le_ec_3),
+     .multi_byte_3(MultiByte_3),
+     .Rx_Byte_in_3(Rx_Byte_3[7:0])
+	);
+
+
+wb_adapt_i2c_tri  WB2I2c (
+     .clk_1(wb_clk_i_1),
+     .rst_1(wb_rst_i_1),
+     .Start_tr_1(Start_tr_1),
+     .wb_ack_1(wb_ack_o_1),
+     .reponse_n_1(reponse_1),
+     .read_nc_1(read_nc_1),
+     .wb_we_1(wb_we_i_1),
+     .wb_addr_1(wb_adr_i_1[4:0]),
+		.clk_2(wb_clk_i_2),
+     .rst_2(wb_rst_i_2),
+     .Start_tr_2(Start_tr_2),
+     .wb_ack_2(wb_ack_o_2),
+     .reponse_n_2(reponse_2),
+     .read_nc_2(read_nc_2),
+     .wb_we_2(wb_we_i_2),
+     .wb_addr_2(wb_adr_i_2[4:0]),
+		.clk_3(wb_clk_i_3),
+     .rst_3(wb_rst_i_3),
+     .Start_tr_3(Start_tr_3),
+     .wb_ack_3(wb_ack_o_3),
+     .reponse_n_3(reponse_3),
+     .read_nc_3(read_nc_3),
+     .wb_we_3(wb_we_i_3),
+     .wb_addr_3(wb_adr_i_3[4:0])
+);
+
+
+wb_generic_tri  wb_gen_1 (
+     .wb_clk_in_1(wb_clk_i_1),
+     .wb_rst_in_1(wb_rst_i_1),
+     .wb_adr_in_1(wb_adr_i_1[4:0]),
+     .wb_dat_in_1(wb_dat_i_1[31:0]),
+     .wb_dat_out_1(wb_dat_o_1[31:0]),
+     .wb_sel_in_1(wb_sel_i_1[3:0]),
+     .wb_we_in_1(wb_we_i_1),
+     .wb_stb_in_1(wb_stb_i_1),
+     .wb_cyc_in_1(wb_cyc_i_1),
+     .wb_ack_out_1(wb_ack_o_1),
+     .wb_err_out_1(wb_err_o_1),
+     .wb_int_out_1(wb_int_o_1),
+     .registre0_1(r0_out_1[31:0]),
+     .i2c_msk_reg_1(i2c_msk_reg_1[31:0]),
+     .tip_1(busy_1),
+     .last_bit_1(read_nc_1),
+     .status_i2c_1(SRA_reg_1[7:0]),
+     .i2c_ctrl_reg_1(i2c_ctrl_reg_1[31:0]),
+     .rx_byte_in_1(Rx_Byte_1[7:0]),
+     .data_reg_sel_1(data_reg_sel_1[3:0]),
+     .rx_1(rx_1[127:0]),
+		.wb_clk_in_2(wb_clk_i_2),
+     .wb_rst_in_2(wb_rst_i_2),
+     .wb_adr_in_2(wb_adr_i_2[4:0]),
+     .wb_dat_in_2(wb_dat_i_2[31:0]),
+     .wb_dat_out_2(wb_dat_o_2[31:0]),
+     .wb_sel_in_2(wb_sel_i_2[3:0]),
+     .wb_we_in_2(wb_we_i_2),
+     .wb_stb_in_2(wb_stb_i_2),
+     .wb_cyc_in_2(wb_cyc_i_2),
+     .wb_ack_out_2(wb_ack_o_2),
+     .wb_err_out_2(wb_err_o_2),
+     .wb_int_out_2(wb_int_o_2),
+     .registre0_2(r0_out_2[31:0]),
+     .i2c_msk_reg_2(i2c_msk_reg_2[31:0]),
+     .tip_2(busy_2),
+     .last_bit_2(read_nc_2),
+     .status_i2c_2(SRA_reg_2[7:0]),
+     .i2c_ctrl_reg_2(i2c_ctrl_reg_2[31:0]),
+     .rx_byte_in_2(Rx_Byte_2[7:0]),
+     .data_reg_sel_2(data_reg_sel_2[3:0]),
+     .rx_2(rx_2[127:0]),
+		.wb_clk_in_3(wb_clk_i_3),
+     .wb_rst_in_3(wb_rst_i_3),
+     .wb_adr_in_3(wb_adr_i_3[4:0]),
+     .wb_dat_in_3(wb_dat_i_3[31:0]),
+     .wb_dat_out_3(wb_dat_o_3[31:0]),
+     .wb_sel_in_3(wb_sel_i_3[3:0]),
+     .wb_we_in_3(wb_we_i_3),
+     .wb_stb_in_3(wb_stb_i_3),
+     .wb_cyc_in_3(wb_cyc_i_3),
+     .wb_ack_out_3(wb_ack_o_3),
+     .wb_err_out_3(wb_err_o_3),
+     .wb_int_out_3(wb_int_o_3),
+     .registre0_3(r0_out_3[31:0]),
+     .i2c_msk_reg_3(i2c_msk_reg_3[31:0]),
+     .tip_3(busy_3),
+     .last_bit_3(read_nc_3),
+     .status_i2c_3(SRA_reg_3[7:0]),
+     .i2c_ctrl_reg_3(i2c_ctrl_reg_3[31:0]),
+     .rx_byte_in_3(Rx_Byte_3[7:0]),
+     .data_reg_sel_3(data_reg_sel_3[3:0]),
+     .rx_3(rx_3[127:0])
+);
+
+
+i2c_blk_tri  I2C_ccu (
+     	.scl_1(outscl_1),
+     .sda_out_1(sda_out_1),
+     .reponse_1(reponse_1),
+     .clk_1(wb_clk_i_1),
+     .read_nc_1(read_nc_1),
+     .busy_1(busy_1),
+     .sda_in_1(sda_in_1),
+     .i2c_br_1(S133_1),
+     .reset_1(wb_rst_i_1),
+     .SRA_out_1(SRA_reg_1[7:0]),
+     .MultiByte_1(MultiByte_1),
+     .rx_1byte_1(rx_1byte_1),
+     .msk_1(i2c_msk_reg_1[31:24]),
+     .blktr_idx_1(blktr_idx_1[3:0]),
+     .Start_tr_n_1(Start_tr_1),
+     .le_ec_1(le_ec_1),
+     .Rx_Byte_o_1(Rx_Byte_1[7:0]),
+     .multi_byte_in_1(i2c_dat_out_1[7:0]),
+     .cra_1(i2c_ctrl_reg_1[30:24]),
+     .byte_out_cmd_1(r0_out_1[31:24]),
+     .byte_out3_1(r0_out_1[23:16]),
+     .byte_out4_1(r0_out_1[15:8]),
+     .byte_out5_1(r0_out_1[7:0]),
+		.scl_2(outscl_2),
+     .sda_out_2(sda_out_2),
+     .reponse_2(reponse_2),
+     .clk_2(wb_clk_i_2),
+     .read_nc_2(read_nc_2),
+     .busy_2(busy_2),
+     .sda_in_2(sda_in_2),
+     .i2c_br_2(S133_2),
+     .reset_2(wb_rst_i_2),
+     .SRA_out_2(SRA_reg_2[7:0]),
+     .MultiByte_2(MultiByte_2),
+     .rx_1byte_2(rx_1byte_2),
+     .msk_2(i2c_msk_reg_2[31:24]),
+     .blktr_idx_2(blktr_idx_2[3:0]),
+     .Start_tr_n_2(Start_tr_2),
+     .le_ec_2(le_ec_2),
+     .Rx_Byte_o_2(Rx_Byte_2[7:0]),
+     .multi_byte_in_2(i2c_dat_out_2[7:0]),
+     .cra_2(i2c_ctrl_reg_2[31:24]),
+     .byte_out_cmd_2(r0_out_2[31:24]),
+     .byte_out3_2(r0_out_2[23:16]),
+     .byte_out4_2(r0_out_2[15:8]),
+     .byte_out5_2(r0_out_2[7:0]),
+		.scl_3(outscl_3),
+     .sda_out_3(sda_out_3),
+     .reponse_3(reponse_3),
+     .clk_3(wb_clk_i_3),
+     .read_nc_3(read_nc_3),
+     .busy_3(busy_3),
+     .sda_in_3(sda_in_3),
+     .i2c_br_3(S133_3),
+     .reset_3(wb_rst_i_3),
+     .SRA_out_3(SRA_reg_3[7:0]),
+     .MultiByte_3(MultiByte_3),
+     .rx_1byte_3(rx_1byte_3),
+     .msk_3(i2c_msk_reg_3[31:24]),
+     .blktr_idx_3(blktr_idx_3[3:0]),
+     .Start_tr_n_3(Start_tr_3),
+     .le_ec_3(le_ec_3),
+     .Rx_Byte_o_3(Rx_Byte_3[7:0]),
+     .multi_byte_in_3(i2c_dat_out_3[7:0]),
+     .cra_3(i2c_ctrl_reg_3[31:24]),
+     .byte_out_cmd_3(r0_out_3[31:24]),
+     .byte_out3_3(r0_out_3[23:16]),
+     .byte_out4_3(r0_out_3[15:8]),
+     .byte_out5_3(r0_out_3[7:0])
+);
+
+assign S133_1 = 1'b0;
+assign S133_2 = 1'b0;
+assign S133_3 = 1'b0;
+
+assign O_1[3] = ( data_reg_sel_1[3]) & ( wb_we_i_1);
+assign O_2[3] = ( data_reg_sel_2[3]) & ( wb_we_i_2);
+assign O_3[3] = ( data_reg_sel_3[3]) & ( wb_we_i_3);
+
+assign O_1[2] = ( data_reg_sel_1[2]) & ( wb_we_i_1);
+assign O_2[2] = ( data_reg_sel_2[2]) & ( wb_we_i_2);
+assign O_3[2] = ( data_reg_sel_3[2]) & ( wb_we_i_3);
+
+assign O_1[1] = ( data_reg_sel_1[1]) & ( wb_we_i_1);
+assign O_2[1] = ( data_reg_sel_2[1]) & ( wb_we_i_2);
+assign O_3[1] = ( data_reg_sel_3[1]) & ( wb_we_i_3);
+
+assign O_1[0] = ( data_reg_sel_1[0]) & ( wb_we_i_1);
+assign O_2[0] = ( data_reg_sel_2[0]) & ( wb_we_i_2);
+assign O_3[0] = ( data_reg_sel_3[0]) & ( wb_we_i_3);
+
+
+endmodule
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  i2c_multi_reg
+//      Library Name  :  node_ctrl
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013  (CHANGED 11SEPT13)
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  node_ctrl
+//  Unit    Name :  i2c_multi_reg
+//  Unit    Type :  Text Unit
+//  
+//----------------------------------------------------
+//////////////////////////////////////////
+//////////////////////////////////////////
+// Date        : Tue Nov 20 11:36:53 2012
+//
+// Author      : Ch.Paillard
+//
+// Company     : CERN
+//
+// Description : registre 128 bit pour multi byte transfert i2c
+//
+//////////////////////////////////////////
+//////////////////////////////////////////
+
+
+
+module i2c_multi_reg_iostate(clk,rst,wb_dat_in,i2c_dat_out_i, i2c_dat_out_o,latch,i2c_latch,
+                     Rx_1byte,rx,byte_sel,tip,le_el,multi_byte,Rx_Byte_in, data_i, data_o);
+  
+ input           clk;
+ input    [7:0]  i2c_dat_out_i; 
+ input  [127:0]  data_i;   
+
+ input           rst;
+ input    [3:0]  latch;         
+ output [127:0]  rx;
+ output   [7:0]  i2c_dat_out_o;
+ output [127:0]  data_o;
+ input    [3:0]  byte_sel;     
+ input           tip;                 
+ input           le_el;               
+ input           multi_byte;          
+ input           Rx_1byte;            
+ input  [31:0]   wb_dat_in;  
+ input   [3:0]   i2c_latch;  
+ input   [7:0]   Rx_Byte_in;  
+ reg     [7:0]   i2c_dat_out_o;
+ reg   [127:0]   data_o;
+ 
+ 
+ assign rx = data_i;
+ 
+  always @(posedge clk or posedge rst)
+  begin
+    if(rst) begin
+     // cnt <= #1 {`SPI_CHAR_LEN_BITS+1{1'b0}};
+       data_o[127:0] <= 128'h00000000;
+    end
+    else begin
+    data_o <= data_i; 
+    if (latch[0] && !tip)   // mettre l'equivalent de tip dans les conditions pour empecher l'ecriture depuis wb. pendant i2cactif
+        begin
+         if(byte_sel[3])   // R0
+             data_o[31:24] <= wb_dat_in[31:24];              
+        if(byte_sel[2])
+             data_o[23:16] <= wb_dat_in[23:16];             
+        if(byte_sel[1])
+             data_o[15:8] <= wb_dat_in[15:8];                     
+         if(byte_sel[0])
+             data_o[7:0] <= wb_dat_in[7:0];                          
+      end
+     else if (latch[1]&& !tip)   // R1
+       begin
+         if(byte_sel[3])
+             data_o[63:56] <= wb_dat_in[31:24];               
+        if(byte_sel[2])
+             data_o[55:48] <= wb_dat_in[23:16];               
+        if(byte_sel[1])
+             data_o[47:40] <= wb_dat_in[15:8];                     
+         if(byte_sel[0])
+             data_o[39:32] <= wb_dat_in[7:0];                              
+       end  
+       
+     else if (latch[2]&& !tip)   // R2
+       begin
+         if(byte_sel[3])
+             data_o[95:88] <= wb_dat_in[31:24];              
+        if(byte_sel[2])
+             data_o[87:80] <= wb_dat_in[23:16];              
+        if(byte_sel[1])
+             data_o[79:72] <= wb_dat_in[15:8];                     
+         if(byte_sel[0])
+             data_o[71:64] <= wb_dat_in[7:0];                              
+       end        
+  
+     else if (latch[3]&& !tip)  //R3
+       begin
+         if(byte_sel[3])
+             data_o[127:120] <= wb_dat_in[31:24];              
+        if(byte_sel[2])
+             data_o[119:112] <= wb_dat_in[23:16];               
+        if(byte_sel[1])
+             data_o[111:104] <= wb_dat_in[15:8];                     
+         if(byte_sel[0])
+             data_o[103:96] <= wb_dat_in[7:0];                              
+       end         
+     else    // transfer i2c actif  mais en i2c read !!! lec_ec == 1
+     begin
+        if (tip && le_el  && multi_byte && Rx_1byte)    // lecture i2c
+           begin
+                if(i2c_latch == 4'hf)
+                  data_o[7:0] <= Rx_Byte_in[7:0]; 
+           else if(i2c_latch == 4'he)
+                  data_o[15:8]<= Rx_Byte_in[7:0]; 
+           else if(i2c_latch == 4'hd)
+                  data_o[23:16]<= Rx_Byte_in[7:0]; 
+           else if(i2c_latch == 4'hc)
+                  data_o[31:24]<= Rx_Byte_in[7:0];    
+           else if(i2c_latch == 4'hb)
+                  data_o[39:32]<= Rx_Byte_in[7:0];                 
+           else if(i2c_latch == 4'ha)
+                  data_o[47:40]<= Rx_Byte_in[7:0];              
+           else if(i2c_latch == 4'h9)
+                  data_o[55:48]<= Rx_Byte_in[7:0];                       
+           else if(i2c_latch == 4'h8)
+                  data_o[63:56]<= Rx_Byte_in[7:0];      
+           else if(i2c_latch == 4'h7)
+                  data_o[71:64]<= Rx_Byte_in[7:0];                 
+           else if(i2c_latch == 4'h6)
+                  data_o[79:72]<= Rx_Byte_in[7:0];
+           else if(i2c_latch == 4'h5)
+                  data_o[87:80]<= Rx_Byte_in[7:0];               
+           else if(i2c_latch == 4'h4)
+                  data_o[95:88]<= Rx_Byte_in[7:0];                                   
+           else if(i2c_latch == 4'h3)
+                  data_o[103:96]<= Rx_Byte_in[7:0];
+           else if(i2c_latch == 4'h2)
+                  data_o[111:104]<= Rx_Byte_in[7:0];               
+           else if(i2c_latch == 4'h1)
+                  data_o[119:112]<= Rx_Byte_in[7:0];                      
+           else if(i2c_latch == 4'h0)
+                  data_o[127:120]<= Rx_Byte_in[7:0];                                                    
+         end
+     end     
+     end
+  end
+  
+always @(posedge clk or posedge rst) begin
+	if(rst)
+		i2c_dat_out_o <= 8'h0;
+	else begin
+		if(i2c_latch == 4'h0)				 
+			i2c_dat_out_o <= data_i[31:24];   // ------modif 7.3.13--------------R0 
+		else if(i2c_latch == 4'h1)
+			i2c_dat_out_o <= data_i[23:16];  
+		else if(i2c_latch == 4'h2)
+			i2c_dat_out_o <= data_i[15:8];  
+		else if(i2c_latch == 4'h3)
+			i2c_dat_out_o <= data_i[7:0];	    
+		else if(i2c_latch == 4'h4)   //------------------------------R1
+			i2c_dat_out_o <= data_i[63:56];
+		else if(i2c_latch == 4'h5)
+			i2c_dat_out_o <= data_i[55:48];
+		else if(i2c_latch == 4'h6)
+			i2c_dat_out_o <= data_i[47:40];	 
+		else if(i2c_latch == 4'h7)
+			i2c_dat_out_o <= data_i[39:32]; 
+		else if(i2c_latch == 4'h8)   //------------------------------R2
+			i2c_dat_out_o <= data_i[95:88];
+		else if(i2c_latch == 4'h9)
+			i2c_dat_out_o <= data_i[87:80];
+		else if(i2c_latch == 4'ha)
+			i2c_dat_out_o <= data_i[79:72];	 
+		else if(i2c_latch == 4'hb)
+			i2c_dat_out_o <= data_i[71:64]; 
+		else if(i2c_latch == 4'hc)   //------------------------------R3
+			i2c_dat_out_o <= data_i[127:120];
+		else if(i2c_latch == 4'hd)
+			i2c_dat_out_o <= data_i[119:112];
+		else if(i2c_latch == 4'he)
+			i2c_dat_out_o <= data_i[111:104];	   
+		else if(i2c_latch == 4'hf)
+			i2c_dat_out_o <= data_i[103:96];				     
+	end
+end  
+ 
+endmodule
+ /*
+  assign rx = data_i;
+  always @(posedge clk or posedge rst)
+  begin
+    if(rst)
+       data_o[127:0] <= 128'h89;
+    else 
+    begin
+      data_o <= data_i; 
+    	if (latch[0] && !tip)   
+        begin
+         if(byte_sel[3])   
+             data_o[31:24] <= wb_dat_in[31:24];              
+         if(byte_sel[2])
+             data_o[23:16] <= wb_dat_in[23:16];             
+         if(byte_sel[1])
+             data_o[15:8] <= wb_dat_in[15:8];                     
+         if(byte_sel[0])
+             data_o[7:0] <= wb_dat_in[7:0];                          
+      end
+     else if (latch[1]&& !tip)  
+       begin
+         if(byte_sel[3])
+             data_o[63:56] <= wb_dat_in[31:24];               
+         if(byte_sel[2])
+             data_o[55:48] <= wb_dat_in[23:16];               
+         if(byte_sel[1])
+             data_o[47:40] <= wb_dat_in[15:8];                     
+         if(byte_sel[0])
+             data_o[39:32] <= wb_dat_in[7:0];                              
+       end  
+     else if (latch[2]&& !tip)   // R2
+       begin
+         if(byte_sel[3])
+             data_o[95:88] <= wb_dat_in[31:24];              
+         if(byte_sel[2])
+             data_o[87:80] <= wb_dat_in[23:16];              
+         if(byte_sel[1])
+             data_o[79:72] <= wb_dat_in[15:8];                     
+         if(byte_sel[0])
+             data_o[71:64] <= wb_dat_in[7:0];                              
+       end        
+  
+     else if (latch[3]&& !tip)  //R3
+       begin
+         if(byte_sel[3])
+             data_o[127:120] <= wb_dat_in[31:24];              
+         if(byte_sel[2])
+             data_o[119:112] <= wb_dat_in[23:16];               
+         if(byte_sel[1])
+             data_o[111:104] <= wb_dat_in[15:8];                     
+         if(byte_sel[0])
+             data_o[103:96] <= wb_dat_in[7:0];                              
+       end         
+     else    
+     begin
+        if (tip && le_el  && multi_byte && Rx_1byte)    
+           begin
+                if(i2c_latch == 4'h0)
+                  data_o[7:0] <= Rx_Byte_in[7:0]; 
+           else if(i2c_latch == 4'h1)
+                  data_o[15:8]<= Rx_Byte_in[7:0]; 
+           else if(i2c_latch == 4'h2)
+                  data_o[23:16]<= Rx_Byte_in[7:0]; 
+           else if(i2c_latch == 4'h3)
+                  data_o[31:24]<= Rx_Byte_in[7:0];    
+           else if(i2c_latch == 4'h4)
+                  data_o[39:32]<= Rx_Byte_in[7:0];                 
+           else if(i2c_latch == 4'h5)
+                  data_o[47:40]<= Rx_Byte_in[7:0];              
+           else if(i2c_latch == 4'h6)
+                  data_o[55:48]<= Rx_Byte_in[7:0];                       
+           else if(i2c_latch == 4'h7)
+                  data_o[63:56]<= Rx_Byte_in[7:0];      
+           else if(i2c_latch == 4'h8)
+                  data_o[71:64]<= Rx_Byte_in[7:0];                 
+           else if(i2c_latch == 4'h9)
+                  data_o[79:72]<= Rx_Byte_in[7:0];
+           else if(i2c_latch == 4'ha)
+                  data_o[87:80]<= Rx_Byte_in[7:0];               
+           else if(i2c_latch == 4'hb)
+                  data_o[95:88]<= Rx_Byte_in[7:0];                                   
+           else if(i2c_latch == 4'hc)
+                  data_o[103:96]<= Rx_Byte_in[7:0];
+           else if(i2c_latch == 4'hd)
+                  data_o[111:104]<= Rx_Byte_in[7:0];               
+           else if(i2c_latch == 4'he)
+                  data_o[119:112]<= Rx_Byte_in[7:0];                      
+           else if(i2c_latch == 4'hf)
+                  data_o[127:120]<= Rx_Byte_in[7:0];                                                     
+         end
+     end 
+    end     
+  end
+  
+always @(posedge clk )
+ begin
+   if(i2c_latch == 4'h0)                            
+      i2c_dat_out_o <= data_i[31:24];  
+  else if(i2c_latch == 4'h1)
+      i2c_dat_out_o <= data_i[23:16];  
+  else if(i2c_latch == 4'h2)
+      i2c_dat_out_o <= data_i[15:8];  
+  else if(i2c_latch == 4'h3)
+      i2c_dat_out_o <= data_i[7:0];           
+  else if(i2c_latch == 4'h4)   //------------------------------R1
+      i2c_dat_out_o <= data_i[63:56];
+  else if(i2c_latch == 4'h5)
+      i2c_dat_out_o <= data_i[55:48];
+  else if(i2c_latch == 4'h6)
+      i2c_dat_out_o <= data_i[47:40];      
+  else if(i2c_latch == 4'h7)
+      i2c_dat_out_o <= data_i[39:32]; 
+  else if(i2c_latch == 4'h8)   //------------------------------R2
+      i2c_dat_out_o <= data_i[95:88];
+  else if(i2c_latch == 4'h9)
+      i2c_dat_out_o <= data_i[87:80];
+  else if(i2c_latch == 4'ha)
+      i2c_dat_out_o <= data_i[79:72];      
+  else if(i2c_latch == 4'hb)
+      i2c_dat_out_o <= data_i[71:64]; 
+  else if(i2c_latch == 4'hc)   //------------------------------R3
+      i2c_dat_out_o <= data_i[127:120];
+  else if(i2c_latch == 4'hd)
+      i2c_dat_out_o <= data_i[119:112];
+  else if(i2c_latch == 4'he)
+      i2c_dat_out_o <= data_i[111:104];      
+  else if(i2c_latch == 4'hf)
+      i2c_dat_out_o <= data_i[103:96]; 
+  else 
+  	i2c_dat_out_o <= i2c_dat_out_i;                                
+ end  
+endmodule*/
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  i2c_multi_reg
+//      Library Name  :  node_ctrl
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  node_ctrl
+//  Unit    Name :  i2c_multi_reg
+//  Unit    Type :  Text Unit
+//  
+//----------------------------------------------------
+//////////////////////////////////////////
+//////////////////////////////////////////
+// Date        : Tue Nov 20 11:36:53 2012
+//
+// Author      : Ch.Paillard
+//
+// Company     : CERN
+//
+// Description : registre 128 bit pour multi byte transfert i2c
+//
+//////////////////////////////////////////
+//////////////////////////////////////////
+
+module i2c_multi_reg_tri(clk_1, clk_2, clk_3,rst_1, rst_2, rst_3,wb_dat_in_1, wb_dat_in_2, wb_dat_in_3,i2c_dat_out_1, i2c_dat_out_2, i2c_dat_out_3,latch_1, latch_2, latch_3,i2c_latch_1, i2c_latch_2, i2c_latch_3,
+                     Rx_1byte_1, Rx_1byte_2, Rx_1byte_3,rx_1, rx_2, rx_3,byte_sel_1, byte_sel_2, byte_sel_3,tip_1, tip_2, tip_3,le_el_1, le_el_2, le_el_3,multi_byte_1, multi_byte_2, multi_byte_3,Rx_Byte_in_1, Rx_Byte_in_2, Rx_Byte_in_3);
+
+ input clk_1, clk_2, clk_3;
+ input rst_1, rst_2, rst_3;
+ input [3:0] latch_1, latch_2, latch_3;         
+ output [127:0]  rx_1, rx_2, rx_3;
+ input [3:0]  byte_sel_1, byte_sel_2, byte_sel_3;     
+ input tip_1, tip_2, tip_3;                 
+ input le_el_1, le_el_2, le_el_3;               
+ input multi_byte_1, multi_byte_2, multi_byte_3;          
+ input Rx_1byte_1, Rx_1byte_2, Rx_1byte_3;            
+ input  [31:0]   wb_dat_in_1, wb_dat_in_2, wb_dat_in_3;  
+ input  [3:0]    i2c_latch_1, i2c_latch_2, i2c_latch_3;  
+ input  [7:0]    Rx_Byte_in_1, Rx_Byte_in_2, Rx_Byte_in_3;  
+ output [7:0]    i2c_dat_out_1, i2c_dat_out_2, i2c_dat_out_3; 
+
+	wire [127:0] data_1, data_2, data_3;
+	wire [7:0] i2c_dat_out_1, i2c_dat_out_2, i2c_dat_out_3;
+	wire [127:0] data;
+	wire [7:0] i2c_dat_out;
+
+	i2c_multi_reg_iostate i2c_multi_reg_iostate_1  (.clk(clk_1),.rst(rst_1),.wb_dat_in(wb_dat_in_1),.i2c_dat_out_i(i2c_dat_out_1), .i2c_dat_out_o(i2c_dat_out_2),.latch(latch_1),.i2c_latch(i2c_latch_1),
+                     .Rx_1byte(Rx_1byte_1),.rx(rx_1),.byte_sel(byte_sel_1),.tip(tip_1),.le_el(le_el_1),.multi_byte(multi_byte_1),.Rx_Byte_in(Rx_Byte_in_1), .data_i(data_1), .data_o(data_2));
+
+	i2c_multi_reg_iostate i2c_multi_reg_iostate_2  (.clk(clk_2),.rst(rst_2),.wb_dat_in(wb_dat_in_2),.i2c_dat_out_i(i2c_dat_out_2), .i2c_dat_out_o(i2c_dat_out_3),.latch(latch_2),.i2c_latch(i2c_latch_2),
+                     .Rx_1byte(Rx_1byte_2),.rx(rx_2),.byte_sel(byte_sel_2),.tip(tip_2),.le_el(le_el_2),.multi_byte(multi_byte_2),.Rx_Byte_in(Rx_Byte_in_2), .data_i(data_2), .data_o(data_3));
+
+	i2c_multi_reg_iostate i2c_multi_reg_iostate_3  (.clk(clk_3),.rst(rst_3),.wb_dat_in(wb_dat_in_3),.i2c_dat_out_i(i2c_dat_out_3), .i2c_dat_out_o(i2c_dat_out),.latch(latch_3),.i2c_latch(i2c_latch_3),
+                     .Rx_1byte(Rx_1byte_3),.rx(rx_3),.byte_sel(byte_sel_3),.tip(tip_3),.le_el(le_el_3),.multi_byte(multi_byte_3),.Rx_Byte_in(Rx_Byte_in_3), .data_i(data_3), .data_o(data));
+
+	majority_voter #(.WIDTH(136)) mv (
+		.in1({data_2, i2c_dat_out_2}),
+		.in2({data_3, i2c_dat_out_3}),
+		.in3({data, i2c_dat_out}),
+		.out({data_1, i2c_dat_out_1}),
+		.err()
+	);
+endmodule
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  wb_adapt_i2c
+//      Library Name  :  node_ctrl
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         IF for state selection         :  No
+//         Error (default) state          :  Yes
+//         String typed state variable    :  No
+//         Next state assignments         :  Non blocking
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  node_ctrl
+//  Unit    Name :  wb_adapt_i2c
+//  Unit    Type :  State Machine
+//  
+//----------------------------------------------------
+ 
+
+module wb_adapt_i2c_iostate (clk, rst, Start_tr_i, Start_tr_o, wb_ack, reponse_n, read_nc_i, read_nc_o, wb_we,
+                     wb_addr
+                     , visual_wb2ccu_nc_iddle_current_i, visual_wb2ccu_nc_iddle_current_o);
+ 
+   parameter wb2ccu_nc_iddle = 3'b000,
+            ReadNc          = 3'b001,
+            Reponse_i2c     = 3'b010,
+            S14             = 3'b011,
+            out_crc_ok      = 3'b100;
+            
+  input clk;
+  input [2:0] visual_wb2ccu_nc_iddle_current_i;
+ 
+  input wb_we;
+  input [4:0] wb_addr;
+  wire clk;
+  input rst;
+  wire rst;
+  output Start_tr_o;
+	output [2:0] visual_wb2ccu_nc_iddle_current_o;
+	output read_nc_o;
+	input read_nc_i;
+  input Start_tr_i;
+  reg Start_tr_o;
+  input wb_ack;            
+  wire wb_ack;
+  input reponse_n;  
+  wire reponse_n;
+  reg read_nc_o;
+  wire wb_we;
+  wire [4:0] wb_addr;
+ 
+ 
+  reg [2:0] visual_wb2ccu_nc_iddle_current_o;
+  
+always  @(posedge clk or posedge rst)
+  begin : wb_adapt_i2c_wb2ccu_nc_iddle
+    if (rst === 1'b1)
+    begin
+      Start_tr_o <= 1'b1;
+      read_nc_o <= 1'b0;
+      visual_wb2ccu_nc_iddle_current_o <= wb2ccu_nc_iddle;
+    end
+    else
+    begin
+ 	Start_tr_o <= Start_tr_i;
+      read_nc_o <= read_nc_i;
+      visual_wb2ccu_nc_iddle_current_o <= visual_wb2ccu_nc_iddle_current_i;
+      
+      case (visual_wb2ccu_nc_iddle_current_i)
+        wb2ccu_nc_iddle:
+          begin
+          	read_nc_o <= 1'b0;//new
+            if ((wb_ack == 1'b0) && (reponse_n == 1'b1) && (wb_addr != 5'h0))
+            begin
+              visual_wb2ccu_nc_iddle_current_o <= wb2ccu_nc_iddle;
+            end
+            else if (reponse_n == 1'b0)
+            begin
+              visual_wb2ccu_nc_iddle_current_o <= Reponse_i2c;
+            end
+            else if ((wb_ack == 1'b1) && (reponse_n == 1'b1) && (wb_we == 1'b1)
+                     && (wb_addr == 5'h0))
+            begin
+              Start_tr_o <= 1'b0; 
+              visual_wb2ccu_nc_iddle_current_o <= out_crc_ok;
+            end
+            else
+              visual_wb2ccu_nc_iddle_current_o <= wb2ccu_nc_iddle;
+          end
+ 
+        ReadNc:
+          begin
+            Start_tr_o <= 1'b1;
+            read_nc_o <= 1'b0;
+            visual_wb2ccu_nc_iddle_current_o <= wb2ccu_nc_iddle;
+          end
+ 
+        Reponse_i2c:
+          begin
+            read_nc_o <= 1'b1;  // lecture du resultat
+            visual_wb2ccu_nc_iddle_current_o <= ReadNc;
+          end
+ 
+        S14:
+          begin
+            Start_tr_o <= 1'b1;
+            read_nc_o <= 1'b0;
+            visual_wb2ccu_nc_iddle_current_o <= wb2ccu_nc_iddle;
+          end
+ 
+        out_crc_ok:
+          begin
+          	Start_tr_o <= 1'b0; //new
+            visual_wb2ccu_nc_iddle_current_o <= S14;
+          end
+ 
+        default:
+          begin
+            Start_tr_o <= 1'b1;
+            read_nc_o <= 1'b0;
+            visual_wb2ccu_nc_iddle_current_o <= wb2ccu_nc_iddle;
+          end
+      endcase
+    end
+  end
+ 
+ 
+ 
+endmodule
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  wb_adapt_i2c
+//      Library Name  :  node_ctrl
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         IF for state selection         :  No
+//         Error (default_1, default_2, default_3) state          :  Yes
+//         String typed state variable    :  No
+//         Next state assignments         :  Non blocking
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  node_ctrl
+//  Unit    Name :  wb_adapt_i2c
+//  Unit    Type :  State Machine
+//  
+//----------------------------------------------------
+
+
+module wb_adapt_i2c_tri (clk_1, clk_2, clk_3, rst_1, rst_2, rst_3, Start_tr_1, Start_tr_2, Start_tr_3, wb_ack_1, wb_ack_2, wb_ack_3, reponse_n_1, reponse_n_2, reponse_n_3, read_nc_1, read_nc_2, read_nc_3, wb_we_1, wb_we_2, wb_we_3,
+                     wb_addr_1, wb_addr_2, wb_addr_3
+                     );
+
+   parameter wb2ccu_nc_iddle = 3'b000,
+            ReadNc          = 3'b001,
+            Reponse_i2c     = 3'b010,
+            S14             = 3'b011,
+            out_crc_ok      = 3'b100;
+
+  input clk_1, clk_2, clk_3;
+  input rst_1, rst_2, rst_3;
+  output Start_tr_1, Start_tr_2, Start_tr_3;
+  input wb_ack_1, wb_ack_2, wb_ack_3;            
+  input reponse_n_1, reponse_n_2, reponse_n_3;  
+  output read_nc_1, read_nc_2, read_nc_3;
+  input wb_we_1, wb_we_2, wb_we_3;
+  input [4:0] wb_addr_1, wb_addr_2, wb_addr_3;
+
+	wire Start_tr_1, Start_tr_2, Start_tr_3;
+	wire read_nc_1, read_nc_2, read_nc_3;
+	wire [2:0] visual_wb2ccu_nc_iddle_current_1, visual_wb2ccu_nc_iddle_current_2, visual_wb2ccu_nc_iddle_current_3;
+	wire Start_tr;
+	wire read_nc;
+	wire [2:0] visual_wb2ccu_nc_iddle_current;
+
+	wb_adapt_i2c_iostate  wb_adapt_i2c_iostate_1 (.clk(clk_1), .rst(rst_1), .Start_tr_i(Start_tr_1), .Start_tr_o(Start_tr_2), .wb_ack(wb_ack_1), .reponse_n(reponse_n_1), .read_nc_i(read_nc_1), .read_nc_o(read_nc_2), .wb_we(wb_we_1), .wb_addr(wb_addr_1), .visual_wb2ccu_nc_iddle_current_i(visual_wb2ccu_nc_iddle_current_1), .visual_wb2ccu_nc_iddle_current_o(visual_wb2ccu_nc_iddle_current_2));
+	wb_adapt_i2c_iostate  wb_adapt_i2c_iostate_2 (.clk(clk_2), .rst(rst_2), .Start_tr_i(Start_tr_2), .Start_tr_o(Start_tr_3), .wb_ack(wb_ack_2), .reponse_n(reponse_n_2), .read_nc_i(read_nc_2), .read_nc_o(read_nc_3), .wb_we(wb_we_2), .wb_addr(wb_addr_2), .visual_wb2ccu_nc_iddle_current_i(visual_wb2ccu_nc_iddle_current_2), .visual_wb2ccu_nc_iddle_current_o(visual_wb2ccu_nc_iddle_current_3));
+	wb_adapt_i2c_iostate  wb_adapt_i2c_iostate_3 (.clk(clk_3), .rst(rst_3), .Start_tr_i(Start_tr_3), .Start_tr_o(Start_tr),   .wb_ack(wb_ack_3), .reponse_n(reponse_n_3), .read_nc_i(read_nc_3), .read_nc_o(read_nc),   .wb_we(wb_we_3), .wb_addr(wb_addr_3), .visual_wb2ccu_nc_iddle_current_i(visual_wb2ccu_nc_iddle_current_3), .visual_wb2ccu_nc_iddle_current_o(visual_wb2ccu_nc_iddle_current));
+
+	majority_voter #(.WIDTH(5)) mv (
+		.in1({Start_tr_2, read_nc_2, visual_wb2ccu_nc_iddle_current_2}),
+		.in2({Start_tr_3, read_nc_3, visual_wb2ccu_nc_iddle_current_3}),
+		.in3({Start_tr,   read_nc,   visual_wb2ccu_nc_iddle_current}),
+		.out({Start_tr_1, read_nc_1, visual_wb2ccu_nc_iddle_current_1}),
+		.err()
+	);
+endmodule
+
+
+// missing: i2c_msk_reg_o <=#1 i2c_msk_reg_i;
+// missing: i2c_ctrl_reg_o <=#1 i2c_ctrl_reg_i;
+// missing: registre0_o <=#1 registre0_i;
+// missing: wb_ack_out_o <=#1 wb_ack_out_i;
+// missing: wb_dat_out_o <=#1 wb_dat_out_i;
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  wb_generic
+//      Library Name  :  node_ctrl
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  node_ctrl
+//  Unit    Name :  wb_generic
+//  Unit    Type :  Text Unit
+//  
+//----------------------------------------------------
+//////////////////////////////////////////
+//////////////////////////////////////////
+// Date        : Mon Oct 15 14:43:06 2012
+//
+// Author      : 
+//
+// Company     : 
+//
+// Description : 
+//
+
+//////////////////////////////////////////
+//////////////////////////////////////////                                                            
+////  wb_generic.v
+//---------------dans define                                                   
+`define REG_LEN 32   // nombre de bit des registres
+`define SPI_OFS_BITS	          4:2
+`define GENERIC_R0   0    // data byte 2 byte 3 byte 4 byte 5   du ccu-i2c
+`define STATUS_REG   1   // pour status i2c assoc. avec status_i2c
+`define I2C_MSK      2
+`define I2C_CTRL     3    // assoc avec i2c_ctrl_reg
+`define DATA_REG0     4      // byte 3:0 long registre pour les data des transfert multiple 
+`define DATA_REG1     5      // byte 7:4
+`define DATA_REG2     6      // byte 12:8
+`define DATA_REG3     7      // byte 15:12
+
+`define GENERIC_R0_LEN 32
+`define GENERIC_R1_LEN 32
+`define GENERIC_R2_LEN 32
+`define I2C_CTRL_GO  8   // bit[8] pour demarrer cycle du i2c ccu
+
+
+
+
+module wb_generic_iostate (
+  wb_clk_in, wb_rst_in, wb_adr_in, wb_dat_in, wb_dat_out_i, wb_dat_out_o, wb_sel_in,
+  wb_we_in, wb_stb_in, wb_cyc_in, wb_ack_out_i, wb_ack_out_o, wb_err_out, wb_int_out_i, wb_int_out_o,
+  registre0_i, registre0_o,i2c_msk_reg_i, i2c_msk_reg_o,tip,last_bit,status_i2c,i2c_ctrl_reg_i, i2c_ctrl_reg_o,
+  rx_byte_in,data_reg_sel,rx
+
+);
+
+  parameter Tp = 1;
+
+  input                            wb_clk_in;         
+  input                            wb_int_out_i;         
+  input                  [128-1:0] rx;               
+  input                            tip;              
+  input                            last_bit;             
+  input                      [7:0] status_i2c;                                           
+  input                      [7:0] rx_byte_in;      
+  input                            wb_rst_in;         
+  input                      [4:0] wb_adr_in;         
+  input                   [32-1:0] wb_dat_in;         
+  output                  [32-1:0] wb_dat_out_o;
+  output                           wb_err_out;         
+  output                           wb_int_out_o;
+  output                    [31:0] i2c_ctrl_reg_o;
+  input                     [31:0] i2c_ctrl_reg_i; 
+  output                     [3:0] data_reg_sel;     
+  output            [`REG_LEN-1:0] registre0_o;
+  input             [`REG_LEN-1:0] registre0_i;             
+  output            [`REG_LEN-1:0] i2c_msk_reg_o;
+  input             [`REG_LEN-1:0] i2c_msk_reg_i;         
+  input                   [32-1:0] wb_dat_out_i;         
+  input                      [3:0] wb_sel_in;         
+  input                            wb_we_in;          
+  input                            wb_stb_in;         
+  input                            wb_cyc_in;         
+  output                           wb_ack_out_o;
+  input                            wb_ack_out_i;         
+  reg                       [31:0] i2c_ctrl_reg_o;                                                   
+  reg                     [32-1:0] wb_dat_out_o;
+  reg                              wb_ack_out_o;
+  reg                              wb_int_out_o;                                       
+  reg               [`REG_LEN-1:0] registre0_o;               
+  reg               [`REG_LEN-1:0] i2c_msk_reg_o;            
+  reg                     [32-1:0] wb_datM;           
+  wire                             registre0_sel; 
+  wire                             i2c_ctrl_sel;   
+  wire                             i2c_msk_sel;   
+  wire                     [3:0]   data_reg_sel;  
+ 
+    
+  
+  assign registre0_sel   = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `GENERIC_R0);
+  assign i2c_ctrl_sel    = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `I2C_CTRL); 
+  assign i2c_msk_sel     = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `I2C_MSK);
+  assign data_reg_sel[0] = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `DATA_REG0); 
+  assign data_reg_sel[1] = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `DATA_REG1); 
+  assign data_reg_sel[2] = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `DATA_REG2); 
+  assign data_reg_sel[3] = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `DATA_REG3);  
+  
+    
+ 
+  always @(wb_adr_in or registre0_i  or status_i2c or i2c_msk_reg_i or i2c_ctrl_reg_i or rx or rx_byte_in ) 
+  begin
+    case (wb_adr_in[`SPI_OFS_BITS])
+      `DATA_REG0:    wb_datM = rx[31:0];  
+      `DATA_REG1:    wb_datM = rx[63:32];
+      `DATA_REG2:    wb_datM = rx[95:64];
+      `DATA_REG3:    wb_datM = rx[127:96];
+      `STATUS_REG:   begin
+                       wb_datM[31:24] = status_i2c[7:0];    
+                       wb_datM[23:16] = rx_byte_in[7:0];  
+                       wb_datM[15:0] = 16'hbb;
+                    end
+      `GENERIC_R0:    wb_datM = {{32-`GENERIC_R0_LEN{1'b0}}, registre0_i};
+      `I2C_CTRL:     wb_datM =  i2c_ctrl_reg_i;
+      `I2C_MSK:      wb_datM =   i2c_msk_reg_i;
+      
+      default:      wb_datM = 128'h0;
+    endcase
+  end
+  
+
+  always @(posedge wb_clk_in or posedge wb_rst_in)
+  begin 
+    if (wb_rst_in)
+      wb_dat_out_o <= #1 32'b0;
+    else
+      wb_dat_out_o <= #1 wb_datM;
+  end
+  
+
+  always @(posedge wb_clk_in or posedge wb_rst_in)
+  begin
+    if (wb_rst_in)
+      wb_ack_out_o <= #1 1'b0;
+    else
+      wb_ack_out_o <= #1 wb_cyc_in & wb_stb_in & ~wb_ack_out_i;
+  end
+  
+
+  assign wb_err_out = 1'b0;
+  
+
+  always @(posedge wb_clk_in or posedge wb_rst_in)
+  begin
+    if (wb_rst_in)
+      wb_int_out_o <= #1 1'b0;      // reset de l'interrupt
+    else if (tip && last_bit  )
+      wb_int_out_o <= #1 1'b1;      // interrupt actif
+    else if (wb_ack_out_i)
+      wb_int_out_o <=  1'b0;   
+    else
+    	wb_int_out_o <= wb_int_out_i;
+  end
+  
+
+  always @(posedge wb_clk_in or posedge wb_rst_in)
+  begin
+    if (wb_rst_in)
+     begin
+       registre0_o <= #1 {32{1'b0}}; 
+       i2c_ctrl_reg_o <= #1 32'h8;   
+       i2c_msk_reg_o <= #1 {32{1'b0}}; 
+      end
+    else begin
+    	registre0_o <= #1 registre0_i;
+    	i2c_ctrl_reg_o <= #1 i2c_ctrl_reg_i;   
+      i2c_msk_reg_o <= #1 i2c_msk_reg_i; 
+    	if (registre0_sel && wb_we_in && !tip)
+      begin
+        if (wb_sel_in[0])
+          registre0_o[7:0]  <= #1 wb_dat_in[7:0];
+        if (wb_sel_in[1])
+          registre0_o[15:8] <= #1 wb_dat_in[15:8];
+        if (wb_sel_in[2])
+          registre0_o[23:16] <= #1 wb_dat_in[23:16];
+        if (wb_sel_in[3])
+          registre0_o[31:24] <= #1 wb_dat_in[ 31:24];
+      end           
+    	else if (i2c_msk_sel && wb_we_in && !tip)
+      begin
+        if (wb_sel_in[0])
+          begin
+          i2c_msk_reg_o[7:0]   <= #1 wb_dat_in[7:0];
+          end 
+        if (wb_sel_in[1])
+          i2c_msk_reg_o[15:8] <= #1 wb_dat_in[15:8];
+        if (wb_sel_in[2])
+          i2c_msk_reg_o[23:16] <= #1 wb_dat_in[23:16];
+        if (wb_sel_in[3])
+          i2c_msk_reg_o[31:24] <= #1 wb_dat_in[ 31:24];
+      end
+    	else if (i2c_ctrl_sel && wb_we_in && !tip)
+      begin
+        if (wb_sel_in[0])
+          i2c_ctrl_reg_o[7:0]  <= #1 wb_dat_in[7:0];
+        if (wb_sel_in[1])
+          i2c_ctrl_reg_o[15:8] <= #1 wb_dat_in[15:8];
+        if (wb_sel_in[2])
+          i2c_ctrl_reg_o[23:16] <= #1 wb_dat_in[23:16];
+        if (wb_sel_in[3])
+          i2c_ctrl_reg_o[31:24] <= #1 wb_dat_in[ 31:24];
+      end
+     end           
+  end  
+  
+  
+endmodule
+  
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  wb_generic
+//      Library Name  :  node_ctrl
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  node_ctrl
+//  Unit    Name :  wb_generic
+//  Unit    Type :  Text Unit
+//  
+//----------------------------------------------------
+//////////////////////////////////////////
+//////////////////////////////////////////
+// Date        : Mon Oct 15 14:43:06 2012
+//
+// Author      : 
+//
+// Company     : 
+//
+// Description : 
+//
+
+module wb_generic_tri
+(
+  wb_clk_in_1, wb_clk_in_2, wb_clk_in_3, wb_rst_in_1, wb_rst_in_2, wb_rst_in_3, wb_adr_in_1, wb_adr_in_2, wb_adr_in_3, wb_dat_in_1, wb_dat_in_2, wb_dat_in_3, wb_dat_out_1, wb_dat_out_2, wb_dat_out_3, wb_sel_in_1, wb_sel_in_2, wb_sel_in_3,
+  wb_we_in_1, wb_we_in_2, wb_we_in_3, wb_stb_in_1, wb_stb_in_2, wb_stb_in_3, wb_cyc_in_1, wb_cyc_in_2, wb_cyc_in_3, wb_ack_out_1, wb_ack_out_2, wb_ack_out_3, wb_err_out_1, wb_err_out_2, wb_err_out_3, wb_int_out_1, wb_int_out_2, wb_int_out_3,
+  registre0_1, registre0_2, registre0_3,i2c_msk_reg_1, i2c_msk_reg_2, i2c_msk_reg_3,tip_1, tip_2, tip_3,last_bit_1, last_bit_2, last_bit_3,status_i2c_1, status_i2c_2, status_i2c_3,i2c_ctrl_reg_1, i2c_ctrl_reg_2, i2c_ctrl_reg_3,
+  rx_byte_in_1, rx_byte_in_2, rx_byte_in_3,data_reg_sel_1, data_reg_sel_2, data_reg_sel_3,rx_1, rx_2, rx_3
+
+);
+
+  parameter Tp = 1;
+
+  // Wishbone signals
+  input                            wb_clk_in_1, wb_clk_in_2, wb_clk_in_3;         
+  input                            wb_rst_in_1, wb_rst_in_2, wb_rst_in_3;         
+  input                      [4:0] wb_adr_in_1, wb_adr_in_2, wb_adr_in_3;         
+  input                   [32-1:0] wb_dat_in_1, wb_dat_in_2, wb_dat_in_3;         
+  output                  [32-1:0] wb_dat_out_1, wb_dat_out_2, wb_dat_out_3;         
+  input                      [3:0] wb_sel_in_1, wb_sel_in_2, wb_sel_in_3;         
+  input                            wb_we_in_1, wb_we_in_2, wb_we_in_3;          
+  input                            wb_stb_in_1, wb_stb_in_2, wb_stb_in_3;         
+  input                            wb_cyc_in_1, wb_cyc_in_2, wb_cyc_in_3;         
+  output                           wb_ack_out_1, wb_ack_out_2, wb_ack_out_3;         
+  output                           wb_err_out_1, wb_err_out_2, wb_err_out_3;         
+  output                           wb_int_out_1, wb_int_out_2, wb_int_out_3;         
+  output                    [31:0] i2c_ctrl_reg_1, i2c_ctrl_reg_2, i2c_ctrl_reg_3; 
+  output                     [3:0] data_reg_sel_1, data_reg_sel_2, data_reg_sel_3;     
+  input                  [128-1:0] rx_1, rx_2, rx_3;               
+  input                            tip_1, tip_2, tip_3;              
+  input                            last_bit_1, last_bit_2, last_bit_3;             
+  input [7:0]                      status_i2c_1, status_i2c_2, status_i2c_3;                                           
+  input [7:0]                      rx_byte_in_1, rx_byte_in_2, rx_byte_in_3;      
+  output       [`REG_LEN-1:0]   registre0_1, registre0_2, registre0_3;             
+  output       [`REG_LEN-1:0]   i2c_msk_reg_1, i2c_msk_reg_2, i2c_msk_reg_3;         
+
+	wire [32-1:0] wb_dat_out_1, wb_dat_out_2, wb_dat_out_3;
+	wire wb_ack_out_1, wb_ack_out_2, wb_ack_out_3;
+	wire wb_int_out_1, wb_int_out_2, wb_int_out_3;
+	wire [`REG_LEN-1:0] registre0_1, registre0_2, registre0_3;
+	wire [31:0] i2c_ctrl_reg_1, i2c_ctrl_reg_2, i2c_ctrl_reg_3;
+	wire [`REG_LEN-1:0] i2c_msk_reg_1, i2c_msk_reg_2, i2c_msk_reg_3;
+	wire [32-1:0] wb_dat_out;
+	wire wb_ack_out;
+	wire wb_int_out;
+	wire [`REG_LEN-1:0] registre0;
+	wire [31:0] i2c_ctrl_reg;
+	wire [`REG_LEN-1:0] i2c_msk_reg;
+
+	wb_generic_iostate #(.Tp(Tp) ) wb_generic_iostate_1 (
+  .wb_clk_in(wb_clk_in_1), .wb_rst_in(wb_rst_in_1), .wb_adr_in(wb_adr_in_1), .wb_dat_in(wb_dat_in_1), .wb_dat_out_i(wb_dat_out_1), .wb_dat_out_o(wb_dat_out_2), .wb_sel_in(wb_sel_in_1),
+  .wb_we_in(wb_we_in_1), .wb_stb_in(wb_stb_in_1), .wb_cyc_in(wb_cyc_in_1), .wb_ack_out_i(wb_ack_out_1), .wb_ack_out_o(wb_ack_out_2), .wb_err_out(wb_err_out_1), .wb_int_out_i(wb_int_out_1), .wb_int_out_o(wb_int_out_2),
+  .registre0_i(registre0_1), .registre0_o(registre0_2),.i2c_msk_reg_i(i2c_msk_reg_1), .i2c_msk_reg_o(i2c_msk_reg_2),.tip(tip_1),.last_bit(last_bit_1),.status_i2c(status_i2c_1),.i2c_ctrl_reg_i(i2c_ctrl_reg_1), .i2c_ctrl_reg_o(i2c_ctrl_reg_2),
+  .rx_byte_in(rx_byte_in_1),.data_reg_sel(data_reg_sel_1),.rx(rx_1));
+
+	wb_generic_iostate #(.Tp(Tp) ) wb_generic_iostate_2 (
+  .wb_clk_in(wb_clk_in_2), .wb_rst_in(wb_rst_in_2), .wb_adr_in(wb_adr_in_2), .wb_dat_in(wb_dat_in_2), .wb_dat_out_i(wb_dat_out_2), .wb_dat_out_o(wb_dat_out_3), .wb_sel_in(wb_sel_in_2),
+  .wb_we_in(wb_we_in_2), .wb_stb_in(wb_stb_in_2), .wb_cyc_in(wb_cyc_in_2), .wb_ack_out_i(wb_ack_out_2), .wb_ack_out_o(wb_ack_out_3), .wb_err_out(wb_err_out_2), .wb_int_out_i(wb_int_out_2), .wb_int_out_o(wb_int_out_3),
+  .registre0_i(registre0_2), .registre0_o(registre0_3),.i2c_msk_reg_i(i2c_msk_reg_2), .i2c_msk_reg_o(i2c_msk_reg_3),.tip(tip_2),.last_bit(last_bit_2),.status_i2c(status_i2c_2),.i2c_ctrl_reg_i(i2c_ctrl_reg_2), .i2c_ctrl_reg_o(i2c_ctrl_reg_3),
+  .rx_byte_in(rx_byte_in_2),.data_reg_sel(data_reg_sel_2),.rx(rx_2));
+
+	wb_generic_iostate #(.Tp(Tp) ) wb_generic_iostate_3 (
+  .wb_clk_in(wb_clk_in_3), .wb_rst_in(wb_rst_in_3), .wb_adr_in(wb_adr_in_3), .wb_dat_in(wb_dat_in_3), .wb_dat_out_i(wb_dat_out_3), .wb_dat_out_o(wb_dat_out), .wb_sel_in(wb_sel_in_3),
+  .wb_we_in(wb_we_in_3), .wb_stb_in(wb_stb_in_3), .wb_cyc_in(wb_cyc_in_3), .wb_ack_out_i(wb_ack_out_3), .wb_ack_out_o(wb_ack_out), .wb_err_out(wb_err_out_3), .wb_int_out_i(wb_int_out_3), .wb_int_out_o(wb_int_out),
+  .registre0_i(registre0_3), .registre0_o(registre0),.i2c_msk_reg_i(i2c_msk_reg_3), .i2c_msk_reg_o(i2c_msk_reg),.tip(tip_3),.last_bit(last_bit_3),.status_i2c(status_i2c_3),.i2c_ctrl_reg_i(i2c_ctrl_reg_3), .i2c_ctrl_reg_o(i2c_ctrl_reg),
+  .rx_byte_in(rx_byte_in_3),.data_reg_sel(data_reg_sel_3),.rx(rx_3));
+
+	majority_voter #(.WIDTH(37+32-1+`REG_LEN-1+`REG_LEN-1)) mv (
+		.in1({wb_dat_out_2, wb_ack_out_2, wb_int_out_2, registre0_2, i2c_ctrl_reg_2, i2c_msk_reg_2}),
+		.in2({wb_dat_out_3, wb_ack_out_3, wb_int_out_3, registre0_3, i2c_ctrl_reg_3, i2c_msk_reg_3}),
+		.in3({wb_dat_out, wb_ack_out, wb_int_out, registre0, i2c_ctrl_reg, i2c_msk_reg}),
+		.out({wb_dat_out_1, wb_ack_out_1, wb_int_out_1, registre0_1, i2c_ctrl_reg_1, i2c_msk_reg_1}),
+		.err()
+	);
+endmodule
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  i2c_blk
+//      Library Name  :  new_i2c_2
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  new_i2c_2
+//  Unit    Name :  i2c_blk
+//  Unit    Type :  Block Diagram
+//  
+//----------------------------------------------------
+ 
+ 
+
+module i2c_blk_tri 
+
+ (
+input  clk_1,
+input  clk_2,
+input  clk_3,
+output  scl_1,
+output  scl_2,
+output  scl_3,
+output  sda_out_1,
+output  sda_out_2,
+output  sda_out_3,
+output  reponse_1,
+output  reponse_2,
+output  reponse_3,
+input  read_nc_1,
+input  read_nc_2,
+input  read_nc_3,
+output  busy_1,
+output  busy_2,
+output  busy_3,
+input  sda_in_1,
+input  sda_in_2,
+input  sda_in_3,
+input  i2c_br_1,
+input  i2c_br_2,
+input  i2c_br_3,
+input  reset_1,
+input  reset_2,
+input  reset_3,
+output [7:0]  SRA_out_1,
+output [7:0]  SRA_out_2,
+output [7:0]  SRA_out_3,
+output  MultiByte_1,
+output  MultiByte_2,
+output  MultiByte_3,
+output  rx_1byte_1,
+output  rx_1byte_2,
+output  rx_1byte_3,
+input [7:0]  msk_1,
+input [7:0]  msk_2,
+input [7:0]  msk_3,
+output [3:0]  blktr_idx_1,   
+output [3:0]  blktr_idx_2,   
+output [3:0]  blktr_idx_3,   
+input  Start_tr_n_1,   
+input  Start_tr_n_2,   
+input  Start_tr_n_3,   
+output  le_ec_1,
+output  le_ec_2,
+output  le_ec_3,
+output [7:0]  Rx_Byte_o_1,
+output [7:0]  Rx_Byte_o_2,
+output [7:0]  Rx_Byte_o_3,
+input [7:0]  multi_byte_in_1,
+input [7:0]  multi_byte_in_2,
+input [7:0]  multi_byte_in_3,
+input [6:0]  cra_1,
+input [6:0]  cra_2,
+input [6:0]  cra_3,
+input [7:0]  byte_out_cmd_1,
+input [7:0]  byte_out_cmd_2,
+input [7:0]  byte_out_cmd_3,
+input [7:0]  byte_out3_1,  
+input [7:0]  byte_out3_2,  
+input [7:0]  byte_out3_3,  
+input [7:0]  byte_out4_1,    
+input [7:0]  byte_out4_2,    
+input [7:0]  byte_out4_3,    
+input [7:0]  byte_out5_1,     
+input [7:0]  byte_out5_2,     
+input [7:0]  byte_out5_3     
+);
+
+
+wire  sti2c_out_1;
+wire  sti2c_out_2;
+wire  sti2c_out_3;
+wire  ext_mode_1;
+wire  ext_mode_2;
+wire  ext_mode_3;
+wire  start_i2c_1;
+wire  start_i2c_2;
+wire  start_i2c_3;
+wire [4:0]  nbyte_1;
+wire [4:0]  nbyte_2;
+wire [4:0]  nbyte_3;
+wire [1:0]  msk_op_1;
+wire [1:0]  msk_op_2;
+wire [1:0]  msk_op_3;
+wire  stop_cond_1;
+wire  stop_cond_2;
+wire  stop_cond_3;
+wire  ext_multi_mode_1;
+wire  ext_multi_mode_2;
+wire  ext_multi_mode_3;
+wire  sda_gnd_1;
+wire  sda_gnd_2;
+wire  sda_gnd_3;
+wire [7:0]  data_outY_1;
+wire [7:0]  data_outY_2;
+wire [7:0]  data_outY_3;
+wire  rw_b_ext_1;
+wire  rw_b_ext_2;
+wire  rw_b_ext_3;
+wire  ack_ok_1;
+wire  ack_ok_2;
+wire  ack_ok_3;
+wire  busy_i2c_1;
+wire  busy_i2c_2;
+wire  busy_i2c_3;
+wire  hor_1;
+wire  hor_2;
+wire  hor_3;
+wire [7:0]  out_i2c_1;
+wire [7:0]  out_i2c_2;
+wire [7:0]  out_i2c_3;
+
+
+
+
+div_prog_sm_tri  CLK_DIV (
+     .clk_1(clk_1),
+     .clk_out_1(hor_1),
+     .reset_1(reset_1),
+     .div_1(cra_1[1:0]),
+		.clk_2(clk_2),
+     .clk_out_2(hor_2),
+     .reset_2(reset_2),
+     .div_2(cra_2[1:0]),
+		.clk_3(clk_3),
+     .clk_out_3(hor_3),
+     .reset_3(reset_3),
+     .div_3(cra_3[1:0])
+	);
+
+
+master_cmd_sm_tri  Exec_cmd (
+     .clock2_1(hor_1),
+     .cmd_1(out_i2c_1[7:0]),
+     .rx_byte_o_1(Rx_Byte_o_1[7:0]),
+     .busy_1(busy_i2c_1),
+     .sda_1(sda_out_1),
+     .scl_1(scl_1),
+     .sda_bi_1(sda_in_1),
+     .reset_1(reset_1),
+     .start_i2c_1(sti2c_out_1),
+     .ack_ok_1(ack_ok_1),
+     .data_in_1(data_outY_1[7:0]),
+     .data_in2_1(byte_out5_1[7:0]),
+     .nbyte_1(nbyte_1[4:0]),
+     .sda_gnd_1(sda_gnd_1),
+     .ext_mode_1(ext_mode_1),
+     .MultiByte_1(MultiByte_1),
+     .multi_byte_in_1(multi_byte_in_1[7:0]),
+     .le_ec_1(le_ec_1),
+     .rx_1byte_1(rx_1byte_1),
+     .ext_multi_mode_1(ext_multi_mode_1),
+     .rw_b_ext_1(rw_b_ext_1),
+     .stop_cond_1(stop_cond_1),
+     .blktr_idx_1(blktr_idx_1[3:0]),
+		.clock2_2(hor_2),
+     .cmd_2(out_i2c_2[7:0]),
+     .rx_byte_o_2(Rx_Byte_o_2[7:0]),
+     .busy_2(busy_i2c_2),
+     .sda_2(sda_out_2),
+     .scl_2(scl_2),
+     .sda_bi_2(sda_in_2),
+     .reset_2(reset_2),
+     .start_i2c_2(sti2c_out_2),
+     .ack_ok_2(ack_ok_2),
+     .data_in_2(data_outY_2[7:0]),
+     .data_in2_2(byte_out5_2[7:0]),
+     .nbyte_2(nbyte_2[4:0]),
+     .sda_gnd_2(sda_gnd_2),
+     .ext_mode_2(ext_mode_2),
+     .MultiByte_2(MultiByte_2),
+     .multi_byte_in_2(multi_byte_in_2[7:0]),
+     .le_ec_2(le_ec_2),
+     .rx_1byte_2(rx_1byte_2),
+     .ext_multi_mode_2(ext_multi_mode_2),
+     .rw_b_ext_2(rw_b_ext_2),
+     .stop_cond_2(stop_cond_2),
+     .blktr_idx_2(blktr_idx_2[3:0]),
+		.clock2_3(hor_3),
+     .cmd_3(out_i2c_3[7:0]),
+     .rx_byte_o_3(Rx_Byte_o_3[7:0]),
+     .busy_3(busy_i2c_3),
+     .sda_3(sda_out_3),
+     .scl_3(scl_3),
+     .sda_bi_3(sda_in_3),
+     .reset_3(reset_3),
+     .start_i2c_3(sti2c_out_3),
+     .ack_ok_3(ack_ok_3),
+     .data_in_3(data_outY_3[7:0]),
+     .data_in2_3(byte_out5_3[7:0]),
+     .nbyte_3(nbyte_3[4:0]),
+     .sda_gnd_3(sda_gnd_3),
+     .ext_mode_3(ext_mode_3),
+     .MultiByte_3(MultiByte_3),
+     .multi_byte_in_3(multi_byte_in_3[7:0]),
+     .le_ec_3(le_ec_3),
+     .rx_1byte_3(rx_1byte_3),
+     .ext_multi_mode_3(ext_multi_mode_3),
+     .rw_b_ext_3(rw_b_ext_3),
+     .stop_cond_3(stop_cond_3),
+     .blktr_idx_3(blktr_idx_3[3:0])
+	);
+
+
+i_mask_op_fc_tri  CMSK_op (
+     .mask_in_1(msk_1[7:0]),
+     .data_in_1(Rx_Byte_o_1[7:0]),
+     .data_pass_1(byte_out4_1[7:0]),
+     .data_out_1(data_outY_1[7:0]),
+     .op_1(msk_op_1[1:0]),
+     .clk_1(clk_1),
+     .reset_1(reset_1),
+		.mask_in_2(msk_2[7:0]),
+     .data_in_2(Rx_Byte_o_2[7:0]),
+     .data_pass_2(byte_out4_2[7:0]),
+     .data_out_2(data_outY_2[7:0]),
+     .op_2(msk_op_2[1:0]),
+     .clk_2(clk_2),
+     .reset_2(reset_2),
+		.mask_in_3(msk_3[7:0]),
+     .data_in_3(Rx_Byte_o_3[7:0]),
+     .data_pass_3(byte_out4_3[7:0]),
+     .data_out_3(data_outY_3[7:0]),
+     .op_3(msk_op_3[1:0]),
+     .clk_3(clk_3),
+     .reset_3(reset_3)
+	);
+
+
+sync_start_tri  sync_clk (
+     .reset_1(reset_1),
+     .clk_1(clk_1),
+     .sti2c_in_1(start_i2c_1),
+     .sti2c_out_1(sti2c_out_1),
+		.reset_2(reset_2),
+     .clk_2(clk_2),
+     .sti2c_in_2(start_i2c_2),
+     .sti2c_out_2(sti2c_out_2),
+		.reset_3(reset_3),
+     .clk_3(clk_3),
+     .sti2c_in_3(start_i2c_3),
+     .sti2c_out_3(sti2c_out_3)
+	);
+
+
+decode_sm_back_tri  CMD_decod (
+     .reset_1(reset_1),
+     .ack_ok_in_1(ack_ok_1),
+     .clk_1(clk_1),
+     .cmd_in_1(byte_out_cmd_1[7:0]),
+     .nbyte_1(nbyte_1[4:0]),
+     .out_i2c_1(out_i2c_1[7:0]),
+     .i2c_busy_1(busy_i2c_1),
+     .start_i2c_1(start_i2c_1),
+     .crc_ok_1(Start_tr_n_1),
+     .occup_1(busy_1),
+     .addr_i2c_1(byte_out3_1[7:0]),
+     .read_nc_1(read_nc_1),
+     .rep_out_1(reponse_1),
+     .msk_op_1(msk_op_1[1:0]),
+     .SRA_1(SRA_out_1[7:0]),
+     .SDA_LOW_1(sda_gnd_1),
+     .ext_mode_1(ext_mode_1),
+     .i2c_br_1(i2c_br_1),
+     .EBRDCST_1(cra_1[6]),
+     .MultiByte_1(MultiByte_1),
+     .nbyte_in_1(cra_1[5:2]),
+     .ext_multi_mode_1(ext_multi_mode_1),
+     .rw_b_ext_1(rw_b_ext_1),
+     .stop_cond_in_1(stop_cond_1),
+		.reset_2(reset_2),
+     .ack_ok_in_2(ack_ok_2),
+     .clk_2(clk_2),
+     .cmd_in_2(byte_out_cmd_2[7:0]),
+     .nbyte_2(nbyte_2[4:0]),
+     .out_i2c_2(out_i2c_2[7:0]),
+     .i2c_busy_2(busy_i2c_2),
+     .start_i2c_2(start_i2c_2),
+     .crc_ok_2(Start_tr_n_2),
+     .occup_2(busy_2),
+     .addr_i2c_2(byte_out3_2[7:0]),
+     .read_nc_2(read_nc_2),
+     .rep_out_2(reponse_2),
+     .msk_op_2(msk_op_2[1:0]),
+     .SRA_2(SRA_out_2[7:0]),
+     .SDA_LOW_2(sda_gnd_2),
+     .ext_mode_2(ext_mode_2),
+     .i2c_br_2(i2c_br_2),
+     .EBRDCST_2(cra_2[6]),
+     .MultiByte_2(MultiByte_2),
+     .nbyte_in_2(cra_2[5:2]),
+     .ext_multi_mode_2(ext_multi_mode_2),
+     .rw_b_ext_2(rw_b_ext_2),
+     .stop_cond_in_2(stop_cond_2),
+		.reset_3(reset_3),
+     .ack_ok_in_3(ack_ok_3),
+     .clk_3(clk_3),
+     .cmd_in_3(byte_out_cmd_3[7:0]),
+     .nbyte_3(nbyte_3[4:0]),
+     .out_i2c_3(out_i2c_3[7:0]),
+     .i2c_busy_3(busy_i2c_3),
+     .start_i2c_3(start_i2c_3),
+     .crc_ok_3(Start_tr_n_3),
+     .occup_3(busy_3),
+     .addr_i2c_3(byte_out3_3[7:0]),
+     .read_nc_3(read_nc_3),
+     .rep_out_3(reponse_3),
+     .msk_op_3(msk_op_3[1:0]),
+     .SRA_3(SRA_out_3[7:0]),
+     .SDA_LOW_3(sda_gnd_3),
+     .ext_mode_3(ext_mode_3),
+     .i2c_br_3(i2c_br_3),
+     .EBRDCST_3(cra_3[6]),
+     .MultiByte_3(MultiByte_3),
+     .nbyte_in_3(cra_3[5:2]),
+     .ext_multi_mode_3(ext_multi_mode_3),
+     .rw_b_ext_3(rw_b_ext_3),
+     .stop_cond_in_3(stop_cond_3)
+	);
+
+endmodule
+
+
+`timescale 1ns / 1ps
+
+
+
+
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  master_cmd_sm
+//      Library Name  :  new_i2c_2
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         IF for state selection         :  No
+//         Error (default) state          :  Yes
+//         String typed state variable    :  No
+//         Next state assignments         :  Non blocking
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  new_i2c_2
+//  Unit    Name :  master_cmd_sm
+//  Unit    Type :  State Machine
+//  
+//----------------------------------------------------
+
+module master_cmd_sm_iostate (clock2, cmd, rx_byte_o_i, rx_byte_o_o, busy_i, busy_o, sda_i, sda_o, scl_i, scl_o, sda_bi, reset,
+                      start_i2c, ack_ok_i, ack_ok_o, data_in, data_in2, nbyte, sda_gnd_i, sda_gnd_o,
+                      ext_mode, MultiByte, multi_byte_in, le_ec_i, le_ec_o, rx_1byte_i, rx_1byte_o,
+                      ext_multi_mode, rw_b_ext, stop_cond_i, stop_cond_o, blktr_idx_i, blktr_idx_o
+                      , status_i, status_o, visual_rst_state_current_i, visual_rst_state_current_o, nb_byte_i, nb_byte_o, address_i, address_o, ack_multi_i, ack_multi_o, nb_bit_i, nb_bit_o, registre_i, registre_o, i2c_mode_i, i2c_mode_o);
+ 
+  input clock2;
+  input [3:0] i2c_mode_i;
+ 
+  input start_i2c;
+  input [7:0] registre_i;
+  input [7:0] data_in;
+  input [3:0] nb_bit_i;
+  input [7:0] data_in2;
+  input ack_multi_i;           
+  input [7:0] address_i;
+  input [4:0] nbyte;
+  input [4:0] nb_byte_i;       
+  input ext_mode;
+  input MultiByte;        
+  input [7:0] multi_byte_in; 
+  input [5:0] visual_rst_state_current_i;
+ 
+ 
+ 
+  input ext_multi_mode;
+  input stop_cond_i;
+  input rw_b_ext;
+  input status_i;
+  input [7:0] cmd;
+  output [7:0] rx_byte_o_o;
+  output [3:0] i2c_mode_o;
+  output status_o;
+  output [7:0] registre_o;
+  output busy_o;
+  output [3:0] nb_bit_o;
+  output sda_o;
+  output ack_multi_o;
+  output [7:0] address_o;
+  output scl_o;
+  output [4:0] nb_byte_o;
+  output ack_ok_o;
+  input ack_ok_i;
+  output sda_gnd_o;
+  input sda_gnd_i;
+  output le_ec_o;
+  input le_ec_i;
+  output [5:0] visual_rst_state_current_o;
+  output rx_1byte_o;
+  input rx_1byte_i;         
+  output stop_cond_o;
+  output [3:0] blktr_idx_o;
+  input [3:0] blktr_idx_i;  
+  input [7:0] rx_byte_o_i;
+  reg [7:0] rx_byte_o_o;
+  input busy_i;
+  reg busy_o;
+  input sda_i;
+  reg sda_o;
+  input scl_i;
+  reg scl_o;
+  input sda_bi;
+  wire sda_bi;
+  input reset;
+  reg ack_ok_o;
+  reg sda_gnd_o;
+  wire ext_mode;
+  wire MultiByte;
+  wire [7:0] multi_byte_in;
+  reg le_ec_o;
+  reg rx_1byte_o;
+  wire ext_multi_mode;
+  wire rw_b_ext;
+  reg stop_cond_o;
+  reg [3:0] blktr_idx_o;
+  reg [3:0] nb_bit_o;
+	reg [7:0] address_o;
+	reg [7:0] rx_byte;
+  reg status_o;
+	reg [7:0] registre_o;
+	reg ack_multi_o;
+	reg [4:0] nb_byte_o;
+	reg [3:0] i2c_mode_o;
+	parameter rst_state = 6'b000000,
+            Ack_read  = 6'b000001,
+            READ      = 6'b000010,
+            S30       = 6'b000011,
+            S31       = 6'b000100,
+            S32       = 6'b000101,
+            S44       = 6'b000110,
+            S46busy_o = 6'b000111,
+            main      = 6'b001000,
+            repos     = 6'b001001,
+            s10       = 6'b001010,
+            s17Rd     = 6'b001011,
+            s22       = 6'b001100,
+            s4Rd      = 6'b001101,
+            s5Rd      = 6'b001110,
+            s_dat_rdy = 6'b001111,
+            thd_sda   = 6'b010000,
+            s7_stop   = 6'b010001,
+            s6_stop   = 6'b010010,
+            s8_stop   = 6'b010011,
+            tsu_sto   = 6'b010100,
+            S0        = 6'b010101,
+            S1        = 6'b010110,
+            S11       = 6'b010111,
+            S9        = 6'b011000,
+            S3_scl1   = 6'b011001,
+            S18delai  = 6'b011010,
+            S19       = 6'b011011,
+            S4        = 6'b011100,
+            S5        = 6'b011101,
+            S6_scl0   = 6'b011110,
+            S8_sda_1  = 6'b011111,
+            TST_ACK   = 6'b100000;
+ 
+ 
+  reg [5:0] visual_rst_state_current_o;
+	// Synchronous process
+  always  @(posedge clock2 or posedge reset) begin : master_cmd_sm_rst_state
+    if (reset == 1'b1) begin
+	status_o <= 1'b0;
+	rx_byte_o_o <= 8'h0;
+	stop_cond_o <= 1'b0;
+	blktr_idx_o <= 4'h0;
+	visual_rst_state_current_o <= rst_state;
+	
+	busy_o      <= 1'b0;    //added 1 oct 2015
+	scl_o       <= 1'b1;    //added 1 oct 2015
+	sda_o       <= 1'b1;    //added 1 oct 2015
+	nb_byte_o   <= 5'h0;    //added 1 oct 2015 
+	le_ec_o     <= 1'b0;    //added 1 oct 2015
+	address_o   <= 8'h0;    //added 1 oct 2015
+	ack_multi_o <= 1'b0;    //added 1 oct 2015
+	rx_1byte_o  <= 1'b0;    //added 1 oct 2015
+	nb_bit_o    <= 4'b1000; //added 1 oct 2015
+	ack_ok_o    <= 1'b0;    //added 1 oct 2015
+	registre_o  <= 8'h0;    //added 1 oct 2015
+	sda_gnd_o   <= 1'b0;    //added 1 oct 2015
+	 
+    end
+    else begin
+      status_o    <= status_i;
+      rx_byte_o_o <= rx_byte_o_i;
+      stop_cond_o <= stop_cond_i;
+      blktr_idx_o <= blktr_idx_i;
+      visual_rst_state_current_o <= visual_rst_state_current_i;
+      busy_o <= busy_i;
+      scl_o <= scl_i;
+      sda_o <= sda_i;
+      nb_byte_o <= nb_byte_i;
+      le_ec_o <= le_ec_i;
+      address_o <= address_i;
+      ack_multi_o <= ack_multi_i;
+      rx_1byte_o <= rx_1byte_i;
+      nb_bit_o <= nb_bit_i;
+      ack_ok_o <= ack_ok_i;
+      registre_o <= registre_i;
+      sda_gnd_o <= sda_gnd_i;  
+	i2c_mode_o <= i2c_mode_i;
+	
+      case (visual_rst_state_current_i)
+        rst_state:
+          begin
+            busy_o <= 1'b0;
+            scl_o <= 1'b1;
+            sda_o <= 1'b1;
+            nb_byte_o <= 5'h0;
+            le_ec_o <= 1'b0;
+            address_o <= 8'h0;
+            ack_multi_o <= 1'b0;
+            rx_1byte_o <= 1'b0;
+            nb_bit_o <= 4'b1000;
+            ack_ok_o <= 1'b0;
+            registre_o <= 8'h0;
+            sda_gnd_o <= 1'b0;  
+            blktr_idx_o <= 4'h0;
+            visual_rst_state_current_o <= repos;
+          end
+ 
+        Ack_read:
+          begin
+            if (nb_byte_i == nbyte)
+            begin
+              sda_o <= 1'b0;
+              visual_rst_state_current_o <= s7_stop;
+            end
+            else if ((nb_byte_i != nbyte) && MultiByte)
+            begin
+              ack_multi_o <= 1'b0;
+              sda_o <= 1'b1;
+              rx_1byte_o <= 1'b0;
+              visual_rst_state_current_o <= READ;
+            end
+            else
+              visual_rst_state_current_o <= Ack_read;
+          end
+ 
+        READ:
+          begin
+            scl_o <= 1'b1;
+            visual_rst_state_current_o <= s4Rd;
+          end
+ 
+        S30:
+          begin
+            scl_o <= 1'b1;
+            visual_rst_state_current_o <= S31;
+            blktr_idx_o <= blktr_idx_i + 4'h1;
+            rx_1byte_o <= 1'b0;
+          end
+ 
+        S31:
+          begin
+            visual_rst_state_current_o <= S32;
+          end
+ 
+        S32:
+          begin
+            scl_o <= 1'b0;
+            nb_bit_o <= 4'b0111;
+            visual_rst_state_current_o <= Ack_read;
+          end
+ 
+        S44:
+          begin
+            sda_o <= address_i[7];
+            visual_rst_state_current_o <= s_dat_rdy;
+          end
+ 
+        S46busy_o:
+          begin
+            busy_o <= 1'b0;
+            scl_o <= 1'b1;
+            sda_o <= 1'b1;
+            nb_byte_o <= 5'h0;
+            le_ec_o <= 1'b0;
+            address_o <= 8'h0;
+            ack_multi_o <= 1'b0;
+            rx_1byte_o <= 1'b0;
+            nb_bit_o <= 4'b1000;
+            ack_ok_o <= 1'b0;
+            registre_o <= 8'h0;
+            sda_gnd_o <= 1'b0;  
+            blktr_idx_o <= 4'h0;
+            visual_rst_state_current_o <= repos;
+          end
+ 
+        main:
+          begin
+            if (nb_byte_i == 5'h0)
+            begin
+              sda_o <= 1'b0;
+              ack_ok_o <= 1'b0;
+              visual_rst_state_current_o <= s10;
+            end
+            else if ((nb_byte_i > 5'h0) && (cmd[0]))
+            begin
+              nb_bit_o <= (nb_bit_i - 1);
+              blktr_idx_o <= 4'h0;
+              ack_multi_o <= 1'b0;
+              sda_o <= 1'b1;
+              rx_1byte_o <= 1'b0;
+              visual_rst_state_current_o <= READ;
+            end
+            else if (nb_byte_i > 5'b00000)
+            begin
+              scl_o <= 1'b1;
+              visual_rst_state_current_o <= S3_scl1;
+            end
+            else
+              visual_rst_state_current_o <= main;
+          end
+ 
+        repos:
+          begin
+            if (start_i2c)
+            begin
+              nb_byte_o <= 5'h0;
+              le_ec_o <= cmd[0];
+              address_o <= cmd;  
+              busy_o <= 1'b1;
+              sda_o <= 1'b1;
+              status_o <= 1'b0; 
+              stop_cond_o <= 1'b0;
+              rx_1byte_o <= 1'b0;
+              i2c_mode_o <= {ext_multi_mode,rw_b_ext,MultiByte,cmd[0]};
+ 
+              if((nb_byte_i != 5'b00000) && (nb_byte_i != nbyte))
+              begin
+              case  ({ext_multi_mode,rw_b_ext,MultiByte,cmd[0]})
+                     4'b0000,4'b0100,4'b1000,4'b1100:
+                    begin
+                      if (nb_byte_i == 5'b00001)
+                         begin
+                          address_o <= data_in;
+                          sda_o <=     data_in[7];
+                         end
+                      if (nb_byte_i == 5'b00010)
+                         begin
+                          address_o <= data_in2;
+                          sda_o <=     data_in2[7];
+                         end
+                    end
+                   4'b1110:
+                     begin
+                      if(nb_byte_i == 5'b00010)
+                        begin
+                         address_o <= {cmd[7:1],1'b1};
+                         sda_o <= cmd[7];
+                        end
+                      if(nb_byte_i == 5'b00001)
+                         begin
+                          address_o <= data_in;
+                          sda_o <=     data_in[7];
+                      end
+                      if(nb_byte_i >= 5'b00011)
+                         begin
+                           address_o <= multi_byte_in;
+                           sda_o <=    multi_byte_in[7];
+                         end
+                      end
+                   4'b0110,4'b0010:  
+                        begin
+                         address_o <= multi_byte_in;
+                         sda_o <= multi_byte_in[7];
+                        end
+                   4'b1010:   
+                       begin
+                          if(nb_byte_i == 5'b00001)
+                             begin
+                                address_o <= data_in;  
+                                sda_o <= data_in[7];
+                             end
+                           else
+                              begin
+                                address_o <= multi_byte_in;
+                                sda_o <= multi_byte_in[7];
+                              end
+                       end
+ 
+ 
+                   default:
+                       address_o <= 1;
+              endcase
+              end 
+              visual_rst_state_current_o <= main;
+            end
+            else if ((sda_bi == 1'b1) && (!(start_i2c)))
+            begin
+              sda_gnd_o <= 1'b0;
+              visual_rst_state_current_o <= repos;
+            end
+            else if ((sda_bi == 1'b0) && (!(start_i2c)))
+            begin
+              sda_gnd_o <= 1'b1;
+              visual_rst_state_current_o <= repos;
+            end
+            else
+              visual_rst_state_current_o <= repos;
+          end
+ 
+        s10:
+          begin
+            visual_rst_state_current_o <= thd_sda;
+          end
+ 
+        s17Rd:
+          begin
+            if (nb_bit_i == 4'b0000)
+            begin
+              rx_byte_o_o <= registre_i;
+              scl_o <= 1'b0;
+              nb_byte_o <= nb_byte_i + 5'h1; 
+              //blktr_idx_o <= blktr_idx_i + 4'h1;
+              visual_rst_state_current_o <= s22;
+            end
+            else
+            begin
+              scl_o <= 1'b0;
+              registre_o <= (registre_i << 1);
+              nb_bit_o <= (nb_bit_i-1);
+              visual_rst_state_current_o <= s5Rd;
+            end
+          end
+ 
+        s22:
+          begin
+            rx_1byte_o <= 1'b1;
+            if (MultiByte && (nb_byte_i != nbyte))
+              begin
+                ack_multi_o <= 1'b1;
+                sda_o <= 1'b0;
+               end
+            else
+              sda_o <= 1'b1;
+            visual_rst_state_current_o <= S30;
+          end
+ 
+        s4Rd:
+          begin
+              registre_o[0] <= sda_bi;
+            visual_rst_state_current_o <= s17Rd;
+          end
+ 
+        s5Rd:
+          begin
+            ack_multi_o <= 1'b0;
+            sda_o <= 1'b1;
+            rx_1byte_o <= 1'b0;
+            visual_rst_state_current_o <= READ;
+          end
+ 
+        s_dat_rdy:
+          begin
+            scl_o <= 1'b1;
+            visual_rst_state_current_o <= S3_scl1;
+          end
+ 
+        thd_sda:
+          begin
+            scl_o <= 1'b0;
+            visual_rst_state_current_o <= S44;
+          end
+ 
+        s7_stop:
+          begin
+            scl_o <= 1'b1;
+            stop_cond_o <= 1'b1;
+            visual_rst_state_current_o <= s8_stop;
+          end
+ 
+        s6_stop:
+          begin
+            busy_o<= 1'b0;
+            visual_rst_state_current_o <= S46busy_o;
+          end
+ 
+        s8_stop:
+          begin
+            visual_rst_state_current_o <= tsu_sto;
+          end
+ 
+        tsu_sto:
+          begin
+            sda_o <= 1'b1;
+            visual_rst_state_current_o <= s6_stop;
+          end
+ 
+        S0:
+          begin
+            scl_o <= 1'b1;
+            visual_rst_state_current_o <= S1;
+          end
+ 
+        S1:
+          begin
+            visual_rst_state_current_o <= S11;
+          end
+ 
+        S11:
+          begin
+            sda_o <= 1'b1;
+            visual_rst_state_current_o <= S9;
+          end
+ 
+        S9:
+          begin
+            busy_o<= 1'b0;
+            visual_rst_state_current_o <= S46busy_o;
+          end
+ 
+        S3_scl1:
+          begin
+            nb_bit_o <= (nb_bit_i - 1);
+            address_o <= (address_i << 1);
+            visual_rst_state_current_o <= S4;
+          end
+ 
+        S18delai:
+          begin
+            if ((!(status_i)) && (nb_byte_i == nbyte && ext_mode == 1'b0))
+            begin
+              sda_o <= 1'b0;
+              visual_rst_state_current_o <= s7_stop;
+            end
+            else if ((!(status_i)) && ((nb_byte_i == nbyte) && (ext_mode == 1'b1)))
+            begin
+              sda_o <= 1'b1;
+              visual_rst_state_current_o <= S0;
+            end
+            else if ((!(status_i)) && (nb_byte_i != nbyte))
+            begin
+              rx_1byte_o <= 1'b0;
+ 
+              i2c_mode_o <= {ext_multi_mode,rw_b_ext,MultiByte,cmd[0]};
+ 
+              if((nb_byte_i != 5'b00000) && (nb_byte_i != nbyte))
+
+              begin
+              case  ({ext_multi_mode,rw_b_ext,MultiByte,cmd[0]})
+                     4'b0000,4'b0100,4'b1000,4'b1100:
+                    begin
+                      if (nb_byte_i == 5'b00001)
+                         begin
+                          address_o <= data_in;
+                          sda_o <=     data_in[7];
+                         end
+                      if (nb_byte_i == 5'b00010)
+                         begin
+                          address_o <= data_in2;
+                          sda_o <=     data_in2[7];
+                         end
+                    end
+                   4'b1110:
+                     begin
+                      if(nb_byte_i == 5'b00010)
+                        begin
+                         address_o <= {cmd[7:1],1'b1};
+                         sda_o <= cmd[7];
+                        end
+                      if(nb_byte_i == 5'b00001)
+                         begin
+                          address_o <= data_in;
+                          sda_o <=     data_in[7];
+                      end
+                      if(nb_byte_i >= 5'b00011)
+                         begin
+                           address_o <= multi_byte_in;
+                           sda_o <=    multi_byte_in[7];
+                         end
+                      end
+                   4'b0110,4'b0010:  
+                        begin
+                         address_o <= multi_byte_in;
+                         sda_o <= multi_byte_in[7];
+                        end
+                   4'b1010:    
+                       begin
+                          if(nb_byte_i == 5'b00001)
+                             begin
+                                address_o <= data_in;  
+                                sda_o <= data_in[7];
+                             end
+                           else
+                              begin
+                                address_o <= multi_byte_in;
+                                sda_o <= multi_byte_in[7];
+                              end
+                       end
+ 
+ 
+                   default:
+                       address_o <= 1;
+              endcase
+              end 
+              visual_rst_state_current_o <= main;
+            end
+            else if (status_i)
+            begin
+              sda_o <= 1'b0;
+              visual_rst_state_current_o <= s7_stop;
+            end
+            else
+            begin
+              scl_o <= 1'b1;
+              visual_rst_state_current_o <= S3_scl1;
+            end
+          end
+ 
+        S19:
+          begin
+            scl_o <= 1'b0;
+            visual_rst_state_current_o <= S18delai;
+          end
+ 
+        S4:
+          begin
+            scl_o <= 1'b0;
+            visual_rst_state_current_o <= S6_scl0;
+          end
+ 
+        S5:
+          begin
+            scl_o <= 1'b1;
+            visual_rst_state_current_o <= S3_scl1;
+          end
+ 
+        S6_scl0:
+          begin
+            if (nb_bit_i == 4'b0000)
+            begin
+              sda_o <= 1'b1;
+              if(!le_ec_i && ext_multi_mode && (nb_byte_i >= 5'b00010))
+                blktr_idx_o <= blktr_idx_i + 4'b0001;
+              if(!le_ec_i && MultiByte && (!ext_multi_mode) && (nb_byte_i >=
+               5'b00001))
+                blktr_idx_o <= blktr_idx_i + 4'b0001;
+              visual_rst_state_current_o <= S8_sda_1;
+            end
+            else
+            begin
+              sda_o <= address_i[7];
+              visual_rst_state_current_o <= S5;
+            end
+          end
+ 
+        S8_sda_1:
+          begin
+            scl_o <= 1'b1;
+            if(sda_bi == 1'b1)
+                begin
+                 status_o <= 1'b1;
+                 ack_ok_o <= 1'b0;
+                 end
+            else
+               begin
+                 status_o <= 1'b0;
+                 ack_ok_o <= 1'b1;
+               end
+            visual_rst_state_current_o <= TST_ACK;
+          end
+ 
+        TST_ACK:
+          begin
+            nb_byte_o <= nb_byte_i + 5'b00001;
+            nb_bit_o <= 4'b1000;
+            visual_rst_state_current_o <= S19;
+          end
+ 
+        default:
+          begin
+            status_o <= 1'b0;
+            rx_byte_o_o <= 8'h0;
+            stop_cond_o <= 1'b0;
+            blktr_idx_o <= 4'h0;
+            visual_rst_state_current_o <= rst_state;
+          end
+      endcase
+    end
+  end
+ 
+ 
+ 
+endmodule
+
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  master_cmd_sm
+//      Library Name  :  new_i2c_2
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         IF for state selection         :  No
+//         Error (default_1, default_2, default_3) state          :  Yes
+//         String typed state variable    :  No
+//         Next state assignments         :  Non blocking
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  new_i2c_2
+//  Unit    Name :  master_cmd_sm
+//  Unit    Type :  State Machine
+//  
+//----------------------------------------------------
+
+module master_cmd_sm_tri (clock2_1, clock2_2, clock2_3, cmd_1, cmd_2, cmd_3, rx_byte_o_1, rx_byte_o_2, rx_byte_o_3, busy_1, busy_2, busy_3, sda_1, sda_2, sda_3, scl_1, scl_2, scl_3, sda_bi_1, sda_bi_2, sda_bi_3, reset_1, reset_2, reset_3,
+                      start_i2c_1, start_i2c_2, start_i2c_3, ack_ok_1, ack_ok_2, ack_ok_3, data_in_1, data_in_2, data_in_3, data_in2_1, data_in2_2, data_in2_3, nbyte_1, nbyte_2, nbyte_3, sda_gnd_1, sda_gnd_2, sda_gnd_3,
+                      ext_mode_1, ext_mode_2, ext_mode_3, MultiByte_1, MultiByte_2, MultiByte_3, multi_byte_in_1, multi_byte_in_2, multi_byte_in_3, le_ec_1, le_ec_2, le_ec_3, rx_1byte_1, rx_1byte_2, rx_1byte_3,
+                      ext_multi_mode_1, ext_multi_mode_2, ext_multi_mode_3, rw_b_ext_1, rw_b_ext_2, rw_b_ext_3, stop_cond_1, stop_cond_2, stop_cond_3, blktr_idx_1, blktr_idx_2, blktr_idx_3
+                      );
+
+  input clock2_1, clock2_2, clock2_3;
+  input [7:0] cmd_1, cmd_2, cmd_3;
+  output [7:0] rx_byte_o_1, rx_byte_o_2, rx_byte_o_3;
+  output busy_1, busy_2, busy_3;
+  output sda_1, sda_2, sda_3;
+  output scl_1, scl_2, scl_3;
+  input sda_bi_1, sda_bi_2, sda_bi_3;
+  input reset_1, reset_2, reset_3;
+  input start_i2c_1, start_i2c_2, start_i2c_3;
+  output ack_ok_1, ack_ok_2, ack_ok_3;
+  input [7:0] data_in_1, data_in_2, data_in_3;
+  input [7:0] data_in2_1, data_in2_2, data_in2_3;
+  input [4:0] nbyte_1, nbyte_2, nbyte_3;
+  output sda_gnd_1, sda_gnd_2, sda_gnd_3;
+  input ext_mode_1, ext_mode_2, ext_mode_3;
+  input MultiByte_1, MultiByte_2, MultiByte_3;        
+  input [7:0] multi_byte_in_1, multi_byte_in_2, multi_byte_in_3; 
+  output le_ec_1, le_ec_2, le_ec_3;
+  output rx_1byte_1, rx_1byte_2, rx_1byte_3;         
+  input ext_multi_mode_1, ext_multi_mode_2, ext_multi_mode_3;
+  input rw_b_ext_1, rw_b_ext_2, rw_b_ext_3;
+  output stop_cond_1, stop_cond_2, stop_cond_3;
+  output [3:0] blktr_idx_1, blktr_idx_2, blktr_idx_3;  
+  
+
+	wire status_1, status_2, status_3;
+	wire [7:0] rx_byte_o_1, rx_byte_o_2, rx_byte_o_3;
+	wire stop_cond_1, stop_cond_2, stop_cond_3;
+	wire [3:0] blktr_idx_1, blktr_idx_2, blktr_idx_3;
+	wire [5:0] visual_rst_state_current_1, visual_rst_state_current_2, visual_rst_state_current_3;
+	wire busy_1, busy_2, busy_3;
+	wire scl_1, scl_2, scl_3;
+	wire sda_1, sda_2, sda_3;
+	wire [4:0] nb_byte_1, nb_byte_2, nb_byte_3;
+	wire le_ec_1, le_ec_2, le_ec_3;
+	wire [7:0] address_1, address_2, address_3;
+	wire ack_multi_1, ack_multi_2, ack_multi_3;
+	wire rx_1byte_1, rx_1byte_2, rx_1byte_3;
+	wire [3:0] nb_bit_1, nb_bit_2, nb_bit_3;
+	wire ack_ok_1, ack_ok_2, ack_ok_3;
+	wire [7:0] registre_1, registre_2, registre_3;
+	wire sda_gnd_1, sda_gnd_2, sda_gnd_3;
+	wire [3:0] i2c_mode_1, i2c_mode_2, i2c_mode_3;
+	
+	wire status_nv1, status_nv2, status_nv3;
+	wire [7:0] rx_byte_o_nv1, rx_byte_o_nv2, rx_byte_o_nv3;
+	wire stop_cond_nv1, stop_cond_nv2, stop_cond_nv3;
+	wire [3:0] blktr_idx_nv1, blktr_idx_nv2, blktr_idx_nv3;
+	wire [5:0] visual_rst_state_current_nv1, visual_rst_state_current_nv2, visual_rst_state_current_nv3;
+	wire busy_nv1, busy_nv2, busy_nv3;
+	wire scl_nv1, scl_nv2, scl_nv3;
+	wire sda_nv1, sda_nv2, sda_nv3;
+	wire [4:0] nb_byte_nv1, nb_byte_nv2, nb_byte_nv3;
+	wire le_ec_nv1, le_ec_nv2, le_ec_nv3;
+	wire [7:0] address_nv1, address_nv2, address_nv3;
+	wire ack_multi_nv1, ack_multi_nv2, ack_multi_nv3;
+	wire rx_1byte_nv1, rx_1byte_nv2, rx_1byte_nv3;
+	wire [3:0] nb_bit_nv1, nb_bit_nv2, nb_bit_nv3;
+	wire ack_ok_nv1, ack_ok_nv2, ack_ok_nv3;
+	wire [7:0] registre_nv1, registre_nv2, registre_nv3;
+	wire sda_gnd_nv1, sda_gnd_nv2, sda_gnd_nv3;
+	wire [3:0] i2c_mode_nv1, i2c_mode_nv2, i2c_mode_nv3;	
+	
+	//wire status;
+	//wire [7:0] rx_byte_o;
+	//wire stop_cond;
+	//wire [3:0] blktr_idx;
+	//wire [5:0] visual_rst_state_current;
+	//wire busy;
+	//wire scl;
+	//wire sda;
+	//wire [4:0] nb_byte;
+	//wire le_ec;
+	//wire [7:0] address;
+	//wire ack_multi;
+	//wire rx_1byte;
+	//wire [3:0] nb_bit;
+	//wire ack_ok;
+	//wire [7:0] registre;
+	//wire sda_gnd;
+	//wire [3:0] i2c_mode;
+
+	master_cmd_sm_iostate master_cmd_sm_iostate_1   (
+			.clock2(clock2_1), 
+			.cmd(cmd_1), 
+			.rx_byte_o_i(rx_byte_o_1), 
+			.rx_byte_o_o(rx_byte_o_nv1), 
+			.busy_i(busy_1), 
+			.busy_o(busy_nv1), 
+			.sda_i(sda_1), 
+			.sda_o(sda_nv1), 
+			.scl_i(scl_1), 
+			.scl_o(scl_nv1), 
+			.sda_bi(sda_bi_1), 
+			.reset(reset_1),
+                      
+			.start_i2c(start_i2c_1), 
+			.ack_ok_i(ack_ok_1), 
+			.ack_ok_o(ack_ok_nv1), 
+			.data_in(data_in_1), 
+			.data_in2(data_in2_1), 
+			.nbyte(nbyte_1), 
+			.sda_gnd_i(sda_gnd_1), 
+			.sda_gnd_o(sda_gnd_nv1),
+                      
+			.ext_mode(ext_mode_1), 
+			.MultiByte(MultiByte_1), 
+			.multi_byte_in(multi_byte_in_1), 
+			.le_ec_i(le_ec_1), 
+			.le_ec_o(le_ec_nv1), 
+			.rx_1byte_i(rx_1byte_1), 
+			.rx_1byte_o(rx_1byte_nv1),
+                      
+			.ext_multi_mode(ext_multi_mode_1), 
+			.rw_b_ext(rw_b_ext_1), 
+			.stop_cond_i(stop_cond_1), 
+			.stop_cond_o(stop_cond_nv1), 
+			.blktr_idx_i(blktr_idx_1), 
+			.blktr_idx_o(blktr_idx_nv1), 
+			.status_i(status_1), 
+			.status_o(status_nv1), 
+			.visual_rst_state_current_i(visual_rst_state_current_1), 
+			.visual_rst_state_current_o(visual_rst_state_current_nv1), 
+			.nb_byte_i(nb_byte_1), 
+			.nb_byte_o(nb_byte_nv1), 
+			.address_i(address_1), 
+			.address_o(address_nv1), 
+			.ack_multi_i(ack_multi_1), 
+			.ack_multi_o(ack_multi_nv1), 
+			.nb_bit_i(nb_bit_1), 
+			.nb_bit_o(nb_bit_nv1), 
+			.registre_i(registre_1), 
+			.registre_o(registre_nv1), 
+			.i2c_mode_i(i2c_mode_1), 
+			.i2c_mode_o(i2c_mode_nv1));
+
+	master_cmd_sm_iostate master_cmd_sm_iostate_2   (
+			
+			.clock2(clock2_2), 
+			.cmd(cmd_2), 
+			.rx_byte_o_i(rx_byte_o_2), 
+			.rx_byte_o_o(rx_byte_o_nv2), 
+			.busy_i(busy_2), 
+			.busy_o(busy_nv2), 
+			.sda_i(sda_2), 
+			.sda_o(sda_nv2), 
+			.scl_i(scl_2), 
+			.scl_o(scl_nv2), 
+			.sda_bi(sda_bi_2), 
+			.reset(reset_2),
+                      
+			.start_i2c(start_i2c_2), 
+			.ack_ok_i(ack_ok_2), 
+			.ack_ok_o(ack_ok_nv2), 
+			.data_in(data_in_2), 
+			.data_in2(data_in2_2), 
+			.nbyte(nbyte_2), 
+			.sda_gnd_i(sda_gnd_2), 
+			.sda_gnd_o(sda_gnd_nv2),
+                      
+			.ext_mode(ext_mode_2), 
+			.MultiByte(MultiByte_2), 
+			.multi_byte_in(multi_byte_in_2), 
+			.le_ec_i(le_ec_2), 
+			.le_ec_o(le_ec_nv2), 
+			.rx_1byte_i(rx_1byte_2), 
+			.rx_1byte_o(rx_1byte_nv2),
+                      
+			.ext_multi_mode(ext_multi_mode_2), 
+			.rw_b_ext(rw_b_ext_2), 
+			.stop_cond_i(stop_cond_2), 
+			.stop_cond_o(stop_cond_nv2), 
+			.blktr_idx_i(blktr_idx_2), 
+			.blktr_idx_o(blktr_idx_nv2), 
+			.status_i(status_2), 
+			.status_o(status_nv2), 
+			.visual_rst_state_current_i(visual_rst_state_current_2), 
+			.visual_rst_state_current_o(visual_rst_state_current_nv2), 
+			.nb_byte_i(nb_byte_2), 
+			.nb_byte_o(nb_byte_nv2), 
+			.address_i(address_2), 
+			.address_o(address_nv2), 
+			.ack_multi_i(ack_multi_2), 
+			.ack_multi_o(ack_multi_nv2), 
+			.nb_bit_i(nb_bit_2), 
+			.nb_bit_o(nb_bit_nv2), 
+			.registre_i(registre_2), 
+			.registre_o(registre_nv2), 
+			.i2c_mode_i(i2c_mode_2), 
+			.i2c_mode_o(i2c_mode_nv2));
+
+	master_cmd_sm_iostate master_cmd_sm_iostate_3   (
+			.clock2(clock2_3), 
+			.cmd(cmd_3), 
+			.rx_byte_o_i(rx_byte_o_3), 
+			.rx_byte_o_o(rx_byte_o_nv3), 
+			.busy_i(busy_3), 
+			.busy_o(busy_nv3), 
+			.sda_i(sda_3), 
+			.sda_o(sda_nv3), 
+			.scl_i(scl_3), 
+			.scl_o(scl_nv3), 
+			.sda_bi(sda_bi_3), 
+			.reset(reset_3),
+                      
+			.start_i2c(start_i2c_3), 
+			.ack_ok_i(ack_ok_3), 
+			.ack_ok_o(ack_ok_nv3), 
+			.data_in(data_in_3), 
+			.data_in2(data_in2_3), 
+			.nbyte(nbyte_3), 
+			.sda_gnd_i(sda_gnd_3), 
+			.sda_gnd_o(sda_gnd_nv3),
+                      
+			.ext_mode(ext_mode_3), 
+			.MultiByte(MultiByte_3), 
+			.multi_byte_in(multi_byte_in_3), 
+			.le_ec_i(le_ec_3), 
+			.le_ec_o(le_ec_nv3), 
+			.rx_1byte_i(rx_1byte_3), 
+			.rx_1byte_o(rx_1byte_nv3),
+                      
+			.ext_multi_mode(ext_multi_mode_3), 
+			.rw_b_ext(rw_b_ext_3), 
+			.stop_cond_i(stop_cond_3), 
+			.stop_cond_o(stop_cond_nv3), 
+			.blktr_idx_i(blktr_idx_3), 
+			.blktr_idx_o(blktr_idx_nv3), 
+			.status_i(status_3), 
+			.status_o(status_nv3), 
+			.visual_rst_state_current_i(visual_rst_state_current_3), 
+			.visual_rst_state_current_o(visual_rst_state_current_nv3), 
+			.nb_byte_i(nb_byte_3), 
+			.nb_byte_o(nb_byte_nv3), 
+			.address_i(address_3), 
+			.address_o(address_nv3), 
+			.ack_multi_i(ack_multi_3), 
+			.ack_multi_o(ack_multi_nv3), 
+			.nb_bit_i(nb_bit_3), 
+			.nb_bit_o(nb_bit_nv3), 
+			.registre_i(registre_3), 
+			.registre_o(registre_nv3), 
+			.i2c_mode_i(i2c_mode_3), 
+			.i2c_mode_o(i2c_mode_nv3));
+
+	//majority_voter #(.WIDTH(57)) mv_1 (
+	//	.in1({status_2, rx_byte_o_2, stop_cond_2, blktr_idx_2, visual_rst_state_current_2, busy_2, scl_2, sda_2, nb_byte_2, le_ec_2, address_2, ack_multi_2, rx_1byte_2, nb_bit_2, ack_ok_2, registre_2, sda_gnd_2, i2c_mode_2}),
+	//	.in2({status_3, rx_byte_o_3, stop_cond_3, blktr_idx_3, visual_rst_state_current_3, busy_3, scl_3, sda_3, nb_byte_3, le_ec_3, address_3, ack_multi_3, rx_1byte_3, nb_bit_3, ack_ok_3, registre_3, sda_gnd_3, i2c_mode_3}),
+	//	.in3({status,   rx_byte_o,   stop_cond,   blktr_idx,   visual_rst_state_current,   busy,   scl,   sda,   nb_byte,   le_ec,   address,   ack_multi,   rx_1byte,   nb_bit,   ack_ok,   registre,   sda_gnd, i2c_mode}),
+	//	.out({status_1, rx_byte_o_1, stop_cond_1, blktr_idx_1, visual_rst_state_current_1, busy_1, scl_1, sda_1, nb_byte_1, le_ec_1, address_1, ack_multi_1, rx_1byte_1, nb_bit_1, ack_ok_1, registre_1, sda_gnd_1, i2c_mode_1}),
+	//	.err()
+	//);
+
+	majority_voter #(.WIDTH(57)) mv_1 (
+		.in1({status_nv1,  rx_byte_o_nv1,  stop_cond_nv1,  blktr_idx_nv1,  visual_rst_state_current_nv1,  busy_nv1,  scl_nv1,  sda_nv1,  nb_byte_nv1,  le_ec_nv1,  address_nv1,  ack_multi_nv1,  rx_1byte_nv1,  nb_bit_nv1,  ack_ok_nv1,  registre_nv1,  sda_gnd_nv1,  i2c_mode_nv1  }),
+		.in2({status_nv2,  rx_byte_o_nv2,  stop_cond_nv2,  blktr_idx_nv2,  visual_rst_state_current_nv2,  busy_nv2,  scl_nv2,  sda_nv2,  nb_byte_nv2,  le_ec_nv2,  address_nv2,  ack_multi_nv2,  rx_1byte_nv2,  nb_bit_nv2,  ack_ok_nv2,  registre_nv2,  sda_gnd_nv2,  i2c_mode_nv2  }),
+		.in3({status_nv3,  rx_byte_o_nv3,  stop_cond_nv3,  blktr_idx_nv3,  visual_rst_state_current_nv3,  busy_nv3,  scl_nv3,  sda_nv3,  nb_byte_nv3,  le_ec_nv3,  address_nv3,  ack_multi_nv3,  rx_1byte_nv3,  nb_bit_nv3,  ack_ok_nv3,  registre_nv3,  sda_gnd_nv3,  i2c_mode_nv3  }),
+		.out({status_1,    rx_byte_o_1,    stop_cond_1,    blktr_idx_1,    visual_rst_state_current_1,    busy_1,    scl_1,    sda_1,    nb_byte_1,    le_ec_1,    address_1,    ack_multi_1,    rx_1byte_1,    nb_bit_1,    ack_ok_1,    registre_1,    sda_gnd_1,    i2c_mode_1}   ),
+		.err()
+	);
+	
+	majority_voter #(.WIDTH(57)) mv_2 (
+		.in1({status_nv1,  rx_byte_o_nv1,  stop_cond_nv1,  blktr_idx_nv1,  visual_rst_state_current_nv1,  busy_nv1,  scl_nv1,  sda_nv1,  nb_byte_nv1,  le_ec_nv1,  address_nv1,  ack_multi_nv1,  rx_1byte_nv1,  nb_bit_nv1,  ack_ok_nv1,  registre_nv1,  sda_gnd_nv1,  i2c_mode_nv1  }),
+		.in2({status_nv2,  rx_byte_o_nv2,  stop_cond_nv2,  blktr_idx_nv2,  visual_rst_state_current_nv2,  busy_nv2,  scl_nv2,  sda_nv2,  nb_byte_nv2,  le_ec_nv2,  address_nv2,  ack_multi_nv2,  rx_1byte_nv2,  nb_bit_nv2,  ack_ok_nv2,  registre_nv2,  sda_gnd_nv2,  i2c_mode_nv2  }),
+		.in3({status_nv3,  rx_byte_o_nv3,  stop_cond_nv3,  blktr_idx_nv3,  visual_rst_state_current_nv3,  busy_nv3,  scl_nv3,  sda_nv3,  nb_byte_nv3,  le_ec_nv3,  address_nv3,  ack_multi_nv3,  rx_1byte_nv3,  nb_bit_nv3,  ack_ok_nv3,  registre_nv3,  sda_gnd_nv3,  i2c_mode_nv3  }),
+		.out({status_2,    rx_byte_o_2,    stop_cond_2,    blktr_idx_2,    visual_rst_state_current_2,    busy_2,    scl_2,    sda_2,    nb_byte_2,    le_ec_2,    address_2,    ack_multi_2,    rx_1byte_2,    nb_bit_2,    ack_ok_2,    registre_2,    sda_gnd_2,    i2c_mode_2}   ),
+		.err()
+	);
+	
+	majority_voter #(.WIDTH(57)) mv_3 (
+		.in1({status_nv1,  rx_byte_o_nv1,  stop_cond_nv1,  blktr_idx_nv1,  visual_rst_state_current_nv1,  busy_nv1,  scl_nv1,  sda_nv1,  nb_byte_nv1,  le_ec_nv1,  address_nv1,  ack_multi_nv1,  rx_1byte_nv1,  nb_bit_nv1,  ack_ok_nv1,  registre_nv1,  sda_gnd_nv1,  i2c_mode_nv1  }),
+		.in2({status_nv2,  rx_byte_o_nv2,  stop_cond_nv2,  blktr_idx_nv2,  visual_rst_state_current_nv2,  busy_nv2,  scl_nv2,  sda_nv2,  nb_byte_nv2,  le_ec_nv2,  address_nv2,  ack_multi_nv2,  rx_1byte_nv2,  nb_bit_nv2,  ack_ok_nv2,  registre_nv2,  sda_gnd_nv2,  i2c_mode_nv2  }),
+		.in3({status_nv3,  rx_byte_o_nv3,  stop_cond_nv3,  blktr_idx_nv3,  visual_rst_state_current_nv3,  busy_nv3,  scl_nv3,  sda_nv3,  nb_byte_nv3,  le_ec_nv3,  address_nv3,  ack_multi_nv3,  rx_1byte_nv3,  nb_bit_nv3,  ack_ok_nv3,  registre_nv3,  sda_gnd_nv3,  i2c_mode_nv3  }),
+		.out({status_3,    rx_byte_o_3,    stop_cond_3,    blktr_idx_3,    visual_rst_state_current_3,    busy_3,    scl_3,    sda_3,    nb_byte_3,    le_ec_3,    address_3,    ack_multi_3,    rx_1byte_3,    nb_bit_3,    ack_ok_3,    registre_3,    sda_gnd_3,    i2c_mode_3}   ),
+		.err()
+	);
+	
+	
+		
+endmodule
+
+
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  i_mask_op_fc
+//      Library Name  :  new_i2c_2
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  new_i2c_2
+//  Unit    Name :  i_mask_op_fc
+//  Unit    Type :  Flow Chart
+//  
+//----------------------------------------------------
+ 
+
+module i_mask_op_fc_iostate (mask_in, data_in, data_pass, data_out, op, clk, reset
+                     , visual_0_data_out_i, visual_0_data_out_o);
+ 
+  input [7:0] mask_in;
+  input [7:0] visual_0_data_out_i;
+ 
+ 
+  input [7:0] data_in;
+  input [7:0] data_pass;
+  output [7:0] data_out;
+  output [7:0] visual_0_data_out_o;
+	input [1:0] op;
+  input clk;
+  input reset;
+  reg [7:0] visual_0_data_out_o;
+
+always @( posedge (clk) or posedge (reset) )
+  begin   :mask_op
+
+    if (reset)
+    begin
+        visual_0_data_out_o <= 8'b00000000;
+    end
+    else
+    begin
+      visual_0_data_out_o <= visual_0_data_out_i;
+      if (op == 2'b00)
+      begin
+          visual_0_data_out_o <= data_pass;
+      end
+      else
+      begin
+        if (op == 2'b01)
+        begin
+            visual_0_data_out_o <= (data_in & mask_in);
+        end
+        else
+        begin
+          if (op == 2'b10)
+          begin
+              visual_0_data_out_o <= (data_in | mask_in);
+          end
+          else
+          begin
+            if (op == 2'b11)
+            begin
+                visual_0_data_out_o <= (data_in ^ mask_in);
+            end
+          end
+        end
+      end
+    end
+  end
+ 
+    assign data_out = visual_0_data_out_i;
+ 
+ 
+endmodule
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  i_mask_op_fc
+//      Library Name  :  new_i2c_2
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  new_i2c_2
+//  Unit    Name :  i_mask_op_fc
+//  Unit    Type :  Flow Chart
+//  
+//----------------------------------------------------
+
+module i_mask_op_fc_tri (mask_in_1, mask_in_2, mask_in_3, data_in_1, data_in_2, data_in_3, data_pass_1, data_pass_2, data_pass_3, data_out_1, data_out_2, data_out_3, op_1, op_2, op_3, clk_1, clk_2, clk_3, reset_1, reset_2, reset_3
+                     );
+
+  input [7:0] mask_in_1, mask_in_2, mask_in_3;
+  input [7:0] data_in_1, data_in_2, data_in_3;
+  input [7:0] data_pass_1, data_pass_2, data_pass_3;
+  output [7:0] data_out_1, data_out_2, data_out_3;
+  input [1:0] op_1, op_2, op_3;
+  input clk_1, clk_2, clk_3;
+  input reset_1, reset_2, reset_3;
+
+	wire [7:0] visual_0_data_out_1, visual_0_data_out_2, visual_0_data_out_3;
+	wire [7:0] visual_0_data_out;
+
+	i_mask_op_fc_iostate i_mask_op_fc_iostate_1   (.mask_in(mask_in_1), .data_in(data_in_1), .data_pass(data_pass_1), .data_out(data_out_1), .op(op_1), .clk(clk_1), .reset(reset_1), .visual_0_data_out_i(visual_0_data_out_1), .visual_0_data_out_o(visual_0_data_out_2));
+
+	i_mask_op_fc_iostate i_mask_op_fc_iostate_2   (.mask_in(mask_in_2), .data_in(data_in_2), .data_pass(data_pass_2), .data_out(data_out_2), .op(op_2), .clk(clk_2), .reset(reset_2), .visual_0_data_out_i(visual_0_data_out_2), .visual_0_data_out_o(visual_0_data_out_3));
+
+	i_mask_op_fc_iostate i_mask_op_fc_iostate_3   (.mask_in(mask_in_3), .data_in(data_in_3), .data_pass(data_pass_3), .data_out(data_out_3), .op(op_3), .clk(clk_3), .reset(reset_3), .visual_0_data_out_i(visual_0_data_out_3), .visual_0_data_out_o(visual_0_data_out));
+
+	majority_voter #(.WIDTH(8)) mv (
+		.in1({visual_0_data_out_2}),
+		.in2({visual_0_data_out_3}),
+		.in3({visual_0_data_out}),
+		.out({visual_0_data_out_1}),
+		.err()
+	);
+endmodule
+
+
+// missing: sti2c_out_o <=#1 sti2c_out_i;
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  sync_start
+//      Library Name  :  new_i2c_2
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  new_i2c_2
+//  Unit    Name :  sync_start
+//  Unit    Type :  Flow Chart
+//  
+//----------------------------------------------------
+ 
+
+
+module sync_start_iostate (reset, clk, sti2c_in, sti2c_out_i, sti2c_out_o
+                   );
+
+  input reset;
+  input sti2c_out_i;
+  wire reset;
+  input clk;
+  wire clk;
+  input sti2c_in;
+  wire sti2c_in;
+  output sti2c_out_o;
+	reg sti2c_out_o;
+ 
+ 
+  always
+    @( negedge (clk) or posedge (reset) )
+  begin   :Start
+ 
+    if (reset)
+    begin
+      sti2c_out_o <= 1'b0;
+    end
+    else
+    begin
+      sti2c_out_o <= sti2c_in;
+    end
+  end
+ 
+ 
+ 
+endmodule
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  sync_start
+//      Library Name  :  new_i2c_2
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  new_i2c_2
+//  Unit    Name :  sync_start
+//  Unit    Type :  Flow Chart
+//  
+//----------------------------------------------------
+
+module sync_start_tri (reset_1, reset_2, reset_3, clk_1, clk_2, clk_3, sti2c_in_1, sti2c_in_2, sti2c_in_3, sti2c_out_1, sti2c_out_2, sti2c_out_3
+                   );
+
+  input reset_1, reset_2, reset_3;
+  input clk_1, clk_2, clk_3;
+  input sti2c_in_1, sti2c_in_2, sti2c_in_3;
+  output sti2c_out_1, sti2c_out_2, sti2c_out_3;
+
+	wire sti2c_out_1, sti2c_out_2, sti2c_out_3;
+	wire sti2c_out;
+
+	sync_start_iostate sync_start_iostate_1   (.reset(reset_1), .clk(clk_1), .sti2c_in(sti2c_in_1), .sti2c_out_i(sti2c_out_1), .sti2c_out_o(sti2c_out_2));
+
+	sync_start_iostate sync_start_iostate_2   (.reset(reset_2), .clk(clk_2), .sti2c_in(sti2c_in_2), .sti2c_out_i(sti2c_out_2), .sti2c_out_o(sti2c_out_3));
+
+	sync_start_iostate sync_start_iostate_3   (.reset(reset_3), .clk(clk_3), .sti2c_in(sti2c_in_3), .sti2c_out_i(sti2c_out_3), .sti2c_out_o(sti2c_out));
+
+	majority_voter #(.WIDTH(1)) mv (
+		.in1({sti2c_out_2}),
+		.in2({sti2c_out_3}),
+		.in3({sti2c_out}),
+		.out({sti2c_out_1}),
+		.err()
+	);
+endmodule
+
+
+// missing: visual_res_current_o <=#1 visual_res_current_i;
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  decode_sm_back
+//      Library Name  :  new_i2c_2
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         IF for state selection         :  No
+//         Error (default) state          :  Yes
+//         String typed state variable    :  No
+//         Next state assignments         :  Non blocking
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  new_i2c_2
+//  Unit    Name :  decode_sm_back
+//  Unit    Type :  State Machine
+//  
+//----------------------------------------------------
+
+ 
+module decode_sm_back_iostate (reset, ack_ok_in, clk, cmd_in, nbyte_i, nbyte_o, out_i2c_i, out_i2c_o, i2c_busy,
+                       start_i2c_i, start_i2c_o, crc_ok, occup_i, occup_o, addr_i2c, read_nc, rep_out_i, rep_out_o,
+                       msk_op_i, msk_op_o, SRA_i, SRA_o, SDA_LOW, ext_mode_i, ext_mode_o, i2c_br, EBRDCST,
+                       MultiByte_i, MultiByte_o, nbyte_in, ext_multi_mode_i, ext_multi_mode_o, rw_b_ext_i, rw_b_ext_o,
+                       stop_cond_in
+                       , lire_i2c_i, lire_i2c_o, visual_res_current_i, visual_res_current_o);
+`include "Table_Commande.v"
+ 
+  input reset;
+  input [4:0] visual_res_current_i;
+ 
+ 
+ 
+  input crc_ok;
+  input [7:0] addr_i2c;
+  input read_nc;
+  input rep_out_i;
+  input [1:0] msk_op_i;
+  input [7:0] SRA_i;
+  input SDA_LOW;
+  input i2c_br;
+  input EBRDCST;
+  input lire_i2c_i;
+  input [3:0] nbyte_in;
+  input stop_cond_in;
+  input ack_ok_in;
+  input clk;
+  input [7:0] cmd_in;
+  wire [7:0] cmd_in;
+  output [4:0] nbyte_o;
+	output [4:0] visual_res_current_o;
+	output rw_b_ext_o;
+	output [7:0] out_i2c_o;
+	output start_i2c_o;
+	output occup_o;
+	input occup_i;
+  output rep_out_o;
+	output [1:0] msk_op_o;
+	input [4:0] nbyte_i;
+  output [7:0] SRA_o;
+	output ext_mode_o;
+	input ext_mode_i;
+  output MultiByte_o;
+	input MultiByte_i;        
+  output lire_i2c_o;
+	output ext_multi_mode_o;
+	input ext_multi_mode_i;   
+  input rw_b_ext_i;
+  reg [4:0] nbyte_o;
+  input [7:0] out_i2c_i;
+  reg [7:0] out_i2c_o;
+  input i2c_busy;
+  input start_i2c_i;
+  reg start_i2c_o;
+  wire crc_ok;
+  reg occup_o;
+  wire [7:0] addr_i2c;
+  wire read_nc;
+  reg rep_out_o;
+  reg [1:0] msk_op_o;
+  reg [7:0] SRA_o;
+  wire SDA_LOW;
+  reg ext_mode_o;
+  wire i2c_br;
+  wire EBRDCST;
+  reg MultiByte_o;
+  wire [3:0] nbyte_in;
+  reg ext_multi_mode_o;
+  reg rw_b_ext_o;
+  wire stop_cond_in;
+  reg lire_i2c_o;
+	wire [7:0] com;
+ 
+  parameter res             = 5'b00000,
+            S55             = 5'b00001,
+            S56             = 5'b00010,
+            S58             = 5'b00011,
+            State_start_i2c = 5'b00100,
+            WaitBusy_st     = 5'b00101,
+            a7_out          = 5'b00110,
+            attente         = 5'b00111,
+            lec_cmd         = 5'b01000,
+            rd_wr_err       = 5'b01001,
+            re_nc           = 5'b01010,
+            sen_ad_10bit_2  = 5'b01011,
+            send_ad_10bit   = 5'b01100,
+            tr_cor          = 5'b01101,
+            wait_r_nc       = 5'b01110,
+            RMW_normal      = 5'b01111,
+            RMW_ext         = 5'b10000,
+            att_busy0       = 5'b10001,
+            s13             = 5'b10010,
+            s6              = 5'b10011,
+            start_i2c1      = 5'b10100;
+ 
+ 
+  reg [4:0] visual_res_current_o;
+	// Synchronous process
+  always  @(posedge clk or posedge reset)
+  begin : decode_sm_back_res
+ 
+    if (reset === 1'b1)
+    begin
+      out_i2c_o <= 8'h0;
+      start_i2c_o <= 1'b0;
+      lire_i2c_o <= 1'b0;
+      msk_op_o <= 2'b0;
+      SRA_o <= 8'h0;
+      ext_mode_o <= 1'b0;
+      nbyte_o <= 5'b0;
+      rep_out_o <= 1'b1;
+      MultiByte_o <= 1'b0;
+      occup_o <= 1'b0;
+      ext_multi_mode_o <= 1'b0;
+      rw_b_ext_o <= 1'b0;  // write
+      visual_res_current_o <= res;
+    end
+    else
+    begin
+ 	out_i2c_o <= out_i2c_i;
+      start_i2c_o <= start_i2c_i;
+      lire_i2c_o <= lire_i2c_i;
+      msk_op_o <= msk_op_i;
+      SRA_o <= SRA_i;
+      ext_mode_o <= ext_mode_i;
+      nbyte_o <= nbyte_i;
+      rep_out_o <= rep_out_i;
+      MultiByte_o <= MultiByte_i;
+      occup_o <= occup_i;
+      ext_multi_mode_o <= ext_multi_mode_i;
+      rw_b_ext_o <= rw_b_ext_i;
+      
+      visual_res_current_o <= visual_res_current_i;
+      
+      case (visual_res_current_i)
+        res:
+          begin
+            start_i2c_o <= 1'b0;
+            occup_o <= 1'b0;
+            rep_out_o <= 1'b1;
+            lire_i2c_o <= 1'b0;
+            msk_op_o <= 2'b0;
+            ext_mode_o <= 1'b0;
+            MultiByte_o <= 1'b0;
+            
+            ext_multi_mode_o <= 1'b0;
+            rw_b_ext_o <= 1'b0;  // 28.5.13
+            visual_res_current_o <= attente;
+          end
+ 
+        S55:
+          begin
+            //lire_i2c = 1'b1;
+            start_i2c_o <= 1'b1;
+            SRA_o[6] <= 1'b0;
+            lire_i2c_o <= 1'b1; //19nov2012
+            visual_res_current_o <= State_start_i2c;
+          end
+ 
+        S56:
+          begin
+            visual_res_current_o <= tr_cor;
+          end
+ 
+        S58:
+          begin
+            if (i2c_busy)
+            begin
+              start_i2c_o <= 1'b0;
+              visual_res_current_o <= S58;
+            end
+            else if ((~(i2c_busy)) && (!(ack_ok_in)))
+            begin
+              SRA_o[2] <= 1'b0;
+              SRA_o[6] <= 1'b1;
+              visual_res_current_o <= rd_wr_err;
+            end
+            else if ((~(i2c_busy)) && (!(lire_i2c_i) && ack_ok_in))
+            begin
+              SRA_o[2] <= 1'b1;
+              visual_res_current_o <= S56;
+            end
+            else if ((~(i2c_busy)) && (lire_i2c_i && ack_ok_in))
+            begin
+              SRA_o[2] <= 1'b1;
+              rep_out_o <= 1'b0;
+              visual_res_current_o <= wait_r_nc;
+            end
+            else
+              visual_res_current_o <= S58;
+          end
+ 
+        State_start_i2c:
+          begin
+            start_i2c_o <= 1'b1;
+            visual_res_current_o <= WaitBusy_st;
+          end
+ 
+        WaitBusy_st:
+          begin
+            if (i2c_busy == 1'b0)
+            begin
+              visual_res_current_o <= WaitBusy_st;
+            end
+            else
+            begin
+              visual_res_current_o <= S58;
+            end
+          end
+ 
+        a7_out:
+          begin
+            if (com >= 8'h10 && 8'h15 >= com)
+            begin
+              if (com >= 8'h10 && 8'h12 >= com)
+              begin
+                nbyte_o <= 4'b0010;
+                out_i2c_o[0] <= 1'b1;// addresse[0] = 1 read
+                visual_res_current_o <= RMW_normal;
+              end
+              else if ((com >= 8'h13) && (8'h15 >= com ))
+              begin
+                nbyte_o <= 4'b0011;
+                visual_res_current_o <= RMW_ext;
+              end
+              else
+              begin
+                nbyte_o <= 4'b0010;
+                out_i2c_o[0] <= 1'b1;// addresse[0] = 1 read
+                visual_res_current_o <= RMW_normal;
+              end
+            end
+            else if (com == 8'h0)
+            begin
+              nbyte_o <= 5'b0010;
+              out_i2c_o[0] <= 1'b0;
+              visual_res_current_o <= S55;
+            end
+            else if (com == 8'h2)
+            begin
+              nbyte_o <= 5'b0011;
+              rw_b_ext_o <= 1'b0;//write
+              out_i2c_o[0] <= 1'b0;
+              visual_res_current_o <= S55;
+            end
+            else if (com == 8'h16) 
+            begin
+              MultiByte_o <= 1'b1;
+              if(nbyte_in == 4'h0)
+                  nbyte_o <= 5'h11;  // 29.3.13
+              else
+                  nbyte_o <= {1'b0,nbyte_in}+5'h1 ;
+              out_i2c_o[0] <= 1'b0;
+              visual_res_current_o <= S55;
+            end
+            else if (com == 8'h1)
+            begin
+              nbyte_o <= 5'b0010;
+              out_i2c_o[0] <= 1'b1;
+              //lecture
+              start_i2c_o <= 1'b1;
+              SRA_o[6] <= 1'b0;
+              lire_i2c_o <= 1'b1; //19nov2012
+              visual_res_current_o <= State_start_i2c;
+            end
+            else if (com == 8'h17)
+            begin
+              MultiByte_o <= 1'b1;
+              if(nbyte_in == 4'h0)
+                 nbyte_o <= 5'h11;
+              else
+                 nbyte_o <= {1'b0,nbyte_in} + 5'h1; 
+              out_i2c_o[0] <= 1'b1;
+              //lecture
+              start_i2c_o <= 1'b1;
+              SRA_o[6] <= 1'b0;
+              lire_i2c_o <= 1'b1; //19nov2012
+              visual_res_current_o <= State_start_i2c;
+            end
+            else if (com == {3'b0, I2C_write_multi_ext[6:2]})
+            begin
+              MultiByte_o <= 1'b1;
+              nbyte_o <= {1'b0,nbyte_in} +5'h2;
+              ext_multi_mode_o <= 1'b1;
+              rw_b_ext_o <= 1'b0;
+              out_i2c_o[0] <= 1'b0;
+              visual_res_current_o <= S55;
+            end
+            else if (com == {3'b0, I2C_read_multi_ext[6:2]})
+            begin
+              MultiByte_o <= 1'b1;
+              ext_mode_o <= 1'b1;
+              nbyte_o <=   5'b00010; // pour addr multi
+              ext_multi_mode_o <= 1'b1;
+              start_i2c_o <= 1'b1;
+              rw_b_ext_o <= 1'b1;  //r
+              visual_res_current_o <= send_ad_10bit;
+            end
+            else if (com == 8'h3)
+            begin
+              ext_mode_o <= 1'b1;
+              nbyte_o <= 5'b0010;
+              start_i2c_o <= 1'b1;
+              out_i2c_o[0]<= 1'b0;
+              rw_b_ext_o <= 1'b1; //r
+              visual_res_current_o <= send_ad_10bit;
+            end
+            else
+            begin
+              SRA_o[5]  <= 1'b1;
+              visual_res_current_o <= tr_cor;
+            end
+          end
+ 
+        attente:
+          begin
+            if (crc_ok)
+            begin
+              visual_res_current_o <= attente;
+            end
+            else if (!(crc_ok) && ((i2c_br && EBRDCST) || !(i2c_br)))
+            begin
+              visual_res_current_o <= lec_cmd;
+            end
+            else
+              visual_res_current_o <= attente;
+          end
+ 
+        lec_cmd:
+          begin
+            if (SDA_LOW == 1'b0)
+            begin
+              occup_o <= 1'b1; //nov 2012
+              out_i2c_o <= (addr_i2c << 1);
+              SRA_o[2] <= 1'b0;
+              visual_res_current_o <= a7_out;
+            end
+            else if (SDA_LOW == 1'b1)
+            begin
+              occup_o <= 1'b1; //nov 2012
+              
+              SRA_o <= 8'h08;
+              
+              rep_out_o <= 1'b0;
+              visual_res_current_o <= wait_r_nc;
+            end
+            else
+              visual_res_current_o <= lec_cmd;
+          end
+ 
+        rd_wr_err:
+          begin
+            rep_out_o <= 1'b0;
+            visual_res_current_o <= wait_r_nc;
+          end
+ 
+        re_nc:
+          begin
+            if (read_nc)
+            begin
+              visual_res_current_o <= re_nc;
+            end
+            else if (!(read_nc))
+            begin
+              visual_res_current_o <= tr_cor;
+            end
+            else
+              visual_res_current_o <= re_nc;
+          end
+ 
+        sen_ad_10bit_2:
+          begin
+            if (i2c_busy)
+            begin
+              visual_res_current_o <= sen_ad_10bit_2;
+            end
+            else if (!(i2c_busy) && !(stop_cond_in))
+            begin
+              nbyte_o <= 5'h8;
+              
+              out_i2c_o[0] <= 1'b1;
+              if(com == {3'b0,I2C_read_multi_ext[6:2]})
+                  nbyte_o <= {1'b0,nbyte_in}+ 5'h1;
+              else
+                  nbyte_o <= 5'h2;
+              start_i2c_o <= 1'b1;
+              SRA_o[6] <= 1'b0;
+              lire_i2c_o <= 1'b1; //19nov2012
+              visual_res_current_o <= State_start_i2c;
+            end
+            else if (stop_cond_in)
+            begin
+              rep_out_o <= 1'b0;
+              visual_res_current_o <= wait_r_nc;
+            end
+            else
+              visual_res_current_o <= sen_ad_10bit_2;
+          end
+ 
+        send_ad_10bit:
+          begin
+            if (!(i2c_busy))
+            begin
+              visual_res_current_o <= send_ad_10bit;
+            end
+            else if (i2c_busy)
+            begin
+              visual_res_current_o <= sen_ad_10bit_2;
+            end
+            else
+              visual_res_current_o <= send_ad_10bit;
+          end
+ 
+        tr_cor:
+          begin
+            start_i2c_o <= 1'b0;
+            occup_o <= 1'b0;
+            rep_out_o <= 1'b1;
+            lire_i2c_o <= 1'b0;
+            msk_op_o <= 2'b0;
+            ext_mode_o <= 1'b0;
+            MultiByte_o <= 1'b0;
+            ext_multi_mode_o <= 1'b0;
+            rw_b_ext_o <= 1'b0;  // 28.5.13
+            visual_res_current_o <= attente;
+          end
+ 
+        wait_r_nc:
+          begin
+            if (read_nc)
+            begin
+              visual_res_current_o <= re_nc;
+            end
+            else if (!(read_nc))
+            begin
+              visual_res_current_o <= wait_r_nc;
+            end
+            else
+              visual_res_current_o <= wait_r_nc;
+          end
+ 
+        RMW_normal:
+          begin
+             start_i2c_o <= 1'b1;
+            visual_res_current_o <= start_i2c1;
+          end
+ 
+        RMW_ext:
+          begin
+             start_i2c_o <= 1'b1;
+            visual_res_current_o <= start_i2c1;
+          end
+ 
+        att_busy0:
+          begin
+            if (i2c_busy)
+            begin
+              visual_res_current_o <= s6;
+            end
+            else if (!(i2c_busy))
+            begin
+              visual_res_current_o <= att_busy0;
+            end
+            else
+              visual_res_current_o <= att_busy0;
+          end
+ 
+        s13:
+          begin
+            if (ack_ok_in)
+            begin
+              
+              visual_res_current_o <= S55;
+            end
+            else if (!(ack_ok_in))
+            begin
+              
+              SRA_o[6] <= 1'b1;
+              visual_res_current_o <= rd_wr_err;
+            end
+            else
+            begin
+              
+              if ((com >= 8'h10) && (8'h12 >= com))
+              begin
+                nbyte_o <= 4'b0010;
+                out_i2c_o[0] <= 1'b1;// addresse[0] = 1 read
+                visual_res_current_o <= RMW_normal;
+              end
+              else if ((com >= 8'h13) && (8'h15 >= com))
+              begin
+                nbyte_o <= 4'b0011;
+                visual_res_current_o <= RMW_ext;
+              end
+              else
+              begin
+                nbyte_o <= 4'b0010;
+                out_i2c_o[0] <= 1'b1;// addresse[0] = 1 read
+                visual_res_current_o <= RMW_normal;
+              end
+            end
+          end
+ 
+        s6:
+          begin
+            if (i2c_busy)
+            begin
+              visual_res_current_o <= s6;
+            end
+            else if (((ack_ok_in) && !(i2c_busy)) && ((cmd_in == 8'h10) || (
+                     cmd_in == 8'h13)))
+            begin
+              start_i2c_o <= 1'b0;
+              msk_op_o <= 2'b01;
+              out_i2c_o[0] <= 1'b0;
+              visual_res_current_o <= s13;
+            end
+            else if (((ack_ok_in) && !(i2c_busy)) && ((cmd_in == 8'h11) || (
+                     cmd_in == 8'h14)))
+            begin
+              start_i2c_o <= 1'b0;
+              msk_op_o <= 2'b10;
+              out_i2c_o[0] <= 1'b0;
+              visual_res_current_o <= s13;
+            end
+            else if (((ack_ok_in) && !(i2c_busy)) && ((cmd_in == 8'h12) || (
+                     cmd_in == 8'h15)))
+            begin
+              start_i2c_o <= 1'b0;
+              msk_op_o <= 2'b11;
+              out_i2c_o[0] <= 1'b0;
+              visual_res_current_o <= s13;
+            end
+            else if ((!(ack_ok_in)) && !(i2c_busy))
+            begin
+              if (ack_ok_in)
+              begin
+                start_i2c_o <= 1'b0;
+                visual_res_current_o <= S55;
+              end
+              else if (!(ack_ok_in))
+              begin
+                start_i2c_o <= 1'b0;
+                SRA_o[6] <= 1'b1;
+                visual_res_current_o <= rd_wr_err;
+              end
+              else
+              begin
+                start_i2c_o <= 1'b0;
+                if (com >= 8'h10 && 8'h12 >= com)
+                begin
+                  nbyte_o <= 4'b0010;
+                  out_i2c_o[0] <= 1'b1;// addresse[0] = 1 read
+                  visual_res_current_o <= RMW_normal;
+                end
+                else if ((com >= 8'h13) && (8'h15 >= com))
+                begin
+                  nbyte_o <= 4'b0011;
+                  visual_res_current_o <= RMW_ext;
+                end
+                else
+                begin
+                  nbyte_o <= 4'b0010;
+                  out_i2c_o[0] <= 1'b1;// addresse[0] = 1 read
+                  visual_res_current_o <= RMW_normal;
+                end
+              end
+            end
+            else
+              visual_res_current_o <= s6;
+          end
+ 
+        start_i2c1:
+          begin
+            visual_res_current_o <= att_busy0;
+          end
+ 
+        default:
+          begin
+            out_i2c_o <= 8'h0;
+            start_i2c_o <= 1'b0;
+            lire_i2c_o <= 1'b0;
+            msk_op_o <= 2'b0;
+            SRA_o <= 8'h0;
+            ext_mode_o <= 1'b0;
+            nbyte_o <= 5'b0;
+            
+            rep_out_o <= 1'b1;
+            MultiByte_o <= 1'b0;
+            occup_o <= 1'b0;
+            ext_multi_mode_o <= 1'b0;
+            rw_b_ext_o <= 1'b0;  // write
+            visual_res_current_o <= res;
+          end
+      endcase
+    end
+  end
+ 
+  assign com[7:0] = cmd_in[7:0];
+ 
+ 
+endmodule
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  decode_sm_back
+//      Library Name  :  new_i2c_2
+//  
+//      Creation Date :  Mon Jun 24 09:42:13 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         IF for state selection         :  No
+//         Error (default_1, default_2, default_3) state          :  Yes
+//         String typed state variable    :  No
+//         Next state assignments         :  Non blocking
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  new_i2c_2
+//  Unit    Name :  decode_sm_back
+//  Unit    Type :  State Machine
+//  
+//----------------------------------------------------
+
+module decode_sm_back_tri (reset_1, reset_2, reset_3, ack_ok_in_1, ack_ok_in_2, ack_ok_in_3, clk_1, clk_2, clk_3, cmd_in_1, cmd_in_2, cmd_in_3, nbyte_1, nbyte_2, nbyte_3, out_i2c_1, out_i2c_2, out_i2c_3, i2c_busy_1, i2c_busy_2, i2c_busy_3,
+                       start_i2c_1, start_i2c_2, start_i2c_3, crc_ok_1, crc_ok_2, crc_ok_3, occup_1, occup_2, occup_3, addr_i2c_1, addr_i2c_2, addr_i2c_3, read_nc_1, read_nc_2, read_nc_3, rep_out_1, rep_out_2, rep_out_3,
+                       msk_op_1, msk_op_2, msk_op_3, SRA_1, SRA_2, SRA_3, SDA_LOW_1, SDA_LOW_2, SDA_LOW_3, ext_mode_1, ext_mode_2, ext_mode_3, i2c_br_1, i2c_br_2, i2c_br_3, EBRDCST_1, EBRDCST_2, EBRDCST_3,
+                       MultiByte_1, MultiByte_2, MultiByte_3, nbyte_in_1, nbyte_in_2, nbyte_in_3, ext_multi_mode_1, ext_multi_mode_2, ext_multi_mode_3, rw_b_ext_1, rw_b_ext_2, rw_b_ext_3,
+                       stop_cond_in_1, stop_cond_in_2, stop_cond_in_3
+                       );
+
+`include "Table_Commande.v"
+
+  input reset_1, reset_2, reset_3;
+  input ack_ok_in_1, ack_ok_in_2, ack_ok_in_3;
+  input clk_1, clk_2, clk_3;
+  input [7:0] cmd_in_1, cmd_in_2, cmd_in_3;
+  output [4:0] nbyte_1, nbyte_2, nbyte_3;
+  output [7:0] out_i2c_1, out_i2c_2, out_i2c_3;
+  input i2c_busy_1, i2c_busy_2, i2c_busy_3;
+  output start_i2c_1, start_i2c_2, start_i2c_3;
+  input crc_ok_1, crc_ok_2, crc_ok_3;
+  output occup_1, occup_2, occup_3;
+  input [7:0] addr_i2c_1, addr_i2c_2, addr_i2c_3;
+  input read_nc_1, read_nc_2, read_nc_3;
+  output rep_out_1, rep_out_2, rep_out_3;
+  output [1:0] msk_op_1, msk_op_2, msk_op_3;
+  output [7:0] SRA_1, SRA_2, SRA_3;
+  input SDA_LOW_1, SDA_LOW_2, SDA_LOW_3;
+  output ext_mode_1, ext_mode_2, ext_mode_3;
+  input i2c_br_1, i2c_br_2, i2c_br_3;
+  input EBRDCST_1, EBRDCST_2, EBRDCST_3;
+  output MultiByte_1, MultiByte_2, MultiByte_3;        
+  input [3:0] nbyte_in_1, nbyte_in_2, nbyte_in_3;
+  output ext_multi_mode_1, ext_multi_mode_2, ext_multi_mode_3;   
+  output rw_b_ext_1, rw_b_ext_2, rw_b_ext_3;
+  input stop_cond_in_1, stop_cond_in_2, stop_cond_in_3;
+
+	wire [7:0] out_i2c_1, out_i2c_2, out_i2c_3;
+	wire start_i2c_1, start_i2c_2, start_i2c_3;
+	wire lire_i2c_1, lire_i2c_2, lire_i2c_3;
+	wire [1:0] msk_op_1, msk_op_2, msk_op_3;
+	wire [7:0] SRA_1, SRA_2, SRA_3;
+	wire ext_mode_1, ext_mode_2, ext_mode_3;
+	wire [4:0] nbyte_1, nbyte_2, nbyte_3;
+	wire rep_out_1, rep_out_2, rep_out_3;
+	wire MultiByte_1, MultiByte_2, MultiByte_3;
+	wire occup_1, occup_2, occup_3;
+	wire ext_multi_mode_1, ext_multi_mode_2, ext_multi_mode_3;
+	wire rw_b_ext_1, rw_b_ext_2, rw_b_ext_3;
+	wire [4:0] visual_res_current_1, visual_res_current_2, visual_res_current_3;
+	wire [7:0] out_i2c;
+	wire start_i2c;
+	wire lire_i2c;
+	wire [1:0] msk_op;
+	wire [7:0] SRA;
+	wire ext_mode;
+	wire [4:0] nbyte;
+	wire rep_out;
+	wire MultiByte;
+	wire occup;
+	wire ext_multi_mode;
+	wire rw_b_ext;
+	wire [4:0] visual_res_current;
+
+	decode_sm_back_iostate decode_sm_back_iostate_1   (.reset(reset_1), .ack_ok_in(ack_ok_in_1), .clk(clk_1), .cmd_in(cmd_in_1), .nbyte_i(nbyte_1), .nbyte_o(nbyte_2), .out_i2c_i(out_i2c_1), .out_i2c_o(out_i2c_2), .i2c_busy(i2c_busy_1),
+                       .start_i2c_i(start_i2c_1), .start_i2c_o(start_i2c_2), .crc_ok(crc_ok_1), .occup_i(occup_1), .occup_o(occup_2), .addr_i2c(addr_i2c_1), .read_nc(read_nc_1), .rep_out_i(rep_out_1), .rep_out_o(rep_out_2),
+                       .msk_op_i(msk_op_1), .msk_op_o(msk_op_2), .SRA_i(SRA_1), .SRA_o(SRA_2), .SDA_LOW(SDA_LOW_1), .ext_mode_i(ext_mode_1), .ext_mode_o(ext_mode_2), .i2c_br(i2c_br_1), .EBRDCST(EBRDCST_1),
+                       .MultiByte_i(MultiByte_1), .MultiByte_o(MultiByte_2), .nbyte_in(nbyte_in_1), .ext_multi_mode_i(ext_multi_mode_1), .ext_multi_mode_o(ext_multi_mode_2), .rw_b_ext_i(rw_b_ext_1), .rw_b_ext_o(rw_b_ext_2),
+                       .stop_cond_in(stop_cond_in_1), .lire_i2c_i(lire_i2c_1), .lire_i2c_o(lire_i2c_2), .visual_res_current_i(visual_res_current_1), .visual_res_current_o(visual_res_current_2));
+
+	decode_sm_back_iostate decode_sm_back_iostate_2   (.reset(reset_2), .ack_ok_in(ack_ok_in_2), .clk(clk_2), .cmd_in(cmd_in_2), .nbyte_i(nbyte_2), .nbyte_o(nbyte_3), .out_i2c_i(out_i2c_2), .out_i2c_o(out_i2c_3), .i2c_busy(i2c_busy_2),
+                       .start_i2c_i(start_i2c_2), .start_i2c_o(start_i2c_3), .crc_ok(crc_ok_2), .occup_i(occup_2), .occup_o(occup_3), .addr_i2c(addr_i2c_2), .read_nc(read_nc_2), .rep_out_i(rep_out_2), .rep_out_o(rep_out_3),
+                       .msk_op_i(msk_op_2), .msk_op_o(msk_op_3), .SRA_i(SRA_2), .SRA_o(SRA_3), .SDA_LOW(SDA_LOW_2), .ext_mode_i(ext_mode_2), .ext_mode_o(ext_mode_3), .i2c_br(i2c_br_2), .EBRDCST(EBRDCST_2),
+                       .MultiByte_i(MultiByte_2), .MultiByte_o(MultiByte_3), .nbyte_in(nbyte_in_2), .ext_multi_mode_i(ext_multi_mode_2), .ext_multi_mode_o(ext_multi_mode_3), .rw_b_ext_i(rw_b_ext_2), .rw_b_ext_o(rw_b_ext_3),
+                       .stop_cond_in(stop_cond_in_2), .lire_i2c_i(lire_i2c_2), .lire_i2c_o(lire_i2c_3), .visual_res_current_i(visual_res_current_2), .visual_res_current_o(visual_res_current_3));
+
+	decode_sm_back_iostate decode_sm_back_iostate_3   (.reset(reset_3), .ack_ok_in(ack_ok_in_3), .clk(clk_3), .cmd_in(cmd_in_3), .nbyte_i(nbyte_3), .nbyte_o(nbyte), .out_i2c_i(out_i2c_3), .out_i2c_o(out_i2c), .i2c_busy(i2c_busy_3),
+                       .start_i2c_i(start_i2c_3), .start_i2c_o(start_i2c), .crc_ok(crc_ok_3), .occup_i(occup_3), .occup_o(occup), .addr_i2c(addr_i2c_3), .read_nc(read_nc_3), .rep_out_i(rep_out_3), .rep_out_o(rep_out),
+                       .msk_op_i(msk_op_3), .msk_op_o(msk_op), .SRA_i(SRA_3), .SRA_o(SRA), .SDA_LOW(SDA_LOW_3), .ext_mode_i(ext_mode_3), .ext_mode_o(ext_mode), .i2c_br(i2c_br_3), .EBRDCST(EBRDCST_3),
+                       .MultiByte_i(MultiByte_3), .MultiByte_o(MultiByte), .nbyte_in(nbyte_in_3), .ext_multi_mode_i(ext_multi_mode_3), .ext_multi_mode_o(ext_multi_mode), .rw_b_ext_i(rw_b_ext_3), .rw_b_ext_o(rw_b_ext),
+                       .stop_cond_in(stop_cond_in_3), .lire_i2c_i(lire_i2c_3), .lire_i2c_o(lire_i2c), .visual_res_current_i(visual_res_current_3), .visual_res_current_o(visual_res_current));
+
+	majority_voter #(.WIDTH(36)) mv (
+		.in1({out_i2c_2, start_i2c_2, lire_i2c_2, msk_op_2, SRA_2, ext_mode_2, nbyte_2, rep_out_2, MultiByte_2, occup_2, ext_multi_mode_2, rw_b_ext_2, visual_res_current_2}),
+		.in2({out_i2c_3, start_i2c_3, lire_i2c_3, msk_op_3, SRA_3, ext_mode_3, nbyte_3, rep_out_3, MultiByte_3, occup_3, ext_multi_mode_3, rw_b_ext_3, visual_res_current_3}),
+		.in3({out_i2c,   start_i2c,   lire_i2c,   msk_op,   SRA,   ext_mode,   nbyte,   rep_out,   MultiByte,   occup,   ext_multi_mode, rw_b_ext, visual_res_current}),
+		.out({out_i2c_1, start_i2c_1, lire_i2c_1, msk_op_1, SRA_1, ext_mode_1, nbyte_1, rep_out_1, MultiByte_1, occup_1, ext_multi_mode_1, rw_b_ext_1, visual_res_current_1}),
+		.err()
+	);
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/vldb/code/Testbench/SCA-model/I2C_generate.v b/vldb/code/Testbench/SCA-model/I2C_generate.v
new file mode 100644
index 0000000..f280391
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/I2C_generate.v
@@ -0,0 +1,1054 @@
+
+
+module i2c_gener_tri (
+                input  [15:0]  reset_1,
+                input  [15:0]  reset_2,
+                input  [15:0]  reset_3,
+                input  [15:0]  clock_1,
+                input  [15:0]  clock_2,
+                input  [15:0]  clock_3,
+                input [31:0]   wb_stb_i_1,
+                input [31:0]   wb_stb_i_2,
+                input [31:0]   wb_stb_i_3,
+                input          wb_we_1 ,
+                input          wb_we_2 ,
+                input          wb_we_3 ,
+                input          wb_cyc_1,
+                input          wb_cyc_2,
+                input          wb_cyc_3,
+                input   [3:0]  wb_sel_1,
+                input   [3:0]  wb_sel_2,
+                input   [3:0]  wb_sel_3,
+                input  [31:0]  wb_dat_i_1,
+                input  [31:0]  wb_dat_i_2,
+                input  [31:0]  wb_dat_i_3,
+                input   [4:0]  wb_adr_i_1,
+                input   [4:0]  wb_adr_i_2,
+                input   [4:0]  wb_adr_i_3,
+                input  [15:0]  SDA_in_1,
+                input  [15:0]  SDA_in_2,
+                input  [15:0]  SDA_in_3,
+                output [15:0]  SCL_1,
+                output [15:0]  SCL_2,
+                output [15:0]  SCL_3,
+                output [15:0]  SDA_OUT_1,
+                output [15:0]  SDA_OUT_2,
+                output [15:0]  SDA_OUT_3,
+		output [15:0]  SCLEN_1,
+		output [15:0]  SCLEN_2,
+		output [15:0]  SCLEN_3,		
+                output [31:0]  wb_dat_o0_1 , 
+                output [31:0]  wb_dat_o0_2 , 
+                output [31:0]  wb_dat_o0_3 , 
+                output [31:0]  wb_dat_o1_1,
+                output [31:0]  wb_dat_o1_2,
+                output [31:0]  wb_dat_o1_3,
+                output [31:0]  wb_dat_o2_1,
+                output [31:0]  wb_dat_o2_2,
+                output [31:0]  wb_dat_o2_3,
+                output [31:0]  wb_dat_o3_1,
+                output [31:0]  wb_dat_o3_2,
+                output [31:0]  wb_dat_o3_3,
+                output [31:0]  wb_dat_o4_1,
+                output [31:0]  wb_dat_o4_2,
+                output [31:0]  wb_dat_o4_3,
+                output [31:0]  wb_dat_o5_1,
+                output [31:0]  wb_dat_o5_2,
+                output [31:0]  wb_dat_o5_3,
+                output [31:0]  wb_dat_o6_1,
+                output [31:0]  wb_dat_o6_2,
+                output [31:0]  wb_dat_o6_3,
+                output [31:0]  wb_dat_o7_1,
+                output [31:0]  wb_dat_o7_2,
+                output [31:0]  wb_dat_o7_3,
+                output [31:0]  wb_dat_o8_1,
+                output [31:0]  wb_dat_o8_2,
+                output [31:0]  wb_dat_o8_3,
+                output [31:0]  wb_dat_o9_1,
+                output [31:0]  wb_dat_o9_2,
+                output [31:0]  wb_dat_o9_3,
+                output [31:0]  wb_dat_o10_1,
+                output [31:0]  wb_dat_o10_2,
+                output [31:0]  wb_dat_o10_3,
+                output [31:0]  wb_dat_o11_1,
+                output [31:0]  wb_dat_o11_2,
+                output [31:0]  wb_dat_o11_3,
+                output [31:0]  wb_dat_o12_1,
+                output [31:0]  wb_dat_o12_2,
+                output [31:0]  wb_dat_o12_3,
+                output [31:0]  wb_dat_o13_1,
+                output [31:0]  wb_dat_o13_2,
+                output [31:0]  wb_dat_o13_3,
+                output [31:0]  wb_dat_o14_1,
+                output [31:0]  wb_dat_o14_2,
+                output [31:0]  wb_dat_o14_3,
+                output [31:0]  wb_dat_o15_1,
+                output [31:0]  wb_dat_o15_2,
+                output [31:0]  wb_dat_o15_3,
+                output         wb_ack_out_1,
+                output         wb_ack_out_2,
+                output         wb_ack_out_3,
+                output [15:0]  wb_i2c_int_1,
+                output [15:0]  wb_i2c_int_2,
+                output [15:0]  wb_i2c_int_3
+);
+
+wire [31:0]  bus_1 [15:0];
+wire [31:0]  bus_2 [15:0];
+wire [31:0]  bus_3 [15:0];
+wire [15:0]  wb_ack_i2c_1;
+wire [15:0]  wb_ack_i2c_2;
+wire [15:0]  wb_ack_i2c_3;
+
+wb_i2c_tri i2c_ch_0 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[0]),
+                  .wb_rst_i_1(reset_1[0]),
+                  .wb_stb_i_1(wb_stb_i_1[2]),
+                  .wb_dat_o_1(bus_1[0]),
+                  .wb_ack_o_1(wb_ack_i2c_1[0]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[0]),
+                  .sda_in_1(SDA_in_1[0]),
+                  .wb_int_o_1(wb_i2c_int_1[0]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),                  
+                  .sda_out_1(SDA_OUT_1[0]),		  
+                  
+                  .wb_clk_i_2(clock_2[0]),
+                  .wb_rst_i_2(reset_2[0]),
+                  .wb_stb_i_2(wb_stb_i_2[2]),
+                  .wb_dat_o_2(bus_2[0]),
+                  .wb_ack_o_2(wb_ack_i2c_2[0]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[0]),
+                  .sda_in_2(SDA_in_2[0]),
+                  .wb_int_o_2(wb_i2c_int_2[0]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),                  
+                  .sda_out_2(SDA_OUT_2[0]),
+                  
+                  .wb_clk_i_3(clock_3[0]),
+                  .wb_rst_i_3(reset_3[0]),
+                  .wb_stb_i_3(wb_stb_i_3[2]),
+                  .wb_dat_o_3(bus_3[0]),
+                  .wb_ack_o_3(wb_ack_i2c_3[0]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[0]),
+                  .sda_in_3(SDA_in_3[0]),
+                  .wb_int_o_3(wb_i2c_int_3[0]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[0]),
+		  
+		  .sclen_1(SCLEN_1[0]),
+		  .sclen_2(SCLEN_2[0]),
+		  .sclen_3(SCLEN_3[0])
+		  
+);
+
+
+wb_i2c_tri i2c_ch_1 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[1]),
+                  .wb_rst_i_1(reset_1[1]),
+                  .wb_stb_i_1(wb_stb_i_1[3]),
+                  .wb_dat_o_1(bus_1[1]),
+                  .wb_ack_o_1(wb_ack_i2c_1[1]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[1]),
+                  .sda_in_1(SDA_in_1[1]),
+                  .wb_int_o_1(wb_i2c_int_1[1]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[1]),
+                  .wb_clk_i_2(clock_2[1]),
+                  .wb_rst_i_2(reset_2[1]),
+                  .wb_stb_i_2(wb_stb_i_2[3]),
+                  .wb_dat_o_2(bus_2[1]),
+                  .wb_ack_o_2(wb_ack_i2c_2[1]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[1]),
+                  .sda_in_2(SDA_in_2[1]),
+                  .wb_int_o_2(wb_i2c_int_2[1]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[1]),
+                  .wb_clk_i_3(clock_3[1]),
+                  .wb_rst_i_3(reset_3[1]),
+                  .wb_stb_i_3(wb_stb_i_3[3]),
+                  .wb_dat_o_3(bus_3[1]),
+                  .wb_ack_o_3(wb_ack_i2c_3[1]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[1]),
+                  .sda_in_3(SDA_in_3[1]),
+                  .wb_int_o_3(wb_i2c_int_3[1]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[1]),
+		  
+		  .sclen_1(SCLEN_1[1]),
+		  .sclen_2(SCLEN_2[1]),
+		  .sclen_3(SCLEN_3[1])
+);
+
+
+wb_i2c_tri i2c_ch_2 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[2]),
+                  .wb_rst_i_1(reset_1[2]),
+                  .wb_stb_i_1(wb_stb_i_1[4]),
+                  .wb_dat_o_1(bus_1[2]),
+                  .wb_ack_o_1(wb_ack_i2c_1[2]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[2]),
+                  .sda_in_1(SDA_in_1[2]),
+                  .wb_int_o_1(wb_i2c_int_1[2]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[2]),
+                  .wb_clk_i_2(clock_2[2]),
+                  .wb_rst_i_2(reset_2[2]),
+                  .wb_stb_i_2(wb_stb_i_2[4]),
+                  .wb_dat_o_2(bus_2[2]),
+                  .wb_ack_o_2(wb_ack_i2c_2[2]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[2]),
+                  .sda_in_2(SDA_in_2[2]),
+                  .wb_int_o_2(wb_i2c_int_2[2]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[2]),
+                  .wb_clk_i_3(clock_3[2]),
+                  .wb_rst_i_3(reset_3[2]),
+                  .wb_stb_i_3(wb_stb_i_3[4]),
+                  .wb_dat_o_3(bus_3[2]),
+                  .wb_ack_o_3(wb_ack_i2c_3[2]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[2]),
+                  .sda_in_3(SDA_in_3[2]),
+                  .wb_int_o_3(wb_i2c_int_3[2]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[2]),
+		  
+		  .sclen_1(SCLEN_1[2]),
+		  .sclen_2(SCLEN_2[2]),
+		  .sclen_3(SCLEN_3[2])
+);
+
+
+wb_i2c_tri i2c_ch_3 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[3]),
+                  .wb_rst_i_1(reset_1[3]),
+                  .wb_stb_i_1(wb_stb_i_1[5]),
+                  .wb_dat_o_1(bus_1[3]),
+                  .wb_ack_o_1(wb_ack_i2c_1[3]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[3]),
+                  .sda_in_1(SDA_in_1[3]),
+                  .wb_int_o_1(wb_i2c_int_1[3]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[3]),
+                  .wb_clk_i_2(clock_2[3]),
+                  .wb_rst_i_2(reset_2[3]),
+                  .wb_stb_i_2(wb_stb_i_2[5]),
+                  .wb_dat_o_2(bus_2[3]),
+                  .wb_ack_o_2(wb_ack_i2c_2[3]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[3]),
+                  .sda_in_2(SDA_in_2[3]),
+                  .wb_int_o_2(wb_i2c_int_2[3]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[3]),
+                  .wb_clk_i_3(clock_3[3]),
+                  .wb_rst_i_3(reset_3[3]),
+                  .wb_stb_i_3(wb_stb_i_3[5]),
+                  .wb_dat_o_3(bus_3[3]),
+                  .wb_ack_o_3(wb_ack_i2c_3[3]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[3]),
+                  .sda_in_3(SDA_in_3[3]),
+                  .wb_int_o_3(wb_i2c_int_3[3]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[3]),
+		  
+		  .sclen_1(SCLEN_1[3]),
+		  .sclen_2(SCLEN_2[3]),
+		  .sclen_3(SCLEN_3[3])
+);
+
+
+wb_i2c_tri i2c_ch_4 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[4]),
+                  .wb_rst_i_1(reset_1[4]),
+                  .wb_stb_i_1(wb_stb_i_1[6]),
+                  .wb_dat_o_1(bus_1[4]),
+                  .wb_ack_o_1(wb_ack_i2c_1[4]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[4]),
+                  .sda_in_1(SDA_in_1[4]),
+                  .wb_int_o_1(wb_i2c_int_1[4]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[4]),
+                  .wb_clk_i_2(clock_2[4]),
+                  .wb_rst_i_2(reset_2[4]),
+                  .wb_stb_i_2(wb_stb_i_2[6]),
+                  .wb_dat_o_2(bus_2[4]),
+                  .wb_ack_o_2(wb_ack_i2c_2[4]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[4]),
+                  .sda_in_2(SDA_in_2[4]),
+                  .wb_int_o_2(wb_i2c_int_2[4]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[4]),
+                  .wb_clk_i_3(clock_3[4]),
+                  .wb_rst_i_3(reset_3[4]),
+                  .wb_stb_i_3(wb_stb_i_3[6]),
+                  .wb_dat_o_3(bus_3[4]),
+                  .wb_ack_o_3(wb_ack_i2c_3[4]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[4]),
+                  .sda_in_3(SDA_in_3[4]),
+                  .wb_int_o_3(wb_i2c_int_3[4]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  
+                  .sda_out_3(SDA_OUT_3[4]),
+		  
+		  .sclen_1(SCLEN_1[4]),
+		  .sclen_2(SCLEN_2[4]),
+		  .sclen_3(SCLEN_3[4])
+);
+
+
+wb_i2c_tri i2c_ch_5 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[5]),
+                  .wb_rst_i_1(reset_1[5]),
+                  .wb_stb_i_1(wb_stb_i_1[7]),
+                  .wb_dat_o_1(bus_1[5]),
+                  .wb_ack_o_1(wb_ack_i2c_1[5]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[5]),
+                  .sda_in_1(SDA_in_1[5]),
+                  .wb_int_o_1(wb_i2c_int_1[5]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[5]),
+                  .wb_clk_i_2(clock_2[5]),
+                  .wb_rst_i_2(reset_2[5]),
+                  .wb_stb_i_2(wb_stb_i_2[7]),
+                  .wb_dat_o_2(bus_2[5]),
+                  .wb_ack_o_2(wb_ack_i2c_2[5]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[5]),
+                  .sda_in_2(SDA_in_2[5]),
+                  .wb_int_o_2(wb_i2c_int_2[5]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[5]),
+                  .wb_clk_i_3(clock_3[5]),
+                  .wb_rst_i_3(reset_3[5]),
+                  .wb_stb_i_3(wb_stb_i_3[7]),
+                  .wb_dat_o_3(bus_3[5]),
+                  .wb_ack_o_3(wb_ack_i2c_3[5]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[5]),
+                  .sda_in_3(SDA_in_3[5]),
+                  .wb_int_o_3(wb_i2c_int_3[5]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[5]),
+		  
+		  .sclen_1(SCLEN_1[5]),
+		  .sclen_2(SCLEN_2[5]),
+		  .sclen_3(SCLEN_3[5])
+);
+
+
+wb_i2c_tri i2c_ch_6 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[6]),
+                  .wb_rst_i_1(reset_1[6]),
+                  .wb_stb_i_1(wb_stb_i_1[8]),
+                  .wb_dat_o_1(bus_1[6]),
+                  .wb_ack_o_1(wb_ack_i2c_1[6]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[6]),
+                  .sda_in_1(SDA_in_1[6]),
+                  .wb_int_o_1(wb_i2c_int_1[6]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[6]),
+                  .wb_clk_i_2(clock_2[6]),
+                  .wb_rst_i_2(reset_2[6]),
+                  .wb_stb_i_2(wb_stb_i_2[8]),
+                  .wb_dat_o_2(bus_2[6]),
+                  .wb_ack_o_2(wb_ack_i2c_2[6]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[6]),
+                  .sda_in_2(SDA_in_2[6]),
+                  .wb_int_o_2(wb_i2c_int_2[6]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[6]),
+                  .wb_clk_i_3(clock_3[6]),
+                  .wb_rst_i_3(reset_3[6]),
+                  .wb_stb_i_3(wb_stb_i_3[8]),
+                  .wb_dat_o_3(bus_3[6]),
+                  .wb_ack_o_3(wb_ack_i2c_3[6]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[6]),
+                  .sda_in_3(SDA_in_3[6]),
+                  .wb_int_o_3(wb_i2c_int_3[6]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[6]),
+		  
+		  .sclen_1(SCLEN_1[6]),
+		  .sclen_2(SCLEN_2[6]),
+		  .sclen_3(SCLEN_3[6])
+);
+
+
+wb_i2c_tri i2c_ch_7 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[7]),
+                  .wb_rst_i_1(reset_1[7]),
+                  .wb_stb_i_1(wb_stb_i_1[9]),
+                  .wb_dat_o_1(bus_1[7]),
+                  .wb_ack_o_1(wb_ack_i2c_1[7]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[7]),
+                  .sda_in_1(SDA_in_1[7]),
+                  .wb_int_o_1(wb_i2c_int_1[7]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[7]),
+                  .wb_clk_i_2(clock_2[7]),
+                  .wb_rst_i_2(reset_2[7]),
+                  .wb_stb_i_2(wb_stb_i_2[9]),
+                  .wb_dat_o_2(bus_2[7]),
+                  .wb_ack_o_2(wb_ack_i2c_2[7]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[7]),
+                  .sda_in_2(SDA_in_2[7]),
+                  .wb_int_o_2(wb_i2c_int_2[7]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[7]),
+                  .wb_clk_i_3(clock_3[7]),
+                  .wb_rst_i_3(reset_3[7]),
+                  .wb_stb_i_3(wb_stb_i_3[9]),
+                  .wb_dat_o_3(bus_3[7]),
+                  .wb_ack_o_3(wb_ack_i2c_3[7]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[7]),
+                  .sda_in_3(SDA_in_3[7]),
+                  .wb_int_o_3(wb_i2c_int_3[7]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[7]),
+		  
+		  .sclen_1(SCLEN_1[7]),
+		  .sclen_2(SCLEN_2[7]),
+		  .sclen_3(SCLEN_3[7])
+);
+
+
+wb_i2c_tri i2c_ch_8 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[8]),
+                  .wb_rst_i_1(reset_1[8]),
+                  .wb_stb_i_1(wb_stb_i_1[10]),
+                  .wb_dat_o_1(bus_1[8]),
+                  .wb_ack_o_1(wb_ack_i2c_1[8]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[8]),
+                  .sda_in_1(SDA_in_1[8]),
+                  .wb_int_o_1(wb_i2c_int_1[8]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  .sda_out_1(SDA_OUT_1[8]),
+                  .wb_clk_i_2(clock_2[8]),
+                  .wb_rst_i_2(reset_2[8]),
+                  .wb_stb_i_2(wb_stb_i_2[10]),
+                  .wb_dat_o_2(bus_2[8]),
+                  .wb_ack_o_2(wb_ack_i2c_2[8]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[8]),
+                  .sda_in_2(SDA_in_2[8]),
+                  .wb_int_o_2(wb_i2c_int_2[8]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  .sda_out_2(SDA_OUT_2[8]),
+                  .wb_clk_i_3(clock_3[8]),
+                  .wb_rst_i_3(reset_3[8]),
+                  .wb_stb_i_3(wb_stb_i_3[10]),
+                  .wb_dat_o_3(bus_3[8]),
+                  .wb_ack_o_3(wb_ack_i2c_3[8]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[8]),
+                  .sda_in_3(SDA_in_3[8]),
+                  .wb_int_o_3(wb_i2c_int_3[8]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[8]),
+		  
+		  .sclen_1(SCLEN_1[8]),
+		  .sclen_2(SCLEN_2[8]),
+		  .sclen_3(SCLEN_3[8])
+);
+
+
+wb_i2c_tri i2c_ch_9 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[9]),
+                  .wb_rst_i_1(reset_1[9]),
+                  .wb_stb_i_1(wb_stb_i_1[11]),
+                  .wb_dat_o_1(bus_1[9]),
+                  .wb_ack_o_1(wb_ack_i2c_1[9]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[9]),
+                  .sda_in_1(SDA_in_1[9]),
+                  .wb_int_o_1(wb_i2c_int_1[9]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[9]),
+                  .wb_clk_i_2(clock_2[9]),
+                  .wb_rst_i_2(reset_2[9]),
+                  .wb_stb_i_2(wb_stb_i_2[11]),
+                  .wb_dat_o_2(bus_2[9]),
+                  .wb_ack_o_2(wb_ack_i2c_2[9]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[9]),
+                  .sda_in_2(SDA_in_2[9]),
+                  .wb_int_o_2(wb_i2c_int_2[9]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[9]),
+                  .wb_clk_i_3(clock_3[9]),
+                  .wb_rst_i_3(reset_3[9]),
+                  .wb_stb_i_3(wb_stb_i_3[11]),
+                  .wb_dat_o_3(bus_3[9]),
+                  .wb_ack_o_3(wb_ack_i2c_3[9]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[9]),
+                  .sda_in_3(SDA_in_3[9]),
+                  .wb_int_o_3(wb_i2c_int_3[9]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[9]),
+		  
+		  .sclen_1(SCLEN_1[9]),
+		  .sclen_2(SCLEN_2[9]),
+		  .sclen_3(SCLEN_3[9])
+);
+
+
+wb_i2c_tri i2c_ch_10 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[10]),
+                  .wb_rst_i_1(reset_1[10]),
+                  .wb_stb_i_1(wb_stb_i_1[12]),
+                  .wb_dat_o_1(bus_1[10]),
+                  .wb_ack_o_1(wb_ack_i2c_1[10]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[10]),
+                  .sda_in_1(SDA_in_1[10]),
+                  .wb_int_o_1(wb_i2c_int_1[10]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[10]),
+                  .wb_clk_i_2(clock_2[10]),
+                  .wb_rst_i_2(reset_2[10]),
+                  .wb_stb_i_2(wb_stb_i_2[12]),
+                  .wb_dat_o_2(bus_2[10]),
+                  .wb_ack_o_2(wb_ack_i2c_2[10]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[10]),
+                  .sda_in_2(SDA_in_2[10]),
+                  .wb_int_o_2(wb_i2c_int_2[10]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[10]),
+                  .wb_clk_i_3(clock_3[10]),
+                  .wb_rst_i_3(reset_3[10]),
+                  .wb_stb_i_3(wb_stb_i_3[12]),
+                  .wb_dat_o_3(bus_3[10]),
+                  .wb_ack_o_3(wb_ack_i2c_3[10]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[10]),
+                  .sda_in_3(SDA_in_3[10]),
+                  .wb_int_o_3(wb_i2c_int_3[10]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[10]),
+		  
+		  .sclen_1(SCLEN_1[10]),
+		  .sclen_2(SCLEN_2[10]),
+		  .sclen_3(SCLEN_3[10])
+);
+
+
+wb_i2c_tri i2c_ch_11 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[11]),
+                  .wb_rst_i_1(reset_1[11]),
+                  .wb_stb_i_1(wb_stb_i_1[13]),
+                  .wb_dat_o_1(bus_1[11]),
+                  .wb_ack_o_1(wb_ack_i2c_1[11]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[11]),
+                  .sda_in_1(SDA_in_1[11]),
+                  .wb_int_o_1(wb_i2c_int_1[11]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[11]),
+                  .wb_clk_i_2(clock_2[11]),
+                  .wb_rst_i_2(reset_2[11]),
+                  .wb_stb_i_2(wb_stb_i_2[13]),
+                  .wb_dat_o_2(bus_2[11]),
+                  .wb_ack_o_2(wb_ack_i2c_2[11]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[11]),
+                  .sda_in_2(SDA_in_2[11]),
+                  .wb_int_o_2(wb_i2c_int_2[11]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[11]),
+                  .wb_clk_i_3(clock_3[11]),
+                  .wb_rst_i_3(reset_3[11]),
+                  .wb_stb_i_3(wb_stb_i_3[13]),
+                  .wb_dat_o_3(bus_3[11]),
+                  .wb_ack_o_3(wb_ack_i2c_3[11]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[11]),
+                  .sda_in_3(SDA_in_3[11]),
+                  .wb_int_o_3(wb_i2c_int_3[11]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[11]),
+		  
+		  .sclen_1(SCLEN_1[11]),
+		  .sclen_2(SCLEN_2[11]),
+		  .sclen_3(SCLEN_3[11])
+);
+
+
+wb_i2c_tri i2c_ch_12 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[12]),
+                  .wb_rst_i_1(reset_1[12]),
+                  .wb_stb_i_1(wb_stb_i_1[14]),
+                  .wb_dat_o_1(bus_1[12]),
+                  .wb_ack_o_1(wb_ack_i2c_1[12]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[12]),
+                  .sda_in_1(SDA_in_1[12]),
+                  .wb_int_o_1(wb_i2c_int_1[12]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[12]),
+                  .wb_clk_i_2(clock_2[12]),
+                  .wb_rst_i_2(reset_2[12]),
+                  .wb_stb_i_2(wb_stb_i_2[14]),
+                  .wb_dat_o_2(bus_2[12]),
+                  .wb_ack_o_2(wb_ack_i2c_2[12]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[12]),
+                  .sda_in_2(SDA_in_2[12]),
+                  .wb_int_o_2(wb_i2c_int_2[12]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[12]),
+                  .wb_clk_i_3(clock_3[12]),
+                  .wb_rst_i_3(reset_3[12]),
+                  .wb_stb_i_3(wb_stb_i_3[14]),
+                  .wb_dat_o_3(bus_3[12]),
+                  .wb_ack_o_3(wb_ack_i2c_3[12]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[12]),
+                  .sda_in_3(SDA_in_3[12]),
+                  .wb_int_o_3(wb_i2c_int_3[12]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[12]),
+		  
+		  .sclen_1(SCLEN_1[12]),
+		  .sclen_2(SCLEN_2[12]),
+		  .sclen_3(SCLEN_3[12])
+);
+
+
+wb_i2c_tri i2c_ch_13 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[13]),
+                  .wb_rst_i_1(reset_1[13]),
+                  .wb_stb_i_1(wb_stb_i_1[15]),
+                  .wb_dat_o_1(bus_1[13]),
+                  .wb_ack_o_1(wb_ack_i2c_1[13]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[13]),
+                  .sda_in_1(SDA_in_1[13]),
+                  .wb_int_o_1(wb_i2c_int_1[13]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[13]),
+                  .wb_clk_i_2(clock_2[13]),
+                  .wb_rst_i_2(reset_2[13]),
+                  .wb_stb_i_2(wb_stb_i_2[15]),
+                  .wb_dat_o_2(bus_2[13]),
+                  .wb_ack_o_2(wb_ack_i2c_2[13]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[13]),
+                  .sda_in_2(SDA_in_2[13]),
+                  .wb_int_o_2(wb_i2c_int_2[13]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[13]),
+                  .wb_clk_i_3(clock_3[13]),
+                  .wb_rst_i_3(reset_3[13]),
+                  .wb_stb_i_3(wb_stb_i_3[15]),
+                  .wb_dat_o_3(bus_3[13]),
+                  .wb_ack_o_3(wb_ack_i2c_3[13]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[13]),
+                  .sda_in_3(SDA_in_3[13]),
+                  .wb_int_o_3(wb_i2c_int_3[13]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[13]),
+		  
+		  .sclen_1(SCLEN_1[13]),
+		  .sclen_2(SCLEN_2[13]),
+		  .sclen_3(SCLEN_3[13])
+);
+
+
+wb_i2c_tri i2c_ch_14 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[14]),
+                  .wb_rst_i_1(reset_1[14]),
+                  .wb_stb_i_1(wb_stb_i_1[16]),
+                  .wb_dat_o_1(bus_1[14]),
+                  .wb_ack_o_1(wb_ack_i2c_1[14]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[14]),
+                  .sda_in_1(SDA_in_1[14]),
+                  .wb_int_o_1(wb_i2c_int_1[14]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[14]),
+                  .wb_clk_i_2(clock_2[14]),
+                  .wb_rst_i_2(reset_2[14]),
+                  .wb_stb_i_2(wb_stb_i_2[16]),
+                  .wb_dat_o_2(bus_2[14]),
+                  .wb_ack_o_2(wb_ack_i2c_2[14]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[14]),
+                  .sda_in_2(SDA_in_2[14]),
+                  .wb_int_o_2(wb_i2c_int_2[14]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[14]),
+                  .wb_clk_i_3(clock_3[14]),
+                  .wb_rst_i_3(reset_3[14]),
+                  .wb_stb_i_3(wb_stb_i_3[16]),
+                  .wb_dat_o_3(bus_3[14]),
+                  .wb_ack_o_3(wb_ack_i2c_3[14]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[14]),
+                  .sda_in_3(SDA_in_3[14]),
+                  .wb_int_o_3(wb_i2c_int_3[14]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[14]),
+		  
+		  .sclen_1(SCLEN_1[14]),
+		  .sclen_2(SCLEN_2[14]),
+		  .sclen_3(SCLEN_3[14])
+);
+
+
+wb_i2c_tri i2c_ch_15 (
+		  .wb_err_o_1(),
+		  .wb_err_o_2(),
+		  .wb_err_o_3(),
+                  .wb_clk_i_1(clock_1[15]),
+                  .wb_rst_i_1(reset_1[15]),
+                  .wb_stb_i_1(wb_stb_i_1[17]),
+                  .wb_dat_o_1(bus_1[15]),
+                  .wb_ack_o_1(wb_ack_i2c_1[15]),
+                  .wb_adr_i_1(wb_adr_i_1[4:0]),
+                  .wb_dat_i_1(wb_dat_i_1),
+                  .scl_1(SCL_1[15]),
+                  .sda_in_1(SDA_in_1[15]),
+                  .wb_int_o_1(wb_i2c_int_1[15]),
+                  .wb_cyc_i_1(wb_cyc_1),
+                  .wb_we_i_1(wb_we_1),
+                  .wb_sel_i_1(wb_sel_1),
+                  
+                  .sda_out_1(SDA_OUT_1[15]),
+                  .wb_clk_i_2(clock_2[15]),
+                  .wb_rst_i_2(reset_2[15]),
+                  .wb_stb_i_2(wb_stb_i_2[17]),
+                  .wb_dat_o_2(bus_2[15]),
+                  .wb_ack_o_2(wb_ack_i2c_2[15]),
+                  .wb_adr_i_2(wb_adr_i_2[4:0]),
+                  .wb_dat_i_2(wb_dat_i_2),
+                  .scl_2(SCL_2[15]),
+                  .sda_in_2(SDA_in_2[15]),
+                  .wb_int_o_2(wb_i2c_int_2[15]),
+                  .wb_cyc_i_2(wb_cyc_2),
+                  .wb_we_i_2(wb_we_2),
+                  .wb_sel_i_2(wb_sel_2),
+                  
+                  .sda_out_2(SDA_OUT_2[15]),
+                  .wb_clk_i_3(clock_3[15]),
+                  .wb_rst_i_3(reset_3[15]),
+                  .wb_stb_i_3(wb_stb_i_3[17]),
+                  .wb_dat_o_3(bus_3[15]),
+                  .wb_ack_o_3(wb_ack_i2c_3[15]),
+                  .wb_adr_i_3(wb_adr_i_3[4:0]),
+                  .wb_dat_i_3(wb_dat_i_3),
+                  .scl_3(SCL_3[15]),
+                  .sda_in_3(SDA_in_3[15]),
+                  .wb_int_o_3(wb_i2c_int_3[15]),
+                  .wb_cyc_i_3(wb_cyc_3),
+                  .wb_we_i_3(wb_we_3),
+                  .wb_sel_i_3(wb_sel_3),
+                  .sda_out_3(SDA_OUT_3[15]),
+		  
+		  .sclen_1(SCLEN_1[15]),
+		  .sclen_2(SCLEN_2[15]),
+		  .sclen_3(SCLEN_3[15])
+        );
+
+
+assign wb_dat_o0_1[31:0]  = bus_1[0];
+assign wb_dat_o0_2[31:0]  = bus_2[0];
+assign wb_dat_o0_3[31:0]  = bus_3[0];
+
+assign wb_dat_o1_1[31:0]  = bus_1[1];
+assign wb_dat_o1_2[31:0]  = bus_2[1];
+assign wb_dat_o1_3[31:0]  = bus_3[1];
+
+assign wb_dat_o2_1[31:0]  = bus_1[2];
+assign wb_dat_o2_2[31:0]  = bus_2[2];
+assign wb_dat_o2_3[31:0]  = bus_3[2];
+
+assign wb_dat_o3_1[31:0]  = bus_1[3];
+assign wb_dat_o3_2[31:0]  = bus_2[3];
+assign wb_dat_o3_3[31:0]  = bus_3[3];
+
+assign wb_dat_o4_1[31:0]  = bus_1[4];
+assign wb_dat_o4_2[31:0]  = bus_2[4];
+assign wb_dat_o4_3[31:0]  = bus_3[4];
+
+assign wb_dat_o5_1[31:0]  = bus_1[5];
+assign wb_dat_o5_2[31:0]  = bus_2[5];
+assign wb_dat_o5_3[31:0]  = bus_3[5];
+
+assign wb_dat_o6_1[31:0]  = bus_1[6];
+assign wb_dat_o6_2[31:0]  = bus_2[6];
+assign wb_dat_o6_3[31:0]  = bus_3[6];
+
+assign wb_dat_o7_1[31:0]  = bus_1[7];
+assign wb_dat_o7_2[31:0]  = bus_2[7];
+assign wb_dat_o7_3[31:0]  = bus_3[7];
+
+assign wb_dat_o8_1[31:0]  = bus_1[8];
+assign wb_dat_o8_2[31:0]  = bus_2[8];
+assign wb_dat_o8_3[31:0]  = bus_3[8];
+
+assign wb_dat_o9_1[31:0]  = bus_1[9];
+assign wb_dat_o9_2[31:0]  = bus_2[9];
+assign wb_dat_o9_3[31:0]  = bus_3[9];
+
+assign wb_dat_o10_1[31:0] = bus_1[10];
+assign wb_dat_o10_2[31:0] = bus_2[10];
+assign wb_dat_o10_3[31:0] = bus_3[10];
+
+assign wb_dat_o11_1[31:0] = bus_1[11];
+assign wb_dat_o11_2[31:0] = bus_2[11];
+assign wb_dat_o11_3[31:0] = bus_3[11];
+
+assign wb_dat_o12_1[31:0] = bus_1[12];
+assign wb_dat_o12_2[31:0] = bus_2[12];
+assign wb_dat_o12_3[31:0] = bus_3[12];
+
+assign wb_dat_o13_1[31:0] = bus_1[13];
+assign wb_dat_o13_2[31:0] = bus_2[13];
+assign wb_dat_o13_3[31:0] = bus_3[13];
+
+assign wb_dat_o14_1[31:0] = bus_1[14];
+assign wb_dat_o14_2[31:0] = bus_2[14];
+assign wb_dat_o14_3[31:0] = bus_3[14];
+
+assign wb_dat_o15_1[31:0] = bus_1[15];
+assign wb_dat_o15_2[31:0] = bus_2[15];
+assign wb_dat_o15_3[31:0] = bus_3[15];
+
+assign wb_ack_out_1 = wb_ack_i2c_1[0] || wb_ack_i2c_1[1] || wb_ack_i2c_1[2] || wb_ack_i2c_1[3] || wb_ack_i2c_1[4] || wb_ack_i2c_1[5] ||  wb_ack_i2c_1[6] || wb_ack_i2c_1[7] || wb_ack_i2c_1[8] || wb_ack_i2c_1[9] || wb_ack_i2c_1[10] || wb_ack_i2c_1[11] || wb_ack_i2c_1[12] || wb_ack_i2c_1[13] ||  wb_ack_i2c_1[14] || wb_ack_i2c_1[15];
+assign wb_ack_out_2 = wb_ack_i2c_2[0] || wb_ack_i2c_2[1] || wb_ack_i2c_2[2] || wb_ack_i2c_2[3] || wb_ack_i2c_2[4] || wb_ack_i2c_2[5] ||  wb_ack_i2c_2[6] || wb_ack_i2c_2[7] || wb_ack_i2c_2[8] || wb_ack_i2c_2[9] || wb_ack_i2c_2[10] || wb_ack_i2c_2[11] || wb_ack_i2c_2[12] || wb_ack_i2c_2[13] ||  wb_ack_i2c_2[14] || wb_ack_i2c_2[15];
+assign wb_ack_out_3 = wb_ack_i2c_3[0] || wb_ack_i2c_3[1] || wb_ack_i2c_3[2] || wb_ack_i2c_3[3] || wb_ack_i2c_3[4] || wb_ack_i2c_3[5] ||  wb_ack_i2c_3[6] || wb_ack_i2c_3[7] || wb_ack_i2c_3[8] || wb_ack_i2c_3[9] || wb_ack_i2c_3[10] || wb_ack_i2c_3[11] || wb_ack_i2c_3[12] || wb_ack_i2c_3[13] ||  wb_ack_i2c_3[14] || wb_ack_i2c_3[15];
+
+endmodule
+
+
+
diff --git a/vldb/code/Testbench/SCA-model/I2C_prog_divider.v b/vldb/code/Testbench/SCA-model/I2C_prog_divider.v
new file mode 100644
index 0000000..969a8d6
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/I2C_prog_divider.v
@@ -0,0 +1,296 @@
+
+/////////////////////////////////////////////////////////////////////////////
+// Design Name:    GBT_SCA                                                 //
+// Module Name:    Progr_Divider  (tri version)                            //
+// Made by:        Alessandro Caratelli                                    //
+//                                                                         //
+// Description:    Programmable divider clk_gating for I2C modules         // 
+// Company:        CERN (PH-ESE)                                           //
+// Create Date:    01/dec/2013                                             //
+/////////////////////////////////////////////////////////////////////////////
+
+
+
+//`define TB
+`timescale 1ns / 1ps
+module div_cnt # ( 
+	parameter  div0 = 100,
+	parameter  div1 = 50,
+	parameter  div2 = 25,
+	parameter  div3 = 10
+	)(
+	input             clk,
+	input             reset,
+	input       [1:0] div,	
+		
+	output reg  [6:0] count,
+	input       [6:0] count_voted,
+	output wire       clk_en
+	);
+
+	assign clk_en = ~(|count_voted);
+
+	always @(negedge clk or posedge reset) begin: counter
+		if(reset) count <= {7{1'b0}};
+		else begin
+			if(!count) begin 
+				case(div)
+				2'b00: count <= div0;
+				2'b01: count <= div1;
+				2'b10: count <= div2;
+				2'b11: count <= div3;
+				endcase
+			end
+			else count <= count_voted - 7'h01;
+		end
+	end
+
+endmodule
+
+
+module div_prog_voter(
+	input      [6:0] count_in_1,  count_in_2,  count_in_3,
+	output reg [6:0] count_out,
+	input            en_in_1,  en_in_2,  en_in_3,
+	output reg       en_out	
+	);
+	integer i;
+	always @(*) begin
+		en_out = (en_in_1 != en_in_2) ? en_in_3 : en_in_1;
+		for(i=0; i<7; i=i+1) count_out[i] = (count_in_1[i] != count_in_2[i]) ? count_in_3[i] : count_in_1[i];
+	end
+endmodule
+
+
+module div_prog_sm_tri # ( 
+
+	parameter     div0 = 100,
+	parameter     div1 = 50,
+	parameter     div2 = 25,
+	parameter     div3 = 10
+	)(
+	input         clk_1,          clk_2,          clk_3,
+	input         reset_1,        reset_2,        reset_3,
+	input [1:0]   div_1,          div_2,          div_3,	
+	output wire   clk_out_1,      clk_out_2,      clk_out_3
+	);	
+	wire  [6:0]   count_1,        count_2,        count_3;
+	wire  [6:0]   count_1_voted,  count_2_voted,  count_3_voted;
+	wire          clk_en_1,       clk_en_2,       clk_en_3;     
+	wire          clk_en_1_voted, clk_en_2_voted, clk_en_3_voted; 
+
+	and clk_gating_1 (clk_out_1, clk_1, clk_en_1_voted);
+	and clk_gating_2 (clk_out_2, clk_2, clk_en_2_voted);
+	and clk_gating_3 (clk_out_3, clk_3, clk_en_3_voted);
+	
+	div_prog_voter div_voter_1 (
+		.count_in_1(count_1[6:0]),
+		.count_in_2(count_2[6:0]),
+		.count_in_3(count_3[6:0]),
+		.count_out(count_1_voted[6:0]),
+		.en_in_1(clk_en_2),
+		.en_in_2(clk_en_3),
+		.en_in_3(clk_en_1),
+		.en_out(clk_en_1_voted)
+	);
+	
+	div_prog_voter div_voter_2 (
+		.count_in_1(count_2[6:0]),
+		.count_in_2(count_3[6:0]),
+		.count_in_3(count_1[6:0]),
+		.count_out(count_2_voted[6:0]),
+		.en_in_1(clk_en_3),
+		.en_in_2(clk_en_1),
+		.en_in_3(clk_en_2),
+		.en_out(clk_en_2_voted)
+	);	
+	
+	div_prog_voter div_voter_3 (
+		.count_in_1(count_3[6:0]),
+		.count_in_2(count_1[6:0]),
+		.count_in_3(count_2[6:0]),
+		.count_out(count_3_voted[6:0]),
+		.en_in_1(clk_en_1),
+		.en_in_2(clk_en_2),
+		.en_in_3(clk_en_3),
+		.en_out(clk_en_3_voted)
+	);	
+	
+	div_cnt # (
+		.div0(div0),
+		.div1(div1),
+		.div2(div2),
+		.div3(div3)
+	) div_cnt_1 (
+		.clk(clk_1),
+		.reset(reset_1),
+		.div(div_1),	
+	
+		.count(count_1[6:0]),
+		.count_voted(count_1_voted[6:0]),
+		.clk_en(clk_en_1)
+	);
+
+	div_cnt # (
+		.div0(div0),
+		.div1(div1),
+		.div2(div2),
+		.div3(div3)
+	) div_cnt_2 (
+		.clk(clk_2),
+		.reset(reset_2),
+		.div(div_2),		
+	
+		.count(count_2[6:0]),
+		.count_voted(count_2_voted[6:0]),
+		.clk_en(clk_en_2)
+	);
+
+	div_cnt # (
+		.div0(div0),
+		.div1(div1),
+		.div2(div2),
+		.div3(div3)
+	) div_cnt_3 (
+		.clk(clk_3),
+		.reset(reset_3),
+		.div(div_3),	
+	
+		.count(count_3[6:0]),
+		.count_voted(count_3_voted[6:0]),
+		.clk_en(clk_en_3)
+	);
+
+endmodule
+
+
+
+
+
+
+
+
+`ifdef TB
+module div_test();
+	
+	reg  [1:0] div;
+	reg  reset;
+	reg  clk;
+	wire clk_out_1, clk_out_2, clk_out_3;
+	
+	div_prog_sm_tri div_tb (
+		.clk_1(clk),           .clk_2(clk),           .clk_3(clk),
+		.reset_1(reset),       .reset_2(reset),       .reset_3(reset),
+		.div_1(div),           .div_2(div),           .div_3(div),     
+		.clk_out_1(clk_out_1), .clk_out_2(clk_out_2), .clk_out_3(clk_out_3)
+	);
+	
+	initial begin
+		clk = 1'b0;
+		forever #12.5 clk = ~clk;
+	end
+	
+	initial begin
+		reset = 1'b0;
+		div = 2'b0; 
+		#500;reset = 1'b1;
+		#10;reset = 1'b0;
+		forever begin
+			#(2500*5+({$random}%3000)); 
+			@(posedge clk) div = {$random}%4;
+		end
+	end
+	
+endmodule
+`endif	
+		
+	
+/*	
+`timescale 1ns / 1ps
+module div_prog_sm_tri # ( 
+	parameter     div0 = 100,
+	parameter     div1 = 50,
+	parameter     div2 = 25,
+	parameter     div3 = 10
+	)(
+	input         clk_1,          clk_2,          clk_3,
+	input         reset_1,        reset_2,        reset_3,
+	input [1:0]   div_1,          div_2,          div_3,	
+	output wire   clk_out_1,      clk_out_2,      clk_out_3
+	);
+	
+	reg [6:0]     count_1,        count_2,        count_3;
+	reg [6:0]     count_1_voted,  count_2_voted,  count_3_voted;
+	wire          clk_en_1,       clk_en_2,       clk_en_3;     
+	reg           clk_en_1_voted, clk_en_2_voted, clk_en_3_voted; 
+
+	integer i;
+
+	always @(*) begin: majority_voter
+		for(i=0; i<7; i=i+1) begin
+			count_1_voted[i] = (count_1[i] != count_2[i]) ? count_3[i] : count_1[i];
+			count_2_voted[i] = (count_2[i] != count_3[i]) ? count_1[i] : count_2[i];
+			count_3_voted[i] = (count_3[i] != count_1[i]) ? count_2[i] : count_3[i];
+		end
+		clk_en_1_voted = (clk_en_1 != clk_en_2) ? clk_en_3 : clk_en_1;
+		clk_en_2_voted = (clk_en_2 != clk_en_3) ? clk_en_1 : clk_en_2;
+		clk_en_3_voted = (clk_en_3 != clk_en_1) ? clk_en_2 : clk_en_3;
+	end
+
+	and clk_gating_1 (clk_out_1, clk_1, clk_en_1_voted);
+	and clk_gating_2 (clk_out_2, clk_2, clk_en_2_voted);
+	and clk_gating_3 (clk_out_3, clk_3, clk_en_3_voted);
+	
+	assign clk_en_1 = ~(|count_1_voted);
+	assign clk_en_2 = ~(|count_2_voted);
+	assign clk_en_3 = ~(|count_3_voted);
+
+	always @(negedge clk_1 or posedge reset_1) begin: counter_1
+		if(reset_1) count_1 <= {7{1'b0}};
+		else begin
+			if(!count_1) begin 
+				case(div_1)
+				2'b00: count_1 <= div0;
+				2'b01: count_1 <= div1;
+				2'b10: count_1 <= div2;
+				2'b11: count_1 <= div3;
+				endcase
+			end
+			else count_1 <= count_1_voted - 7'h01;
+		end
+	end
+
+	always @(negedge clk_2 or posedge reset_2) begin: counter_2
+		if(reset_2) count_2 <= {7{1'b0}};
+		else begin
+			if(!count_2) begin 
+				case(div_2)
+				2'b00: count_2 <= div0;
+				2'b01: count_2 <= div1;
+				2'b10: count_2 <= div2;
+				2'b11: count_2 <= div3;
+				endcase
+			end
+			else count_2 <= count_2_voted - 7'h01;
+		end
+	end
+	
+	always @(negedge clk_3 or posedge reset_3) begin: counter_3
+		if(reset_3) count_3 <= {7{1'b0}};
+		else begin
+			if(!count_3) begin 
+				case(div_3)
+				2'b00: count_3 <= div0;
+				2'b01: count_3 <= div1;
+				2'b10: count_3 <= div2;
+				2'b11: count_3 <= div3;
+				endcase
+			end
+			else count_3 <= count_3_voted - 7'h01;
+		end
+	end
+
+endmodule
+*/
+	
+
diff --git a/vldb/code/Testbench/SCA-model/I2C_slavle_wb.v b/vldb/code/Testbench/SCA-model/I2C_slavle_wb.v
new file mode 100644
index 0000000..1f18f02
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/I2C_slavle_wb.v
@@ -0,0 +1,811 @@
+///////////////////////////////////////////////////
+//
+// i2c_slave_TMR.v
+// Created on Jun  3  2008 
+// by Sandro Bonacini
+// CERN PH/ESE/ME
+//
+///////////////////////////////////////////////////
+`timescale 1ps/1ps
+
+module i2c_slave ( SCL1, resetB1, clk1, wb_dat_i1, wb_we1, wb_stb1,  wb_cyc1,
+			wb_ack1, chip_id1, ADDR10BIT1, INCREMENT_ADDR1, wb_dat_o1, SDAo1,
+			SDAen1, wb_adr1, SDAi1,  SCL2, resetB2, clk2, wb_dat_i2, wb_we2,
+			wb_stb2,  wb_cyc2, wb_ack2, chip_id2, ADDR10BIT2, INCREMENT_ADDR2,
+			wb_dat_o2, SDAo2, SDAen2, wb_adr2, SDAi2, SCL3, resetB3, clk3,
+			wb_dat_i3, wb_we3, wb_stb3,  wb_cyc3, wb_ack3, chip_id3,
+			ADDR10BIT3, INCREMENT_ADDR3, wb_dat_o3, SDAo3, SDAen3, wb_adr3,
+			SDAi3 );
+
+	parameter [3:0] CHIP_ID_WIDTH = 3;
+
+    input     	    SCL1;
+	input			SDAi1;
+    input  	    resetB1;
+    input   	    clk1;
+	input [7:0] wb_dat_i1;     // databus input
+	input       wb_ack1;     // bus cycle acknowledge output
+	input [CHIP_ID_WIDTH-1:0] chip_id1;
+	input ADDR10BIT1;
+	input INCREMENT_ADDR1;
+	output        wb_we1;      // write enable input
+	output        wb_stb1;     // stobe/core select signal
+	output        wb_cyc1;     // valid bus cycle input
+	output [7:0] wb_dat_o1;     // databus output
+	output SDAo1;
+	output SDAen1;
+	output [9-CHIP_ID_WIDTH:0] wb_adr1;
+
+    input     	    SCL2;
+	input			SDAi2;
+    input  	    resetB2;
+    input   	    clk2;
+	input [7:0] wb_dat_i2;     // databus input
+	input       wb_ack2;     // bus cycle acknowledge output
+	input [CHIP_ID_WIDTH-1:0] chip_id2;
+	input ADDR10BIT2;
+	input INCREMENT_ADDR2;
+	output        wb_we2;      // write enable input
+	output        wb_stb2;     // stobe/core select signal
+	output        wb_cyc2;     // valid bus cycle input
+	output [7:0] wb_dat_o2;     // databus output
+	output SDAo2;
+	output SDAen2;
+	output [9-CHIP_ID_WIDTH:0] wb_adr2;
+
+    input     	    SCL3;
+	input			SDAi3;
+    input  	    resetB3;
+    input   	    clk3;
+	input [7:0] wb_dat_i3;     // databus input
+	input       wb_ack3;     // bus cycle acknowledge output
+	input [CHIP_ID_WIDTH-1:0] chip_id3;
+	input ADDR10BIT3;
+	input INCREMENT_ADDR3;
+	output        wb_we3;      // write enable input 
+	output        wb_stb3;     // stobe/core select signal
+	output        wb_cyc3;     // valid bus cycle input
+	output [7:0] wb_dat_o3;     // databus output
+	output SDAo3;
+	output SDAen3;
+	output [9-CHIP_ID_WIDTH:0] wb_adr3;
+
+	wire [7:0] wb_dat_oV;     // databus wire
+	wire [9-CHIP_ID_WIDTH:0] wb_adrV;
+	
+	
+    wire [1:0]  state1;
+	wire [3:0] i1;
+	wire [8:0] watchdog1;
+	wire [7:0] buffer1;
+
+    wire [1:0]  state2;
+	wire [3:0] i2;
+	wire [8:0] watchdog2;
+	wire [7:0] buffer2;
+
+    wire [1:0]  state3;
+	wire [3:0] i3;
+	wire [8:0] watchdog3;
+	wire [7:0] buffer3;
+
+    wire [1:0]  stateV;
+	wire [3:0] iV;
+	wire [8:0] watchdogV;
+	wire [7:0] bufferV;
+
+
+	i2c_slave_iostate slave1 ( 
+		.SCL(SCL1),
+		.SDAi(SDAi1),
+		.wb_adr(wb_adr1),
+		.wb_dat_i(wb_dat_i1),
+		.wb_dat_o(wb_dat_o1),
+		.SDAo(SDAo1),
+		.SDAen(SDAen1),
+		.state(state1),
+		.wb_ack(wb_ack1),
+		.wb_cyc(wb_cyc1),
+		.wb_stb(wb_stb1),
+		.wb_we(wb_we1),
+		.i(i1),
+		.buffer(buffer1),
+		.i_voted(iV),
+		.buffer_voted(bufferV),
+		.wb_dat_o_voted(wb_dat_oV),
+		.SDAo_voted(SDAoV),
+		.SDAen_voted(SDAenV),
+		.state_voted(stateV),
+		.wb_adr_voted(wb_adrV),
+		.wb_we_voted(wb_weV),
+		.wb_cyc_voted(wb_cycV),
+		.readcycle(readcycle1),
+		.selected(selected1),
+		.readcycle_voted(readcycleV),
+		.selected_voted(selectedV),
+		.watchdog(watchdog1),
+		.watchdog_voted(watchdogV),
+		.chip_id(chip_id1),
+		.ADDR10BIT(ADDR10BIT1),
+		.INCREMENT_ADDR(INCREMENT_ADDR1),
+		.clk(clk1),
+		.en_clk(en_clk1),
+		.en_clk_voted(en_clkV),
+		.resetB(resetB1)
+	);
+
+	i2c_slave_iostate slave2 ( 
+		.SCL(SCL2),
+		.SDAi(SDAi2),
+		.wb_adr(wb_adr2),
+		.wb_dat_i(wb_dat_i2),
+		.wb_dat_o(wb_dat_o2),
+		.SDAo(SDAo2),
+		.SDAen(SDAen2),
+		.state(state2),
+		.wb_ack(wb_ack2),
+		.wb_cyc(wb_cyc2),
+		.wb_stb(wb_stb2),
+		.wb_we(wb_we2),
+		.i(i2),
+		.buffer(buffer2),
+		.i_voted(i1),
+		.buffer_voted(buffer1),
+		.wb_dat_o_voted(wb_dat_o1),
+		.SDAo_voted(SDAo1),
+		.SDAen_voted(SDAen1),
+		.state_voted(state1),
+		.wb_adr_voted(wb_adr1),
+		.wb_we_voted(wb_we1),
+		.wb_cyc_voted(wb_cyc1),
+		.readcycle(readcycle2),
+		.selected(selected2),
+		.readcycle_voted(readcycle1),
+		.selected_voted(selected1),
+		.watchdog(watchdog2),
+		.watchdog_voted(watchdog1),
+		.chip_id(chip_id2),
+		.ADDR10BIT(ADDR10BIT2),
+		.INCREMENT_ADDR(INCREMENT_ADDR2),
+		.clk(clk2),
+		.en_clk(en_clk2),
+		.en_clk_voted(en_clk1),
+		.resetB(resetB2)
+	);
+
+	i2c_slave_iostate slave3 ( 
+		.SCL(SCL3),
+		.SDAi(SDAi3),
+		.wb_adr(wb_adr3),
+		.wb_dat_i(wb_dat_i3),
+		.wb_dat_o(wb_dat_o3),
+		.SDAo(SDAo3),
+		.SDAen(SDAen3),
+		.state(state3),
+		.wb_ack(wb_ack3),
+		.wb_cyc(wb_cyc3),
+		.wb_stb(wb_stb3),
+		.wb_we(wb_we3),
+		.i(i3),
+		.buffer(buffer3),
+		.i_voted(i2),
+		.buffer_voted(buffer2),
+		.wb_dat_o_voted(wb_dat_o2),
+		.SDAo_voted(SDAo2),
+		.SDAen_voted(SDAen2),
+		.state_voted(state2),
+		.wb_adr_voted(wb_adr2),
+		.wb_we_voted(wb_we2),
+		.wb_cyc_voted(wb_cyc2),
+		.readcycle(readcycle3),
+		.selected(selected3),
+		.readcycle_voted(readcycle2),
+		.selected_voted(selected1),
+		.watchdog(watchdog3),
+		.watchdog_voted(watchdog2),
+		.chip_id(chip_id3),
+		.ADDR10BIT(ADDR10BIT3),
+		.INCREMENT_ADDR(INCREMENT_ADDR3),
+		.clk(clk3),
+		.en_clk(en_clk3),
+		.en_clk_voted(en_clk2),
+		.resetB(resetB3)
+	);
+
+	majority_voter #(45) mv (
+		.in1({en_clk1, i1, buffer1, wb_dat_o1, SDAo1, SDAen1, state1, wb_adr1, wb_we1, wb_cyc1, readcycle1, selected1, watchdog1}),
+		.in2({en_clk2, i2, buffer2, wb_dat_o2, SDAo2, SDAen2, state2, wb_adr2, wb_we2, wb_cyc2, readcycle2, selected2, watchdog2}),
+		.in3({en_clk3, i3, buffer3, wb_dat_o3, SDAo3, SDAen3, state3, wb_adr3, wb_we3, wb_cyc3, readcycle3, selected3, watchdog3}),
+		.out({en_clkV, iV, bufferV, wb_dat_oV, SDAoV, SDAenV, stateV, wb_adrV, wb_weV, wb_cycV, readcycleV, selectedV, watchdogV}),
+		.err()
+	);
+
+endmodule
+
+
+///////////////////////////////////////////////////
+//
+// i2c_slave_iostate.v
+// Created on Jun  3  2008 
+// by Sandro Bonacini
+// CERN PH/ESE/ME
+//
+///////////////////////////////////////////////////
+`timescale 1ps/1ps
+
+module i2c_slave_iostate ( SCL, resetB, clk, wb_dat_i, wb_we, wb_stb,  wb_cyc,
+				wb_ack, chip_id, ADDR10BIT, INCREMENT_ADDR, wb_dat_o, SDAo,
+				SDAen, wb_adr, SDAi, wb_dat_o_voted, wb_adr_voted,   state, i,
+				watchdog, buffer, state_voted, i_voted, watchdog_voted,
+				buffer_voted, en_clk, selected, readcycle, en_clk_voted,
+				selected_voted, readcycle_voted, wb_we_voted, SDAen_voted,
+				SDAo_voted, wb_cyc_voted );
+
+
+	parameter [3:0] CHIP_ID_WIDTH = 3;
+
+
+    input     	    SCL;
+	input			SDAi;
+    input  	    resetB;
+    input   	    clk;
+	input [7:0] wb_dat_i;     // databus input
+	input       wb_ack;     // bus cycle acknowledge output
+	input [CHIP_ID_WIDTH-1:0] chip_id;
+	input ADDR10BIT;
+	input INCREMENT_ADDR;
+	output        wb_we;      // write enable input
+	output        wb_stb;     // stobe/core select signal
+	output        wb_cyc;     // valid bus cycle input
+	output [7:0] wb_dat_o;     // databus output
+	output SDAo;
+	output SDAen;
+	output [9-CHIP_ID_WIDTH:0] wb_adr;
+
+
+	input [7:0] wb_dat_o_voted;     // databus wire
+	input [9-CHIP_ID_WIDTH:0] wb_adr_voted;
+	
+	
+    output [1:0]  state;
+	output [3:0] i;
+	output [8:0] watchdog;
+	output [7:0] buffer;
+	output en_clk;
+	output selected;
+	output readcycle;
+    input [1:0]  state_voted;
+	input [3:0] i_voted;
+	input [8:0] watchdog_voted;
+	input [7:0] buffer_voted;
+	input en_clk_voted;
+	input selected_voted;
+	input readcycle_voted;
+	input wb_we_voted;
+	input SDAen_voted;
+	input SDAo_voted;
+	input wb_cyc_voted;
+
+	I2C_synchronizer synch1 ( 
+		.S_SCL(S_SCL),
+		.clk40(clk),
+		.SCL(SCL),
+		.SDA(SDAi),
+		.START(START),
+		.STOP(STOP),
+		.resetB(resetB),
+		.S_SDA(S_SDA)
+	);
+
+//	i2c_slave_iostate #(.ADDR10BIT(1),.CHIP_ID(4'b0100)) slave  (
+	i2c_control #(.CHIP_ID_WIDTH(CHIP_ID_WIDTH)) slave1  (
+		.SDAi(S_SDA),
+		.SCL(S_SCL),
+		.START(START | START_late),
+		.STOP(STOP),
+		.resetB(resetB),
+		.clk(clkg),
+		.wb_adr(wb_adr),
+		.wb_dat_i(wb_dat_i),
+		.wb_dat_o(wb_dat_o),
+		.SDAo(SDAo),
+		.SDAen(SDAen),
+		.state(state),
+		.wb_ack(wb_ack),
+		.wb_cyc(wb_cyc),
+		.wb_stb(wb_stb),
+		.wb_we(wb_we),
+		.i(i),
+		.buffer(buffer),
+		.i_voted(i_voted),
+		.buffer_voted(buffer_voted),
+		.wb_dat_o_voted(wb_dat_o_voted),
+		.SDAo_voted(SDAo_voted),
+		.SDAen_voted(SDAen_voted),
+		.state_voted(state_voted),
+		.wb_adr_voted(wb_adr_voted),
+		.wb_we_voted(wb_we_voted),
+		.wb_cyc_voted(wb_cyc_voted),
+		.readcycle(readcycle),
+		.selected(selected),
+		.readcycle_voted(readcycle_voted),
+		.selected_voted(selected_voted),
+		.watchdog(watchdog),
+		.watchdog_voted(watchdog_voted),
+		.chip_id(chip_id),
+		.ADDR10BIT(ADDR10BIT),
+		.INCREMENT_ADDR(INCREMENT_ADDR)
+	);
+	
+	i2c_clock_gating i2c_clock_gating1 (
+		.START(START),
+		.START_late(START_late),
+		.clk(clk),
+		.clkg(clkg),
+		.en_clk(en_clk),
+		.en_clk_voted(en_clk_voted),
+		.STOP(STOP | (state_voted==0)),
+		.resetB(resetB)
+	);
+
+
+endmodule
+
+///////////////////////////////////////////////////
+//
+// i2c_control.v
+// Created on Jun  3  2008 
+// by Sandro Bonacini
+// CERN PH/ESE/ME
+//
+///////////////////////////////////////////////////
+`timescale 1ps/1ps
+
+module i2c_control (SDAi, SCL, START, STOP, resetB, clk, wb_adr, wb_cyc, wb_stb, wb_ack,
+							wb_we, wb_dat_i, wb_dat_o, SDAo, SDAen, state, i, buffer, i_voted,
+							buffer_voted, wb_dat_o_voted, SDAo_voted, SDAen_voted, state_voted,
+							wb_adr_voted, wb_cyc_voted, wb_we_voted, readcycle, selected,
+							readcycle_voted, selected_voted, watchdog, watchdog_voted, chip_id,
+							ADDR10BIT, INCREMENT_ADDR );
+
+	parameter [3:0] CHIP_ID_WIDTH = 3;
+//	parameter [CHIP_ID_WIDTH-1:0] CHIP_ID = 1;
+//	parameter [0:0] ADDR10BIT = 0;
+//	parameter [0:0] INCREMENT_ADDR = 1;
+	parameter [8:0] WATCHDOG_PRESET = 511;
+
+    //  input ports
+    input     	    SDAi;
+    input     	    SCL;
+    input   	    START;
+    input   	    STOP;
+    input   	    resetB;
+    input   	    clk;
+	
+//	output [6-CHIP_ID_WIDTH+(ADDR10BIT*3):0] wb_adr;    
+	output [6-CHIP_ID_WIDTH+3:0] wb_adr;    
+	input [7:0] wb_dat_i;     // databus input
+	output [7:0] wb_dat_o;     // databus output
+	output        wb_we;      // write enable input
+	output        wb_stb;     // stobe/core select signal
+	output        wb_cyc;     // valid bus cycle input
+	input       wb_ack;     // bus cycle acknowledge output
+	input [CHIP_ID_WIDTH-1:0] chip_id;
+	input ADDR10BIT;
+	input INCREMENT_ADDR;
+
+	
+    input [1:0] state_voted; 	
+	input [3:0] i_voted;
+	input [7:0] buffer_voted;
+	input [7:0]	wb_dat_o_voted;
+//	input [6-CHIP_ID_WIDTH+(ADDR10BIT*3):0] wb_adr_voted;
+	input [6-CHIP_ID_WIDTH+3:0] wb_adr_voted;
+	input SDAo_voted, SDAen_voted, wb_we_voted, wb_cyc_voted;
+	input readcycle_voted, selected_voted;
+	input [8:0]	watchdog_voted;
+      
+    //  output ports
+    output  [1:0]  state;
+    output  	    SDAo;
+    output  [7:0]   buffer;
+    output  	    SDAen;
+	output [3:0] i;
+	output readcycle, selected;
+	output [8:0] watchdog;
+
+    reg [7:0]   wb_dat_o;
+//	reg [6-CHIP_ID_WIDTH+(ADDR10BIT*3):0] wb_adr;
+	reg [6-CHIP_ID_WIDTH+3:0] wb_adr;
+	reg SDAo, SDAen, wb_we, wb_cyc;
+	reg [8:0] watchdog;
+	
+	wire wb_stb = wb_cyc;
+
+	parameter [1:0]  // synopsys enum mystates
+		IDLE = 2'd0,
+		ADDR = 2'd1,
+		ADDR2 = 2'd2,
+		RXTX = 2'd3;
+	
+	
+	reg [3:0] i;
+	reg [1:0] /* synopsys enum mystates */ state; 
+	reg SCL_late;
+	reg [7:0] buffer;
+	reg readcycle;
+	reg selected;
+	
+    always  @(posedge clk or negedge resetB) begin
+		if (~resetB) begin
+	    	i 	    	<=#1 0;
+	    	buffer 	<=#1 0;
+	    	wb_dat_o    	<=#1 0;
+	    	SDAo	 	<=#1 1'b1;
+	    	SDAen   	<=#1 1'b0;
+	    	state 	<=#1 IDLE;
+			SCL_late <=#1 0;
+			wb_adr <=#1 0;
+			wb_we <=#1 0;
+			wb_cyc <=#1 0;
+			selected <=#1 0;
+			readcycle <=#1 0;
+			watchdog <=#1 WATCHDOG_PRESET;
+		end
+		else begin
+			i <=#1 i_voted;
+			state <=#1 state_voted;
+			SCL_late <=#1 SCL;
+			wb_dat_o <=#1 wb_dat_o_voted;
+			SDAo <=#1 SDAo_voted;
+			SDAen <=#1 SDAen_voted;
+			buffer <=#1 buffer_voted;
+			wb_adr <=#1 wb_adr_voted;
+			wb_we <=#1 wb_we_voted;
+			wb_cyc <=#1 wb_cyc_voted;
+			readcycle <=#1 readcycle_voted;
+			selected <=#1 selected_voted;
+			
+			case (state_voted) //synopsys full_case parallel_case
+				IDLE: begin
+					SDAen <=#1 0;
+					wb_cyc <=#1 0;
+				end
+				
+				ADDR: begin
+					if ({SCL_late,SCL}=='b01) i<=#1 i_voted + 1;
+
+					if (i_voted<8) begin
+						SDAen <=#1 0;
+						if ({SCL_late,SCL}=='b01) begin
+							buffer <=#1 {buffer_voted[6:0], SDAi};	
+						end
+					end
+					
+					if (i_voted==8) begin
+						if ({SCL_late,SCL}=='b10) begin
+							if (!ADDR10BIT) begin // 7-bit addressing
+								if (buffer_voted[7:8-CHIP_ID_WIDTH] == chip_id) begin
+									SDAen<=#1 1; // ACK
+									SDAo<=#1 0;
+									wb_adr<=#1 buffer_voted[7-CHIP_ID_WIDTH:1];
+									readcycle<=#1 buffer_voted[0];
+									if (buffer_voted[0]) begin
+										wb_we <=#1 0;
+										wb_cyc <=#1 1;
+									end
+								end
+								else state <=#1 IDLE;
+							end
+							else begin // 10-bit addressing
+								if (buffer_voted[7:1] == {5'b11110,chip_id[CHIP_ID_WIDTH-1:CHIP_ID_WIDTH-2]}) begin
+									
+									if (buffer_voted[0]) begin
+										if (selected_voted) begin
+											wb_we <=#1 0;
+											wb_cyc <=#1 1;
+											SDAen<=#1 1; // ACK
+											SDAo<=#1 0;
+											readcycle<=#1 buffer_voted[0];
+										end
+										else begin
+											state <=#1 IDLE;
+											selected <=#1 0;
+										end
+									end
+									else begin
+										SDAen<=#1 1; // ACK
+										SDAo<=#1 0;
+										readcycle<=#1 buffer_voted[0];
+									end
+								end
+								else begin
+									state <=#1 IDLE;
+									selected <=#1 0;
+								end
+							end
+						end
+					end
+					
+					if (i_voted==9) begin
+						if (buffer_voted[0]) begin
+							i <=#1 0;
+							state <=#1 RXTX;
+							buffer <=#1 wb_dat_i;
+							wb_cyc <=#1 0;
+						end
+						else begin
+							if ({SCL_late,SCL}=='b10) begin
+								i<=#1 0;
+								SDAen <=#1 0;
+								if(!ADDR10BIT) begin // 7-bit addressing
+									state <=#1 RXTX;
+								end
+								else begin // 10-bit addressing
+									state <=#1 ADDR2;
+								end
+							end
+						end
+					end
+				end
+				
+				ADDR2: if (!ADDR10BIT) begin // 7-bit addressing
+					state <=#1 IDLE;
+				end
+				else begin // 10-bit addressing
+					if ({SCL_late,SCL}=='b01) i<=#1 i_voted + 1;
+
+					if (i_voted<8) begin
+						SDAen <=#1 0;
+						if ({SCL_late,SCL}=='b01) begin
+							buffer <=#1 {buffer_voted[6:0], SDAi};	
+						end
+					end
+					
+					if (i_voted==8) begin
+						if ({SCL_late,SCL}=='b10) begin
+							if (buffer_voted[7:10-CHIP_ID_WIDTH] == chip_id[CHIP_ID_WIDTH-3:0]) begin
+								SDAen<=#1 1; // ACK
+								SDAo<=#1 0;
+								wb_adr<=#1 buffer_voted[9-CHIP_ID_WIDTH:0];
+								selected <=#1 1;
+							end
+							else begin
+								state <=#1 IDLE;
+								selected <=#1 0;
+							end
+						end
+					end
+					
+					if (i_voted==9) begin
+						if ({SCL_late,SCL}=='b10) begin
+							i<=#1 0;
+							SDAen <=#1 0;
+							state <=#1 RXTX;
+						end
+					end
+				end
+				
+				
+				
+				
+				
+				RXTX: if (!readcycle) begin // RX
+					if ({SCL_late,SCL}=='b01) i<=#1 i_voted + 1;
+
+					if (i_voted<8) begin
+						SDAo <=#1 1;
+						SDAen <=#1 0;
+						if ({SCL_late,SCL}=='b01) begin
+							buffer <=#1 {buffer_voted[6:0], SDAi};	
+						end
+					end
+
+					if (i_voted==8) begin
+						if ({SCL_late,SCL}=='b10) begin
+							SDAen<=#1 1; // ACK
+							SDAo<=#1 0;
+							wb_dat_o<=#1 buffer_voted;
+							wb_we <=#1 1;
+							wb_cyc <=#1 1;
+						end
+					end
+
+					if (i_voted==9) begin
+						if ({SCL_late,SCL}=='b10) begin
+							SDAen<=#1 0;
+							i<=#1 0;
+							if (INCREMENT_ADDR) wb_adr<=#1 wb_adr_voted + 1;
+							//state <=#1 IDLE;
+						end
+					end
+
+				end
+ 				else begin // TX
+					if ({SCL_late,SCL}=='b10) i<=#1 i_voted + 1;
+
+					if (i_voted<8) begin
+						SDAen <=#1 1;
+						if ({SCL_late,SCL}=='b10) begin
+							SDAo <=#1 buffer_voted[7];
+							buffer <=#1 buffer_voted << 1;
+						end
+					end
+
+					if (i_voted==8) begin
+						if ({SCL_late,SCL}=='b10) begin
+							SDAen<=#1 0; // ACK
+							wb_we <=#1 0;
+							wb_cyc <=#1 1;
+							if (INCREMENT_ADDR) wb_adr<=#1 wb_adr_voted + 1;
+						end
+					end
+
+					if (i_voted==9) begin
+						SDAen<=#1 0;
+						if ({SCL_late,SCL}=='b01) begin
+							if (~SDAi) begin
+								i<=#1 0;
+								buffer <=#1 wb_dat_i;
+								wb_cyc <=#1 0;
+							end
+							else state <=#1 IDLE;
+						end
+					end
+
+				end
+
+			endcase
+			
+			if (STOP | (watchdog_voted==0)) begin
+				selected <=#1 0;
+				state<=#1 IDLE;
+			end
+
+			if (START) begin
+				state <=#1 ADDR;
+				SDAen <=#1 0;
+				i<=#1 0;
+			end
+
+			if (SCL==1) begin  // Avoid changes when SCL is high
+				SDAen <=#1 SDAen_voted;
+				SDAo <=#1 SDAo_voted;
+			end
+			
+			if (wb_ack & wb_we_voted) wb_cyc <=#1 0;
+			
+			if (({SCL_late,SCL}=='b10) | (state_voted==IDLE)) watchdog <=#1 WATCHDOG_PRESET;
+			else watchdog <=#1 watchdog_voted - 1;
+		end
+	end
+
+endmodule
+
+///////////////////////////////////////////////////
+//
+// i2c_synchronizer.v
+// Created on Jun  3  2008 
+// by Sandro Bonacini
+// CERN PH/ESE/ME
+//
+///////////////////////////////////////////////////
+`timescale 1ps/1ps
+module I2C_synchronizer ( S_SCL, clk40, SCL, SDA, START, STOP, resetB, S_SDA  );
+
+    input  clk40, SCL, SDA, resetB;
+    
+    output S_SCL, START, STOP, S_SDA;
+    
+	reg S_SCL, S_SDA, SCL_late, SDA_late, sda_fall, sda_rise;
+	reg [1:0] sda_fall_late, sda_rise_late;
+
+	assign START = (sda_fall_late == 'b01);
+	assign STOP = (sda_rise_late == 'b01);
+	
+	always @(posedge clk40 or negedge resetB) begin
+		if (~resetB) begin
+			S_SCL <=#1 0;
+			S_SDA <=#1 1;
+			SCL_late<=#1 0;
+			SDA_late<=#1 1;
+			sda_rise_late <=#1 0;
+			sda_fall_late <=#1 0;
+		end
+		else begin
+			{S_SCL, SCL_late} <=#1 {SCL_late, SCL};
+			{S_SDA, SDA_late} <=#1 {SDA_late, SDA};
+
+			sda_fall_late <=#1 {sda_fall_late[0], sda_fall};
+			sda_rise_late <=#1 {sda_rise_late[0], sda_rise};
+		end
+	end
+	
+	always @(posedge SDA or negedge resetB) begin
+		if (~resetB) sda_rise <=#1 0;
+		else sda_rise <=#1 SCL;
+	end
+
+	always @(negedge SDA or negedge resetB) begin
+		if (~resetB) sda_fall <=#1 0;
+		else sda_fall <=#1 SCL;
+	end
+
+endmodule
+
+
+/*
+modul I2C_synchronizer ( S_SCL, clk40, SCL, SDA, START, STOP, resetB, S_SDA  );
+
+    input  clk40, SCL, SDA, resetB;
+    
+    output S_SCL, START, STOP, S_SDA;
+    
+    wire net68, net95, net99, net70, net86, net79, net77, net74, net90, net107, 
+        net69, net82, net65;
+	
+    E_dff_R I23 ( .D(net77), .CK(clk40), .RESb(resetB), .Q(S_SDA) );
+    E_dff_R I25 ( .D(net95), .CK(clk40), .RESb(resetB), .Q(net86) );
+    E_dff_R I24 ( .D(net99), .CK(clk40), .RESb(resetB), .Q(net90) );
+    E_Inv1 I27 ( .A(net82), .Y(STOP) );
+    E_Inv1 I26 ( .A(net86), .Y(net74) );
+    E_Inv1 I29 ( .A(net79), .Y(START) );
+    E_Nand2 I28 ( .A(net95), .B(net74), .Y(net82) );
+    E_dff_R I2 ( .D(SCL), .CK(clk40), .RESb(resetB), .Q(net107) );
+    E_dff_R I3 ( .D(net107), .CK(clk40), .RESb(resetB), .Q(S_SCL) );
+    E_dff_R I11 ( .D(SCL), .CK(net70), .RESb(resetB), .Q(net69) );
+    E_Inv1 I13 ( .A(SDA), .Y(net70) );
+    E_dff_R I12 ( .D(SCL), .CK(SDA), .RESb(resetB), .Q(net65) );
+    E_Nand2 I31 ( .A(net99), .B(net68), .Y(net79) );
+    E_dff_R I15 ( .D(net69), .CK(clk40), .RESb(resetB), .Q(net99) );
+    E_dff_R I14 ( .D(net65), .CK(clk40), .RESb(resetB), .Q(net95) );
+    E_Inv1 I30 ( .A(net90), .Y(net68) );
+    E_dff_R I16 ( .D(SDA), .CK(clk40), .RESb(resetB), .Q(net77) );
+    
+endmodul
+
+*/
+///////////////////////////////////////////////////
+//
+// i2c_clock_gating_iostate.v
+// Created on Jun  3  2008 
+// by Sandro Bonacini
+// CERN PH/ESE/ME
+//
+///////////////////////////////////////////////////
+`timescale 1ps/1ps
+module i2c_clock_gating (START, START_late, clk, clkg, en_clk, en_clk_voted,
+						STOP, resetB);
+	
+	output START_late, clkg, en_clk;
+	input START, STOP, en_clk_voted, clk, resetB;
+
+	reg START_late;
+	reg en_clk, en_clk_latched;
+	always @(clk) begin
+		if (~clk) en_clk_latched = en_clk_voted | START;
+	end
+	
+	assign  clkg = clk & en_clk_latched;
+		
+	always @(posedge clk or negedge resetB) begin
+		if (~resetB) begin
+			en_clk <=#1 0;
+			START_late <=#1 0;
+		end
+		else begin
+			en_clk <=#1 en_clk_voted;
+			if (START) en_clk <=#1 1;
+			else begin
+				if (STOP) en_clk <=#1 0;
+			end
+			
+			//if ((state==0) & (!START)) en_clk <=#1 0;
+			START_late <=#1 START;
+		end
+	end
+
+endmodule
+
+
+
diff --git a/vldb/code/Testbench/SCA-model/JTAG_channel.v b/vldb/code/Testbench/SCA-model/JTAG_channel.v
new file mode 100644
index 0000000..d97a492
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/JTAG_channel.v
@@ -0,0 +1,1232 @@
+
+
+/////////////////////////////////////////////////////////////////////////////
+// Design Name:    GBT_SCA                                                 //
+// Module Name:    JTAG_Master_Top (TRI Version)                           //
+// Made by:        Alessandro Caratelli                                    //
+//                                                                         //
+// Description:    JTAG Master fully configurable Wishbon compatible       //
+// Company:        CERN (PH-ESE)                                           //
+// Create Date:    11/April/2013-Created                                   //
+// Last modif:     1 October 2015 (for GBT-SCA V2.0)                       //
+//                                                                         //
+/////////////////////////////////////////////////////////////////////////////
+
+
+`include "JTAG_define.v"
+`include "global_defines.v"
+
+
+module JTAG_Master_Top_tri (
+	 output        TCK_pad_o_1, TCK_pad_o_2, TCK_pad_o_3,         
+	 input         TDI_pad_i_1, TDI_pad_i_2, TDI_pad_i_3,         
+	 output        TDO_pad_o_1, TDO_pad_o_2, TDO_pad_o_3,  
+	 output        TMS_pad_o_1, TMS_pad_o_2, TMS_pad_o_3,      
+	 output        RST_pad_o_1, RST_pad_o_2, RST_pad_o_3,      
+	 input         wb_clk_i_1,  wb_clk_i_2,  wb_clk_i_3,         
+	 input         wb_rst_i_1,  wb_rst_i_2,  wb_rst_i_3,         
+	 input   [5:0] wb_adr_i_1,  wb_adr_i_2,  wb_adr_i_3,       
+	 input  [31:0] wb_dat_i_1,  wb_dat_i_2,  wb_dat_i_3,      
+	 output [31:0] wb_dat_o_1,  wb_dat_o_2,  wb_dat_o_3,    
+	 input   [3:0] wb_sel_i_1,  wb_sel_i_2,  wb_sel_i_3,        
+	 input         wb_we_i_1,   wb_we_i_2,   wb_we_i_3,         
+	 input         wb_stb_i_1,  wb_stb_i_2,  wb_stb_i_3,       
+	 input         wb_cyc_i_1,  wb_cyc_i_2,  wb_cyc_i_3,       
+	 output        wb_ack_o_1,  wb_ack_o_2,  wb_ack_o_3,        
+	 output        wb_err_o_1,  wb_err_o_2,  wb_err_o_3,         
+	 output        wb_int_o_1,  wb_int_o_2,  wb_int_o_3
+	`ifdef WithSEUcounter                                               
+	,output SEUclear_1,SEUclear_2,SEUclear_3,
+	 input  [`SEUcnt_nbit-1:0] SEU_cnt_1, SEU_cnt_2, SEU_cnt_3
+	`endif	         
+);
+
+	wire    [`JTAG_MaxTrLen-1:0] rx_1,               rx_2,               rx_3;
+	wire    [`JTAG_MaxTrLen-1:0] TMStx_1,            TMStx_2,            TMStx_3;
+	wire       [`JTAG_NBits-1:0] char_len_1,         char_len_2,         char_len_3;
+	wire [`JTAVDivFregLEN-1:0]   divider_1,          divider_2,          divider_3;
+	wire [`JTAG_CTRL_BIT_NB-1:0] ctrl_1,             ctrl_2,             ctrl_3;
+	
+	wire [3:0] JTAG_TDO_txsel_1,   JTAG_TDO_txsel_2,   JTAG_TDO_txsel_3;
+	wire [3:0] JTAG_TMS_txsel_1,   JTAG_TMS_txsel_2,   JTAG_TMS_txsel_3;
+	wire	   Inv_RxEdge_1,       Inv_RxEdge_2,	   Inv_RxEdge_3;
+	wire	   Inv_TxEdge_1,       Inv_TxEdge_2,	   Inv_TxEdge_3;
+	wire	   go_1,	       go_2,		   go_3;
+	wire	   SendReset_1,        SendReset_2,	   SendReset_3;
+	wire	   lsb_1,	       lsb_2,		   lsb_3;
+	wire	   ie_1,	       ie_2,		   ie_3;
+	wire	   Inv_IdlSt_1,        Inv_IdlSt_2,	   Inv_IdlSt_3;
+	wire	   JTAG_divider_sel_1, JTAG_divider_sel_2, JTAG_divider_sel_3;
+	wire	   JTAG_ctrl_sel_1,    JTAG_ctrl_sel_2,    JTAG_ctrl_sel_3;
+	wire	   tip_1,	       tip_2,		   tip_3;
+	wire	   pos_edge_1,         pos_edge_2,	   pos_edge_3;
+	wire	   neg_edge_1,         neg_edge_2,	   neg_edge_3;
+	wire	   last_bit_1,         last_bit_2,	   last_bit_3;
+	wire	   rst_done_1,         rst_done_2,	   rst_done_3;
+	wire	   sclk_o_1,	       sclk_o_2,	   sclk_o_3;
+
+
+
+	JTAG_WB_Interface_tri JTAG__WB_Interface (
+
+                  `ifdef WithSEUcounter
+                        .SEUclear_1(SEUclear_1),
+                        .SEUclear_2(SEUclear_2),
+                        .SEUclear_3(SEUclear_3),
+                        .SEU_cnt_1(SEU_cnt_1), 
+                        .SEU_cnt_2(SEU_cnt_2), 
+                        .SEU_cnt_3(SEU_cnt_3),
+                  `endif
+
+			.wb_clk_in_1(wb_clk_i_1), 
+			.wb_rst_in_1(wb_rst_i_1), 
+			.wb_adr_in_1(wb_adr_i_1), 
+			.wb_dat_in_1(wb_dat_i_1), 
+			.wb_dat_out_1(wb_dat_o_1), 
+			.wb_sel_in_1(wb_sel_i_1), 
+			.wb_we_in_1(wb_we_i_1), 
+			.wb_stb_in_1(wb_stb_i_1), 
+			.wb_cyc_in_1(wb_cyc_i_1), 
+			.wb_ack_out_1(wb_ack_o_1), 
+			.wb_err_out_1(wb_err_o_1), 
+			.wb_int_out_1(wb_int_o_1), 
+			.rx_1(rx_1), 
+			.TMStx_1(TMStx_1), 
+			.tip_1(tip_1), 
+			.pos_edge_1(pos_edge_1), 
+			.neg_edge_1(neg_edge_1), 
+			.last_bit_1(last_bit_1), 
+			.divider_1(divider_1), 
+			.ctrl_1(ctrl_1), 
+			.ie_1(ie_1), 
+			.rst_done_1(rst_done_1), 
+			.JTAG_divider_sel_1(JTAG_divider_sel_1), 
+			.JTAG_ctrl_sel_1(JTAG_ctrl_sel_1), 
+			.JTAG_TDO_txsel_1(JTAG_TDO_txsel_1), 
+			.JTAG_TMS_txsel_1(JTAG_TMS_txsel_1),
+		.wb_clk_in_2(wb_clk_i_2), 
+			.wb_rst_in_2(wb_rst_i_2), 
+			.wb_adr_in_2(wb_adr_i_2), 
+			.wb_dat_in_2(wb_dat_i_2), 
+			.wb_dat_out_2(wb_dat_o_2), 
+			.wb_sel_in_2(wb_sel_i_2), 
+			.wb_we_in_2(wb_we_i_2), 
+			.wb_stb_in_2(wb_stb_i_2), 
+			.wb_cyc_in_2(wb_cyc_i_2), 
+			.wb_ack_out_2(wb_ack_o_2), 
+			.wb_err_out_2(wb_err_o_2), 
+			.wb_int_out_2(wb_int_o_2), 
+			.rx_2(rx_2), 
+			.TMStx_2(TMStx_2), 
+			.tip_2(tip_2), 
+			.pos_edge_2(pos_edge_2), 
+			.neg_edge_2(neg_edge_2), 
+			.last_bit_2(last_bit_2), 
+			.divider_2(divider_2), 
+			.ctrl_2(ctrl_2), 
+			.ie_2(ie_2), 
+			.rst_done_2(rst_done_2), 
+			.JTAG_divider_sel_2(JTAG_divider_sel_2), 
+			.JTAG_ctrl_sel_2(JTAG_ctrl_sel_2), 
+			.JTAG_TDO_txsel_2(JTAG_TDO_txsel_2), 
+			.JTAG_TMS_txsel_2(JTAG_TMS_txsel_2),
+		.wb_clk_in_3(wb_clk_i_3), 
+			.wb_rst_in_3(wb_rst_i_3), 
+			.wb_adr_in_3(wb_adr_i_3), 
+			.wb_dat_in_3(wb_dat_i_3), 
+			.wb_dat_out_3(wb_dat_o_3), 
+			.wb_sel_in_3(wb_sel_i_3), 
+			.wb_we_in_3(wb_we_i_3), 
+			.wb_stb_in_3(wb_stb_i_3), 
+			.wb_cyc_in_3(wb_cyc_i_3), 
+			.wb_ack_out_3(wb_ack_o_3), 
+			.wb_err_out_3(wb_err_o_3), 
+			.wb_int_out_3(wb_int_o_3), 
+			.rx_3(rx_3), 
+			.TMStx_3(TMStx_3), 
+			.tip_3(tip_3), 
+			.pos_edge_3(pos_edge_3), 
+			.neg_edge_3(neg_edge_3), 
+			.last_bit_3(last_bit_3), 
+			.divider_3(divider_3), 
+			.ctrl_3(ctrl_3), 
+			.ie_3(ie_3), 
+			.rst_done_3(rst_done_3), 
+			.JTAG_divider_sel_3(JTAG_divider_sel_3), 
+			.JTAG_ctrl_sel_3(JTAG_ctrl_sel_3), 
+			.JTAG_TDO_txsel_3(JTAG_TDO_txsel_3), 
+			.JTAG_TMS_txsel_3(JTAG_TMS_txsel_3)
+	);
+
+
+	JTAG_clock_gen_tri JTAG__clock_gen (	
+			.clk_in_1(wb_clk_i_1), 
+			.rst_1(wb_rst_i_1), 
+			.go_1(go_1 && ~SendReset_1), 
+			.enable_1(tip_1), 
+			.last_clk_1(last_bit_1),
+			.divider_1(divider_1), 
+			.clk_out_1(sclk_o_1), 
+			.pos_edge_1(pos_edge_1), 
+			.neg_edge_1(neg_edge_1),
+		.clk_in_2(wb_clk_i_2), 
+			.rst_2(wb_rst_i_2), 
+			.go_2(go_2 && ~SendReset_2), 
+			.enable_2(tip_2), 
+			.last_clk_2(last_bit_2),
+			.divider_2(divider_2), 
+			.clk_out_2(sclk_o_2), 
+			.pos_edge_2(pos_edge_2), 
+			.neg_edge_2(neg_edge_2),
+		.clk_in_3(wb_clk_i_3), 
+			.rst_3(wb_rst_i_3), 
+			.go_3(go_3 && ~SendReset_3), 
+			.enable_3(tip_3), 
+			.last_clk_3(last_bit_3),
+			.divider_3(divider_3), 
+			.clk_out_3(sclk_o_3), 
+			.pos_edge_3(pos_edge_3), 
+			.neg_edge_3(neg_edge_3)
+	);
+
+
+	JTAG_areset_tri JTAG__areset (
+			.clk_1(wb_clk_i_1),			//system clock
+			.rst_1(wb_rst_i_1),			//system reset
+			.SendReset_1(SendReset_1),		//GO sygnal for sending asyncronous reset
+			.Inv_IdlSt_1(Inv_IdlSt_1),		//it inverts the level (standard active low)
+			.len_1(char_len_1[`JTAG_NBits-1:0]),
+			.rst_done_1(rst_done_1),
+			.reset_pad_o_1(RST_pad_o_1),
+		.clk_2(wb_clk_i_2),				//system clock
+			.rst_2(wb_rst_i_2),			//system reset
+			.SendReset_2(SendReset_2),		//GO sygnal for sending asyncronous reset
+			.Inv_IdlSt_2(Inv_IdlSt_2),		//it inverts the level (standard active low)
+			.len_2(char_len_2[`JTAG_NBits-1:0]),
+			.rst_done_2(rst_done_2),
+			.reset_pad_o_2(RST_pad_o_2),
+		.clk_3(wb_clk_i_3),				//system clock
+			.rst_3(wb_rst_i_3),			//system reset
+			.SendReset_3(SendReset_3),		//GO sygnal for sending asyncronous reset
+			.Inv_IdlSt_3(Inv_IdlSt_3),		//it inverts the level (standard active low)
+			.len_3(char_len_3[`JTAG_NBits-1:0]),
+			.rst_done_3(rst_done_3),
+			.reset_pad_o_3(RST_pad_o_3)
+	);
+
+
+	JTAG_shift_tri JTAG__shift (
+			.clk_1(wb_clk_i_1), 
+			.rst_1(wb_rst_i_1), 
+			.len_1(char_len_1[`JTAG_NBits-1:0]),
+			.lsb_1(lsb_1), 
+			.go_1(go_1 && ~SendReset_1), 
+			.pos_edge_1(pos_edge_1), 
+			.neg_edge_1(neg_edge_1), 
+			.Inv_RxEdge_1(Inv_RxEdge_1), 
+			.Inv_TxEdge_1(Inv_TxEdge_1),
+			.Inv_IdlSt_1(Inv_IdlSt_1),
+			.tip_1(tip_1), 
+			.last_1(last_bit_1),
+			.p_in_1(wb_dat_i_1), 
+			.dataTDO_1(rx_1),
+			.dataTMS_1(TMStx_1),
+			.latchTDO_1(JTAG_TDO_txsel_1[3:0] & {4{wb_we_i_1}}), 
+			.latchTMS_1(JTAG_TMS_txsel_1[3:0] & {4{wb_we_i_1}}), 
+			.byte_sel_1(wb_sel_i_1),
+			.s_in_1(TDI_pad_i_1), 
+			.s_outTDO_1(TDO_pad_o_1),
+			.s_outTMS_1(TMS_pad_o_1),
+		.clk_2(wb_clk_i_2), 
+			.rst_2(wb_rst_i_2), 
+			.len_2(char_len_2[`JTAG_NBits-1:0]),
+			.lsb_2(lsb_2), 
+			.go_2(go_2 && ~SendReset_2), 
+			.pos_edge_2(pos_edge_2), 
+			.neg_edge_2(neg_edge_2), 
+			.Inv_RxEdge_2(Inv_RxEdge_2), 
+			.Inv_TxEdge_2(Inv_TxEdge_2),
+			.Inv_IdlSt_2(Inv_IdlSt_2),
+			.tip_2(tip_2), 
+			.last_2(last_bit_2),
+			.p_in_2(wb_dat_i_2), 
+			.dataTDO_2(rx_2),
+			.dataTMS_2(TMStx_2),
+			.latchTDO_2(JTAG_TDO_txsel_2[3:0] & {4{wb_we_i_2}}), 
+			.latchTMS_2(JTAG_TMS_txsel_2[3:0] & {4{wb_we_i_2}}), 
+			.byte_sel_2(wb_sel_i_2),
+			.s_in_2(TDI_pad_i_2), 
+			.s_outTDO_2(TDO_pad_o_2),
+			.s_outTMS_2(TMS_pad_o_2),
+		.clk_3(wb_clk_i_3), 
+			.rst_3(wb_rst_i_3), 
+			.len_3(char_len_3[`JTAG_NBits-1:0]),
+			.lsb_3(lsb_3), 
+			.go_3(go_3 && ~SendReset_3), 
+			.pos_edge_3(pos_edge_3), 
+			.neg_edge_3(neg_edge_3), 
+			.Inv_RxEdge_3(Inv_RxEdge_3), 
+			.Inv_TxEdge_3(Inv_TxEdge_3),
+			.Inv_IdlSt_3(Inv_IdlSt_3),
+			.tip_3(tip_3), 
+			.last_3(last_bit_3),
+			.p_in_3(wb_dat_i_3), 
+			.dataTDO_3(rx_3),
+			.dataTMS_3(TMStx_3),
+			.latchTDO_3(JTAG_TDO_txsel_3[3:0] & {4{wb_we_i_3}}), 
+			.latchTMS_3(JTAG_TMS_txsel_3[3:0] & {4{wb_we_i_3}}), 
+			.byte_sel_3(wb_sel_i_3),
+			.s_in_3(TDI_pad_i_3), 
+			.s_outTDO_3(TDO_pad_o_3),
+			.s_outTMS_3(TMS_pad_o_3)
+	);
+
+
+	assign Inv_IdlSt_1        =  ctrl_1[`JTAG_CTRL_Inv_IdlSt];
+	assign Inv_IdlSt_2        =  ctrl_2[`JTAG_CTRL_Inv_IdlSt];
+	assign Inv_IdlSt_3        =  ctrl_3[`JTAG_CTRL_Inv_IdlSt];
+
+	assign go_1               =  ctrl_1[`JTAG_CTRL_GO];
+	assign go_2               =  ctrl_2[`JTAG_CTRL_GO];
+	assign go_3               =  ctrl_3[`JTAG_CTRL_GO];
+
+	assign char_len_1         =  ctrl_1[`JTAG_CTRL_CHAR_LEN];
+	assign char_len_2         =  ctrl_2[`JTAG_CTRL_CHAR_LEN];
+	assign char_len_3         =  ctrl_3[`JTAG_CTRL_CHAR_LEN];
+
+	assign lsb_1              = ~ctrl_1[`JTAG_CTRL_Inv_TrDir];
+	assign lsb_2              = ~ctrl_2[`JTAG_CTRL_Inv_TrDir];
+	assign lsb_3              = ~ctrl_3[`JTAG_CTRL_Inv_TrDir];
+
+	assign ie_1             =  ctrl_1[`JTAG_CTRL_IE];  //01-Oct-2015
+	assign ie_2             =  ctrl_2[`JTAG_CTRL_IE];  //01-Oct-2015
+	assign ie_3             =  ctrl_3[`JTAG_CTRL_IE];  //01-Oct-2015
+
+	//assign ie_1               =  1'b1;  //01-Oct-2015
+	//assign ie_2               =  1'b1;  //01-Oct-2015
+	//assign ie_3               =  1'b1;  //01-Oct-2015
+	
+	assign SendReset_1        =  ctrl_1[`JTAG_CTRL_RES];
+	assign SendReset_2        =  ctrl_2[`JTAG_CTRL_RES];
+	assign SendReset_3        =  ctrl_3[`JTAG_CTRL_RES];
+
+	assign Inv_RxEdge_1       = (~Inv_IdlSt_1) ? ctrl_1[`JTAG_CTRL_Inv_RxEdge] : ~ctrl_1[`JTAG_CTRL_Inv_RxEdge];
+	assign Inv_RxEdge_2       = (~Inv_IdlSt_2) ? ctrl_2[`JTAG_CTRL_Inv_RxEdge] : ~ctrl_2[`JTAG_CTRL_Inv_RxEdge];
+	assign Inv_RxEdge_3       = (~Inv_IdlSt_3) ? ctrl_3[`JTAG_CTRL_Inv_RxEdge] : ~ctrl_3[`JTAG_CTRL_Inv_RxEdge];
+
+	assign Inv_TxEdge_1       = (~Inv_IdlSt_1) ? ctrl_1[`JTAG_CTRL_Inv_TxEdge] : ~ctrl_1[`JTAG_CTRL_Inv_TxEdge];
+	assign Inv_TxEdge_2       = (~Inv_IdlSt_2) ? ctrl_2[`JTAG_CTRL_Inv_TxEdge] : ~ctrl_2[`JTAG_CTRL_Inv_TxEdge];
+	assign Inv_TxEdge_3       = (~Inv_IdlSt_3) ? ctrl_3[`JTAG_CTRL_Inv_TxEdge] : ~ctrl_3[`JTAG_CTRL_Inv_TxEdge];
+	
+	assign TCK_pad_o_1       = (Inv_IdlSt_1) ? sclk_o_1 : ~sclk_o_1;
+	assign TCK_pad_o_2       = (Inv_IdlSt_2) ? sclk_o_2 : ~sclk_o_2;
+	assign TCK_pad_o_3       = (Inv_IdlSt_3) ? sclk_o_3 : ~sclk_o_3;
+
+	assign wb_err_o_1       = 1'b0;
+	assign wb_err_o_2       = 1'b0;
+	assign wb_err_o_3       = 1'b0;
+endmodule
+
+
+/////////////////////////////////////////////////////////////////////////////
+// Design Name:    GBT_SCA                                                 //
+// Module Name:    JTAG_areset (TRI Version)                               //
+// Description:    JTAG Master fully configurable Wishbon compatible       //
+// Company:        CERN (PH-ESE)                                           //
+// Made by:        Alessandro Caratelli                                    //
+// Create Date:    11/April/2013-Created                                   //
+//                 27/June/2013-Small Modifications                        //
+/////////////////////////////////////////////////////////////////////////////
+`include "JTAG_define.v"
+module JTAG_areset_iostate (clk,rst,SendReset,Inv_IdlSt,len,rst_done,reset_pad_o, clkdiv_i, clkdiv_o, cnt_i, cnt_o, tip_i, tip_o);
+
+  input                  clk;                                                      
+  input                  tip_i;
+  input  [`JTAG_NBits:0] cnt_i;
+  input                  clkdiv_i;
+  input                  rst;                   
+  input                  SendReset;          
+  input                  Inv_IdlSt;           
+  input[`JTAG_NBits-1:0] len;
+  output                 rst_done;            
+  output                 tip_o;
+  output [`JTAG_NBits:0] cnt_o;
+  output                 clkdiv_o;
+  output                 reset_pad_o;      
+  
+  reg    [`JTAG_NBits:0] cnt_o;
+  reg                    tip_o;
+  reg                    clkdiv_o;
+  wire                   rst_done;
+  wire                   reset_pad_o;
+  
+  assign rst_done = !(|cnt_i) ? 1'b1 : 1'b0;
+  
+  assign reset_pad_o = ~Inv_IdlSt ? (tip_i ? 1'b0 : 1'b1) : (tip_i ? 1'b1 : 1'b0);
+  
+  always @ (posedge clk or posedge rst) begin
+    if(rst) clkdiv_o <= 1'b0;
+       else clkdiv_o <= ~clkdiv_i;
+      end
+  
+  always @(posedge clk or posedge rst) begin
+    if(rst) 
+      cnt_o <= {`JTAG_NBits+1{1'b1}};
+    else
+      if(~tip_i) 
+                  cnt_o <= !(|len) ? `JTAG_NBits'b1 : {1'b0, len};
+            else
+                  cnt_o <= (clkdiv_i) ? (cnt_i - {{`JTAG_NBits{1'b0}}, 1'b1}) : cnt_i;
+      end
+      
+      always @(posedge clk or posedge rst) begin
+            if(rst) 
+                  tip_o <= 1'b0;
+            else begin
+                  tip_o <= tip_i;
+                  if(SendReset && ~tip_i) 
+                        tip_o <=1'b1;
+                  else 
+                        if(tip_i)
+                              tip_o <= !(|cnt_i) ? 1'b0 : 1'b1;
+                        else
+                              tip_o <= 1'b0;
+                  end
+            end      
+endmodule
+
+`include "JTAG_define.v"
+module JTAG_areset_tri (clk_1, clk_2, clk_3,rst_1, rst_2, rst_3,SendReset_1, SendReset_2, SendReset_3,Inv_IdlSt_1, Inv_IdlSt_2, Inv_IdlSt_3,len_1, len_2, len_3,rst_done_1, rst_done_2, rst_done_3,reset_pad_o_1, reset_pad_o_2, reset_pad_o_3);
+
+      input                    clk_1, clk_2, clk_3;      
+      input                    rst_1, rst_2, rst_3;       
+      input                    SendReset_1, SendReset_2, SendReset_3;      
+      input                    Inv_IdlSt_1, Inv_IdlSt_2, Inv_IdlSt_3;      
+      input  [`JTAG_NBits-1:0] len_1, len_2, len_3;
+      output                   rst_done_1, rst_done_2, rst_done_3;            
+      output                   reset_pad_o_1, reset_pad_o_2, reset_pad_o_3;      
+
+      wire clkdiv_1, clkdiv_2, clkdiv_3;
+      wire [`JTAG_NBits:0] cnt_1, cnt_2, cnt_3;
+      wire tip_1, tip_2, tip_3;
+      wire clkdiv;
+      wire [`JTAG_NBits:0] cnt;
+      wire tip;
+      
+      JTAG_areset_iostate JTAG_areset_iostate_1   (.clk(clk_1),.rst(rst_1),.SendReset(SendReset_1),.Inv_IdlSt(Inv_IdlSt_1),.len(len_1),.rst_done(rst_done_1),.reset_pad_o(reset_pad_o_1), .clkdiv_i(clkdiv_1), .clkdiv_o(clkdiv_2), .cnt_i(cnt_1), .cnt_o(cnt_2), .tip_i(tip_1), .tip_o(tip_2));
+
+      JTAG_areset_iostate JTAG_areset_iostate_2   (.clk(clk_2),.rst(rst_2),.SendReset(SendReset_2),.Inv_IdlSt(Inv_IdlSt_2),.len(len_2),.rst_done(rst_done_2),.reset_pad_o(reset_pad_o_2), .clkdiv_i(clkdiv_2), .clkdiv_o(clkdiv_3), .cnt_i(cnt_2), .cnt_o(cnt_3), .tip_i(tip_2), .tip_o(tip_3));
+
+      JTAG_areset_iostate JTAG_areset_iostate_3   (.clk(clk_3),.rst(rst_3),.SendReset(SendReset_3),.Inv_IdlSt(Inv_IdlSt_3),.len(len_3),.rst_done(rst_done_3),.reset_pad_o(reset_pad_o_3), .clkdiv_i(clkdiv_3), .clkdiv_o(clkdiv), .cnt_i(cnt_3), .cnt_o(cnt), .tip_i(tip_3), .tip_o(tip));
+
+      majority_voter #(.WIDTH(3+`JTAG_NBits)) mv (
+            .in1({clkdiv_2, cnt_2, tip_2}),
+            .in2({clkdiv_3, cnt_3, tip_3}),
+            .in3({clkdiv, cnt, tip}),
+            .out({clkdiv_1, cnt_1, tip_1}),
+            .err()
+      );
+endmodule
+
+
+
+
+
+/////////////////////////////////////////////////////////////////////////////
+// Design Name:    GBT_SCA                                                 //
+// Module Name:    JTAG_clkgen(TRI Version)                                //
+// Description:    JTAG Master fully configurable Wishbon compatible       //
+// Company:        CERN (PH-ESE)                                           //
+// Made by:        Alessandro Caratelli                                    //
+// Create Date:    11/April/2013-Created                                   //
+//                 27/June/2013-Small Modifications                        //
+/////////////////////////////////////////////////////////////////////////////
+`include "JTAG_define.v"
+module JTAG_clock_gen_iostate (clk_in, rst, go, enable, last_clk, divider, clk_out_i, clk_out_o, pos_edge_i, pos_edge_o, neg_edge_i, neg_edge_o, cnt_i, cnt_o); 
+  parameter Tp = 1;
+  
+  input  clk_in;   								
+  input  neg_edge_i; 
+  input  pos_edge_i; 								
+  input  clk_out_i; 
+  input  [`JTAVDivFregLEN-1:0] cnt_i;       // input clock (system clock)
+  input  rst;      								// reset
+  input  enable;  							 	// clock enable
+  input  go;       								// start transfer
+  input  last_clk; 								// last clock
+  input  [`JTAVDivFregLEN-1:0] divider;  	// clock divider (output clock is divided by this value)
+  output clk_out_o;                          
+  reg    clk_out_o;
+  output pos_edge_o;
+  output neg_edge_o;
+  output    [`JTAVDivFregLEN-1:0] cnt_o;
+  reg    pos_edge_o;
+  reg    neg_edge_o;                       
+  wire   cnt_zero; 								// conter is equal to zero
+  wire   cnt_one;  								// conter is equal to one
+  reg    [`JTAVDivFregLEN-1:0] cnt_o;
+	// clock counter 
+  
+  assign cnt_zero = cnt_i == {`JTAVDivFregLEN{1'b0}};
+  assign cnt_one  = cnt_i == {{`JTAVDivFregLEN-1{1'b0}}, 1'b1};
+  
+  // Counter counts half period
+  always @(posedge clk_in or posedge rst)
+  begin
+    if(rst)
+      cnt_o <=  {`JTAVDivFregLEN{1'b1}};
+    else
+      begin
+		   cnt_o <= cnt_i;
+			if(!enable || cnt_zero)
+				cnt_o <=  divider;
+			else
+				cnt_o <=  cnt_i - {{`JTAVDivFregLEN-1{1'b0}}, 1'b1};
+      end
+  end
+  
+  // clk_out is asserted every other half period
+  always @(posedge clk_in or posedge rst)
+  begin
+    if(rst)
+      clk_out_o <=  1'b0;
+    else
+      clk_out_o <=  (enable && cnt_zero && (!last_clk || clk_out_i)) ? ~clk_out_i : clk_out_i;
+  end
+   
+  // Pos and neg edge signals
+  always @(posedge clk_in or posedge rst)
+  begin
+    if(rst)
+      begin
+        pos_edge_o  <=  1'b0;
+        neg_edge_o  <=  1'b0;
+      end
+    else
+      begin
+        pos_edge_o  <=  (enable && !clk_out_i && cnt_one) || (!(|divider) && clk_out_i) || (!(|divider) && go && !enable);
+        neg_edge_o  <=  (enable && clk_out_i && cnt_one)  || (!(|divider) && !clk_out_i && enable);
+      end
+  end
+endmodule
+
+`include "JTAG_define.v"
+module JTAG_clock_gen_tri (clk_in_1, clk_in_2, clk_in_3, rst_1, rst_2, rst_3, go_1, go_2, go_3, enable_1, enable_2, enable_3, last_clk_1, last_clk_2, last_clk_3, divider_1, divider_2, divider_3, clk_out_1, clk_out_2, clk_out_3, pos_edge_1, pos_edge_2, pos_edge_3, neg_edge_1, neg_edge_2, neg_edge_3);
+
+	parameter Tp = 1;
+
+	input  clk_in_1, clk_in_2, clk_in_3;   								
+	input  rst_1, rst_2, rst_3;      								
+	input  enable_1, enable_2, enable_3;  							 	
+	input  go_1, go_2, go_3;       								
+	input  last_clk_1, last_clk_2, last_clk_3; 								
+	input  [`JTAVDivFregLEN-1:0] divider_1, divider_2, divider_3;  	
+	output clk_out_1, clk_out_2, clk_out_3;  								
+	output pos_edge_1, pos_edge_2, pos_edge_3; 								
+	output neg_edge_1, neg_edge_2, neg_edge_3; 								
+
+	wire [`JTAVDivFregLEN-1:0] cnt_1, cnt_2, cnt_3;
+	wire clk_out_1, clk_out_2, clk_out_3;
+	wire pos_edge_1, pos_edge_2, pos_edge_3;
+	wire neg_edge_1, neg_edge_2, neg_edge_3;
+	wire [`JTAVDivFregLEN-1:0] cnt;
+	wire clk_out;
+	wire pos_edge;
+	wire neg_edge;
+
+	JTAG_clock_gen_iostate #(.Tp(Tp) ) JTAG_clock_gen_iostate_1 (.clk_in(clk_in_1), .rst(rst_1), .go(go_1), .enable(enable_1), .last_clk(last_clk_1), .divider(divider_1), .clk_out_i(clk_out_1), .clk_out_o(clk_out_2), .pos_edge_i(pos_edge_1), .pos_edge_o(pos_edge_2), .neg_edge_i(neg_edge_1), .neg_edge_o(neg_edge_2), .cnt_i(cnt_1), .cnt_o(cnt_2));
+
+	JTAG_clock_gen_iostate #(.Tp(Tp) ) JTAG_clock_gen_iostate_2 (.clk_in(clk_in_2), .rst(rst_2), .go(go_2), .enable(enable_2), .last_clk(last_clk_2), .divider(divider_2), .clk_out_i(clk_out_2), .clk_out_o(clk_out_3), .pos_edge_i(pos_edge_2), .pos_edge_o(pos_edge_3), .neg_edge_i(neg_edge_2), .neg_edge_o(neg_edge_3), .cnt_i(cnt_2), .cnt_o(cnt_3));
+
+	JTAG_clock_gen_iostate #(.Tp(Tp) ) JTAG_clock_gen_iostate_3 (.clk_in(clk_in_3), .rst(rst_3), .go(go_3), .enable(enable_3), .last_clk(last_clk_3), .divider(divider_3), .clk_out_i(clk_out_3), .clk_out_o(clk_out), .pos_edge_i(pos_edge_3), .pos_edge_o(pos_edge), .neg_edge_i(neg_edge_3), .neg_edge_o(neg_edge), .cnt_i(cnt_3), .cnt_o(cnt));
+
+	majority_voter #(.WIDTH(4+`JTAVDivFregLEN-1)) mv (
+		.in1({cnt_2, clk_out_2, pos_edge_2, neg_edge_2}),
+		.in2({cnt_3, clk_out_3, pos_edge_3, neg_edge_3}),
+		.in3({cnt, clk_out, pos_edge, neg_edge}),
+		.out({cnt_1, clk_out_1, pos_edge_1, neg_edge_1}),
+		.err()
+	);
+endmodule
+
+
+
+
+
+/////////////////////////////////////////////////////////////////////////////
+// Design Name:    GBT_SCA                                                 //
+// Module Name:    JTAG_shift (TRI Version)                                //
+// Description:    JTAG Master fully configurable Wishbon compatible       //
+// Company:        CERN (PH-ESE)                                           //
+// Made by:        Alessandro Caratelli                                    //
+// Create Date:    11/April/2013-Created                                   //
+//                 27/June/2013-Small Modifications                        //
+/////////////////////////////////////////////////////////////////////////////
+
+`include "JTAG_define.v"
+`timescale 1ns / 1ps
+module JTAG_shift_iostate (clk, rst, latchTDO, latchTMS, byte_sel, len, lsb, go,
+                  pos_edge, neg_edge, Inv_RxEdge, Inv_TxEdge,
+                  tip_i, tip_o, last,  dataTMS_i, dataTMS_o,dataTDO_i, dataTDO_o,
+                  p_in, s_in, s_outTDO,s_outTMS, Inv_IdlSt, cnt_i, cnt_o, serial_outTDO_i, serial_outTDO_o, serial_outTMS_i, serial_outTMS_o);
+
+  parameter Tp = 1;
+  
+  input                      clk;                                             
+  input [`JTAG_MaxTrLen-1:0] dataTDO_i;      
+  input                      s_in;                                             
+  input                      serial_outTMS_i;
+  input                      serial_outTDO_i;
+  input                      Inv_IdlSt;
+  input      [`JTAG_NBits:0] cnt_i;      // system clock
+  input                      rst;        // reset
+  input                [3:0] latchTDO;   // latch signal for storing the data in shift register
+  input                [3:0] latchTMS;   // latch signal for storing the data in shift register
+  input                [3:0] byte_sel;   // byte select signals for storing the data in shift register
+  input    [`JTAG_NBits-1:0] len;        // data len in bits (minus one)
+  input                      lsb;        // lbs first on the line
+  input                      go;         // start stansfer
+  input                      pos_edge;   // recognize posedge of sclk
+  input                      neg_edge;   // recognize negedge of sclk
+  input                      Inv_RxEdge; // s_in is sampled on negative edge 
+  input                      Inv_TxEdge; // s_out is driven on negative edge
+  output                     tip_o;
+  output[`JTAG_MaxTrLen-1:0] dataTDO_o;
+  output                     s_outTDO;                                      
+  output                     serial_outTMS_o;
+  output                     serial_outTDO_o;
+  output                     s_outTMS;                                      
+  input                      tip_i;                                              
+  output     [`JTAG_NBits:0] cnt_o;
+  output                     last;                                             
+  input               [31:0] p_in;                                  
+  output[`JTAG_MaxTrLen-1:0] dataTMS_o;
+  input [`JTAG_MaxTrLen-1:0] dataTMS_i;      
+  
+  
+  reg                        serial_outTDO_o;
+  reg                        serial_outTMS_o;
+  wire                       s_outTDO, s_outTMS;
+  reg                        tip_o;                         
+  reg        [`JTAG_NBits:0] cnt_o;
+  reg   [`JTAG_MaxTrLen-1:0] dataTDO_o; 
+  reg   [`JTAG_MaxTrLen-1:0] dataTMS_o; 
+  wire       [`JTAG_NBits:0] tx_bit_pos;   
+  wire       [`JTAG_NBits:0] rx_bit_pos;   
+  wire                       rx_clk;                                           
+  wire                       tx_clk;                                           
+              
+  
+  assign last = !(|cnt_i); //se zero
+  
+  assign rx_clk = (Inv_RxEdge ? pos_edge : neg_edge) && tip_i;
+  
+  assign tx_clk = (Inv_TxEdge ? neg_edge : pos_edge) && tip_i;
+  
+  assign tx_bit_pos = lsb ? ({!(|len), len} - cnt_i) : (cnt_i - {{`JTAG_NBits{1'b0}},1'b1});
+  
+  assign rx_bit_pos = lsb ? ({!(|len), len} - (~Inv_RxEdge ? cnt_i + {{`JTAG_NBits{1'b0}},1'b1} : cnt_i) ) : 
+                            ( (~Inv_RxEdge ? cnt_i : cnt_i - {{`JTAG_NBits{1'b0}},1'b1}) );
+									 
+  // Character bit counter
+  always @(posedge clk or posedge rst)
+  begin
+    if(rst)
+      cnt_o <= #Tp {`JTAG_NBits+1{1'b0}};
+    else
+      begin
+			cnt_o <= cnt_i;
+			if(tip_i)
+				cnt_o <= #Tp pos_edge ? (cnt_i - {{`JTAG_NBits{1'b0}}, 1'b1}) : cnt_i;
+			else
+				cnt_o <= #Tp !(|len) ? {1'b1, {`JTAG_NBits{1'b0}}} : {1'b0, len};
+      end
+	end
+  
+  // Transfer in progress
+  always @(posedge clk or posedge rst)
+  begin
+   if(rst)
+      	tip_o <= #Tp 1'b0;
+  	else begin 
+		if(go && ~tip_i)
+    		tip_o <= #Tp 1'b1;
+		else if(tip_i && last && pos_edge)
+    		tip_o <= #Tp 1'b0;
+		else tip_o <= #Tp tip_i; 
+		end
+  end
+  
+  // Sending bits to the line
+  always @(posedge clk or posedge rst)
+  begin
+    if (rst)
+      serial_outTDO_o   <= #Tp 1'b1;
+    else
+      serial_outTDO_o <= #Tp (tx_clk || !tip_i) ? dataTDO_i[tx_bit_pos[`JTAG_NBits-1:0]] : serial_outTDO_i;
+  end
+  
+  assign s_outTDO = (tip_i) ? serial_outTDO_i : ~Inv_IdlSt;
+  
+  always @(posedge clk or posedge rst)
+  begin
+    if (rst)
+      serial_outTMS_o   <= #Tp 1'b1;
+    else
+      serial_outTMS_o <= #Tp (tx_clk || !tip_i) ? dataTMS_i[tx_bit_pos[`JTAG_NBits-1:0]] : serial_outTMS_i;
+  end
+  assign s_outTMS = (tip_i) ? serial_outTMS_i : ~Inv_IdlSt;
+  
+  
+  // Receiving bits from the line
+  always @(posedge clk or posedge rst)
+  begin
+    if (rst)
+      dataTDO_o   <= #Tp {`JTAG_MaxTrLen{1'b0}};
+
+    else begin
+			dataTDO_o <= dataTDO_i;
+			if (latchTDO[0] && !tip_i)
+			begin
+			  if (byte_sel[3])
+				 dataTDO_o[31:24] <= #Tp p_in[31:24];
+			  if (byte_sel[2])
+				 dataTDO_o[23:16] <= #Tp p_in[23:16];
+			  if (byte_sel[1])
+				 dataTDO_o[15:8] <= #Tp p_in[15:8];
+			  if (byte_sel[0])
+				 dataTDO_o[7:0] <= #Tp p_in[7:0];
+			end
+			else if (latchTDO[1] && !tip_i)
+			begin
+			  if (byte_sel[3])
+				 dataTDO_o[63:56] <= #Tp p_in[31:24];
+			  if (byte_sel[2])
+				 dataTDO_o[55:48] <= #Tp p_in[23:16];
+			  if (byte_sel[1])
+				 dataTDO_o[47:40] <= #Tp p_in[15:8];
+			  if (byte_sel[0])
+				 dataTDO_o[39:32] <= #Tp p_in[7:0];
+			end
+			else if (latchTDO[2] && !tip_i)
+			begin
+			  if (byte_sel[3])
+				 dataTDO_o[95:88] <= #Tp p_in[31:24];
+			  if (byte_sel[2])
+				 dataTDO_o[87:80] <= #Tp p_in[23:16];
+			  if (byte_sel[1])
+				 dataTDO_o[79:72] <= #Tp p_in[15:8];
+			  if (byte_sel[0])
+				 dataTDO_o[71:64] <= #Tp p_in[7:0];
+			end
+			else if (latchTDO[3] && !tip_i)
+			begin
+			  if (byte_sel[3])
+				 dataTDO_o[127:120] <= #Tp p_in[31:24];
+			  if (byte_sel[2])
+				 dataTDO_o[119:112] <= #Tp p_in[23:16];
+			  if (byte_sel[1])
+				 dataTDO_o[111:104] <= #Tp p_in[15:8];
+			  if (byte_sel[0])
+				 dataTDO_o[103:96] <= #Tp p_in[7:0];
+			end
+			else dataTDO_o[rx_bit_pos[`JTAG_NBits-1:0]] <= #Tp rx_clk ? s_in : dataTDO_i[rx_bit_pos[`JTAG_NBits-1:0]];
+		end
+  end
+
+ always @(posedge clk or posedge rst)
+  begin
+    if (rst)
+      dataTMS_o   <= #Tp {`JTAG_MaxTrLen{1'b0}};
+    else begin
+		dataTMS_o   <= #Tp dataTMS_i;
+		if (latchTMS[0] && !tip_i)
+			begin
+			  if (byte_sel[3])
+				 dataTMS_o[31:24] <= #Tp p_in[31:24];
+			  if (byte_sel[2])
+				 dataTMS_o[23:16] <= #Tp p_in[23:16];
+			  if (byte_sel[1])
+				 dataTMS_o[15:8] <= #Tp p_in[15:8];
+			  if (byte_sel[0])
+				 dataTMS_o[7:0] <= #Tp p_in[7:0];
+			end
+			else if (latchTMS[1] && !tip_i)
+			begin
+			  if (byte_sel[3])
+				 dataTMS_o[63:56] <= #Tp p_in[31:24];
+			  if (byte_sel[2])
+				 dataTMS_o[55:48] <= #Tp p_in[23:16];
+			  if (byte_sel[1])
+				 dataTMS_o[47:40] <= #Tp p_in[15:8];
+			  if (byte_sel[0])
+				 dataTMS_o[39:32] <= #Tp p_in[7:0];
+			end
+			else if (latchTMS[2] && !tip_i)
+			begin
+			  if (byte_sel[3])
+				 dataTMS_o[95:88] <= #Tp p_in[31:24];
+			  if (byte_sel[2])
+				 dataTMS_o[87:80] <= #Tp p_in[23:16];
+			  if (byte_sel[1])
+				 dataTMS_o[79:72] <= #Tp p_in[15:8];
+			  if (byte_sel[0])
+				 dataTMS_o[71:64] <= #Tp p_in[7:0];
+			end
+			else if (latchTMS[3] && !tip_i)
+			begin
+			  if (byte_sel[3])
+				 dataTMS_o[127:120] <= #Tp p_in[31:24];
+			  if (byte_sel[2])
+				 dataTMS_o[119:112] <= #Tp p_in[23:16];
+			  if (byte_sel[1])
+				 dataTMS_o[111:104] <= #Tp p_in[15:8];
+			  if (byte_sel[0])
+				 dataTMS_o[103:96] <= #Tp p_in[7:0];
+			end
+		end
+   
+  end 
+endmodule 
+
+
+`include "JTAG_define.v"
+
+module JTAG_shift_tri (clk_1, clk_2, clk_3, rst_1, rst_2, rst_3, latchTDO_1, latchTDO_2, latchTDO_3, latchTMS_1, latchTMS_2, latchTMS_3, byte_sel_1, byte_sel_2, byte_sel_3, len_1, len_2, len_3, lsb_1, lsb_2, lsb_3, go_1, go_2, go_3,
+                  pos_edge_1, pos_edge_2, pos_edge_3, neg_edge_1, neg_edge_2, neg_edge_3, Inv_RxEdge_1, Inv_RxEdge_2, Inv_RxEdge_3, Inv_TxEdge_1, Inv_TxEdge_2, Inv_TxEdge_3,
+                  tip_1, tip_2, tip_3, last_1, last_2, last_3,  dataTMS_1, dataTMS_2, dataTMS_3,dataTDO_1, dataTDO_2, dataTDO_3,
+                  p_in_1, p_in_2, p_in_3, s_in_1, s_in_2, s_in_3, s_outTDO_1, s_outTDO_2, s_outTDO_3,s_outTMS_1, s_outTMS_2, s_outTMS_3, Inv_IdlSt_1, Inv_IdlSt_2, Inv_IdlSt_3);
+
+	input                       clk_1, clk_2, clk_3;         
+	input                       rst_1, rst_2, rst_3;         
+	input                 [3:0] latchTDO_1, latchTDO_2, latchTDO_3;     
+	input                 [3:0] latchTMS_1, latchTMS_2, latchTMS_3;       
+	input                 [3:0] byte_sel_1, byte_sel_2, byte_sel_3;     
+	input     [`JTAG_NBits-1:0] len_1, len_2, len_3;         
+	input                       lsb_1, lsb_2, lsb_3;         
+	input                       go_1, go_2, go_3;          
+	input                       pos_edge_1, pos_edge_2, pos_edge_3;     
+	input                       neg_edge_1, neg_edge_2, neg_edge_3;     
+	input                       Inv_RxEdge_1, Inv_RxEdge_2, Inv_RxEdge_3;    
+	input                       Inv_TxEdge_1, Inv_TxEdge_2, Inv_TxEdge_3;   
+	output                      tip_1, tip_2, tip_3;          
+	output                      last_1, last_2, last_3;        
+	input                [31:0] p_in_1, p_in_2, p_in_3;    
+	output [`JTAG_MaxTrLen-1:0] dataTMS_1, dataTMS_2, dataTMS_3;
+	output [`JTAG_MaxTrLen-1:0] dataTDO_1, dataTDO_2, dataTDO_3;
+	input                       s_in_1, s_in_2, s_in_3;    
+	output                      s_outTDO_1, s_outTDO_2, s_outTDO_3;        
+	output                      s_outTMS_1, s_outTMS_2, s_outTMS_3;        
+	input                       Inv_IdlSt_1, Inv_IdlSt_2, Inv_IdlSt_3;
+
+	wire [`JTAG_NBits:0] cnt_1, cnt_2, cnt_3;
+	wire tip_1, tip_2, tip_3;
+	wire serial_outTDO_1, serial_outTDO_2, serial_outTDO_3;
+	wire serial_outTMS_1, serial_outTMS_2, serial_outTMS_3;
+	wire [`JTAG_MaxTrLen-1:0] dataTDO_1, dataTDO_2, dataTDO_3;
+	wire [`JTAG_MaxTrLen-1:0] dataTMS_1, dataTMS_2, dataTMS_3;
+	wire [`JTAG_NBits:0] cnt;
+	wire tip;
+	wire serial_outTDO;
+	wire serial_outTMS;
+	wire [`JTAG_MaxTrLen-1:0] dataTDO;
+	wire [`JTAG_MaxTrLen-1:0] dataTMS;
+
+	JTAG_shift_iostate #(.Tp(1) ) JTAG_shift_iostate_1 (.clk(clk_1), .rst(rst_1), .latchTDO(latchTDO_1), .latchTMS(latchTMS_1), .byte_sel(byte_sel_1), .len(len_1), .lsb(lsb_1), .go(go_1),
+                  .pos_edge(pos_edge_1), .neg_edge(neg_edge_1), .Inv_RxEdge(Inv_RxEdge_1), .Inv_TxEdge(Inv_TxEdge_1),
+                  .tip_i(tip_1), .tip_o(tip_2), .last(last_1),  .dataTMS_i(dataTMS_1), .dataTMS_o(dataTMS_2),.dataTDO_i(dataTDO_1), .dataTDO_o(dataTDO_2),
+                  .p_in(p_in_1), .s_in(s_in_1), .s_outTDO(s_outTDO_1),.s_outTMS(s_outTMS_1), .Inv_IdlSt(Inv_IdlSt_1), .cnt_i(cnt_1), .cnt_o(cnt_2), .serial_outTDO_i(serial_outTDO_1), .serial_outTDO_o(serial_outTDO_2), .serial_outTMS_i(serial_outTMS_1), .serial_outTMS_o(serial_outTMS_2)); 
+
+	JTAG_shift_iostate #(.Tp(1) ) JTAG_shift_iostate_2 (.clk(clk_2), .rst(rst_2), .latchTDO(latchTDO_2), .latchTMS(latchTMS_2), .byte_sel(byte_sel_2), .len(len_2), .lsb(lsb_2), .go(go_2),
+                  .pos_edge(pos_edge_2), .neg_edge(neg_edge_2), .Inv_RxEdge(Inv_RxEdge_2), .Inv_TxEdge(Inv_TxEdge_2),
+                  .tip_i(tip_2), .tip_o(tip_3), .last(last_2),  .dataTMS_i(dataTMS_2), .dataTMS_o(dataTMS_3),.dataTDO_i(dataTDO_2), .dataTDO_o(dataTDO_3),
+                  .p_in(p_in_2), .s_in(s_in_2), .s_outTDO(s_outTDO_2),.s_outTMS(s_outTMS_2), .Inv_IdlSt(Inv_IdlSt_2), .cnt_i(cnt_2), .cnt_o(cnt_3), .serial_outTDO_i(serial_outTDO_2), .serial_outTDO_o(serial_outTDO_3), .serial_outTMS_i(serial_outTMS_2), .serial_outTMS_o(serial_outTMS_3)); 
+
+	JTAG_shift_iostate #(.Tp(1) ) JTAG_shift_iostate_3 (.clk(clk_3), .rst(rst_3), .latchTDO(latchTDO_3), .latchTMS(latchTMS_3), .byte_sel(byte_sel_3), .len(len_3), .lsb(lsb_3), .go(go_3),
+                  .pos_edge(pos_edge_3), .neg_edge(neg_edge_3), .Inv_RxEdge(Inv_RxEdge_3), .Inv_TxEdge(Inv_TxEdge_3),
+                  .tip_i(tip_3), .tip_o(tip), .last(last_3),  .dataTMS_i(dataTMS_3), .dataTMS_o(dataTMS),.dataTDO_i(dataTDO_3), .dataTDO_o(dataTDO),
+                  .p_in(p_in_3), .s_in(s_in_3), .s_outTDO(s_outTDO_3),.s_outTMS(s_outTMS_3), .Inv_IdlSt(Inv_IdlSt_3), .cnt_i(cnt_3), .cnt_o(cnt), .serial_outTDO_i(serial_outTDO_3), .serial_outTDO_o(serial_outTDO), .serial_outTMS_i(serial_outTMS_3), .serial_outTMS_o(serial_outTMS)); 
+
+	majority_voter #(.WIDTH(6+`JTAG_NBits+`JTAG_MaxTrLen-1+`JTAG_MaxTrLen-1)) mv (
+		.in1({cnt_2, tip_2, serial_outTDO_2, serial_outTMS_2, dataTDO_2, dataTMS_2}),
+		.in2({cnt_3, tip_3, serial_outTDO_3, serial_outTMS_3, dataTDO_3, dataTMS_3}),
+		.in3({cnt, tip, serial_outTDO, serial_outTMS, dataTDO, dataTMS}),
+		.out({cnt_1, tip_1, serial_outTDO_1, serial_outTMS_1, dataTDO_1, dataTMS_1}),
+		.err()
+	);
+endmodule 
+
+
+/////////////////////////////////////////////////////////////////////////////
+// Design Name:    GBT_SCA                                                 //
+// Module Name:    JTAG_Wishbone_Interface (TRI Version)                   //
+// Description:    JTAG Master fully configurable Wishbon compatible       //
+// Company:        CERN (PH-ESE)                                           //
+// Made by:        Alessandro Caratelli                                    //
+// Create Date:    11/April/2013-Created                                   //
+//                 27/June/2013-Small Modifications                        //
+/////////////////////////////////////////////////////////////////////////////
+
+`include "JTAG_define.v"
+module JTAG_WB_Interface_iostate(wb_clk_in, wb_rst_in, wb_adr_in, wb_dat_in, wb_dat_out_i, wb_dat_out_o, wb_sel_in,
+                        wb_we_in, wb_stb_in, wb_cyc_in, wb_ack_out_i, wb_ack_out_o, wb_err_out, wb_int_out_i, wb_int_out_o,
+                        rx, TMStx, tip, pos_edge, neg_edge, last_bit,JTAG_divider_sel, JTAG_ctrl_sel, JTAG_TDO_txsel, JTAG_TMS_txsel,
+                        divider_i, divider_o,      ctrl_i, ctrl_o, ie,  rst_done
+                        `ifdef WithSEUcounter 
+                              ,SEU_cnt, SEUclear_o
+                        `endif
+                        );
+                                                                                                      
+  // Wishbone signals //
+  input                          wb_clk_in;                           
+  input                          last_bit;                            
+  input                          rst_done;                              
+  input                          ie;              
+  input                          wb_rst_in;       // synchronous active high reset
+  input                  [5:0]   wb_adr_in;       // lower address bits
+  input                 [31:0]   wb_dat_in;       // databus in
+  output                [31:0]   wb_dat_out_o;
+  output                         JTAG_divider_sel;	
+  output                         JTAG_ctrl_sel;   	
+  output                 [3:0]   JTAG_TDO_txsel;  
+  output                 [3:0]   JTAG_TMS_txsel;    
+  input                 [31:0]   wb_dat_out_i;    // databus out
+  input                  [3:0]   wb_sel_in;       // byte select in
+  input                          wb_we_in;        // write enable in
+  input                          wb_stb_in;       // stobe/core select signal
+  input                          wb_cyc_in;       // valid bus cycle in
+  output                         wb_ack_out_o;
+  input                          wb_ack_out_i;    // bus cycle acknowledge out
+  output                         wb_err_out;      // termination error
+  output                         wb_int_out_o;
+  input                          wb_int_out_i;    // interrupt request signal out
+  input  [`JTAG_CTRL_BIT_NB-1:0] ctrl_i;       
+  input    [`JTAVDivFregLEN-1:0] divider_i;
+  output [`JTAG_CTRL_BIT_NB-1:0] ctrl_o; 
+  input     [`JTAG_MaxTrLen-1:0] rx;              // rx register
+  input     [`JTAG_MaxTrLen-1:0] TMStx;           // TMStx Register
+  input                          tip;             // transfer in progress
+  input                          pos_edge;        // recognize posedge of sclk
+  input                          neg_edge;        // recognize negedge of sclk
+  output   [`JTAVDivFregLEN-1:0] divider_o;
+  `ifdef WithSEUcounter
+  input       [`SEUcnt_nbit-1:0] SEU_cnt;     //SEU Counter Register
+  output                         SEUclear_o;
+  reg                            SEUclear_o;
+  `endif
+  reg      [`JTAVDivFregLEN-1:0] divider_o;            // Divider register
+  reg    [`JTAG_CTRL_BIT_NB-1:0] ctrl_o;               // Control and status register
+  reg                     [31:0] wb_dat_m;             // wb data out      
+  reg                     [31:0] wb_dat_out_o;
+  reg                            wb_ack_out_o;
+  reg                            wb_int_out_o;
+  wire                           JTAG_divider_sel;     // divider register select
+  wire                           JTAG_ctrl_sel;        // ctrl register select
+  wire                    [3:0]  JTAG_TDO_txsel;       // tx_l register select
+  wire                    [3:0]  JTAG_TMS_txsel;       // TMS_TX REGISTER SELECT
+  wire                           JTAG_go_auto_sel;
+  
+  // Address decoder //
+  assign JTAG_divider_sel    = wb_cyc_in & wb_stb_in & (wb_adr_in == `JTAG_DEVIDE);
+  assign JTAG_TDO_txsel[0]   = wb_cyc_in & wb_stb_in & (wb_adr_in == `JTAG_TDO_tx0);
+  assign JTAG_TDO_txsel[1]   = wb_cyc_in & wb_stb_in & (wb_adr_in == `JTAG_TDO_tx1);
+  assign JTAG_TDO_txsel[2]   = wb_cyc_in & wb_stb_in & (wb_adr_in == `JTAG_TDO_tx2);
+  assign JTAG_TDO_txsel[3]   = wb_cyc_in & wb_stb_in & (wb_adr_in == `JTAG_TDO_tx3);
+  assign JTAG_TMS_txsel[0]   = wb_cyc_in & wb_stb_in & (wb_adr_in == `JTAG_TMS_tx0);
+  assign JTAG_TMS_txsel[1]   = wb_cyc_in & wb_stb_in & (wb_adr_in == `JTAG_TMS_tx1);
+  assign JTAG_TMS_txsel[2]   = wb_cyc_in & wb_stb_in & (wb_adr_in == `JTAG_TMS_tx2);
+  assign JTAG_TMS_txsel[3]   = wb_cyc_in & wb_stb_in & (wb_adr_in == `JTAG_TMS_tx3);
+  
+  `ifdef WithSEUcounter
+      wire SEU_cnt_sel;
+      assign SEU_cnt_sel = wb_cyc_in & wb_stb_in & (wb_adr_in == `SEU_cnt);
+  `endif
+
+  // Read from registers //
+  always @(wb_adr_in or rx or ctrl_i or divider_i or TMStx or SEU_cnt)
+  begin
+    case (wb_adr_in)
+      `JTAG_TDI_rx0:    wb_dat_m = rx[31:0];
+      `JTAG_TDI_rx1:    wb_dat_m = rx[63:32];
+      `JTAG_TDI_rx2:    wb_dat_m = rx[95:64];
+      `JTAG_TDI_rx3:    wb_dat_m = {{128-`JTAG_MaxTrLen{1'b0}}, rx[`JTAG_MaxTrLen-1:96]};            
+      `JTAG_CTRL:       wb_dat_m = {{32-`JTAG_CTRL_BIT_NB{1'b0}}, ctrl_i};
+      `JTAG_STATUS:     wb_dat_m = {30'b0, ctrl_i[`JTAG_CTRL_RES], ctrl_i[`JTAG_CTRL_GO]};//25-Oct-2015
+      `JTAG_DEVIDE:     wb_dat_m = {{32-`JTAVDivFregLEN{1'b0}}, divider_i};
+      `JTAG_TMS_tx0:    wb_dat_m = TMStx[31:0];
+      `JTAG_TMS_tx1:    wb_dat_m = TMStx[63:32];
+      `JTAG_TMS_tx2:    wb_dat_m = TMStx[95:64];
+      `JTAG_TMS_tx3:    wb_dat_m = {{128-`JTAG_MaxTrLen{1'b0}}, TMStx[`JTAG_MaxTrLen-1:96]};
+      `ifdef WithSEUcounter
+      `SEU_cnt:         wb_dat_m = {{(32-`SEUcnt_nbit){1'b0}}, SEU_cnt};
+      `endif
+      default:          wb_dat_m = 32'b0;
+    endcase
+  end
+  
+  // Send data on Wishbone //
+  always @(posedge wb_clk_in or posedge wb_rst_in) begin
+    if (wb_rst_in) begin
+         wb_dat_out_o <=  32'b0;
+      end 
+    else begin
+         wb_dat_out_o <=  wb_dat_m;
+      end
+  end
+  
+  // Ack on Wishbone //
+  always @(posedge wb_clk_in or posedge wb_rst_in) begin
+    if (wb_rst_in) begin
+         wb_ack_out_o <=  1'b0;
+      end
+    else begin
+         wb_ack_out_o <=  wb_cyc_in & wb_stb_in & ~wb_ack_out_i;
+      end
+  end
+  
+  // Interrupt on Wishbone //
+  always @(posedge wb_clk_in or posedge wb_rst_in)
+  begin
+    if (wb_rst_in)
+      wb_int_out_o <=  1'b0;
+    else if ((tip && last_bit && pos_edge && ie) | (rst_done)) //25-Oct-2015 
+      wb_int_out_o <=  1'b1;
+    else if (wb_ack_out_i)
+      wb_int_out_o <=  1'b0;
+    else wb_int_out_o <=  wb_int_out_i;
+  end
+  
+  // Divider register //
+  always @(posedge wb_clk_in or posedge wb_rst_in)
+  begin
+      if (wb_rst_in) begin
+      	divider_o <=  {`JTAVDivFregLEN{1'b0}};
+      end
+      else begin 
+      	divider_o <=  divider_i;
+      	if (JTAG_divider_sel && wb_we_in && !tip) begin
+        		if (wb_sel_in[0]) begin
+          			divider_o[7:0] <=  wb_dat_in[7:0];
+        		end
+        		if (wb_sel_in[1]) begin
+          			divider_o[`JTAVDivFregLEN-1:8] <=  wb_dat_in[`JTAVDivFregLEN-1:8];
+        		end
+      	end
+      end
+  end
+  
+`ifdef WithSEUcounter  // SEU Counter Register //
+ 
+  always @(posedge wb_clk_in or posedge wb_rst_in)
+  begin
+      if (wb_rst_in) 
+      	SEUclear_o <=  1'b0;
+      else begin 
+      	if (SEU_cnt_sel && wb_we_in && wb_sel_in[0]) 
+		SEUclear_o <=  1'b1;
+      	else 
+		SEUclear_o <=  1'b0;
+      end
+  end 
+`endif  
+  
+   
+   // Ctrl register //
+  	always @(posedge wb_clk_in or posedge wb_rst_in) begin // 25-Oct-2015 
+		if (wb_rst_in) begin
+			ctrl_o <=  {`JTAG_CTRL_BIT_NB{1'b0}}; 
+			ctrl_o[`JTAG_CTRL_Inv_RxEdge] <= 1'b0; 
+			ctrl_o[`JTAG_CTRL_Inv_TxEdge] <= 1'b0;
+			ctrl_o[`JTAG_CTRL_Inv_TrDir]  <= 1'b0;
+			ctrl_o[`JTAG_CTRL_Inv_IdlSt]  <= 1'b0;
+			ctrl_o[`JTAG_CTRL_CHAR_LEN]   <= 1'b0;
+			ctrl_o[`JTAG_CTRL_IE]         <= 1'b1;
+			ctrl_o[`JTAG_CTRL_GO]         <= 1'b0;
+			ctrl_o[`JTAG_CTRL_RES]        <= 1'b0;
+		end		
+		else begin
+			ctrl_o <=  ctrl_i; 
+			if (wb_cyc_in & wb_stb_in & wb_we_in && !tip) begin
+				if (wb_adr_in != `JTAG_CTRL) begin
+					ctrl_o[`JTAG_CTRL_Inv_RxEdge] <=  ctrl_i[`JTAG_CTRL_Inv_RxEdge];
+					ctrl_o[`JTAG_CTRL_Inv_TxEdge] <=  ctrl_i[`JTAG_CTRL_Inv_TxEdge];
+					ctrl_o[`JTAG_CTRL_Inv_TrDir]  <=  ctrl_i[`JTAG_CTRL_Inv_TrDir];
+					ctrl_o[`JTAG_CTRL_Inv_IdlSt]  <=  ctrl_i[`JTAG_CTRL_Inv_IdlSt]; 
+					ctrl_o[`JTAG_CTRL_CHAR_LEN]   <=  ctrl_i[`JTAG_CTRL_CHAR_LEN];
+					case(wb_adr_in)
+					`JTAG_GO_AUTO: begin
+						ctrl_o[`JTAG_CTRL_IE]  <= 1'b1;
+						ctrl_o[`JTAG_CTRL_GO]  <= 1'b1;
+						ctrl_o[`JTAG_CTRL_RES] <= 1'b0;
+						end
+					`JTAG_GO_MANUAL: begin
+						ctrl_o[`JTAG_CTRL_IE]  <= 1'b0;
+						ctrl_o[`JTAG_CTRL_GO]  <= 1'b1;
+						ctrl_o[`JTAG_CTRL_RES] <= 1'b0;
+						end
+					`JTAG_RES: begin
+						ctrl_o[`JTAG_CTRL_IE]  <= 1'b1;
+						ctrl_o[`JTAG_CTRL_GO]  <= 1'b0;
+						ctrl_o[`JTAG_CTRL_RES] <= 1'b1;
+						end
+					default: begin
+						ctrl_o[`JTAG_CTRL_IE]  <= ctrl_i[`JTAG_CTRL_IE];
+						ctrl_o[`JTAG_CTRL_GO]  <= ctrl_i[`JTAG_CTRL_GO];
+						ctrl_o[`JTAG_CTRL_RES] <= ctrl_i[`JTAG_CTRL_RES];
+						end
+					endcase
+				end
+				else begin
+					ctrl_o[`JTAG_CTRL_GO]  <=  1'b0;
+					ctrl_o[`JTAG_CTRL_IE]  <=  1'b1;
+					ctrl_o[`JTAG_CTRL_RES] <=  1'b0;
+					if (wb_sel_in[0])  
+						ctrl_o[`JTAG_CTRL_CHAR_LEN] <=  wb_dat_in[`JTAG_CTRL_CHAR_LEN];
+					else 
+						ctrl_o[`JTAG_CTRL_CHAR_LEN] <=  ctrl_i[`JTAG_CTRL_CHAR_LEN];
+					if (wb_sel_in[1]) begin
+						ctrl_o[`JTAG_CTRL_Inv_RxEdge] <=  wb_dat_in[`JTAG_CTRL_Inv_RxEdge];
+						ctrl_o[`JTAG_CTRL_Inv_TxEdge] <=  wb_dat_in[`JTAG_CTRL_Inv_TxEdge];
+						ctrl_o[`JTAG_CTRL_Inv_TrDir]  <=  wb_dat_in[`JTAG_CTRL_Inv_TrDir]; 
+						ctrl_o[`JTAG_CTRL_Inv_IdlSt]  <=  wb_dat_in[`JTAG_CTRL_Inv_IdlSt]; 
+					end
+					else begin
+						ctrl_o[`JTAG_CTRL_Inv_RxEdge] <=  ctrl_i[`JTAG_CTRL_Inv_RxEdge];
+						ctrl_o[`JTAG_CTRL_Inv_TxEdge] <=  ctrl_i[`JTAG_CTRL_Inv_TxEdge];
+						ctrl_o[`JTAG_CTRL_Inv_TrDir]  <=  ctrl_i[`JTAG_CTRL_Inv_TrDir];
+						ctrl_o[`JTAG_CTRL_Inv_IdlSt]  <=  ctrl_i[`JTAG_CTRL_Inv_IdlSt]; 
+					end	
+				end
+			end
+			else begin
+				if((tip && last_bit && pos_edge) || rst_done) begin
+					ctrl_o[`JTAG_CTRL_GO]  <=  1'b0;
+					ctrl_o[`JTAG_CTRL_RES] <=  1'b0;
+				end
+				else begin
+					ctrl_o[`JTAG_CTRL_GO]  <= ctrl_i[`JTAG_CTRL_GO];
+					ctrl_o[`JTAG_CTRL_RES] <= ctrl_i[`JTAG_CTRL_RES];	
+				end
+				ctrl_o[`JTAG_CTRL_Inv_RxEdge] <=  ctrl_i[`JTAG_CTRL_Inv_RxEdge];
+				ctrl_o[`JTAG_CTRL_Inv_TxEdge] <=  ctrl_i[`JTAG_CTRL_Inv_TxEdge];
+				ctrl_o[`JTAG_CTRL_Inv_TrDir]  <=  ctrl_i[`JTAG_CTRL_Inv_TrDir];
+				ctrl_o[`JTAG_CTRL_Inv_IdlSt]  <=  ctrl_i[`JTAG_CTRL_Inv_IdlSt]; 
+				ctrl_o[`JTAG_CTRL_CHAR_LEN]   <=  ctrl_i[`JTAG_CTRL_CHAR_LEN];
+				ctrl_o[`JTAG_CTRL_IE]         <=  ctrl_i[`JTAG_CTRL_IE];
+			end
+		end
+	end
+			
+  
+ endmodule
+
+`include "JTAG_define.v"
+
+module  JTAG_WB_Interface_tri(wb_clk_in_1, wb_clk_in_2, wb_clk_in_3, wb_rst_in_1, wb_rst_in_2, wb_rst_in_3, wb_adr_in_1, wb_adr_in_2, wb_adr_in_3, wb_dat_in_1, wb_dat_in_2, wb_dat_in_3, wb_dat_out_1, wb_dat_out_2, wb_dat_out_3, wb_sel_in_1, wb_sel_in_2, wb_sel_in_3,
+                              wb_we_in_1, wb_we_in_2, wb_we_in_3, wb_stb_in_1, wb_stb_in_2, wb_stb_in_3, wb_cyc_in_1, wb_cyc_in_2, wb_cyc_in_3, wb_ack_out_1, wb_ack_out_2, wb_ack_out_3, wb_err_out_1, wb_err_out_2, wb_err_out_3, wb_int_out_1, wb_int_out_2, wb_int_out_3,
+                              rx_1, rx_2, rx_3, TMStx_1, TMStx_2, TMStx_3, tip_1, tip_2, tip_3, pos_edge_1, pos_edge_2, pos_edge_3, neg_edge_1, neg_edge_2, neg_edge_3, last_bit_1, last_bit_2, last_bit_3,
+                              divider_1, divider_2, divider_3,	ctrl_1, ctrl_2, ctrl_3, ie_1, ie_2, ie_3,  rst_done_1, rst_done_2, rst_done_3,
+                              `ifdef WithSEUcounter
+                              SEUclear_1,SEUclear_2,SEUclear_3,SEU_cnt_1, SEU_cnt_2, SEU_cnt_3,
+                              `endif
+                              JTAG_divider_sel_1, JTAG_divider_sel_2, JTAG_divider_sel_3, JTAG_ctrl_sel_1, JTAG_ctrl_sel_2, JTAG_ctrl_sel_3, JTAG_TDO_txsel_1, JTAG_TDO_txsel_2, JTAG_TDO_txsel_3, JTAG_TMS_txsel_1, JTAG_TMS_txsel_2, JTAG_TMS_txsel_3);
+
+  // Wishbone signals //
+  input    		wb_clk_in_1, wb_clk_in_2, wb_clk_in_3;         	      // master clock in
+  input           wb_rst_in_1, wb_rst_in_2, wb_rst_in_3;         		// synchronous active high reset
+  input   [5:0] 	wb_adr_in_1, wb_adr_in_2, wb_adr_in_3;         		// lower address bits
+  input  [31:0]	wb_dat_in_1, wb_dat_in_2, wb_dat_in_3;         		// databus in
+  output [31:0]	wb_dat_out_1, wb_dat_out_2, wb_dat_out_3;         	// databus out
+  input   [3:0]	wb_sel_in_1, wb_sel_in_2, wb_sel_in_3;         		// byte select in
+  input           wb_we_in_1, wb_we_in_2, wb_we_in_3;          		// write enable in
+  input           wb_stb_in_1, wb_stb_in_2, wb_stb_in_3;         		// stobe/core select signal
+  input           wb_cyc_in_1, wb_cyc_in_2, wb_cyc_in_3;         		// valid bus cycle in
+  output          wb_ack_out_1, wb_ack_out_2, wb_ack_out_3;         	// bus cycle acknowledge out
+  output          wb_err_out_1, wb_err_out_2, wb_err_out_3;         	// termination error
+  output          wb_int_out_1, wb_int_out_2, wb_int_out_3;         	// interrupt request signal out
+
+  // internal signals //
+  input	[`JTAG_MaxTrLen-1:0] rx_1, rx_2, rx_3;      			// rx register
+  input	[`JTAG_MaxTrLen-1:0] TMStx_1, TMStx_2, TMStx_3;   		// TMStx Register
+  input	tip_1, tip_2, tip_3;               	                        // transfer in progress
+  input	pos_edge_1, pos_edge_2, pos_edge_3;                         // recognize posedge of sclk
+  input	neg_edge_1, neg_edge_2, neg_edge_3;                         // recognize negedge of sclk
+  input	last_bit_1, last_bit_2, last_bit_3;                         // marks last character bit
+  input	rst_done_1, rst_done_2, rst_done_3;	                        // reset signal sent
+  input	ie_1, ie_2, ie_3;				
+
+  output    [`JTAVDivFregLEN-1:0] 	divider_1, divider_2, divider_3;	// Divider register
+  output    [`JTAG_CTRL_BIT_NB-1:0] ctrl_1, ctrl_2, ctrl_3; 		// Control and status register
+  output	JTAG_divider_sel_1, JTAG_divider_sel_2, JTAG_divider_sel_3; // divider register select
+  output	JTAG_ctrl_sel_1, JTAG_ctrl_sel_2, JTAG_ctrl_sel_3;     	// ctrl register select
+  output	[3:0] JTAG_TDO_txsel_1, JTAG_TDO_txsel_2, JTAG_TDO_txsel_3; // tx_l register select
+  output	[3:0] JTAG_TMS_txsel_1, JTAG_TMS_txsel_2, JTAG_TMS_txsel_3;	// TMS_TX REGISTER SELECT
+  
+  `ifdef WithSEUcounter                                                 // SEU Counter Register 
+  output SEUclear_1,SEUclear_2,SEUclear_3;
+  input  [`SEUcnt_nbit-1:0] SEU_cnt_1, SEU_cnt_2, SEU_cnt_3;
+  `endif		
+
+  wire [31:0] wb_dat_out_1, wb_dat_out_2, wb_dat_out_3;
+  wire wb_ack_out_1, wb_ack_out_2, wb_ack_out_3;
+  wire wb_int_out_1, wb_int_out_2, wb_int_out_3;
+  wire [`JTAVDivFregLEN-1:0] divider_1, divider_2, divider_3;
+  wire [`JTAG_CTRL_BIT_NB-1:0] ctrl_1, ctrl_2, ctrl_3;
+  wire [31:0] wb_dat_out;
+  wire wb_ack_out;
+  wire wb_int_out;
+  wire [`JTAVDivFregLEN-1:0] divider;
+  wire [`JTAG_CTRL_BIT_NB-1:0] ctrl;
+	
+  `ifdef WithSEUcounter 
+  wire SEUclear,SEUclear_1,SEUclear_2,SEUclear_3;
+  `endif
+
+	JTAG_WB_Interface_iostate JTAG_WB_Interface_iostate_1  (.wb_clk_in(wb_clk_in_1), .wb_rst_in(wb_rst_in_1), .wb_adr_in(wb_adr_in_1), .wb_dat_in(wb_dat_in_1), .wb_dat_out_i(wb_dat_out_1), .wb_dat_out_o(wb_dat_out_2), .wb_sel_in(wb_sel_in_1),
+				.wb_we_in(wb_we_in_1), .wb_stb_in(wb_stb_in_1), .wb_cyc_in(wb_cyc_in_1), .wb_ack_out_i(wb_ack_out_1), .wb_ack_out_o(wb_ack_out_2), .wb_err_out(wb_err_out_1), .wb_int_out_i(wb_int_out_1), .wb_int_out_o(wb_int_out_2),
+				.rx(rx_1), .TMStx(TMStx_1), .tip(tip_1), .pos_edge(pos_edge_1), .neg_edge(neg_edge_1), .last_bit(last_bit_1),
+				.divider_i(divider_1), .divider_o(divider_2),	.ctrl_i(ctrl_1), .ctrl_o(ctrl_2), .ie(ie_1),  .rst_done(rst_done_1),
+				`ifdef WithSEUcounter
+                              .SEUclear_o(SEUclear_2),.SEU_cnt(SEU_cnt_1),
+                        `endif
+				.JTAG_divider_sel(JTAG_divider_sel_1), .JTAG_ctrl_sel(JTAG_ctrl_sel_1), .JTAG_TDO_txsel(JTAG_TDO_txsel_1), .JTAG_TMS_txsel(JTAG_TMS_txsel_1));
+
+	JTAG_WB_Interface_iostate JTAG_WB_Interface_iostate_2  (.wb_clk_in(wb_clk_in_2), .wb_rst_in(wb_rst_in_2), .wb_adr_in(wb_adr_in_2), .wb_dat_in(wb_dat_in_2), .wb_dat_out_i(wb_dat_out_2), .wb_dat_out_o(wb_dat_out_3), .wb_sel_in(wb_sel_in_2),
+				.wb_we_in(wb_we_in_2), .wb_stb_in(wb_stb_in_2), .wb_cyc_in(wb_cyc_in_2), .wb_ack_out_i(wb_ack_out_2), .wb_ack_out_o(wb_ack_out_3), .wb_err_out(wb_err_out_2), .wb_int_out_i(wb_int_out_2), .wb_int_out_o(wb_int_out_3),
+				.rx(rx_2), .TMStx(TMStx_2), .tip(tip_2), .pos_edge(pos_edge_2), .neg_edge(neg_edge_2), .last_bit(last_bit_2),
+				.divider_i(divider_2), .divider_o(divider_3),	.ctrl_i(ctrl_2), .ctrl_o(ctrl_3), .ie(ie_2),  .rst_done(rst_done_2),
+				`ifdef WithSEUcounter
+                              .SEUclear_o(SEUclear_3),.SEU_cnt(SEU_cnt_2),
+                        `endif
+				.JTAG_divider_sel(JTAG_divider_sel_2), .JTAG_ctrl_sel(JTAG_ctrl_sel_2), .JTAG_TDO_txsel(JTAG_TDO_txsel_2), .JTAG_TMS_txsel(JTAG_TMS_txsel_2));
+
+	JTAG_WB_Interface_iostate JTAG_WB_Interface_iostate_3  (.wb_clk_in(wb_clk_in_3), .wb_rst_in(wb_rst_in_3), .wb_adr_in(wb_adr_in_3), .wb_dat_in(wb_dat_in_3), .wb_dat_out_i(wb_dat_out_3), .wb_dat_out_o(wb_dat_out), .wb_sel_in(wb_sel_in_3),
+				.wb_we_in(wb_we_in_3), .wb_stb_in(wb_stb_in_3), .wb_cyc_in(wb_cyc_in_3), .wb_ack_out_i(wb_ack_out_3), .wb_ack_out_o(wb_ack_out), .wb_err_out(wb_err_out_3), .wb_int_out_i(wb_int_out_3), .wb_int_out_o(wb_int_out),
+				.rx(rx_3), .TMStx(TMStx_3), .tip(tip_3), .pos_edge(pos_edge_3), .neg_edge(neg_edge_3), .last_bit(last_bit_3),
+				.divider_i(divider_3), .divider_o(divider),	.ctrl_i(ctrl_3), .ctrl_o(ctrl), .ie(ie_3),  .rst_done(rst_done_3),
+				`ifdef WithSEUcounter
+                              .SEUclear_o(SEUclear),.SEU_cnt(SEU_cnt_3),
+                        `endif
+				.JTAG_divider_sel(JTAG_divider_sel_3), .JTAG_ctrl_sel(JTAG_ctrl_sel_3), .JTAG_TDO_txsel(JTAG_TDO_txsel_3), .JTAG_TMS_txsel(JTAG_TMS_txsel_3));
+
+	
+  `ifdef WithSEUcounter	
+	majority_voter #(.WIDTH(36+`JTAVDivFregLEN-1+`JTAG_CTRL_BIT_NB-1+1)) mv (
+		.in1({wb_dat_out_2, wb_ack_out_2, wb_int_out_2, divider_2, ctrl_2, SEUclear_2}),
+		.in2({wb_dat_out_3, wb_ack_out_3, wb_int_out_3, divider_3, ctrl_3, SEUclear_3}),
+		.in3({wb_dat_out,   wb_ack_out,   wb_int_out,   divider,   ctrl,   SEUclear  }),
+		.out({wb_dat_out_1, wb_ack_out_1, wb_int_out_1, divider_1, ctrl_1, SEUclear_1}),
+		.err()
+	);	
+  `else	
+	majority_voter #(.WIDTH(36+`JTAVDivFregLEN-1+`JTAG_CTRL_BIT_NB-1)) mv (
+		.in1({wb_dat_out_2, wb_ack_out_2, wb_int_out_2, divider_2, ctrl_2}),
+		.in2({wb_dat_out_3, wb_ack_out_3, wb_int_out_3, divider_3, ctrl_3}),
+		.in3({wb_dat_out, wb_ack_out, wb_int_out, divider, ctrl}),
+		.out({wb_dat_out_1, wb_ack_out_1, wb_int_out_1, divider_1, ctrl_1}),
+		.err()
+	);
+  `endif	
+	
+endmodule
+
diff --git a/vldb/code/Testbench/SCA-model/JTAG_define.v b/vldb/code/Testbench/SCA-model/JTAG_define.v
new file mode 100644
index 0000000..321b274
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/JTAG_define.v
@@ -0,0 +1,59 @@
+/////////////////////////////////////////////////////////////////////////////
+//                                                                         //
+// Design Name:    GBT_SCA                                                 //
+// Module Name:    JTAG_defines                                            //
+// Made by:        Alessandro Caratelli                                    //
+//                                                                         //
+// Description:    JTAG Master fully configurable Wishbon compatible       //
+// Company:        CERN (PH-ESE)                                           //
+// Create Date:    11/April/2013-Created                                   //
+// Last modif:     1 October 2015 (for GBT-SCA V2.0)                       //
+//                                                                         //
+/////////////////////////////////////////////////////////////////////////////
+
+	
+
+`ifndef JTAG_DEFINES
+`define JTAG_DEFINES
+
+	//Registers address on wisbound 
+	`define JTAG_TDI_rx0         6'h00 //0                
+	`define JTAG_TDI_rx1         6'h04 //1      
+	`define JTAG_TDI_rx2         6'h08 //2           
+	`define JTAG_TDI_rx3         6'h0c //3
+	`define JTAG_TDO_tx0         6'h00 //0
+	`define JTAG_TDO_tx1         6'h04 //1
+	`define JTAG_TDO_tx2         6'h08 //2
+	`define JTAG_TDO_tx3         6'h0c //3
+	`define JTAG_TMS_tx0         6'h10 //4
+	`define JTAG_TMS_tx1         6'h14 //5
+	`define JTAG_TMS_tx2         6'h18 //6
+	`define JTAG_TMS_tx3         6'h1c //7
+	`define JTAG_CTRL            6'h20 //8
+	`define JTAG_DEVIDE          6'h24 //9
+	`define JTAG_GO_AUTO         6'h28 //a
+	`define JTAG_GO_MANUAL       6'h2c //b
+	`define JTAG_RES             6'h30 //c
+	`define JTAG_STATUS          6'h34 //d
+	`define SEU_cnt              6'h3c //f
+
+	// Bit Position in the Control register
+	
+	`define JTAG_CTRL_RES           16
+	`define JTAG_CTRL_Inv_IdlSt     14
+	`define JTAG_CTRL_Inv_TrDir     11
+	`define JTAG_CTRL_Inv_TxEdge    10
+	`define JTAG_CTRL_Inv_RxEdge     9
+	`define JTAG_CTRL_GO             8
+	`define JTAG_CTRL_IE            12
+	`define JTAG_CTRL_CHAR_LEN     6:0
+
+	//Parameters
+	`define JTAVDivFregLEN          16 // Number of bit in the clock divider register
+	`define JTAG_MaxTrLen          128 // Max transaction numbers (please don't change)
+	`define JTAG_NBits               7 // log(JTAG_MaxTrLen)|2
+	`define JTAG_CTRL_BIT_NB        17 // Number of bits in the control register
+		
+`endif
+
+
diff --git a/vldb/code/Testbench/SCA-model/NodeController.v b/vldb/code/Testbench/SCA-model/NodeController.v
new file mode 100644
index 0000000..7d1de94
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/NodeController.v
@@ -0,0 +1,3459 @@
+//Last modification: 29 Sept 2015 - Change ADC control and parameters
+
+`timescale 1ns / 1ps
+`include "global_defines.v"
+module wb_addr_decod_iostate( wb_addr, wb_stb_slave, wb_stb, wb_con_in_1, wb_con_in_3, wb_con_in_2,wb_con_in_4,
+                      wb_con_in_5,wb_con_in_6,wb_con_in_7,wb_con_in_8,
+                      wb_con_in_9, wb_con_in_10,  wb_con_in_11, wb_con_in_12, wb_con_in_13,
+                      wb_con_in_14, wb_con_in_15, wb_con_in_16,wb_con_in_17,wb_con_in_18,wb_con_in_19, 
+                      wb_con_in_20,wb_con_in_21,
+                      wb_con_data_o);
+
+
+	input [4:0] wb_addr ;
+	input wb_stb ;
+	input [31:0] wb_con_in_1 ;
+	input [31:0] wb_con_in_2 ;
+	input [31:0] wb_con_in_3 ;
+	input [31:0] wb_con_in_4 ;
+	input [31:0] wb_con_in_5 ;
+	input [31:0] wb_con_in_6 ;
+	input [31:0] wb_con_in_7 ;
+	input [31:0] wb_con_in_8 ;
+	input [31:0] wb_con_in_9 ;
+	input [31:0] wb_con_in_10 ;
+	input [31:0] wb_con_in_11 ;
+	input [31:0] wb_con_in_12 ;
+	input [31:0] wb_con_in_13 ;
+	input [31:0] wb_con_in_14 ;
+	input [31:0] wb_con_in_15 ;
+	input [31:0] wb_con_in_16 ;
+	input [31:0] wb_con_in_17 ;
+	input [31:0] wb_con_in_18 ;
+	input [31:0] wb_con_in_19 ;
+	input [31:0] wb_con_in_20 ;
+	input [31:0] wb_con_in_21 ;
+	output [31:0] wb_stb_slave ;
+	output [31:0] wb_con_data_o ;
+
+
+	wire [4:0] wb_addr ;
+	wire wb_stb ;
+	wire [31:0] wb_con_in_1 ;
+	wire [31:0] wb_con_in_2 ;
+	wire [31:0] wb_con_in_3 ;
+	wire [31:0] wb_con_in_4 ;
+	wire [31:0] wb_con_in_5 ;
+	wire [31:0] wb_con_in_6 ;
+	wire [31:0] wb_con_in_7 ;
+	wire [31:0] wb_con_in_8 ;
+	wire [31:0] wb_con_in_9 ;
+	wire [31:0] wb_con_in_10 ;
+	wire [31:0] wb_con_in_11 ;
+	wire [31:0] wb_con_in_12 ;
+	wire [31:0] wb_con_in_13 ;
+	wire [31:0] wb_con_in_14 ;
+	wire [31:0] wb_con_in_15 ;
+	wire [31:0] wb_con_in_16 ;
+	wire [31:0] wb_con_in_17 ;
+	wire [31:0] wb_con_in_18 ;
+	wire [31:0] wb_con_in_19 ;
+	wire [31:0] wb_con_in_20 ;
+	wire [31:0] wb_con_in_21 ;
+
+	reg [31:0] wb_stb_slave ;
+	reg [31:0] wb_con_data_o ;             
+     
+ always @*
+ begin
+   if (wb_stb)
+     case( wb_addr[4:0])
+        5'b00001 :
+           wb_stb_slave = 32'h1;  // SPI
+        5'b00010 :
+           wb_stb_slave = 32'h2;  //GPIO
+        5'b00011 :
+           wb_stb_slave = 32'h4;  // I2C 0         
+         5'b00100 :
+           wb_stb_slave = 32'h8;  // I2c 1        
+         5'b00101 :
+           wb_stb_slave = 32'h10;  // I2c 2         
+         5'b00110 :
+           wb_stb_slave = 32'h20;  // I2c 3
+         5'b00111 :
+           wb_stb_slave = 32'h40;  // I2c 4         
+         5'b01000 :
+           wb_stb_slave = 32'h80;  // I2c 5            
+         5'b01001 :
+           wb_stb_slave = 32'h100; // I2c 6          
+         5'b01010 :
+           wb_stb_slave = 32'h200;  // I2c 7               
+         5'b01011 :
+           wb_stb_slave = 32'h400;  // i2c 8 
+         5'b01100 :
+           wb_stb_slave = 32'h800;   // I2c 9            
+         5'b01101 :
+           wb_stb_slave = 32'h1000;   // I2c 10            
+         5'b01110 :
+           wb_stb_slave = 32'h2000;   // I2c 11            
+         5'b01111 :
+           wb_stb_slave = 32'h4000;   // I2c 12            
+         5'b10000 :
+           wb_stb_slave = 32'h8000;   // I2c 13                              
+         5'b10001 :
+           wb_stb_slave = 32'h10000;   // I2c 14
+         5'b10010 :
+           wb_stb_slave = 32'h20000;   // I2c 15            
+         5'b10011 :
+           wb_stb_slave = 32'h40000;   // canal 8'h13   JTAG
+         5'b10100 :
+           wb_stb_slave = 32'h80000;   // canal 8'h14   ADC
+         5'b10101 :
+           wb_stb_slave = 32'h100000;   // canal 8'h15   DAC           
+                                                         
+       default: 
+           wb_stb_slave = 32'h0;  // aucun de selectionne
+    endcase
+   else
+       wb_stb_slave = 32'h0; 
+  end
+always @ (wb_con_in_1 or wb_con_in_2 or wb_con_in_3 or  wb_con_in_4 or wb_con_in_5 or wb_con_in_6  
+          or wb_con_in_7 or wb_con_in_8 or wb_con_in_9 or wb_con_in_10 or wb_con_in_11 or wb_con_in_12
+          or wb_con_in_13 or wb_con_in_14 or wb_con_in_15 or wb_con_in_16 or wb_con_in_17 or wb_con_in_18
+          or wb_con_in_19 or wb_con_in_20 or wb_con_in_21 or wb_addr)   
+   begin
+       case(wb_addr[4:0])
+         5'b00001:
+              wb_con_data_o = wb_con_in_1;  //SPI
+         5'b00010:
+              wb_con_data_o = wb_con_in_2;  // GPIO
+         5'b00011:
+              wb_con_data_o = wb_con_in_3;  // I2c0
+          5'b00100:
+              wb_con_data_o = wb_con_in_4;// I2c1
+          5'b00101:
+              wb_con_data_o = wb_con_in_5;  // I2c2 
+          5'b00110:
+              wb_con_data_o = wb_con_in_6;  // I2c3            
+          5'b00111:
+              wb_con_data_o = wb_con_in_7; // I2c4             
+          5'b01000:
+              wb_con_data_o = wb_con_in_8; // I2c5  
+          5'b01001:
+              wb_con_data_o = wb_con_in_9; // I2c6              
+          5'b01010:
+              wb_con_data_o = wb_con_in_10;// I2c7               
+          5'b01011:
+              wb_con_data_o = wb_con_in_11; // I2c8                  
+          5'b01100:
+              wb_con_data_o = wb_con_in_12; // I2c9                                    
+          5'b01101:
+              wb_con_data_o = wb_con_in_13;// I2c10 
+          5'b01110:
+              wb_con_data_o = wb_con_in_14;// I2c11               
+          5'b01111:
+              wb_con_data_o = wb_con_in_15; // I2c12             
+          5'b10000:
+              wb_con_data_o = wb_con_in_16;// I2c13
+          5'b10001:
+              wb_con_data_o = wb_con_in_17;// I2c14                                               
+          5'b10010:
+              wb_con_data_o = wb_con_in_18;// I2c15 
+          5'b10011:
+              wb_con_data_o = wb_con_in_19;// JTAG 
+          5'b10100:
+              wb_con_data_o = wb_con_in_20;// ADC
+           5'b10101:
+              wb_con_data_o = wb_con_in_21;// DAC
+                                                                                        
+        default:
+             wb_con_data_o = 32'hFFFF;
+    endcase 
+ end 
+endmodule
+
+
+
+module wb_addr_decod_tri( wb_addr_1, wb_addr_2, wb_addr_3, wb_stb_slave_1, wb_stb_slave_2, wb_stb_slave_3, wb_stb_1, wb_stb_2, wb_stb_3, wb_con_in_1_1, wb_con_in_1_2, wb_con_in_1_3, wb_con_in_3_1, wb_con_in_3_2, wb_con_in_3_3, wb_con_in_2_1, wb_con_in_2_2, wb_con_in_2_3,wb_con_in_4_1, wb_con_in_4_2, wb_con_in_4_3,
+                      wb_con_in_5_1, wb_con_in_5_2, wb_con_in_5_3,wb_con_in_6_1, wb_con_in_6_2, wb_con_in_6_3,wb_con_in_7_1, wb_con_in_7_2, wb_con_in_7_3,wb_con_in_8_1, wb_con_in_8_2, wb_con_in_8_3,
+                      wb_con_in_9_1, wb_con_in_9_2, wb_con_in_9_3, wb_con_in_10_1, wb_con_in_10_2, wb_con_in_10_3,  wb_con_in_11_1, wb_con_in_11_2, wb_con_in_11_3, wb_con_in_12_1, wb_con_in_12_2, wb_con_in_12_3, wb_con_in_13_1, wb_con_in_13_2, wb_con_in_13_3,
+                      wb_con_in_14_1, wb_con_in_14_2, wb_con_in_14_3, wb_con_in_15_1, wb_con_in_15_2, wb_con_in_15_3, wb_con_in_16_1, wb_con_in_16_2, wb_con_in_16_3,wb_con_in_17_1, wb_con_in_17_2, wb_con_in_17_3,wb_con_in_18_1, wb_con_in_18_2, wb_con_in_18_3,wb_con_in_19_1, wb_con_in_19_2, wb_con_in_19_3, 
+                      wb_con_in_20_1, wb_con_in_20_2, wb_con_in_20_3,wb_con_in_21_1, wb_con_in_21_2, wb_con_in_21_3,
+                      wb_con_data_o_1, wb_con_data_o_2, wb_con_data_o_3);
+
+	input [4:0] wb_addr_1, wb_addr_2, wb_addr_3 ;
+	input wb_stb_1, wb_stb_2, wb_stb_3 ;
+	input [31:0] wb_con_in_1_1, wb_con_in_1_2, wb_con_in_1_3 ;
+	input [31:0] wb_con_in_2_1, wb_con_in_2_2, wb_con_in_2_3 ;
+	input [31:0] wb_con_in_3_1, wb_con_in_3_2, wb_con_in_3_3 ;
+	input [31:0] wb_con_in_4_1, wb_con_in_4_2, wb_con_in_4_3 ;
+	input [31:0] wb_con_in_5_1, wb_con_in_5_2, wb_con_in_5_3 ;
+	input [31:0] wb_con_in_6_1, wb_con_in_6_2, wb_con_in_6_3 ;
+	input [31:0] wb_con_in_7_1, wb_con_in_7_2, wb_con_in_7_3 ;
+	input [31:0] wb_con_in_8_1, wb_con_in_8_2, wb_con_in_8_3 ;
+	input [31:0] wb_con_in_9_1, wb_con_in_9_2, wb_con_in_9_3 ;
+	input [31:0] wb_con_in_10_1, wb_con_in_10_2, wb_con_in_10_3 ;
+	input [31:0] wb_con_in_11_1, wb_con_in_11_2, wb_con_in_11_3 ;
+	input [31:0] wb_con_in_12_1, wb_con_in_12_2, wb_con_in_12_3 ;
+	input [31:0] wb_con_in_13_1, wb_con_in_13_2, wb_con_in_13_3 ;
+	input [31:0] wb_con_in_14_1, wb_con_in_14_2, wb_con_in_14_3 ;
+	input [31:0] wb_con_in_15_1, wb_con_in_15_2, wb_con_in_15_3 ;
+	input [31:0] wb_con_in_16_1, wb_con_in_16_2, wb_con_in_16_3 ;
+	input [31:0] wb_con_in_17_1, wb_con_in_17_2, wb_con_in_17_3 ;
+	input [31:0] wb_con_in_18_1, wb_con_in_18_2, wb_con_in_18_3 ;
+	input [31:0] wb_con_in_19_1, wb_con_in_19_2, wb_con_in_19_3 ;
+	input [31:0] wb_con_in_20_1, wb_con_in_20_2, wb_con_in_20_3 ;
+	input [31:0] wb_con_in_21_1, wb_con_in_21_2, wb_con_in_21_3 ;
+	output [31:0] wb_stb_slave_1, wb_stb_slave_2, wb_stb_slave_3 ;
+	output [31:0] wb_con_data_o_1, wb_con_data_o_2, wb_con_data_o_3 ;
+
+	wb_addr_decod_iostate wb_addr_decod_iostate_1  ( 
+							.wb_addr(wb_addr_1), 
+							.wb_stb_slave(wb_stb_slave_1), 
+							.wb_stb(wb_stb_1), 
+							.wb_con_in_1(wb_con_in_1_1), 
+							.wb_con_in_3(wb_con_in_3_1), 
+							.wb_con_in_2(wb_con_in_2_1),
+							.wb_con_in_4(wb_con_in_4_1),
+							.wb_con_in_5(wb_con_in_5_1),
+							.wb_con_in_6(wb_con_in_6_1),
+							.wb_con_in_7(wb_con_in_7_1),
+							.wb_con_in_8(wb_con_in_8_1),
+							.wb_con_in_9(wb_con_in_9_1), 
+							.wb_con_in_10(wb_con_in_10_1),  
+							.wb_con_in_11(wb_con_in_11_1), 
+							.wb_con_in_12(wb_con_in_12_1), 
+							.wb_con_in_13(wb_con_in_13_1),
+							.wb_con_in_14(wb_con_in_14_1), 
+							.wb_con_in_15(wb_con_in_15_1), 
+							.wb_con_in_16(wb_con_in_16_1),
+							.wb_con_in_17(wb_con_in_17_1),
+							.wb_con_in_18(wb_con_in_18_1),
+							.wb_con_in_19(wb_con_in_19_1), 
+							.wb_con_in_20(wb_con_in_20_1),
+							.wb_con_in_21(wb_con_in_21_1),
+							.wb_con_data_o(wb_con_data_o_1)
+							);
+
+	wb_addr_decod_iostate wb_addr_decod_iostate_2  ( 
+							.wb_addr(wb_addr_2), 
+							.wb_stb_slave(wb_stb_slave_2), 
+							.wb_stb(wb_stb_2), 
+							.wb_con_in_1(wb_con_in_1_2), 
+							.wb_con_in_3(wb_con_in_3_2), 
+							.wb_con_in_2(wb_con_in_2_2),
+							.wb_con_in_4(wb_con_in_4_2),
+							.wb_con_in_5(wb_con_in_5_2),
+							.wb_con_in_6(wb_con_in_6_2),
+							.wb_con_in_7(wb_con_in_7_2),
+							.wb_con_in_8(wb_con_in_8_2),
+							.wb_con_in_9(wb_con_in_9_2), 
+							.wb_con_in_10(wb_con_in_10_2),  
+							.wb_con_in_11(wb_con_in_11_2), 
+							.wb_con_in_12(wb_con_in_12_2), 
+							.wb_con_in_13(wb_con_in_13_2),
+							.wb_con_in_14(wb_con_in_14_2), 
+							.wb_con_in_15(wb_con_in_15_2), 
+							.wb_con_in_16(wb_con_in_16_2),
+							.wb_con_in_17(wb_con_in_17_2),
+							.wb_con_in_18(wb_con_in_18_2),
+							.wb_con_in_19(wb_con_in_19_2), 
+							.wb_con_in_20(wb_con_in_20_2),
+							.wb_con_in_21(wb_con_in_21_2),
+							.wb_con_data_o(wb_con_data_o_2)
+							);
+
+	wb_addr_decod_iostate wb_addr_decod_iostate_3  ( 
+							.wb_addr(wb_addr_3), 
+							.wb_stb_slave(wb_stb_slave_3), 
+							.wb_stb(wb_stb_3), 
+							.wb_con_in_1(wb_con_in_1_3), 
+							.wb_con_in_3(wb_con_in_3_3), 
+							.wb_con_in_2(wb_con_in_2_3),
+							.wb_con_in_4(wb_con_in_4_3),
+							.wb_con_in_5(wb_con_in_5_3),
+							.wb_con_in_6(wb_con_in_6_3),
+							.wb_con_in_7(wb_con_in_7_3),
+							.wb_con_in_8(wb_con_in_8_3),
+							.wb_con_in_9(wb_con_in_9_3),
+							.wb_con_in_10(wb_con_in_10_3),  
+							.wb_con_in_11(wb_con_in_11_3), 
+							.wb_con_in_12(wb_con_in_12_3), 
+							.wb_con_in_13(wb_con_in_13_3),
+							.wb_con_in_14(wb_con_in_14_3), 
+							.wb_con_in_15(wb_con_in_15_3), 
+							.wb_con_in_16(wb_con_in_16_3),
+							.wb_con_in_17(wb_con_in_17_3),
+							.wb_con_in_18(wb_con_in_18_3),
+							.wb_con_in_19(wb_con_in_19_3), 
+							.wb_con_in_20(wb_con_in_20_3),
+							.wb_con_in_21(wb_con_in_21_3),
+							.wb_con_data_o(wb_con_data_o_3)
+							);
+
+endmodule
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  ack_and
+//      Library Name  :  node_ctrl
+//  
+//      Creation Date :  Mon Jun 24 09:42:12 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  node_ctrl
+//  Unit    Name :  ack_and
+//  Unit    Type :  Text Unit
+//  
+//----------------------------------------------------
+//////////////////////////////////////////
+//////////////////////////////////////////
+// Date        : Tue Jan 15 11:07:06 2013
+//
+// Author      : 
+//
+// Company     : 
+//
+// Description : 
+//
+//////////////////////////////////////////
+//////////////////////////////////////////
+
+
+module ack_and_iostate(ack_in,ack_out);
+	input  [5:0] ack_in;
+	output   ack_out;
+	assign  ack_out =   ack_in[2] || ack_in[1] || ack_in[0] || ack_in[3] || ack_in[4] || ack_in[5];
+endmodule
+
+
+module ack_and_tri(ack_in_1, ack_in_2, ack_in_3,ack_out_1, ack_out_2, ack_out_3);
+	input  [5:0] ack_in_1, ack_in_2, ack_in_3;
+	output       ack_out_1, ack_out_2, ack_out_3;
+	ack_and_iostate ack_and_iostate_1  (.ack_in(ack_in_1),.ack_out(ack_out_1));
+	ack_and_iostate ack_and_iostate_2  (.ack_in(ack_in_2),.ack_out(ack_out_2));
+	ack_and_iostate ack_and_iostate_3  (.ack_in(ack_in_3),.ack_out(ack_out_3));
+endmodule
+
+
+
+
+
+
+
+module sca_node_ctrl_tri 
+
+ (
+`ifdef WithSEUcounter
+output  SEU_NCTRLflag1,
+output  SEU_NCTRLflag2,
+output  SEU_NCTRLflag3,
+`endif
+
+input  clock_1,
+input  clock_2,
+input  clock_3,
+input  tx_dav_1,
+input  tx_dav_2,
+input  tx_dav_3,
+input  wb_ack_i_1,
+input  wb_ack_i_2,
+input  wb_ack_i_3,
+input  wb_err_in_1,
+input  wb_err_in_2,
+input  wb_err_in_3,
+input [5:0]  Int_arb_in_1,
+input [5:0]  Int_arb_in_2,
+input [5:0]  Int_arb_in_3,
+input [15:0]  dataw_in_1,
+input [15:0]  dataw_in_2,
+input [15:0]  dataw_in_3,
+input [31:0]  wb_dat_i_1,
+input [31:0]  wb_dat_i_2,
+input [31:0]  wb_dat_i_3,
+input  rx_ena_1,
+input  rx_ena_2,
+input  rx_ena_3,
+input  reset_1,
+input  reset_2,
+input  reset_3,
+output  wb_cyc_o_1,
+output  wb_cyc_o_2,
+output  wb_cyc_o_3,
+output  wb_stb_o_1,
+output  wb_stb_o_2,
+output  wb_stb_o_3,
+output [31:0]  wb_addr_o_1,
+output [31:0]  wb_addr_o_2,
+output [31:0]  wb_addr_o_3,
+output  rx_dav_1,
+output  rx_dav_2,
+output  rx_dav_3,
+output [7:0]  CRE_1,
+output [7:0]  CRE_2,
+output [7:0]  CRE_3,
+output [15:0]  dataw_out_1,
+output [15:0]  dataw_out_2,
+output [15:0]  dataw_out_3,
+output [31:0]  wb_dat_o_1,
+output [31:0]  wb_dat_o_2,
+output [31:0]  wb_dat_o_3,
+output [3:0]  wb_sel_o_1,
+output [3:0]  wb_sel_o_2,
+output [3:0]  wb_sel_o_3,
+output  tx_ena_1,
+output  tx_ena_2,
+output  tx_ena_3,
+output  wb_we_o_1,
+output  wb_we_o_2,
+output  wb_we_o_3,
+
+output  [31:0] EN_ch_reg_1,//ADDED 30jan14
+output  [31:0] EN_ch_reg_2,//ADDED 30jan14
+output  [31:0] EN_ch_reg_3 //ADDED 30jan14
+);
+
+wire [31:0]  up_data_out_1;
+wire [31:0]  up_data_out_2;
+wire [31:0]  up_data_out_3;
+wire  up_busy_1;
+wire  up_busy_2;
+wire  up_busy_3;
+wire  up_cs_b_1;
+wire  up_cs_b_2;
+wire  up_cs_b_3;
+wire [31:0]  S4_1;
+wire [31:0]  S4_2;
+wire [31:0]  S4_3;
+wire [31:0]  up_addr_1;
+wire [31:0]  up_addr_2;
+wire [31:0]  up_addr_3;
+wire  up_rw_b_1;
+wire  up_rw_b_2;
+wire  up_rw_b_3;
+wire [4:0]    mem_adr_w_1;
+wire [4:0]    mem_adr_w_2;
+wire [4:0]    mem_adr_w_3;
+wire [4:0]    mem_adr_r_1;
+wire [4:0]    mem_adr_r_2;
+wire [4:0]    mem_adr_r_3;
+wire [7:0]    mem_data_w_1;
+wire [7:0]    mem_data_w_2;
+wire [7:0]    mem_data_w_3;
+wire [7:0]    mem_data_r_1;
+wire [7:0]    mem_data_r_2;
+wire [7:0]    mem_data_r_3;
+wire          mem_w_enable_1;
+wire          mem_w_enable_2;
+wire          mem_w_enable_3;
+wire          mem_rst_1;
+wire          mem_rst_2;
+wire          mem_rst_3;
+
+     
+up_2_wishbone_tri  up_2_wishbone
+    (
+     .up_data_in_1(up_data_out_1[31:0]),
+     .up_addr_1(up_addr_1[31:0]),
+     .up_cs_b_1(up_cs_b_1),
+     .up_rw_b_1(up_rw_b_1),
+     .up_data_out_1(S4_1[31:0]),
+     .wb_addr_o_1(wb_addr_o_1[31:0]),
+     .wb_dat_o_1(wb_dat_o_1[31:0]),
+     .wb_sel_o_1(wb_sel_o_1[3:0]),
+     .wb_we_o_1(wb_we_o_1),
+     .wb_stb_o_1(wb_stb_o_1),
+     .wb_ack_i_1(wb_ack_i_1),
+     .wb_dat_i_1(wb_dat_i_1[31:0]),
+     .wb_cyc_o_1(wb_cyc_o_1),
+     .clock_1(clock_1),
+     .reset_1(reset_1),
+     .wb_err_in_1(wb_err_in_1),
+     .up_busy_1(up_busy_1),
+		.up_data_in_2(up_data_out_2[31:0]),
+     .up_addr_2(up_addr_2[31:0]),
+     .up_cs_b_2(up_cs_b_2),
+     .up_rw_b_2(up_rw_b_2),
+     .up_data_out_2(S4_2[31:0]),
+     .wb_addr_o_2(wb_addr_o_2[31:0]),
+     .wb_dat_o_2(wb_dat_o_2[31:0]),
+     .wb_sel_o_2(wb_sel_o_2[3:0]),
+     .wb_we_o_2(wb_we_o_2),
+     .wb_stb_o_2(wb_stb_o_2),
+     .wb_ack_i_2(wb_ack_i_2),
+     .wb_dat_i_2(wb_dat_i_2[31:0]),
+     .wb_cyc_o_2(wb_cyc_o_2),
+     .clock_2(clock_2),
+     .reset_2(reset_2),
+     .wb_err_in_2(wb_err_in_2),
+     .up_busy_2(up_busy_2),
+		.up_data_in_3(up_data_out_3[31:0]),
+     .up_addr_3(up_addr_3[31:0]),
+     .up_cs_b_3(up_cs_b_3),
+     .up_rw_b_3(up_rw_b_3),
+     .up_data_out_3(S4_3[31:0]),
+     .wb_addr_o_3(wb_addr_o_3[31:0]),
+     .wb_dat_o_3(wb_dat_o_3[31:0]),
+     .wb_sel_o_3(wb_sel_o_3[3:0]),
+     .wb_we_o_3(wb_we_o_3),
+     .wb_stb_o_3(wb_stb_o_3),
+     .wb_ack_i_3(wb_ack_i_3),
+     .wb_dat_i_3(wb_dat_i_3[31:0]),
+     .wb_cyc_o_3(wb_cyc_o_3),
+     .clock_3(clock_3),
+     .reset_3(reset_3),
+     .wb_err_in_3(wb_err_in_3),
+     .up_busy_3(up_busy_3)
+	);
+
+nctrl_tri  C0
+    (
+     `ifdef WithSEUcounter
+        .SEU_NCTRLflag1(SEU_NCTRLflag1),
+        .SEU_NCTRLflag2(SEU_NCTRLflag2),
+        .SEU_NCTRLflag3(SEU_NCTRLflag3),
+     `endif    
+     
+     .EN_ch_reg_1(EN_ch_reg_1[31:0]), //ADDED 30jan14
+     .EN_ch_reg_2(EN_ch_reg_2[31:0]), //ADDED 30jan14
+     .EN_ch_reg_3(EN_ch_reg_3[31:0]), //ADDED 30jan14
+     
+     .clock_1(clock_1),
+     .reset_1(reset_1),
+     .up_rw_b_1(up_rw_b_1),
+     .up_data_out_1(up_data_out_1[31:0]),
+     .up_data_in_1(S4_1[31:0]),
+     .up_addr_1(up_addr_1[31:0]),
+     .up_cs_b_1(up_cs_b_1),
+     .tx_ena_1(tx_ena_1),
+     .tx_dav_1(tx_dav_1),
+     .nc_ready_1(),
+     .rx_dav_1(rx_dav_1),
+     .rx_ena_1(rx_ena_1),
+     .dataw_in_1(dataw_in_1[15:0]),
+     .Int_arb_in_1(Int_arb_in_1[5:0]),
+     .up_busy_in_1(up_busy_1),
+     .CRE_1(CRE_1[7:0]),  
+     .dataw_out_1(dataw_out_1[15:0]),
+     //.mem_adr_w_1(mem_adr_w_1[4:0]),
+     //.mem_adr_r_1(mem_adr_r_1[4:0]),
+     //.mem_data_w_1(mem_data_w_1[7:0]),
+     //.mem_data_r_1(mem_data_r_1[7:0]),
+     //.mem_w_enable_1(mem_w_enable_1),
+     //.mem_rst_1(mem_rst_1),
+	
+     .clock_2(clock_2),
+     .reset_2(reset_2),
+     .up_rw_b_2(up_rw_b_2),
+     .up_data_out_2(up_data_out_2[31:0]),
+     .up_data_in_2(S4_2[31:0]),
+     .up_addr_2(up_addr_2[31:0]),
+     .up_cs_b_2(up_cs_b_2),
+     .tx_ena_2(tx_ena_2),
+     .tx_dav_2(tx_dav_2),
+     .nc_ready_2(),
+     .rx_dav_2(rx_dav_2),
+     .rx_ena_2(rx_ena_2),
+     .dataw_in_2(dataw_in_2[15:0]),
+     .Int_arb_in_2(Int_arb_in_2[5:0]),
+     .up_busy_in_2(up_busy_2),
+     .CRE_2(CRE_2[7:0]),  
+     .dataw_out_2(dataw_out_2[15:0]),
+     //.mem_adr_w_2(mem_adr_w_2[4:0]),
+     //.mem_adr_r_2(mem_adr_r_2[4:0]),
+     //.mem_data_w_2(mem_data_w_2[7:0]),
+     //.mem_data_r_2(mem_data_r_2[7:0]),
+     //.mem_w_enable_2(mem_w_enable_2),
+     //.mem_rst_2(mem_rst_2),
+		
+     .clock_3(clock_3),
+     .reset_3(reset_3),
+     .up_rw_b_3(up_rw_b_3),
+     .up_data_out_3(up_data_out_3[31:0]),
+     .up_data_in_3(S4_3[31:0]),
+     .up_addr_3(up_addr_3[31:0]),
+     .up_cs_b_3(up_cs_b_3),
+     .tx_ena_3(tx_ena_3),
+     .tx_dav_3(tx_dav_3),
+     .nc_ready_3(),
+     .rx_dav_3(rx_dav_3),
+     .rx_ena_3(rx_ena_3),
+     .dataw_in_3(dataw_in_3[15:0]),
+     .Int_arb_in_3(Int_arb_in_3[5:0]),
+     .up_busy_in_3(up_busy_3),
+     .CRE_3(CRE_3[7:0]),  
+     .dataw_out_3(dataw_out_3[15:0])
+     //.mem_adr_w_3(mem_adr_w_3[4:0]),
+     //.mem_adr_r_3(mem_adr_r_3[4:0]),
+     //.mem_data_w_3(mem_data_w_3[7:0]),
+     //.mem_data_r_3(mem_data_r_3[7:0]),
+     //.mem_w_enable_3(mem_w_enable_3),
+     //.mem_rst_3(mem_rst_3)
+ 
+	);
+
+
+//mySRAM #(.ADDR_WIDTH(5), .DATA_WIDTH(8)) SRAM_1 (
+//	.addr_w(mem_adr_w_1[4:0]), 
+//	.addr_r(mem_adr_r_1[4:0]),  
+//	.data_w(mem_data_w_1[7:0]),
+//	.data_r(mem_data_r_1[7:0]),
+//	.w_enable(mem_w_enable_1), 
+//	.clk_w(clock_1), 
+//	.reset(reset_1 || mem_rst_1)
+//	 );
+//
+//mySRAM #(.ADDR_WIDTH(5), .DATA_WIDTH(8)) SRAM_2 (
+//	.addr_w(mem_adr_w_2[4:0]), 
+//	.addr_r(mem_adr_r_2[4:0]),  
+//	.data_w(mem_data_w_2[7:0]),
+//	.data_r(mem_data_r_2[7:0]),
+//	.w_enable(mem_w_enable_2), 
+//	.clk_w(clock_2), 
+//	.reset(reset_2 || mem_rst_2)
+//	 );
+//
+//mySRAM #(.ADDR_WIDTH(5), .DATA_WIDTH(8)) SRAM_3 (
+//	.addr_w(mem_adr_w_3[4:0]), 
+//	.addr_r(mem_adr_r_3[4:0]),  
+//	.data_w(mem_data_w_3[7:0]),
+//	.data_r(mem_data_r_3[7:0]),
+//	.w_enable(mem_w_enable_3), 
+//	.clk_w(clock_3), 
+//	.reset(reset_3 || mem_rst_3)
+//	 );
+
+
+endmodule
+
+
+
+module up_2_wishbone_iostate (up_data_in, up_addr, up_cs_b, up_rw_b, up_data_out_iv, up_data_out_ov,
+                      wb_addr_o_iv, wb_addr_o_ov, wb_dat_o_iv, wb_dat_o_ov, wb_sel_o_iv, wb_sel_o_ov, wb_we_o_iv, wb_we_o_ov, wb_stb_o_iv, wb_stb_o_ov,
+                      wb_ack_i, wb_dat_i, wb_cyc_o_iv, wb_cyc_o_ov, clock, reset, wb_err_in,
+                      up_busy_iv, up_busy_ov
+                      , visual_Wish_idle_current_iv, visual_Wish_idle_current_ov);
+ 
+  input [31:0] up_data_in;
+  input wb_we_o_iv;
+  input wb_stb_o_iv;
+  input [1:0] visual_Wish_idle_current_iv;
+
+  input wb_ack_i;
+  input [31:0] wb_dat_i;
+  input wb_cyc_o_iv;
+  input clock;
+  input reset;
+  input wb_err_in;
+  wire [31:0] up_data_in;
+  input [31:0] up_addr;
+  wire [31:0] up_addr;
+  input up_cs_b;
+  wire up_cs_b;
+  input up_rw_b;
+  wire up_rw_b;
+  output [31:0] up_data_out_ov;
+	output up_busy_ov;
+	input [31:0] up_data_out_iv;
+  output [31:0] wb_addr_o_ov;
+	output [1:0] visual_Wish_idle_current_ov;
+	output [31:0] wb_dat_o_ov;
+	input [31:0] wb_dat_o_iv;
+  output [3:0] wb_sel_o_ov;
+	output wb_we_o_ov;
+	output wb_stb_o_ov;
+	output wb_cyc_o_ov;
+	input up_busy_iv;          
+  reg [31:0] up_data_out_ov;
+  input [31:0] wb_addr_o_iv;
+  reg [31:0] wb_addr_o_ov;
+  reg [31:0] wb_dat_o_ov;
+  input [3:0] wb_sel_o_iv;
+  reg [3:0] wb_sel_o_ov;
+  reg wb_we_o_ov;
+  reg wb_stb_o_ov;
+  wire wb_ack_i;
+  wire [31:0] wb_dat_i;
+  reg wb_cyc_o_ov;
+  wire clock;
+  wire reset;
+  wire wb_err_in;
+  reg up_busy_ov;
+  reg [1:0] visual_Wish_idle_current_ov;
+	parameter Wish_idle = 2'b00,
+            CS_enable = 2'b01,
+            Wb_ack    = 2'b10,
+            up2w_read = 2'b11;
+ 
+  
+  always  @(posedge clock or posedge reset)
+  begin : up_2_wishbone_Wish_idle
+    if (reset === 1'b1)
+    begin
+      wb_stb_o_ov <=   1'b0;   
+      wb_cyc_o_ov <=   1'b0;    
+      wb_addr_o_ov <=   32'h0;
+      wb_we_o_ov <=   ~up_rw_b;   
+      wb_sel_o_ov <=  4'hf;   
+      up_busy_ov <=   1'b0;
+      visual_Wish_idle_current_ov <=   Wish_idle;
+    end
+    else
+    begin
+      wb_stb_o_ov    <=   wb_stb_o_iv;   
+      wb_cyc_o_ov    <=   wb_cyc_o_iv;    
+      wb_addr_o_ov   <=   wb_addr_o_iv;
+      wb_we_o_ov     <=   wb_we_o_iv;   
+      wb_sel_o_ov    <=   wb_sel_o_iv;   
+      up_busy_ov     <=   up_busy_iv;
+	wb_dat_o_ov    <=   wb_dat_o_iv;
+	up_data_out_ov <=   up_data_out_iv;
+      visual_Wish_idle_current_ov <=   visual_Wish_idle_current_iv;
+
+      case (visual_Wish_idle_current_iv)
+        Wish_idle:
+          begin
+            if (up_cs_b == 1'b1)
+            begin
+              visual_Wish_idle_current_ov <=   Wish_idle;
+            end
+            else if (up_cs_b == 1'b0)
+            begin
+              wb_addr_o_ov <=   up_addr;   
+              wb_stb_o_ov <=   1'b1;
+              wb_cyc_o_ov <=   1'b1;
+              wb_dat_o_ov <=   up_data_in;
+              wb_we_o_ov <=   ~up_rw_b;
+              up_busy_ov <=   1'b1;
+              visual_Wish_idle_current_ov <=   CS_enable;
+            end
+            else
+              visual_Wish_idle_current_ov <=   Wish_idle;
+          end
+ 
+        CS_enable:
+          begin
+            if ((wb_ack_i == 1'b0) && (wb_err_in == 1'b0))
+            begin
+              visual_Wish_idle_current_ov <=   CS_enable;
+            end
+            else if ((wb_ack_i == 1'b1) && (wb_err_in == 1'b0))
+            begin
+              up_busy_ov <=   1'b0;
+              wb_stb_o_ov <=   1'b0;
+              visual_Wish_idle_current_ov <=   Wb_ack;
+            end
+            else if (wb_err_in == 1'b1)
+            begin
+              wb_stb_o_ov <=   1'b0;   
+              wb_cyc_o_ov <=   1'b0;    
+              wb_addr_o_ov <=   32'h0;
+              wb_we_o_ov <=   ~up_rw_b;   
+              wb_sel_o_ov <=  4'hf;   
+              up_busy_ov <=   1'b0;
+              visual_Wish_idle_current_ov <=   Wish_idle;
+            end
+            else
+              visual_Wish_idle_current_ov <=   CS_enable;
+          end
+ 
+        Wb_ack:
+          begin
+            if (up_rw_b == 1'b0)
+            begin
+              wb_stb_o_ov <=   1'b0;   
+              wb_cyc_o_ov <=   1'b0;    
+              wb_addr_o_ov <=   32'h0;
+              wb_we_o_ov <=   ~up_rw_b;   
+              wb_sel_o_ov <=  4'hf;   
+              up_busy_ov <=   1'b0;
+              visual_Wish_idle_current_ov <=   Wish_idle;
+            end
+            else if (up_rw_b == 1'b1)
+            begin
+              up_data_out_ov <=   wb_dat_i;
+              visual_Wish_idle_current_ov <=   up2w_read;
+            end
+            else
+              visual_Wish_idle_current_ov <=   Wb_ack;
+          end
+ 
+        up2w_read:
+          begin
+            wb_stb_o_ov <=   1'b0;   
+            wb_cyc_o_ov <=   1'b0;    
+            wb_addr_o_ov <=   32'h0;
+            wb_we_o_ov <=   ~up_rw_b;   
+            wb_sel_o_ov <=  4'hf;   
+            up_busy_ov <=   1'b0;
+            visual_Wish_idle_current_ov <=   Wish_idle;
+          end
+ 
+        default:
+          begin
+            wb_stb_o_ov <=   1'b0;   
+            wb_cyc_o_ov <=   1'b0;    
+            wb_addr_o_ov <=   32'h0;
+            wb_we_o_ov <=   ~up_rw_b;   
+            wb_sel_o_ov <=  4'hf;   
+            up_busy_ov <=   1'b0;
+            visual_Wish_idle_current_ov <=   Wish_idle;
+          end
+      endcase
+    end
+  end
+ 
+ 
+ 
+endmodule
+
+
+
+module up_2_wishbone_tri (up_data_in_1, up_data_in_2, up_data_in_3, up_addr_1, up_addr_2, up_addr_3, up_cs_b_1, up_cs_b_2, up_cs_b_3, up_rw_b_1, up_rw_b_2, up_rw_b_3, up_data_out_1, up_data_out_2, up_data_out_3,
+                      wb_addr_o_1, wb_addr_o_2, wb_addr_o_3, wb_dat_o_1, wb_dat_o_2, wb_dat_o_3, wb_sel_o_1, wb_sel_o_2, wb_sel_o_3, wb_we_o_1, wb_we_o_2, wb_we_o_3, wb_stb_o_1, wb_stb_o_2, wb_stb_o_3,
+                      wb_ack_i_1, wb_ack_i_2, wb_ack_i_3, wb_dat_i_1, wb_dat_i_2, wb_dat_i_3, wb_cyc_o_1, wb_cyc_o_2, wb_cyc_o_3, clock_1, clock_2, clock_3, reset_1, reset_2, reset_3, wb_err_in_1, wb_err_in_2, wb_err_in_3,
+                      up_busy_1, up_busy_2, up_busy_3
+                      );
+
+  input [31:0] up_data_in_1, up_data_in_2, up_data_in_3;
+  input [31:0] up_addr_1, up_addr_2, up_addr_3;
+  input up_cs_b_1, up_cs_b_2, up_cs_b_3;
+  input up_rw_b_1, up_rw_b_2, up_rw_b_3;
+  output [31:0] up_data_out_1, up_data_out_2, up_data_out_3;
+  output [31:0] wb_addr_o_1, wb_addr_o_2, wb_addr_o_3;
+  output [31:0] wb_dat_o_1, wb_dat_o_2, wb_dat_o_3;
+  output [3:0] wb_sel_o_1, wb_sel_o_2, wb_sel_o_3;
+  output wb_we_o_1, wb_we_o_2, wb_we_o_3;
+  output wb_stb_o_1, wb_stb_o_2, wb_stb_o_3;
+  input wb_ack_i_1, wb_ack_i_2, wb_ack_i_3;
+  input [31:0] wb_dat_i_1, wb_dat_i_2, wb_dat_i_3;
+  output wb_cyc_o_1, wb_cyc_o_2, wb_cyc_o_3;
+  input clock_1, clock_2, clock_3;
+  input reset_1, reset_2, reset_3;
+  input wb_err_in_1, wb_err_in_2, wb_err_in_3;
+  output up_busy_1, up_busy_2, up_busy_3;          
+
+	wire wb_stb_o_1, wb_stb_o_2, wb_stb_o_3;
+	wire wb_cyc_o_1, wb_cyc_o_2, wb_cyc_o_3;
+	wire [31:0] wb_addr_o_1, wb_addr_o_2, wb_addr_o_3;
+	wire wb_we_o_1, wb_we_o_2, wb_we_o_3;
+	wire [3:0] wb_sel_o_1, wb_sel_o_2, wb_sel_o_3;
+	wire up_busy_1, up_busy_2, up_busy_3;
+	wire [1:0] visual_Wish_idle_current_1, visual_Wish_idle_current_2, visual_Wish_idle_current_3;
+	wire [31:0] wb_dat_o_1, wb_dat_o_2, wb_dat_o_3;
+	wire [31:0] up_data_out_1, up_data_out_2, up_data_out_3;
+	wire wb_stb_o;
+	wire wb_cyc_o;
+	wire [31:0] wb_addr_o;
+	wire wb_we_o;
+	wire [3:0] wb_sel_o;
+	wire up_busy;
+	wire [1:0] visual_Wish_idle_current;
+	wire [31:0] wb_dat_o;
+	wire [31:0] up_data_out;
+
+	up_2_wishbone_iostate up_2_wishbone_iostate_1   (.up_data_in(up_data_in_1), .up_addr(up_addr_1), .up_cs_b(up_cs_b_1), .up_rw_b(up_rw_b_1), .up_data_out_iv(up_data_out_1), .up_data_out_ov(up_data_out_2),
+                      .wb_addr_o_iv(wb_addr_o_1), .wb_addr_o_ov(wb_addr_o_2), .wb_dat_o_iv(wb_dat_o_1), .wb_dat_o_ov(wb_dat_o_2), .wb_sel_o_iv(wb_sel_o_1), .wb_sel_o_ov(wb_sel_o_2), .wb_we_o_iv(wb_we_o_1), .wb_we_o_ov(wb_we_o_2), .wb_stb_o_iv(wb_stb_o_1), .wb_stb_o_ov(wb_stb_o_2),
+                      .wb_ack_i(wb_ack_i_1), .wb_dat_i(wb_dat_i_1), .wb_cyc_o_iv(wb_cyc_o_1), .wb_cyc_o_ov(wb_cyc_o_2), .clock(clock_1), .reset(reset_1), .wb_err_in(wb_err_in_1),
+                      .up_busy_iv(up_busy_1), .up_busy_ov(up_busy_2), .visual_Wish_idle_current_iv(visual_Wish_idle_current_1), .visual_Wish_idle_current_ov(visual_Wish_idle_current_2));
+
+	up_2_wishbone_iostate up_2_wishbone_iostate_2   (.up_data_in(up_data_in_2), .up_addr(up_addr_2), .up_cs_b(up_cs_b_2), .up_rw_b(up_rw_b_2), .up_data_out_iv(up_data_out_2), .up_data_out_ov(up_data_out_3),
+                      .wb_addr_o_iv(wb_addr_o_2), .wb_addr_o_ov(wb_addr_o_3), .wb_dat_o_iv(wb_dat_o_2), .wb_dat_o_ov(wb_dat_o_3), .wb_sel_o_iv(wb_sel_o_2), .wb_sel_o_ov(wb_sel_o_3), .wb_we_o_iv(wb_we_o_2), .wb_we_o_ov(wb_we_o_3), .wb_stb_o_iv(wb_stb_o_2), .wb_stb_o_ov(wb_stb_o_3),
+                      .wb_ack_i(wb_ack_i_2), .wb_dat_i(wb_dat_i_2), .wb_cyc_o_iv(wb_cyc_o_2), .wb_cyc_o_ov(wb_cyc_o_3), .clock(clock_2), .reset(reset_2), .wb_err_in(wb_err_in_2),
+                      .up_busy_iv(up_busy_2), .up_busy_ov(up_busy_3), .visual_Wish_idle_current_iv(visual_Wish_idle_current_2), .visual_Wish_idle_current_ov(visual_Wish_idle_current_3));
+
+	up_2_wishbone_iostate up_2_wishbone_iostate_3   (.up_data_in(up_data_in_3), .up_addr(up_addr_3), .up_cs_b(up_cs_b_3), .up_rw_b(up_rw_b_3), .up_data_out_iv(up_data_out_3), .up_data_out_ov(up_data_out),
+                      .wb_addr_o_iv(wb_addr_o_3), .wb_addr_o_ov(wb_addr_o), .wb_dat_o_iv(wb_dat_o_3), .wb_dat_o_ov(wb_dat_o), .wb_sel_o_iv(wb_sel_o_3), .wb_sel_o_ov(wb_sel_o), .wb_we_o_iv(wb_we_o_3), .wb_we_o_ov(wb_we_o), .wb_stb_o_iv(wb_stb_o_3), .wb_stb_o_ov(wb_stb_o),
+                      .wb_ack_i(wb_ack_i_3), .wb_dat_i(wb_dat_i_3), .wb_cyc_o_iv(wb_cyc_o_3), .wb_cyc_o_ov(wb_cyc_o), .clock(clock_3), .reset(reset_3), .wb_err_in(wb_err_in_3),
+                      .up_busy_iv(up_busy_3), .up_busy_ov(up_busy), .visual_Wish_idle_current_iv(visual_Wish_idle_current_3), .visual_Wish_idle_current_ov(visual_Wish_idle_current));
+
+	majority_voter #(.WIDTH(106)) mv (
+		.in1({wb_stb_o_2, wb_cyc_o_2, wb_addr_o_2, wb_we_o_2, wb_sel_o_2, up_busy_2, visual_Wish_idle_current_2, wb_dat_o_2, up_data_out_2}),
+		.in2({wb_stb_o_3, wb_cyc_o_3, wb_addr_o_3, wb_we_o_3, wb_sel_o_3, up_busy_3, visual_Wish_idle_current_3, wb_dat_o_3, up_data_out_3}),
+		.in3({wb_stb_o, wb_cyc_o, wb_addr_o, wb_we_o, wb_sel_o, up_busy, visual_Wish_idle_current, wb_dat_o, up_data_out}),
+		.out({wb_stb_o_1, wb_cyc_o_1, wb_addr_o_1, wb_we_o_1, wb_sel_o_1, up_busy_1, visual_Wish_idle_current_1, wb_dat_o_1, up_data_out_1}),
+		.err()
+	);
+endmodule
+
+
+
+
+//--------------------------------------------------
+//  
+//      Verilog code generated by Visual Elite
+//
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  nctrl
+//      Library Name  :  node_ctrl
+//  
+//      Creation Date :  Thu Aug  1 16:01:28 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  Combined file
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         IF for state selection         :  No
+//         Error (default) state          :  Yes
+//         String typed state variable    :  No
+//         Next state assignments         :  Non blocking
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  node_ctrl
+//  Unit    Name :  nctrl
+//  Unit    Type :  State Machine
+//  
+//----------------------------------------------------
+ 
+ 
+
+module nctrl_iostate (clock, reset, up_rw_b_i, up_rw_b_o, up_data_out_i, up_data_out_o, up_data_in, up_addr_i, up_addr_o, up_cs_b_i, up_cs_b_o,
+              tx_ena_i, tx_ena_o, tx_dav, nc_ready_i, nc_ready_o, rx_dav_i, rx_dav_o, rx_ena, dataw_in, dataw_out_i, dataw_out_o,
+              Int_arb_in, up_busy_in, CRE_i, CRE_o, SRA_i, SRA_o, SRB_i, SRB_o, CRA_i, CRA_o, CRB_i, CRB_o, CRC_i, CRC_o, CRD_i, CRD_o, 
+              EN_ch_reg_i, EN_ch_reg_o, AckByte_i, AckByte_o, LenRep_i, LenRep_o, TR_i, TR_o, CH_i, CH_o, CMD_i, CMD_o, LEN_i, LEN_o, rep_node_i, 
+              rep_node_o, SPI_CTRL_i, SPI_CTRL_o, data_in_tmp_i, data_in_tmp_o, data_in_tmp1_i, data_in_tmp1_o, invalid_cmd_i, invalid_cmd_o, 
+              mem0_i, mem0_o, mem1_i, mem1_o, mem2_i, mem2_o, mem3_i, mem3_o, mem4_i, mem4_o, mem5_i, mem5_o, mem6_i, mem6_o, mem7_i, mem7_o, 
+              mem8_i, mem8_o, mem9_i, mem9_o, mem10_i, mem10_o, mem11_i, mem11_o, mem12_i, mem12_o, mem13_i, mem13_o, mem14_i, mem14_o, mem15_i, mem15_o, 
+              mem16_i, mem16_o, mem17_i, mem17_o, mem18_i, mem18_o, mem19_i, mem19_o, mem20_i, mem20_o, mem21_i, mem21_o, 
+              visual_RST_ST_current_i, visual_RST_ST_current_o);
+              
+	`include "Table_Commande.v"
+	
+	
+	input clock;
+	input [6:0] visual_RST_ST_current_i;
+
+	input [7:0] mem21_i;
+	input [7:0] mem20_i;
+	input [7:0] mem19_i;
+	input [7:0] mem18_i;
+	input [7:0] mem17_i;
+	input [7:0] mem16_i;
+	input [7:0] mem15_i;
+	input [7:0] mem14_i;
+	input [7:0] mem13_i;
+	input [7:0] mem12_i;
+	input [7:0] mem11_i;
+	input [7:0] mem10_i;
+	input [7:0] mem9_i;
+	input [7:0] mem8_i;
+	input [7:0] mem7_i;
+	input [7:0] mem6_i;
+	input [7:0] mem5_i;
+	input [7:0] mem4_i;
+	input [7:0] mem3_i;
+	input [7:0] mem2_i;
+	input [7:0] mem1_i;
+	input [7:0] mem0_i;
+	input up_rw_b_i;
+	input up_cs_b_i;
+	input nc_ready_i;
+	input invalid_cmd_i;
+	input [15:0] data_in_tmp1_i;
+	input [15:0] data_in_tmp_i;
+	input [atlantic_nb_bit:0] dataw_out_i;
+	input [15:0] SPI_CTRL_i;
+	input [7:0] rep_node_i;
+	input [wb_nb_bit:0] up_addr_i;
+	input [7:0] LEN_i;
+	input [7:0] CMD_i;
+	input [7:0] CH_i;
+	input [7:0] TR_i;
+	input [7:0] LenRep_i;
+	input [7:0] AckByte_i;
+	input [31:0] EN_ch_reg_i;
+	input [7:0] CRE_i;
+
+	input [7:0] CRD_i;
+	input [7:0] CRC_i;
+	input [7:0] CRB_i;
+	input [7:0] CRA_i;
+	input [7:0] SRB_i;
+	input [7:0] SRA_i;
+	input tx_ena_i;
+	input rx_dav_i;
+
+	input reset;
+	input [wb_nb_bit:0] up_data_in;
+	input tx_dav;
+	input rx_ena;
+	input [atlantic_nb_bit:0] dataw_in;
+	input [5:0] Int_arb_in;
+	input up_busy_in;
+	output up_rw_b_o;
+	output [6:0] visual_RST_ST_current_o;
+	output [7:0] mem21_o;
+	output [7:0] mem20_o;
+	output [7:0] mem19_o;
+	output [7:0] mem18_o;
+	output [7:0] mem17_o;
+	output [7:0] mem16_o;
+	output [7:0] mem15_o;
+	output [7:0] mem14_o;
+	output [7:0] mem13_o;
+	output [7:0] mem12_o;
+	output [7:0] mem11_o;
+	output [7:0] mem10_o;
+	output [7:0] mem9_o;
+	output [7:0] mem8_o;
+	output [7:0] mem7_o;
+	output [7:0] mem6_o;
+	output [7:0] mem5_o;
+	output [7:0] mem4_o;
+	output [7:0] mem3_o;
+	output [7:0] mem2_o;
+	output [7:0] mem1_o;
+	output [7:0] mem0_o;
+	output [7:0] CRE_o;
+	output [wb_nb_bit:0] up_data_out_o;
+	input [wb_nb_bit:0] up_data_out_i;
+	output [wb_nb_bit:0] up_addr_o;
+	output invalid_cmd_o;
+	output [15:0] data_in_tmp1_o;
+	output [15:0] data_in_tmp_o;
+	output up_cs_b_o;
+	output [15:0] SPI_CTRL_o;
+	output [7:0] rep_node_o;
+	output tx_ena_o;
+	output [7:0] LEN_o;
+	output [7:0] CMD_o;
+	output [7:0] CH_o;
+	output [7:0] TR_o;
+	output [7:0] LenRep_o;
+	output [7:0] AckByte_o;
+	output [31:0] EN_ch_reg_o;
+	output nc_ready_o;
+	output [7:0] CRD_o;
+	output [7:0] CRC_o;
+	output [7:0] CRB_o;
+	output [7:0] CRA_o;
+	output [7:0] SRB_o;
+	output [7:0] SRA_o;
+	output rx_dav_o;
+	output [atlantic_nb_bit:0] dataw_out_o;
+	
+  parameter RST_ST         = 7'b0000000,
+            ADC_cmd_valid  = 7'b0000001,
+            BUSY_STATE     = 7'b0000010,
+            CH_errors      = 7'b0000011,
+            CMD_ACCEPT     = 7'b0000100,
+            DAC_cmd_valid  = 7'b0000101,
+            GPIO_cmd_valid = 7'b0000110,
+            I2c_cmd_valid  = 7'b0000111,
+            IntColli       = 7'b0001000,
+            Int_Ack        = 7'b0001001,
+            Interr1        = 7'b0001010,
+            Jtag_cmd_valid = 7'b0001011,
+            REPOS          = 7'b0001100,
+            ReadData       = 7'b0001101,
+            ReadData_15_0  = 7'b0001110,
+            Read_node      = 7'b0001111,
+            Reply_d1_d2    = 7'b0010000,
+            Rx1_data_sup   = 7'b0010001,
+            Rx_Data        = 7'b0010010,
+            Rx_word2       = 7'b0010011,
+            S28            = 7'b0010100,
+            S41            = 7'b0010101,
+            S46csb0        = 7'b0010110,
+            S47csb1        = 7'b0010111,
+            S48busy1       = 7'b0011000,
+            SPI_cmd_valid  = 7'b0011001,
+            Send2Ack       = 7'b0011010,
+            clr_data       = 7'b0011011,
+            delai          = 7'b0011100,
+            tst_busy       = 7'b0011101,
+            tx_dav_ok      = 7'b0011110,
+            Sel_CH_spi     = 7'b0011111,
+            Read_Wish      = 7'b0100000,
+            S0_int_adc     = 7'b0100001,
+            S3_int_adc     = 7'b0100010,
+            Dec_cmd_CH0    = 7'b0100011,
+            NC_invalid     = 7'b0100100,
+            Rd_CRA         = 7'b0100101,
+            Rd_CRB         = 7'b0100110,
+            Rd_CRC         = 7'b0100111,
+            Rd_CRD         = 7'b0101000,
+            Rd_CRE         = 7'b0101001,
+            Wr_CRA         = 7'b0101010,
+            Wr_CRB         = 7'b0101011,
+            Wr_CRC         = 7'b0101100,
+            Wr_CRD         = 7'b0101101,
+            Wr_CRE         = 7'b0101110,
+            Decod_Cmd_CH1  = 7'b0101111,
+            CS_bas         = 7'b0110000,
+            S10            = 7'b0110001,
+            S9             = 7'b0110010,
+            write_up       = 7'b0110011,
+            S0cmd3         = 7'b0110100,
+            S10_cs_0       = 7'b0110101,
+            S3cmd3         = 7'b0110110,
+            S4cmd3         = 7'b0110111,
+            S6cmd3_Read    = 7'b0111000,
+            S7_addten      = 7'b0111001,
+            cmd3_write     = 7'b0111010,
+            Rd_Gpio_int0   = 7'b0111011,
+            Gpio_wr_wait   = 7'b0111100,
+            Rd_Gpio_int1   = 7'b0111101,
+            Rd_Gpio_int2   = 7'b0111110,
+            Rd_Gpio_int3   = 7'b0111111,
+            Rd_Gpio_int4   = 7'b1000000,
+            Rd_Gpio_int5   = 7'b1000001,
+            S0int_i2c      = 7'b1000010,
+            S1int_i2c      = 7'b1000011,
+            S0_int_jtag    = 7'b1000100,
+            S3_int_jtag    = 7'b1000101;
+  
+
+
+
+	reg up_rw_b_o;
+	reg [wb_nb_bit:0] up_data_out_o;
+	reg [wb_nb_bit:0] up_addr_o;
+	reg up_cs_b_o;
+	reg tx_ena_o;
+	reg nc_ready_o;
+	reg rx_dav_o;
+	reg [atlantic_nb_bit:0] dataw_out_o;
+	reg [7:0] CRE_o;
+	reg [7:0] SRB_o;
+	reg [7:0] SRA_o;
+	reg [7:0] CRA_o;
+	reg [7:0] CH_o;
+	reg [7:0] TR_o;
+	reg [7:0] CMD_o;
+	reg [7:0] LEN_o;
+	reg [15:0] data_in_tmp_o;
+	reg [7:0] CRB_o;
+	reg [7:0] CRC_o;
+	reg [7:0] CRD_o;
+	reg [15:0] data_in_tmp1_o;
+	reg [15:0] SPI_CTRL_o;
+	reg [7:0] rep_node_o;
+	reg invalid_cmd_o;
+	reg [7:0] AckByte_o;
+	reg [7:0] LenRep_o;
+	reg [31:0] EN_ch_reg_o;
+	reg [7:0] mem0_o;
+	reg [7:0] mem1_o;
+	reg [7:0] mem2_o;
+	reg [7:0] mem3_o;
+	reg [7:0] mem4_o;
+	reg [7:0] mem5_o;
+	reg [7:0] mem6_o;
+	reg [7:0] mem7_o;
+	reg [7:0] mem8_o;
+	reg [7:0] mem9_o;
+	reg [7:0] mem10_o;
+	reg [7:0] mem11_o;
+	reg [7:0] mem12_o;
+	reg [7:0] mem13_o;
+	reg [7:0] mem14_o;
+	reg [7:0] mem15_o;
+	reg [7:0] mem16_o;
+	reg [7:0] mem17_o;
+	reg [7:0] mem18_o;
+	reg [7:0] mem19_o;
+	reg [7:0] mem20_o;
+	reg [7:0] mem21_o;
+	reg [6:0] visual_RST_ST_current_o;
+	
+	
+	function [7:0] read_mem;
+	input [4:0] adr;
+  	begin
+      case(adr[4:0])
+             0:read_mem = mem0_i;
+  		 1:read_mem = mem1_i; 
+  		 2:read_mem = mem2_i;  
+  		 3:read_mem = mem3_i; 
+  		 4:read_mem = mem4_i; 
+  		 5:read_mem = mem5_i; 
+  		 6:read_mem = mem6_i; 
+  		 7:read_mem = mem7_i; 
+  		 8:read_mem = mem8_i; 
+  		 9:read_mem = mem9_i;
+  		10:read_mem = mem10_i;
+  		11:read_mem = mem11_i;
+  		12:read_mem = mem12_i;
+  		13:read_mem = mem13_i;
+  		14:read_mem = mem14_i;
+  		15:read_mem = mem15_i;
+  		16:read_mem = mem16_i;
+  		17:read_mem = mem17_i;
+  		18:read_mem = mem18_i;
+  		19:read_mem = mem19_i;
+  		20:read_mem = mem20_i;
+  		21:read_mem = mem21_i;
+  		default: read_mem = 8'h00;
+  	endcase
+  end
+  endfunction
+ 
+  
+  always  @(posedge clock or posedge reset)
+  begin : nctrl_RST_ST
+ 
+    if (reset == 1'b1)
+    begin
+      rx_dav_o <=   1'b0;
+      tx_ena_o <=   1'b0;
+      dataw_out_o <=   16'h0000;
+      SRA_o <=   8'h00;
+      SRB_o <=   8'h00;
+      CRA_o <=   8'h00;
+      CRB_o <=   8'h00;
+      CRC_o <=   8'h00;
+      CRD_o <=   8'h00;
+      CRE_o <=   8'h00;
+      EN_ch_reg_o <=   32'h00000001;
+      AckByte_o <=   8'h00;
+      LenRep_o <=   8'h00;
+      TR_o <=   8'h00;
+      CH_o <=   8'h00;
+      CMD_o <=   8'h00;
+      LEN_o <=   8'h00;
+      up_addr_o <=   32'h00000000;
+      rep_node_o <=   8'h00;
+      SPI_CTRL_o <=   16'h0000;
+      nc_ready_o <=   1'b0;
+      data_in_tmp_o <=   16'h0000;
+      data_in_tmp1_o <=   16'h0000;
+      invalid_cmd_o <=   1'b0;
+      up_cs_b_o <=   1'b1;
+      up_rw_b_o <=   1'b0;
+      up_data_out_o <=   32'h00000000;
+      mem0_o  <=   8'h00;  
+      mem1_o  <=   8'h00;
+      mem2_o  <=   8'h00;  
+      mem3_o  <=   8'h00;
+      mem4_o  <=   8'h00;  
+      mem5_o  <=   8'h00;
+      mem6_o  <=   8'h00;  
+      mem7_o  <=   8'h00;
+      mem8_o  <=   8'h00;  
+      mem9_o  <=   8'h00;
+      mem10_o <=   8'h00; 
+      mem11_o <=   8'h00;
+      mem12_o <=   8'h00;  
+      mem13_o <=   8'h00;
+      mem14_o <=   8'h00;  
+      mem15_o <=   8'h00;
+      mem16_o <=   8'h00;  
+      mem17_o <=   8'h00;
+      mem18_o <=   8'h00;  
+      mem19_o <=   8'h00;
+      mem20_o <=   8'h00;  
+      mem21_o <=   8'h00;
+      visual_RST_ST_current_o <=   RST_ST;
+      
+ 
+    end
+    else
+    begin
+            rx_dav_o       <=   rx_dav_i;
+            tx_ena_o       <=   tx_ena_i;
+            dataw_out_o    <=   dataw_out_i;
+            SRA_o          <=   SRA_i;
+            SRB_o          <=   SRB_i;
+            CRA_o          <=   CRA_i;
+            CRB_o          <=   CRB_i;
+            CRC_o          <=   CRC_i;
+            CRD_o          <=   CRD_i;
+            CRE_o          <=   CRE_i;
+            EN_ch_reg_o    <=   EN_ch_reg_i;
+            AckByte_o      <=   AckByte_i;
+            LenRep_o       <=   LenRep_i;
+            TR_o           <=   TR_i;
+            CH_o           <=   CH_i;
+            CMD_o          <=   CMD_i;
+            LEN_o          <=   LEN_i;
+            up_addr_o      <=   up_addr_i;
+            rep_node_o     <=   rep_node_i;
+            SPI_CTRL_o     <=   SPI_CTRL_i;
+            nc_ready_o     <=   nc_ready_i;
+            data_in_tmp_o  <=   data_in_tmp_i;
+            data_in_tmp1_o <=   data_in_tmp1_i;
+            invalid_cmd_o  <=   invalid_cmd_i;
+            up_cs_b_o      <=   up_cs_b_i;
+            up_rw_b_o      <=   up_rw_b_i;
+            up_data_out_o  <=   up_data_out_i;
+            
+            mem0_o         <=   mem0_i;  
+            mem1_o         <=   mem1_i;
+            mem2_o         <=   mem2_i;  
+            mem3_o         <=   mem3_i;
+            mem4_o         <=   mem4_i;  
+            mem5_o         <=   mem5_i;
+            mem6_o         <=   mem6_i;  
+            mem7_o         <=   mem7_i;
+            mem8_o         <=   mem8_i;  
+            mem9_o         <=   mem9_i;
+            mem10_o        <=   mem10_i; 
+            mem11_o        <=   mem11_i;
+            mem12_o        <=   mem12_i;  
+            mem13_o        <=   mem13_i;
+            mem14_o        <=   mem14_i;  
+            mem15_o        <=   mem15_i;
+            mem16_o        <=   mem16_i;  
+            mem17_o        <=   mem17_i;
+            mem18_o        <=   mem18_i;  
+            mem19_o        <=   mem19_i;
+            mem20_o        <=   mem20_i;  
+		mem21_o        <=   mem21_i;
+		
+		visual_RST_ST_current_o <=   visual_RST_ST_current_i; 
+		
+      case (visual_RST_ST_current_i)
+        RST_ST:
+          begin
+            
+            up_cs_b_o <=   1'b1;
+            up_rw_b_o <=   1'b1;     
+            tx_ena_o <=   1'b0;
+            nc_ready_o <=   1'b1;
+            rx_dav_o <=   1'b1;     
+            invalid_cmd_o <=   1'b0;
+            AckByte_o <=   8'h00;
+            LenRep_o <=   8'h00;
+            visual_RST_ST_current_o <=   REPOS;
+          end
+ 
+        ADC_cmd_valid:
+          begin
+            if (invalid_cmd_i == 1'b1)
+            begin
+              
+              
+          	case(CH_i[4:0])
+          	 0:mem0_o   <=   8'h00;
+  		 1:mem1_o   <=   8'h00; 
+  		 2:mem2_o   <=   8'h00;  
+  		 3:mem3_o   <=   8'h00; 
+  		 4:mem4_o   <=   8'h00; 
+  		 5:mem5_o   <=   8'h00; 
+  		 6:mem6_o   <=   8'h00; 
+  		 7:mem7_o   <=   8'h00; 
+  		 8:mem8_o   <=   8'h00; 
+  		 9:mem9_o   <=   8'h00;
+  		10:mem10_o  <=   8'h00;
+  		11:mem11_o  <=   8'h00;
+  		12:mem12_o  <=   8'h00;
+  		13:mem13_o  <=   8'h00;
+  		14:mem14_o  <=   8'h00;
+  		15:mem15_o  <=   8'h00;
+  		16:mem16_o  <=   8'h00;
+  		17:mem17_o  <=   8'h00;
+  		18:mem18_o  <=   8'h00;
+  		19:mem19_o  <=   8'h00;
+  		20:mem20_o  <=   8'h00;
+  		21:mem21_o  <=   8'h00;
+  		endcase
+ 
+              visual_RST_ST_current_o <=   clr_data;
+            end
+            else if (invalid_cmd_i == 1'b0)
+            begin
+              visual_RST_ST_current_o <=   Decod_Cmd_CH1;
+            end
+            else
+              visual_RST_ST_current_o <=   ADC_cmd_valid;
+          end
+ 
+        BUSY_STATE:
+          begin
+            if (tx_dav == 1'b0)
+            begin
+              visual_RST_ST_current_o <=   BUSY_STATE;
+            end
+            else if (tx_dav == 1'b1)
+            begin
+              tx_ena_o <=   1'b1;
+              dataw_out_o[15:8] <=   CH_i[7:0];
+              dataw_out_o[7:0] <=   TR_i[7:0];
+              up_cs_b_o <=   1'b1;
+              visual_RST_ST_current_o <=   tx_dav_ok;
+            end
+            else
+              visual_RST_ST_current_o <=   BUSY_STATE;
+          end
+ 
+        CH_errors:
+          begin
+            if (tx_dav == 1'b0)
+            begin
+              visual_RST_ST_current_o <=   CH_errors;
+            end
+            else if (tx_dav == 1'b1)
+            begin
+              tx_ena_o <=   1'b1;
+              dataw_out_o[15:8] <=   CH_i[7:0];
+              dataw_out_o[7:0] <=   TR_i[7:0];
+              visual_RST_ST_current_o <=   S28;
+            end
+            else
+              visual_RST_ST_current_o <=   CH_errors;
+          end
+ 
+        CMD_ACCEPT:
+          begin
+            if (rx_ena == 1'b1)
+            begin
+              data_in_tmp1_o <=   dataw_in;
+              visual_RST_ST_current_o <=   Rx_Data;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_NODE))
+            begin
+              LenRep_o <=   8'h03;  
+              visual_RST_ST_current_o <=   Dec_cmd_CH0;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_SPI))
+            begin
+              case (CMD_i)
+                SPI_wrt_TX0,
+                SPI_rea_RX0,
+		SPI_wrt_TX1,
+		SPI_rea_RX1,
+		SPI_wrt_TX2,
+		SPI_rea_RX2,
+		SPI_wrt_TX3,
+		SPI_rea_RX3,
+		SPI_wrt_ctrl,
+		SPI_rea_ctrl,
+		SPI_wrt_DIV,
+		SPI_rea_DIV,
+		SPI_wrt_SS,
+		SPI_rea_SS, 
+		SPI_go:     
+                      invalid_cmd_o <=   1'b0;
+              default:
+                invalid_cmd_o <=   1'b1;
+              endcase
+ 
+              if(CMD_i == SPI_wrt_ctrl)
+                  data_in_tmp_o[12] <=   1'b1;  
+              visual_RST_ST_current_o <=   SPI_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_GPIO))
+            begin
+              case(CMD_i)
+                GPIO_R_DAT_IN,GPIO_W_DAT_OUT,GPIO_R_DAT_OUT,GPIO_W_OE:
+                  invalid_cmd_o <=   1'b0;
+                GPIO_R_WE,GPIO_W_INTE,GPIO_R_INTE,GPIO_W_PTRIG,GPIO_R_PTRIG:
+                  invalid_cmd_o <=   1'b0;
+                GPIO_W_AUX,GPIO_R_AUX,GPIO_W_CTRL,GPIO_R_CTRL,GPIO_W_INTS
+              ,GPIO_R_INTS:
+                   invalid_cmd_o <=   1'b0;
+                GPIO_W_ECLK,GPIO_R_ECLK,GPIO_W_NEC,GPIO_R_NEC:
+                    invalid_cmd_o <=   1'b0;
+ 
+              default:
+                invalid_cmd_o <=   1'b1;
+              endcase
+              visual_RST_ST_current_o <=   GPIO_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && ((CH_i >= CH_I2C0) && (CH_I2C15 >= CH_i )))
+            begin
+              case (CMD_i)
+  
+               I2C_READ_SRA,I2C_WRITE_MSK,I2C_READ_MSK,I2C_WRITE_CRA
+              ,I2C_READ_CRA:  // commande direct wb reg
+                  invalid_cmd_o <=   1'b0;
+ 
+               I2C_1BYTE_WRITE,I2C_1BYTE_READ,I2C_1BYTE_WRITE_EXT
+              ,I2C_1byte_READ_EXT,I2C_1byte_rmw_OR,I2C_1byte_rmw_XOR,8'hC2:
+              // commande pour i2c-ccu compatib.
+                  invalid_cmd_o <=   1'b0;
+ 
+                 I2C_W_multi_4byte0,I2C_W_multi_4byte1,I2C_W_multi_4byte2 ,
+               I2C_W_multi_4byte3,I2C_write_multi ,I2C_read_multi:
+              // commande multibyte
+                  invalid_cmd_o <=   1'b0;
+ 
+                 I2C_R_multi_4byte0,I2C_R_multi_4byte1,I2C_R_multi_4byte2
+              ,I2C_R_multi_4byte3:
+                   invalid_cmd_o <=   1'b0;
+ 
+                 I2C_write_multi_ext,I2C_read_multi_ext:
+              // commande multi byte mode ext 10 bit addr
+                   invalid_cmd_o <=   1'b0;
+
+              default:
+                 invalid_cmd_o <=   1'b1;
+              endcase
+              visual_RST_ST_current_o <=   I2c_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_DAC))
+            begin
+              case (CMD_i)
+                DAC_W_CH1,DAC_R_CH1,DAC_W_CH2,DAC_R_CH2,DAC_W_CH3,DAC_R_CH3
+              ,DAC_W_CH4,DAC_R_CH4:
+                invalid_cmd_o <=   1'b0;
+              default:
+                invalid_cmd_o <=   1'b1;
+              endcase
+              visual_RST_ST_current_o <=   DAC_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_JTAG))
+            begin
+              case (CMD_i)
+                     JTG_w_TDO_tx0,
+                     JTG_r_TDI_rx0,
+                     JTG_w_TDO_tx1,
+                     JTG_r_TDI_rx1,
+                     JTG_w_TDO_tx2,
+                     JTG_r_TDI_rx2,
+                     JTG_w_TDO_tx3,
+                     JTG_r_TDI_rx3,
+                     JTG_w_TMS_tx0,
+                     JTG_r_TMS_tx0,
+                     JTG_w_TMS_tx1,
+                     JTG_r_TMS_tx1,
+                     JTG_w_TMS_tx2,
+                     JTG_r_TMS_tx2,
+                     JTG_w_TMS_tx3,
+                     JTG_r_TMS_tx3,
+                     JTG_w_ctrl,
+                     JTG_r_crtl,
+                     JTG_w_div,
+                     JTG_r_div,
+                     JTG_go_auto,
+                     JTG_go_manual,
+                     JTAG_status,
+		     JTAG_RES, 
+		     SEU_read,  
+		     SEU_clear:    
+                     invalid_cmd_o <=   1'b0;
+                default:
+                  invalid_cmd_o <=   1'b1;
+              endcase
+              if(CMD_i == JTG_w_ctrl)
+                   data_in_tmp1_o[12] <=   1'b1;
+              
+              visual_RST_ST_current_o <=   Jtag_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_ADC))
+            begin
+              case(CMD_i)
+                     ADC_GO,      
+                     ADC_W_MUX,    
+                     ADC_R_MUX,    
+                     ADC_W_GAIN,   
+                     ADC_R_GAIN,   
+                     ADC_R_ID,     
+                     ADC_W_CURR,  
+                     ADC_R_CURR,   
+                     ADC_R_DATA,   
+                     ADC_R_CTRL,   
+                     ADC_R_CWD,    
+                     ADC_R_OFFSET, 
+                     FUSE_W_ID,    
+                     FUSE_R_ID,   
+                     FUSE_W_GAIN,  
+                     FUSE_R_GAIN:  
+		 invalid_cmd_o <=   1'b0;
+ 
+              default:
+                 invalid_cmd_o <=   1'b1;
+              endcase
+              visual_RST_ST_current_o <=   ADC_cmd_valid;
+            end
+            else
+              visual_RST_ST_current_o <=   CMD_ACCEPT;
+          end
+ 
+        DAC_cmd_valid:
+          begin
+            if (invalid_cmd_i == 1'b1)
+            begin
+              
+              case(CH_i[4:0])
+             0:mem0_o   <=   8'h00;
+  		 1:mem1_o   <=   8'h00; 
+  		 2:mem2_o   <=   8'h00;  
+  		 3:mem3_o   <=   8'h00; 
+  		 4:mem4_o   <=   8'h00; 
+  		 5:mem5_o   <=   8'h00; 
+  		 6:mem6_o   <=   8'h00; 
+  		 7:mem7_o   <=   8'h00; 
+  		 8:mem8_o   <=   8'h00; 
+  		 9:mem9_o   <=   8'h00;
+  		10:mem10_o  <=   8'h00;
+  		11:mem11_o  <=   8'h00;
+  		12:mem12_o  <=   8'h00;
+  		13:mem13_o  <=   8'h00;
+  		14:mem14_o  <=   8'h00;
+  		15:mem15_o  <=   8'h00;
+  		16:mem16_o  <=   8'h00;
+  		17:mem17_o  <=   8'h00;
+  		18:mem18_o  <=   8'h00;
+  		19:mem19_o  <=   8'h00;
+  		20:mem20_o  <=   8'h00;
+  		21:mem21_o  <=   8'h00;
+  		endcase
+              visual_RST_ST_current_o <=   clr_data;
+            end
+            else if (invalid_cmd_i == 1'b0)
+            begin
+              visual_RST_ST_current_o <=   Decod_Cmd_CH1;
+            end
+            else
+              visual_RST_ST_current_o <=   DAC_cmd_valid;
+          end
+ 
+        GPIO_cmd_valid:
+          begin
+            if (invalid_cmd_i == 1'b1)
+            begin
+              
+              case(CH_i[4:0])
+             0:mem0_o   <=   8'h00;
+  		 1:mem1_o   <=   8'h00; 
+  		 2:mem2_o   <=   8'h00;  
+  		 3:mem3_o   <=   8'h00; 
+  		 4:mem4_o   <=   8'h00; 
+  		 5:mem5_o   <=   8'h00; 
+  		 6:mem6_o   <=   8'h00; 
+  		 7:mem7_o   <=   8'h00; 
+  		 8:mem8_o   <=   8'h00; 
+  		 9:mem9_o   <=   8'h00;
+  		10:mem10_o  <=   8'h00;
+  		11:mem11_o  <=   8'h00;
+  		12:mem12_o  <=   8'h00;
+  		13:mem13_o  <=   8'h00;
+  		14:mem14_o  <=   8'h00;
+  		15:mem15_o  <=   8'h00;
+  		16:mem16_o  <=   8'h00;
+  		17:mem17_o  <=   8'h00;
+  		18:mem18_o  <=   8'h00;
+  		19:mem19_o  <=   8'h00;
+  		20:mem20_o  <=   8'h00;
+  		21:mem21_o  <=   8'h00;
+  		endcase
+              visual_RST_ST_current_o <=   clr_data;
+            end
+            else if (invalid_cmd_i == 1'b0)
+            begin
+              visual_RST_ST_current_o <=   Decod_Cmd_CH1;
+            end
+            else
+              visual_RST_ST_current_o <=   GPIO_cmd_valid;
+          end
+ 
+        I2c_cmd_valid:
+          begin
+            if (invalid_cmd_i == 1'b0)
+            begin
+              up_rw_b_o <=   CMD_i[0];
+              visual_RST_ST_current_o <=   S0cmd3;
+            end
+            else if (invalid_cmd_i == 1'b1)
+            begin
+              
+             case(CH_i[4:0])
+             0:mem0_o   <=   8'h00;
+  		 1:mem1_o   <=   8'h00; 
+  		 2:mem2_o   <=   8'h00;  
+  		 3:mem3_o   <=   8'h00; 
+  		 4:mem4_o   <=   8'h00; 
+  		 5:mem5_o   <=   8'h00; 
+  		 6:mem6_o   <=   8'h00; 
+  		 7:mem7_o   <=   8'h00; 
+  		 8:mem8_o   <=   8'h00; 
+  		 9:mem9_o   <=   8'h00;
+  		10:mem10_o  <=   8'h00;
+  		11:mem11_o  <=   8'h00;
+  		12:mem12_o  <=   8'h00;
+  		13:mem13_o  <=   8'h00;
+  		14:mem14_o  <=   8'h00;
+  		15:mem15_o  <=   8'h00;
+  		16:mem16_o  <=   8'h00;
+  		17:mem17_o  <=   8'h00;
+  		18:mem18_o  <=   8'h00;
+  		19:mem19_o  <=   8'h00;
+  		20:mem20_o  <=   8'h00;
+  		21:mem21_o  <=   8'h00;
+  		endcase
+              visual_RST_ST_current_o <=   clr_data;
+            end
+            else
+              visual_RST_ST_current_o <=   I2c_cmd_valid;
+          end
+ 
+        IntColli:
+          begin
+            if (rx_ena)
+            begin
+              rx_dav_o <=   1'b0;
+              CH_o[7:0] <=   dataw_in[15:8];
+              TR_o[7:0] <=   dataw_in[7:0];
+              visual_RST_ST_current_o <=   tst_busy;
+            end
+            else if (rx_ena == 1'b0)
+            begin
+              
+              TR_o <=   read_mem(Int_arb_in[4:0]);
+              
+              CH_o[7:0] <=   {1'b0,1'b0,Int_arb_in[5:0]};
+              rx_dav_o <=   1'b0;  
+              visual_RST_ST_current_o <=   Int_Ack;
+            end
+            else
+              visual_RST_ST_current_o <=   IntColli;
+          end
+ 
+        Int_Ack:
+          begin
+            if (Int_arb_in == CH_SPI[5:0])
+            begin
+              visual_RST_ST_current_o <=   Sel_CH_spi;
+            end
+            else if (Int_arb_in == CH_GPIO[5:0])
+            begin
+              CH_o <=   8'h02 ; 
+              TR_o <=   8'hff;   
+
+              visual_RST_ST_current_o <=   Rd_Gpio_int0;
+            end
+            else if (Int_arb_in == CH_JTAG[5:0])
+            begin
+              visual_RST_ST_current_o <=   S0_int_jtag;
+            end
+            else if ((Int_arb_in) >= CH_I2C0[5:0] && (CH_I2C15[5:0] >= Int_arb_in))
+            begin
+              visual_RST_ST_current_o <=   S0int_i2c;
+            end
+            else if (Int_arb_in == CH_ADC[5:0])
+            begin
+              visual_RST_ST_current_o <=   S0_int_adc;
+            end
+            else
+              visual_RST_ST_current_o <=   Int_Ack;
+          end
+ 
+        Interr1:
+          begin
+            dataw_out_o[15:0] <=   up_data_in[15:0];
+            visual_RST_ST_current_o <=   ReadData_15_0;
+          end
+ 
+        Jtag_cmd_valid:
+          begin
+            if (invalid_cmd_i == 1'b0)
+            begin
+              visual_RST_ST_current_o <=   Decod_Cmd_CH1;
+            end
+            else if (invalid_cmd_i == 1'b1)
+            begin
+              
+             case(CH_i[4:0])
+             0:mem0_o   <=   8'h00;
+  		 1:mem1_o   <=   8'h00; 
+  		 2:mem2_o   <=   8'h00;  
+  		 3:mem3_o   <=   8'h00; 
+  		 4:mem4_o   <=   8'h00; 
+  		 5:mem5_o   <=   8'h00; 
+  		 6:mem6_o   <=   8'h00; 
+  		 7:mem7_o   <=   8'h00; 
+  		 8:mem8_o   <=   8'h00; 
+  		 9:mem9_o   <=   8'h00;
+  		10:mem10_o  <=   8'h00;
+  		11:mem11_o  <=   8'h00;
+  		12:mem12_o  <=   8'h00;
+  		13:mem13_o  <=   8'h00;
+  		14:mem14_o  <=   8'h00;
+  		15:mem15_o  <=   8'h00;
+  		16:mem16_o  <=   8'h00;
+  		17:mem17_o  <=   8'h00;
+  		18:mem18_o  <=   8'h00;
+  		19:mem19_o  <=   8'h00;
+  		20:mem20_o  <=   8'h00;
+  		21:mem21_o  <=   8'h00;
+  		endcase
+              visual_RST_ST_current_o <=   clr_data;
+            end
+            else
+              visual_RST_ST_current_o <=   Jtag_cmd_valid;
+          end
+ 
+        REPOS:
+          begin
+            if (rx_ena)
+            begin
+              rx_dav_o <=   1'b0;
+              CH_o[7:0] <=   dataw_in[15:8];
+              TR_o[7:0] <=   dataw_in[7:0];
+              visual_RST_ST_current_o <=   tst_busy;
+            end
+            else if (Int_arb_in != 6'b000000)
+            begin
+              rx_dav_o <=   1'b0;
+              visual_RST_ST_current_o <=   delai;
+            end
+            else if ((rx_ena == 1'b0) && (Int_arb_in == 6'b000000))
+            begin
+              visual_RST_ST_current_o <=   REPOS;
+            end
+            else
+              visual_RST_ST_current_o <=   REPOS;
+          end
+ 
+        ReadData:
+          begin
+            dataw_out_o[15:0] <=   up_data_in[15:0];
+            visual_RST_ST_current_o <=   ReadData_15_0;
+          end
+ 
+        ReadData_15_0:
+          begin
+            
+            up_cs_b_o <=   1'b1;
+            up_rw_b_o <=   1'b1;     
+            tx_ena_o <=   1'b0;
+            nc_ready_o <=   1'b1;
+            rx_dav_o <=   1'b1;     
+            invalid_cmd_o <=   1'b0;
+            AckByte_o <=   8'h00;
+            LenRep_o <=   8'h00;
+            visual_RST_ST_current_o <=   REPOS;
+          end
+ 
+        Read_node:
+          begin
+            dataw_out_o[15:8] <=   rep_node_i[7:0];
+            dataw_out_o[7:0] <=   8'h00 ;  
+            visual_RST_ST_current_o <=   Reply_d1_d2;
+          end
+ 
+        Reply_d1_d2:
+          begin
+            
+            up_cs_b_o <=   1'b1;
+            up_rw_b_o <=   1'b1;     
+            tx_ena_o <=   1'b0;
+            nc_ready_o <=   1'b1;
+            rx_dav_o <=   1'b1;     
+            invalid_cmd_o <=   1'b0;
+            AckByte_o <=   8'h00;
+            LenRep_o <=   8'h00;
+            visual_RST_ST_current_o <=   REPOS;
+          end
+ 
+        Rx1_data_sup:
+          begin
+            if (rx_ena == 1'b1)
+            begin
+              visual_RST_ST_current_o <=   Rx1_data_sup;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_NODE))
+            begin
+              LenRep_o <=   8'h03;  
+              visual_RST_ST_current_o <=   Dec_cmd_CH0;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_SPI))
+            begin
+              case (CMD_i)
+                SPI_wrt_TX0,
+                SPI_rea_RX0,
+		SPI_wrt_TX1,
+		SPI_rea_RX1,
+		SPI_wrt_TX2,
+		SPI_rea_RX2,
+		SPI_wrt_TX3,
+		SPI_rea_RX3,
+		SPI_wrt_ctrl,
+		SPI_rea_ctrl,
+		SPI_wrt_DIV,
+		SPI_rea_DIV,
+		SPI_wrt_SS,
+		SPI_rea_SS, 
+		SPI_go: 
+                      invalid_cmd_o <=   1'b0;
+              default:
+                invalid_cmd_o <=   1'b1;
+              endcase
+ 
+              if(CMD_i == SPI_wrt_ctrl)
+                  data_in_tmp_o[12] <=   1'b1;  
+              visual_RST_ST_current_o <=   SPI_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_GPIO))
+            begin
+              case(CMD_i)
+                GPIO_R_DAT_IN,GPIO_W_DAT_OUT,GPIO_R_DAT_OUT,GPIO_W_OE:
+                  invalid_cmd_o <=   1'b0;
+                GPIO_R_WE,GPIO_W_INTE,GPIO_R_INTE,GPIO_W_PTRIG,GPIO_R_PTRIG:
+                  invalid_cmd_o <=   1'b0;
+                GPIO_W_AUX,GPIO_R_AUX,GPIO_W_CTRL,GPIO_R_CTRL,GPIO_W_INTS
+              ,GPIO_R_INTS:
+                   invalid_cmd_o <=   1'b0;
+                GPIO_W_ECLK,GPIO_R_ECLK,GPIO_W_NEC,GPIO_R_NEC:
+                    invalid_cmd_o <=   1'b0;
+ 
+              default:
+                invalid_cmd_o <=   1'b1;
+              endcase
+              visual_RST_ST_current_o <=   GPIO_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && ((CH_i >= CH_I2C0) && (CH_I2C15 >= CH_i )))
+            begin
+              case (CMD_i)
+ 
+               I2C_READ_SRA,I2C_WRITE_MSK,I2C_READ_MSK,I2C_WRITE_CRA
+              ,I2C_READ_CRA:  // commande direct wb reg
+                  invalid_cmd_o <=   1'b0;
+ 
+               I2C_1BYTE_WRITE,I2C_1BYTE_READ,I2C_1BYTE_WRITE_EXT
+              ,I2C_1byte_READ_EXT,I2C_1byte_rmw_OR,I2C_1byte_rmw_XOR,8'hC2:
+              // commande pour i2c-ccu compatib.
+                  invalid_cmd_o <=   1'b0;
+ 
+                 I2C_W_multi_4byte0,I2C_W_multi_4byte1,I2C_W_multi_4byte2 ,
+               I2C_W_multi_4byte3,I2C_write_multi ,I2C_read_multi:
+              // commande multibyte
+                  invalid_cmd_o <=   1'b0;
+ 
+                 I2C_R_multi_4byte0,I2C_R_multi_4byte1,I2C_R_multi_4byte2
+              ,I2C_R_multi_4byte3:
+                   invalid_cmd_o <=   1'b0;
+ 
+                 I2C_write_multi_ext,I2C_read_multi_ext:
+              // commande multi byte mode ext 10 bit addr
+                   invalid_cmd_o <=   1'b0;
+ 
+              default:
+                 invalid_cmd_o <=   1'b1;
+              endcase
+              visual_RST_ST_current_o <=   I2c_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_DAC))
+            begin
+              case (CMD_i)
+                DAC_W_CH1,DAC_R_CH1,DAC_W_CH2,DAC_R_CH2,DAC_W_CH3,DAC_R_CH3
+              ,DAC_W_CH4,DAC_R_CH4:
+                invalid_cmd_o <=   1'b0;
+              default:
+                invalid_cmd_o <=   1'b1;
+              endcase
+              visual_RST_ST_current_o <=   DAC_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_JTAG))
+            begin
+              case (CMD_i)
+                     JTG_w_TDO_tx0,
+                     JTG_r_TDI_rx0,
+                     JTG_w_TDO_tx1,
+                     JTG_r_TDI_rx1,
+                     JTG_w_TDO_tx2,
+                     JTG_r_TDI_rx2,
+                     JTG_w_TDO_tx3,
+                     JTG_r_TDI_rx3,
+                     JTG_w_TMS_tx0,
+                     JTG_r_TMS_tx0,
+                     JTG_w_TMS_tx1,
+                     JTG_r_TMS_tx1,
+                     JTG_w_TMS_tx2,
+                     JTG_r_TMS_tx2,
+                     JTG_w_TMS_tx3,
+                     JTG_r_TMS_tx3,
+                     JTG_w_ctrl,
+                     JTG_r_crtl,
+                     JTG_w_div,
+                     JTG_r_div,
+                     JTG_go_auto,
+                     JTG_go_manual,
+                     JTAG_status,
+		     JTAG_RES, 
+		     SEU_read,  
+		     SEU_clear:
+                     invalid_cmd_o <=   1'b0;
+                default:
+                  invalid_cmd_o <=   1'b1;
+              endcase
+              if(CMD_i == JTG_w_ctrl)
+                   data_in_tmp1_o[12] <=   1'b1;
+              
+              visual_RST_ST_current_o <=   Jtag_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_ADC))
+            begin
+              case(CMD_i)
+                     ADC_GO,      
+                     ADC_W_MUX,    
+                     ADC_R_MUX,    
+                     ADC_W_GAIN,   
+                     ADC_R_GAIN,   
+                     ADC_R_ID,     
+                     ADC_W_CURR,  
+                     ADC_R_CURR,   
+                     ADC_R_DATA,   
+                     ADC_R_CTRL,   
+                     ADC_R_CWD,    
+                     ADC_R_OFFSET, 
+                     FUSE_W_ID,    
+                     FUSE_R_ID,   
+                     FUSE_W_GAIN,  
+                     FUSE_R_GAIN:
+                   invalid_cmd_o <=   1'b0;
+ 
+ 
+              default:
+                 invalid_cmd_o <=   1'b1;
+              endcase
+              visual_RST_ST_current_o <=   ADC_cmd_valid;
+            end
+            else
+              visual_RST_ST_current_o <=   Rx1_data_sup;
+          end
+ 
+        Rx_Data:
+          begin
+            if (rx_ena == 1'b1)
+            begin
+              
+              visual_RST_ST_current_o <=   Rx1_data_sup;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_NODE))
+            begin
+              LenRep_o <=   8'h03;  
+              visual_RST_ST_current_o <=   Dec_cmd_CH0;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_SPI))
+            begin
+              case (CMD_i)
+                SPI_wrt_TX0,
+                SPI_rea_RX0,
+		SPI_wrt_TX1,
+		SPI_rea_RX1,
+		SPI_wrt_TX2,
+		SPI_rea_RX2,
+		SPI_wrt_TX3,
+		SPI_rea_RX3,
+		SPI_wrt_ctrl,
+		SPI_rea_ctrl,
+		SPI_wrt_DIV,
+		SPI_rea_DIV,
+		SPI_wrt_SS,
+		SPI_rea_SS, 
+		SPI_go: 
+                      invalid_cmd_o <=   1'b0;
+              default:
+                invalid_cmd_o <=   1'b1;
+              endcase
+ 
+              if(CMD_i == SPI_wrt_ctrl)
+                  data_in_tmp_o[12] <=   1'b1;  
+              visual_RST_ST_current_o <=   SPI_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_GPIO))
+            begin
+              case(CMD_i)
+                GPIO_R_DAT_IN,GPIO_W_DAT_OUT,GPIO_R_DAT_OUT,GPIO_W_OE:
+                  invalid_cmd_o <=   1'b0;
+                GPIO_R_WE,GPIO_W_INTE,GPIO_R_INTE,GPIO_W_PTRIG,GPIO_R_PTRIG:
+                  invalid_cmd_o <=   1'b0;
+                GPIO_W_AUX,GPIO_R_AUX,GPIO_W_CTRL,GPIO_R_CTRL,GPIO_W_INTS,GPIO_R_INTS:
+                   invalid_cmd_o <=   1'b0;
+                GPIO_W_ECLK,GPIO_R_ECLK,GPIO_W_NEC,GPIO_R_NEC:
+                    invalid_cmd_o <=   1'b0;
+ 
+              default:
+                invalid_cmd_o <=   1'b1;
+              endcase
+              visual_RST_ST_current_o <=   GPIO_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && ((CH_i >= CH_I2C0) && (CH_I2C15 >= CH_i)))
+            begin
+              case (CMD_i)
+ 
+               I2C_READ_SRA,I2C_WRITE_MSK,I2C_READ_MSK,I2C_WRITE_CRA
+              ,I2C_READ_CRA:  // commande direct wb reg
+                  invalid_cmd_o <=   1'b0;
+ 
+               I2C_1BYTE_WRITE,I2C_1BYTE_READ,I2C_1BYTE_WRITE_EXT
+              ,I2C_1byte_READ_EXT,I2C_1byte_rmw_OR,I2C_1byte_rmw_XOR,8'hC2:
+              // commande pour i2c-ccu compatib.
+                  invalid_cmd_o <=   1'b0;
+ 
+                 I2C_W_multi_4byte0,I2C_W_multi_4byte1,I2C_W_multi_4byte2 ,
+               I2C_W_multi_4byte3,I2C_write_multi ,I2C_read_multi:
+              // commande multibyte
+                  invalid_cmd_o <=   1'b0;
+ 
+                 I2C_R_multi_4byte0,I2C_R_multi_4byte1,I2C_R_multi_4byte2
+              ,I2C_R_multi_4byte3:
+                   invalid_cmd_o <=   1'b0;
+ 
+                 I2C_write_multi_ext,I2C_read_multi_ext:
+              // commande multi byte mode ext 10 bit addr
+                   invalid_cmd_o <=   1'b0;
+ 
+              default:
+                 invalid_cmd_o <=   1'b1;
+              endcase
+              visual_RST_ST_current_o <=   I2c_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_DAC))
+            begin
+              case (CMD_i)
+                DAC_W_CH1,DAC_R_CH1,DAC_W_CH2,DAC_R_CH2,DAC_W_CH3,DAC_R_CH3
+              ,DAC_W_CH4,DAC_R_CH4:
+                invalid_cmd_o <=   1'b0;
+              default:
+                invalid_cmd_o <=   1'b1;
+              endcase
+              visual_RST_ST_current_o <=   DAC_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_JTAG))
+            begin
+              case (CMD_i)
+                     JTG_w_TDO_tx0,
+                     JTG_r_TDI_rx0,
+                     JTG_w_TDO_tx1,
+                     JTG_r_TDI_rx1,
+                     JTG_w_TDO_tx2,
+                     JTG_r_TDI_rx2,
+                     JTG_w_TDO_tx3,
+                     JTG_r_TDI_rx3,
+                     JTG_w_TMS_tx0,
+                     JTG_r_TMS_tx0,
+                     JTG_w_TMS_tx1,
+                     JTG_r_TMS_tx1,
+                     JTG_w_TMS_tx2,
+                     JTG_r_TMS_tx2,
+                     JTG_w_TMS_tx3,
+                     JTG_r_TMS_tx3,
+                     JTG_w_ctrl,
+                     JTG_r_crtl,
+                     JTG_w_div,
+                     JTG_r_div,
+                     JTG_go_auto,
+                     JTG_go_manual,
+                     JTAG_status,
+		     JTAG_RES, 
+		     SEU_read,  
+		     SEU_clear:
+                     invalid_cmd_o <=   1'b0;
+                default:
+                     invalid_cmd_o <=   1'b1;
+              endcase
+              if(CMD_i == JTG_w_ctrl)
+                   data_in_tmp1_o[12] <=   1'b1;
+              
+              visual_RST_ST_current_o <=   Jtag_cmd_valid;
+            end
+            else if ((rx_ena == 1'b0) && (CH_i == CH_ADC))
+            begin
+              case(CMD_i)
+                     ADC_GO,      
+                     ADC_W_MUX,    
+                     ADC_R_MUX,    
+                     ADC_W_GAIN,   
+                     ADC_R_GAIN,   
+                     ADC_R_ID,     
+                     ADC_W_CURR,  
+                     ADC_R_CURR,   
+                     ADC_R_DATA,   
+                     ADC_R_CTRL,   
+                     ADC_R_CWD,    
+                     ADC_R_OFFSET, 
+                     FUSE_W_ID,    
+                     FUSE_R_ID,   
+                     FUSE_W_GAIN,  
+                     FUSE_R_GAIN: 
+                   invalid_cmd_o <=   1'b0;
+ 
+              default:
+                 invalid_cmd_o <=   1'b1;
+              endcase
+              visual_RST_ST_current_o <=   ADC_cmd_valid;
+            end
+            else
+              visual_RST_ST_current_o <=   Rx_Data;
+          end
+ 
+        Rx_word2:
+          begin
+            
+            if ((read_mem(CH_i[4:0]) == 8'h00) && (Num_Max_CH >= CH_i) && (EN_ch_reg_i[CH_i[4:0]] == 1'b1) && (TR_i != 8'h00) && (TR_i != 8'hff))
+            begin
+              
+              case(CH_i[4:0])
+              0:mem0_o   <=   TR_i; 
+  		  1:mem1_o   <=   TR_i; 
+  		  2:mem2_o   <=   TR_i; 
+  		  3:mem3_o   <=   TR_i; 
+  		  4:mem4_o   <=   TR_i;
+  		  5:mem5_o   <=   TR_i; 
+  		  6:mem6_o   <=   TR_i; 
+  		  7:mem7_o   <=   TR_i;  
+  		  8:mem8_o   <=   TR_i; 
+  		  9:mem9_o   <=   TR_i; 
+  		 10:mem10_o  <=   TR_i; 
+  		 11:mem11_o  <=   TR_i; 
+  		 12:mem12_o  <=   TR_i; 
+  		 13:mem13_o  <=   TR_i; 
+  		 14:mem14_o  <=   TR_i; 
+  		 15:mem15_o  <=   TR_i; 
+  		 16:mem16_o  <=   TR_i; 
+  		 17:mem17_o  <=   TR_i; 
+  		 18:mem18_o  <=   TR_i; 
+  		 19:mem19_o  <=   TR_i; 
+  		 20:mem20_o  <=   TR_i; 
+  		 21:mem21_o  <=   TR_i;
+  		 endcase 
+              SRB_o <=   TR_i;   
+              data_in_tmp_o <=   dataw_in;
+              visual_RST_ST_current_o <=   CMD_ACCEPT;
+            end
+            
+            else if ((read_mem(CH_i[4:0])!= 8'h00) || (CH_i > Num_Max_CH) || (EN_ch_reg_i[CH_i[4:0]] == 1'b0) || (TR_i == 8'h00) || (TR_i == 8'hff))
+            begin
+              visual_RST_ST_current_o <=   clr_data;
+            end
+            else
+              visual_RST_ST_current_o <=   Rx_word2;
+          end
+ 
+        S28:
+          begin
+            dataw_out_o[15:8] <=   LenRep_i[7:0];    
+            dataw_out_o[7:0]  <=   AckByte_i;
+            
+            visual_RST_ST_current_o <=   Read_node;
+          end
+ 
+        S41:
+          begin
+            if (rx_ena == 1'b0)
+            begin
+              visual_RST_ST_current_o <=   IntColli;
+            end
+            else if (rx_ena)
+            begin
+              rx_dav_o <=   1'b0;
+              CH_o[7:0] <=   dataw_in[15:8];
+              TR_o[7:0] <=   dataw_in[7:0];
+              visual_RST_ST_current_o <=   tst_busy;
+            end
+            else
+              visual_RST_ST_current_o <=   S41;
+          end
+ 
+        S46csb0:
+          begin
+            visual_RST_ST_current_o <=   S48busy1;
+          end
+ 
+        S47csb1:
+          begin
+            
+            nc_ready_o <=   1'b0;
+            visual_RST_ST_current_o <=   BUSY_STATE;
+          end
+ 
+        S48busy1:
+          begin
+            if (up_busy_in == 1'b1)
+            begin
+              visual_RST_ST_current_o <=   S48busy1;
+            end
+            else if (up_busy_in == 1'b0)
+            begin
+              up_cs_b_o <=   1'b1;
+              visual_RST_ST_current_o <=   S47csb1;
+            end
+            else
+              visual_RST_ST_current_o <=   S48busy1;
+          end
+ 
+        SPI_cmd_valid:
+          begin
+            if (invalid_cmd_i == 1'b1)
+            begin
+              
+              case(CH_i[4:0])
+             0:mem0_o   <=   8'h00;
+  		 1:mem1_o   <=   8'h00; 
+  		 2:mem2_o   <=   8'h00;  
+  		 3:mem3_o   <=   8'h00; 
+  		 4:mem4_o   <=   8'h00; 
+  		 5:mem5_o   <=   8'h00; 
+  		 6:mem6_o   <=   8'h00; 
+  		 7:mem7_o   <=   8'h00; 
+  		 8:mem8_o   <=   8'h00; 
+  		 9:mem9_o   <=   8'h00;
+  		10:mem10_o  <=   8'h00;
+  		11:mem11_o  <=   8'h00;
+  		12:mem12_o  <=   8'h00;
+  		13:mem13_o  <=   8'h00;
+  		14:mem14_o  <=   8'h00;
+  		15:mem15_o  <=   8'h00;
+  		16:mem16_o  <=   8'h00;
+  		17:mem17_o  <=   8'h00;
+  		18:mem18_o  <=   8'h00;
+  		19:mem19_o  <=   8'h00;
+  		20:mem20_o  <=   8'h00;
+  		21:mem21_o  <=   8'h00;
+  		endcase
+              visual_RST_ST_current_o <=   clr_data;
+            end
+            else if (invalid_cmd_i == 1'b0)
+            begin
+              visual_RST_ST_current_o <=   Decod_Cmd_CH1;
+            end
+            else
+              visual_RST_ST_current_o <=   SPI_cmd_valid;
+          end
+ 
+        Send2Ack:
+          begin
+            if (TR_i == 8'hff)
+            begin
+              dataw_out_o[15:0] <=   up_data_in[31:16];
+              visual_RST_ST_current_o <=   Interr1;
+            end
+            else if (CMD_i[0] == 1'b0)
+            begin
+              
+              up_cs_b_o <=   1'b1;
+              up_rw_b_o <=   1'b1;     
+              tx_ena_o <=   1'b0;
+              nc_ready_o <=   1'b1;
+              rx_dav_o <=   1'b1;     
+              invalid_cmd_o <=   1'b0;
+              AckByte_o <=   8'h00;
+              LenRep_o <=   8'h00;
+              visual_RST_ST_current_o <=   REPOS;
+            end
+            else if (CMD_i[0] == 1'b1)
+            begin
+              dataw_out_o[15:0] <=   up_data_in[31:16] ;
+              visual_RST_ST_current_o <=   ReadData;
+            end
+            else
+              visual_RST_ST_current_o <=   Send2Ack;
+          end
+ 
+        clr_data:
+          begin
+            if (rx_ena == 1'b1)
+            begin
+              visual_RST_ST_current_o <=   clr_data;
+            end
+            else if (rx_ena == 1'b0)
+            begin
+              if (CH_i > Num_Max_CH) AckByte_o[Inv_CH] <=   1'b1;
+              else
+              begin  
+                if(read_mem(CH_i[4:0]) != 8'h00)   AckByte_o[CH_Busy] <=   1'b1;
+                if(EN_ch_reg_i[CH_i[4:0]] == 1'b0) AckByte_o[CH_dis] <=   1'b1;
+              end
+              if(invalid_cmd_i == 1'b1) AckByte_o[Inv_Cmd]  <=   1'b1;
+              LenRep_o <=   8'h02;  
+              if ((TR_i == 8'h00) || (TR_i == 8'hff))
+                AckByte_o[Inv_TR] <=   1'b1;
+              visual_RST_ST_current_o <=   CH_errors;
+            end
+            else
+              visual_RST_ST_current_o <=   clr_data;
+          end
+ 
+        delai:
+          begin
+            if (rx_ena)
+            begin
+              rx_dav_o <=   1'b0;
+              CH_o[7:0] <=   dataw_in[15:8];
+              TR_o[7:0] <=   dataw_in[7:0];
+              visual_RST_ST_current_o <=   tst_busy;
+            end
+            else if (rx_ena == 1'b0)
+            begin
+              visual_RST_ST_current_o <=   S41;
+            end
+            else
+              visual_RST_ST_current_o <=   delai;
+          end
+ 
+        tst_busy:
+          begin
+            CMD_o[7:0] <=   dataw_in[15:8];
+            LEN_o[7:0] <=   dataw_in[7:0];
+            visual_RST_ST_current_o <=   Rx_word2;
+          end
+ 
+        tx_dav_ok:
+          begin
+            if (CH_i == CH_NODE)
+            begin
+              
+              case(CH_i[4:0])
+             0:mem0_o   <=   8'h00;
+  		 1:mem1_o   <=   8'h00; 
+  		 2:mem2_o   <=   8'h00;  
+  		 3:mem3_o   <=   8'h00; 
+  		 4:mem4_o   <=   8'h00; 
+  		 5:mem5_o   <=   8'h00; 
+  		 6:mem6_o   <=   8'h00; 
+  		 7:mem7_o   <=   8'h00; 
+  		 8:mem8_o   <=   8'h00; 
+  		 9:mem9_o   <=   8'h00;
+  		10:mem10_o  <=   8'h00;
+  		11:mem11_o  <=   8'h00;
+  		12:mem12_o  <=   8'h00;
+  		13:mem13_o  <=   8'h00;
+  		14:mem14_o  <=   8'h00;
+  		15:mem15_o  <=   8'h00;
+  		16:mem16_o  <=   8'h00;
+  		17:mem17_o  <=   8'h00;
+  		18:mem18_o  <=   8'h00;
+  		19:mem19_o  <=   8'h00;
+  		20:mem20_o  <=   8'h00;
+  		21:mem21_o  <=   8'h00;
+  		endcase
+              dataw_out_o[15:8] <=   LenRep_i[7:0];    
+              dataw_out_o[7:0]  <=   AckByte_i;
+              
+              visual_RST_ST_current_o <=   Read_node;
+            end
+            else
+            begin
+              
+              if(( CH_i >= CH_I2C0 ) && (CH_I2C15 >= CH_i))
+                   dataw_out_o[15:8] <=   8'h02;
+              else
+                   dataw_out_o[15:8] <=   8'h06;
+              dataw_out_o[7:0] <=   AckByte_i ; 
+              
+              case(CH_i[4:0])
+             0:mem0_o   <=   8'h00;
+  		 1:mem1_o   <=   8'h00; 
+  		 2:mem2_o   <=   8'h00;  
+  		 3:mem3_o   <=   8'h00; 
+  		 4:mem4_o   <=   8'h00; 
+  		 5:mem5_o   <=   8'h00; 
+  		 6:mem6_o   <=   8'h00; 
+  		 7:mem7_o   <=   8'h00; 
+  		 8:mem8_o   <=   8'h00; 
+  		 9:mem9_o   <=   8'h00;
+  		10:mem10_o  <=   8'h00;
+  		11:mem11_o  <=   8'h00;
+  		12:mem12_o  <=   8'h00;
+  		13:mem13_o  <=   8'h00;
+  		14:mem14_o  <=   8'h00;
+  		15:mem15_o  <=   8'h00;
+  		16:mem16_o  <=   8'h00;
+  		17:mem17_o  <=   8'h00;
+  		18:mem18_o  <=   8'h00;
+  		19:mem19_o  <=   8'h00;
+  		20:mem20_o  <=   8'h00;
+  		21:mem21_o  <=   8'h00;
+  		endcase
+              visual_RST_ST_current_o <=   Send2Ack;
+            end
+          end
+ 
+        Sel_CH_spi:
+          begin
+            up_rw_b_o <=   1'b1; 
+            
+            up_addr_o <=   {16'h0000,1'b0,CH_i[7:0],7'b0000000};
+            
+            
+            visual_RST_ST_current_o <=   Read_Wish;
+          end
+ 
+        Read_Wish:
+          begin
+            up_cs_b_o <=   1'b0;
+            CMD_o[0] <=   1'b1;
+            visual_RST_ST_current_o <=   S46csb0;
+          end
+ 
+        S0_int_adc:
+          begin
+            
+            up_rw_b_o <=   1'b1; 
+            up_addr_o <=   {16'h0000,1'b0,CH_i[7:0],1'b0,ADC_R_DATA[7:2]};
+            visual_RST_ST_current_o <=   S3_int_adc;
+          end
+ 
+        S3_int_adc:
+          begin
+            up_cs_b_o <=   1'b0;
+            CMD_o[0] <=   1'b1;
+            visual_RST_ST_current_o <=   S46csb0;
+          end
+ 
+        Dec_cmd_CH0:
+          begin
+            if (CMD_i == NC_Write_CRD)
+            begin
+              CRD_o[7:0] <=   data_in_tmp_i[15:8];
+              EN_ch_reg_o[23:16] <=   data_in_tmp_i[15:8];
+              if(~data_in_tmp_i[8])  mem16_o <= 8'h0; //i2c13
+              if(~data_in_tmp_i[9])  mem17_o <= 8'h0; //i2c14
+              if(~data_in_tmp_i[10]) mem18_o <= 8'h0; //i2c15
+              if(~data_in_tmp_i[11]) mem19_o <= 8'h0; //jtag
+              if(~data_in_tmp_i[12]) mem20_o <= 8'h0; //adc
+              if(~data_in_tmp_i[13]) mem21_o <= 8'h0; //dac
+              visual_RST_ST_current_o <=   Wr_CRD;
+            end
+            else if (CMD_i == NC_Read_CRA)
+            begin
+              rep_node_o <=   CRA_i;
+              visual_RST_ST_current_o <=   Rd_CRA;
+            end
+            else if (CMD_i == NC_Write_CRA)
+            begin
+              CRA_o[7:0] <=   data_in_tmp_i[15:8];
+              rep_node_o <=   8'h00;
+              visual_RST_ST_current_o <=   Wr_CRA;
+            end
+            else if (CMD_i == NC_Write_CRB)
+            begin
+              CRB_o[7:0] <=   data_in_tmp_i[15:8];
+              EN_ch_reg_o[7:0] <=   {data_in_tmp_i[15:9],1'b1};
+              if(~data_in_tmp_i[9])  mem1_o <= 8'h0; //spi
+              if(~data_in_tmp_i[10]) mem2_o <= 8'h0; //gpio
+              if(~data_in_tmp_i[11]) mem3_o <= 8'h0; //i2c0
+              if(~data_in_tmp_i[12]) mem4_o <= 8'h0; //i2c1
+              if(~data_in_tmp_i[13]) mem5_o <= 8'h0; //i2c2
+              if(~data_in_tmp_i[14]) mem6_o <= 8'h0; //i2c3
+              if(~data_in_tmp_i[15]) mem7_o <= 8'h0; //i2c4
+
+              visual_RST_ST_current_o <=   Wr_CRB;
+            end
+            else if (CMD_i == NC_Read_CRB)
+            begin
+            
+              rep_node_o <=   CRB_i;
+              visual_RST_ST_current_o <=   Rd_CRB;
+            end
+            else if (CMD_i == NC_Write_CRC)
+            begin
+              CRC_o[7:0] <=   data_in_tmp_i[15:8];
+              EN_ch_reg_o[15:8] <=   data_in_tmp_i[15:8];
+              if(~data_in_tmp_i[8])  mem8_o  <= 8'h0; //i2c5
+              if(~data_in_tmp_i[9])  mem9_o  <= 8'h0; //i2c6
+              if(~data_in_tmp_i[10]) mem10_o <= 8'h0; //i2c7
+              if(~data_in_tmp_i[11]) mem11_o <= 8'h0; //i2c8
+              if(~data_in_tmp_i[12]) mem12_o <= 8'h0; //i2c9
+              if(~data_in_tmp_i[13]) mem13_o <= 8'h0; //i2c10
+              if(~data_in_tmp_i[14]) mem14_o <= 8'h0; //i2c11
+              if(~data_in_tmp_i[15]) mem15_o <= 8'h0; //i2c12
+              visual_RST_ST_current_o <=   Wr_CRC;
+            end
+            else if (CMD_i == NC_Read_CRC)
+            begin
+              rep_node_o <=   CRC_i;
+              visual_RST_ST_current_o <=   Rd_CRC;
+            end
+            else if (CMD_i == NC_Read_CRD)
+            begin
+              rep_node_o <=   CRD_i;
+              visual_RST_ST_current_o <=   Rd_CRD;
+            end
+            else if (CMD_i > NC_Read_CRE)
+            begin
+              AckByte_o[Inv_Cmd] <=    1'b1;   
+              visual_RST_ST_current_o <=   NC_invalid;
+            end
+            else if (CMD_i == NC_Write_CRE)
+            begin
+              CRE_o[7:0] <=   data_in_tmp_i[15:8];
+              visual_RST_ST_current_o <=   Wr_CRE;
+            end
+            else if (CMD_i == NC_Read_CRE)
+            begin
+              rep_node_o <=   CRE_i;
+              visual_RST_ST_current_o <=   Rd_CRE;
+            end
+            else
+              visual_RST_ST_current_o <=   Dec_cmd_CH0;
+          end
+ 
+        NC_invalid:
+          begin
+            
+            nc_ready_o <=   1'b0;
+            visual_RST_ST_current_o <=   BUSY_STATE;
+          end
+ 
+        Rd_CRA:
+          begin
+            
+            nc_ready_o <=   1'b0;
+            visual_RST_ST_current_o <=   BUSY_STATE;
+          end
+ 
+        Rd_CRB:
+          begin
+            
+            nc_ready_o <=   1'b0;
+            visual_RST_ST_current_o <=   BUSY_STATE;
+          end
+ 
+        Rd_CRC:
+          begin
+            
+            nc_ready_o <=   1'b0;
+            visual_RST_ST_current_o <=   BUSY_STATE;
+          end
+ 
+        Rd_CRD:
+          begin
+            
+            nc_ready_o <=   1'b0;
+            visual_RST_ST_current_o <=   BUSY_STATE;
+          end
+ 
+        Rd_CRE:
+          begin
+            
+            nc_ready_o <=   1'b0;
+            visual_RST_ST_current_o <=   BUSY_STATE;
+          end
+ 
+        Wr_CRA:
+          begin
+            
+            nc_ready_o <=   1'b0;
+            visual_RST_ST_current_o <=   BUSY_STATE;
+          end
+ 
+        Wr_CRB:
+          begin
+            
+            nc_ready_o <=   1'b0;
+            visual_RST_ST_current_o <=   BUSY_STATE;
+          end
+ 
+        Wr_CRC:
+          begin
+            
+            nc_ready_o <=   1'b0;
+            visual_RST_ST_current_o <=   BUSY_STATE;
+          end
+ 
+        Wr_CRD:
+          begin
+            
+            nc_ready_o <=   1'b0;
+            visual_RST_ST_current_o <=   BUSY_STATE;
+          end
+ 
+        Wr_CRE:
+          begin
+            
+            nc_ready_o <=   1'b0;
+            visual_RST_ST_current_o <=   BUSY_STATE;
+          end
+ 
+        Decod_Cmd_CH1:
+          begin
+            up_rw_b_o <=   CMD_i[0];      
+            up_data_out_o <=   {data_in_tmp_i,data_in_tmp1_i};
+            
+            up_addr_o <=  {16'h0000,1'b0,CH_i[7:0],1'b0,CMD_i[7:2]};
+            visual_RST_ST_current_o <=   write_up;
+          end
+ 
+        CS_bas:
+          begin
+            visual_RST_ST_current_o <=   S9;
+          end
+ 
+        S10:
+          begin
+            if (CMD_i[1] == 1'b0)
+            begin
+              
+              nc_ready_o <=   1'b0;
+              visual_RST_ST_current_o <=   BUSY_STATE;
+            end
+            else if (CMD_i[1] == 1'b1)
+            begin
+              
+              up_cs_b_o <=   1'b1;
+              up_rw_b_o <=   1'b1;     
+              tx_ena_o <=   1'b0;
+              nc_ready_o <=   1'b1;
+              rx_dav_o <=   1'b1;     
+              invalid_cmd_o <=   1'b0;
+              AckByte_o <=   8'h00;
+              LenRep_o <=   8'h00;
+              visual_RST_ST_current_o <=   REPOS;
+            end
+            else
+            begin
+              visual_RST_ST_current_o <=   Decod_Cmd_CH1;
+            end
+          end
+ 
+        S9:
+          begin
+            if (up_busy_in == 1'b1)
+            begin
+              visual_RST_ST_current_o <=   S9;
+            end
+            else if (up_busy_in == 1'b0)
+            begin
+              visual_RST_ST_current_o <=   S10;
+            end
+            else
+              visual_RST_ST_current_o <=   S9;
+          end
+ 
+        write_up:
+          begin
+            up_cs_b_o <=   1'b0;  
+            visual_RST_ST_current_o <=   CS_bas;
+          end
+ 
+        S0cmd3:
+          begin
+            if ((CMD_i[0] || !(CMD_i[0])) && CMD_i[7])
+            begin
+              up_data_out_o[15:0] <=   {data_in_tmp_i[7:0],data_in_tmp1_i[15:8]};
+              up_data_out_o[31:16] <=   {1'b0,1'b0,1'b0,CMD_i[6],CMD_i[5],CMD_i[4],CMD_i[3],CMD_i[2],(data_in_tmp_i[15:8])};
+              
+              
+              up_addr_o <=   {16'h0000,1'b0,CH_i[7:0],7'b0000000};
+              visual_RST_ST_current_o <=   S3cmd3;
+            end
+            else if (CMD_i[0] && !(CMD_i[7]))
+            begin
+              
+              
+              up_addr_o <=  {16'h0000,1'b0,CH_i[7:0],1'b0,CMD_i[7:2]};
+              visual_RST_ST_current_o <=   S6cmd3_Read;
+            end
+            else if (!(CMD_i[7]))
+            begin
+              
+              up_data_out_o <=   {data_in_tmp_i,data_in_tmp1_i};
+              
+              up_addr_o <=   {16'h0000,1'b0,CH_i[7:0],1'b0,CMD_i[7:2]} ;
+              visual_RST_ST_current_o <=   cmd3_write;
+            end
+            else
+              visual_RST_ST_current_o <=   S0cmd3;
+          end
+ 
+        S10_cs_0:
+          begin
+            if (CMD_i[1] == 1'b1)
+            begin
+              
+              up_cs_b_o <=   1'b1;
+              up_rw_b_o <=   1'b1;     
+              tx_ena_o <=   1'b0;
+              nc_ready_o <=   1'b1;
+              rx_dav_o <=   1'b1;     
+              invalid_cmd_o <=   1'b0;
+              AckByte_o <=   8'h00;
+              LenRep_o <=   8'h00;
+              visual_RST_ST_current_o <=   REPOS;
+            end
+            else if (CMD_i[1] == 1'b0)
+            begin
+              
+              nc_ready_o <=   1'b0;
+              visual_RST_ST_current_o <=   BUSY_STATE;
+            end
+            else
+            begin
+              up_rw_b_o <=   CMD_i[0];
+              visual_RST_ST_current_o <=   S0cmd3;
+            end
+          end
+ 
+        S3cmd3:
+          begin
+            up_cs_b_o <=   1'b0;  
+            visual_RST_ST_current_o <=   S4cmd3;
+          end
+ 
+        S4cmd3:
+          begin
+            visual_RST_ST_current_o <=   S7_addten;
+          end
+ 
+        S6cmd3_Read:
+          begin
+            up_cs_b_o <=   1'b0;  
+            visual_RST_ST_current_o <=   S4cmd3;
+          end
+ 
+        S7_addten:
+          begin
+            if (up_busy_in == 1'b1)
+            begin
+              visual_RST_ST_current_o <=   S7_addten;
+            end
+            else if (up_busy_in == 1'b0)
+            begin
+              up_cs_b_o <=   1'b1;
+              visual_RST_ST_current_o <=   S10_cs_0;
+            end
+            else
+              visual_RST_ST_current_o <=   S7_addten;
+          end
+ 
+        cmd3_write:
+          begin
+            up_cs_b_o <=   1'b0;  
+            visual_RST_ST_current_o <=   S4cmd3;
+          end
+ 
+        Rd_Gpio_int0:
+          begin
+            up_rw_b_o <=   1'b1;      
+            
+            up_addr_o <=    {24'h000001,8'h1c};
+            visual_RST_ST_current_o <=   Rd_Gpio_int1;
+          end
+ 
+        Gpio_wr_wait:
+          begin
+            if (up_busy_in == 1'b1)
+            begin
+              visual_RST_ST_current_o <=   Gpio_wr_wait;
+            end
+            else if (up_busy_in == 1'b0)
+            begin
+              
+              nc_ready_o <=   1'b0;
+              visual_RST_ST_current_o <=   BUSY_STATE;
+            end
+            else
+              visual_RST_ST_current_o <=   Gpio_wr_wait;
+          end
+ 
+        Rd_Gpio_int1:
+          begin
+            up_cs_b_o <=   1'b0;  
+            visual_RST_ST_current_o <=   Rd_Gpio_int2;
+          end
+ 
+        Rd_Gpio_int2:
+          begin
+            visual_RST_ST_current_o <=   Rd_Gpio_int3;
+          end
+ 
+        Rd_Gpio_int3:
+          begin
+            if (up_busy_in == 1'b1)
+            begin
+              visual_RST_ST_current_o <=   Rd_Gpio_int3;
+            end
+            else if (up_busy_in == 1'b0)
+            begin
+              
+              up_cs_b_o <=   1'b1;
+              up_rw_b_o <=   1'b0;  
+              up_data_out_o <=   32'h00000000;    
+              visual_RST_ST_current_o <=   Rd_Gpio_int4;
+            end
+            else
+              visual_RST_ST_current_o <=   Rd_Gpio_int3;
+          end
+ 
+        Rd_Gpio_int4:
+          begin
+            up_cs_b_o <=   1'b0;
+            visual_RST_ST_current_o <=   Rd_Gpio_int5;
+          end
+ 
+        Rd_Gpio_int5:
+          begin
+            visual_RST_ST_current_o <=   Gpio_wr_wait;
+          end
+ 
+        S0int_i2c:
+          begin
+            up_rw_b_o <=   1'b1; 
+            
+            up_addr_o <=     {16'h0000,1'b0,CH_i[7:0],7'b0000100};
+            
+            visual_RST_ST_current_o <=   S1int_i2c;
+          end
+ 
+        S1int_i2c:
+          begin
+            up_cs_b_o <=   1'b0;
+            CMD_o[0] <=   1'b1;
+            visual_RST_ST_current_o <=   S46csb0;
+          end
+ 
+        S0_int_jtag:
+          begin
+            up_rw_b_o <=   1'b1;
+            up_addr_o <=   {16'h0000,1'b0,CH_i[7:0],7'b0000000};  
+            
+            visual_RST_ST_current_o <=   S3_int_jtag;
+          end
+ 
+        S3_int_jtag:
+          begin
+            up_cs_b_o <=   1'b0;
+            CMD_o[0] <=   1'b1;
+            visual_RST_ST_current_o <=   S46csb0;
+          end
+ 
+        default:
+          begin
+            
+            
+            rx_dav_o <=   1'b0;
+            tx_ena_o <=   1'b0;
+            dataw_out_o <=   16'h0000;
+            SRA_o <=   8'h00;
+            SRB_o <=   8'h00;
+            CRA_o <=   8'h00;
+            CRB_o <=   8'h00;
+            CRC_o <=   8'h00;
+            CRD_o <=   8'h00;
+            CRE_o <=   8'h00;
+           
+            EN_ch_reg_o <=   32'h00000001;
+            AckByte_o <=   8'h00;
+            LenRep_o <=   8'h00;
+            
+            TR_o <=   8'h00;
+            CH_o <=   8'h00;
+            CMD_o <=   8'h00;
+            LEN_o <=   8'h00;
+            up_addr_o <=   32'h00000000;
+            rep_node_o <=   8'h00;
+            SPI_CTRL_o <=   16'h0000;
+            nc_ready_o <=   1'b0;
+            data_in_tmp_o <=   16'h0000;
+            data_in_tmp1_o <=   16'h0000;
+            invalid_cmd_o <=   1'b0;
+            up_cs_b_o <=   1'b1;
+            up_rw_b_o <=   1'b0;
+            up_data_out_o <=   32'h00000000;
+            
+            mem0_o  <=   8'h00;  
+            mem1_o  <=   8'h00;
+            mem2_o  <=   8'h00;  
+            mem3_o  <=   8'h00;
+            mem4_o  <=   8'h00;  
+            mem5_o  <=   8'h00;
+            mem6_o  <=   8'h00;  
+            mem7_o  <=   8'h00;
+            mem8_o  <=   8'h00;  
+            mem9_o  <=   8'h00;
+            mem10_o <=   8'h00; 
+            mem11_o <=   8'h00;
+            mem12_o <=   8'h00;  
+            mem13_o <=   8'h00;
+            mem14_o <=   8'h00;  
+            mem15_o <=   8'h00;
+            mem16_o <=   8'h00;  
+            mem17_o <=   8'h00;
+            mem18_o <=   8'h00;  
+            mem19_o <=   8'h00;
+            mem20_o <=   8'h00;  
+            mem21_o <=   8'h00;
+
+            visual_RST_ST_current_o <=   RST_ST;
+
+          end
+      endcase
+    end
+  end
+endmodule
+
+
+
+
+
+
+module nctrl_tri (clock_1, clock_2, clock_3, reset_1, reset_2, reset_3, up_rw_b_1, up_rw_b_2, up_rw_b_3, up_data_out_1, up_data_out_2, up_data_out_3, up_data_in_1, up_data_in_2, up_data_in_3, up_addr_1, up_addr_2, up_addr_3, up_cs_b_1, up_cs_b_2, up_cs_b_3,
+              tx_ena_1, tx_ena_2, tx_ena_3, tx_dav_1, tx_dav_2, tx_dav_3, nc_ready_1, nc_ready_2, nc_ready_3, rx_dav_1, rx_dav_2, rx_dav_3, rx_ena_1, rx_ena_2, rx_ena_3, dataw_in_1, dataw_in_2, dataw_in_3, dataw_out_1, dataw_out_2, dataw_out_3,
+              `ifdef WithSEUcounter
+                  SEU_NCTRLflag1,SEU_NCTRLflag2,SEU_NCTRLflag3, //ADDED 17oct13
+              `endif 
+              Int_arb_in_1, Int_arb_in_2, Int_arb_in_3, up_busy_in_1, up_busy_in_2, up_busy_in_3, CRE_1, CRE_2, CRE_3,
+              EN_ch_reg_1, EN_ch_reg_2, EN_ch_reg_3 //ADDED 30jan14 for gating channels
+              );
+
+	`include "Table_Commande.v"
+
+	input clock_1, clock_2, clock_3;
+	input reset_1, reset_2, reset_3;
+	input [wb_nb_bit:0] up_data_in_1, up_data_in_2, up_data_in_3;
+	input tx_dav_1, tx_dav_2, tx_dav_3;
+	input rx_ena_1, rx_ena_2, rx_ena_3;
+	input [atlantic_nb_bit:0] dataw_in_1, dataw_in_2, dataw_in_3;
+	input [5:0] Int_arb_in_1, Int_arb_in_2, Int_arb_in_3;
+	input up_busy_in_1, up_busy_in_2, up_busy_in_3;
+	output up_rw_b_1, up_rw_b_2, up_rw_b_3;
+	output [wb_nb_bit:0] up_data_out_1, up_data_out_2, up_data_out_3;
+	output [wb_nb_bit:0] up_addr_1, up_addr_2, up_addr_3;
+	output up_cs_b_1, up_cs_b_2, up_cs_b_3;
+	output tx_ena_1, tx_ena_2, tx_ena_3;
+	output nc_ready_1, nc_ready_2, nc_ready_3;
+	output rx_dav_1, rx_dav_2, rx_dav_3;
+	output [atlantic_nb_bit:0] dataw_out_1, dataw_out_2, dataw_out_3;
+	output [7:0] CRE_1, CRE_2, CRE_3;
+	
+	output [31:0] EN_ch_reg_1, EN_ch_reg_2, EN_ch_reg_3; //ADDED 30jan14 for gating channels
+	
+	`ifdef WithSEUcounter //ADDED 17oct13
+            output SEU_NCTRLflag1;
+            wire SEU_NCTRLflag1;  
+            output SEU_NCTRLflag2;
+            wire SEU_NCTRLflag2;             
+            output SEU_NCTRLflag3;
+            wire SEU_NCTRLflag3;             
+            
+      `endif 
+	
+	wire rx_dav_1, rx_dav_2, rx_dav_3;
+	wire tx_ena_1, tx_ena_2, tx_ena_3;
+	wire [atlantic_nb_bit:0] dataw_out_1, dataw_out_2, dataw_out_3;
+	wire [7:0] SRA_1, SRA_2, SRA_3;
+	wire [7:0] SRB_1, SRB_2, SRB_3;
+	wire [7:0] CRA_1, CRA_2, CRA_3;
+	wire [7:0] CRB_1, CRB_2, CRB_3;
+	wire [7:0] CRC_1, CRC_2, CRC_3;
+	wire [7:0] CRD_1, CRD_2, CRD_3;
+	wire [7:0] CRE_1, CRE_2, CRE_3;
+	wire [31:0] EN_ch_reg_1, EN_ch_reg_2, EN_ch_reg_3;
+	wire [7:0] AckByte_1, AckByte_2, AckByte_3;
+	wire [7:0] LenRep_1, LenRep_2, LenRep_3;
+	wire [7:0] TR_1, TR_2, TR_3;
+	wire [7:0] CH_1, CH_2, CH_3;
+	wire [7:0] CMD_1, CMD_2, CMD_3;
+	wire [7:0] LEN_1, LEN_2, LEN_3;
+	wire [wb_nb_bit:0] up_addr_1, up_addr_2, up_addr_3;
+	wire [7:0] rep_node_1, rep_node_2, rep_node_3;
+	wire [15:0] SPI_CTRL_1, SPI_CTRL_2, SPI_CTRL_3;
+	wire nc_ready_1, nc_ready_2, nc_ready_3;
+	wire [15:0] data_in_tmp_1, data_in_tmp_2, data_in_tmp_3;
+	wire [15:0] data_in_tmp1_1, data_in_tmp1_2, data_in_tmp1_3;
+	wire invalid_cmd_1, invalid_cmd_2, invalid_cmd_3;
+	wire up_cs_b_1, up_cs_b_2, up_cs_b_3;
+	wire up_rw_b_1, up_rw_b_2, up_rw_b_3;
+	wire [wb_nb_bit:0] up_data_out_1, up_data_out_2, up_data_out_3;
+	wire [7:0] mem0_1, mem0_2, mem0_3;
+	wire [7:0] mem1_1, mem1_2, mem1_3;
+	wire [7:0] mem2_1, mem2_2, mem2_3;
+	wire [7:0] mem3_1, mem3_2, mem3_3;
+	wire [7:0] mem4_1, mem4_2, mem4_3;
+	wire [7:0] mem5_1, mem5_2, mem5_3;
+	wire [7:0] mem6_1, mem6_2, mem6_3;
+	wire [7:0] mem7_1, mem7_2, mem7_3;
+	wire [7:0] mem8_1, mem8_2, mem8_3;
+	wire [7:0] mem9_1, mem9_2, mem9_3;
+	wire [7:0] mem10_1, mem10_2, mem10_3;
+	wire [7:0] mem11_1, mem11_2, mem11_3;
+	wire [7:0] mem12_1, mem12_2, mem12_3;
+	wire [7:0] mem13_1, mem13_2, mem13_3;
+	wire [7:0] mem14_1, mem14_2, mem14_3;
+	wire [7:0] mem15_1, mem15_2, mem15_3;
+	wire [7:0] mem16_1, mem16_2, mem16_3;
+	wire [7:0] mem17_1, mem17_2, mem17_3;
+	wire [7:0] mem18_1, mem18_2, mem18_3;
+	wire [7:0] mem19_1, mem19_2, mem19_3;
+	wire [7:0] mem20_1, mem20_2, mem20_3;
+	wire [7:0] mem21_1, mem21_2, mem21_3;
+	wire [6:0] visual_RST_ST_current_1, visual_RST_ST_current_2, visual_RST_ST_current_3;
+	wire rx_dav;
+	wire tx_ena;
+	wire [atlantic_nb_bit:0] dataw_out;
+	wire [7:0] SRA;
+	wire [7:0] SRB;
+	wire [7:0] CRA;
+	wire [7:0] CRB;
+	wire [7:0] CRC;
+	wire [7:0] CRD;
+	wire [7:0] CRE;
+	wire [31:0] EN_ch_reg;
+	wire [7:0] AckByte;
+	wire [7:0] LenRep;
+	wire [7:0] TR;
+	wire [7:0] CH;
+	wire [7:0] CMD;
+	wire [7:0] LEN;
+	wire [wb_nb_bit:0] up_addr;
+	wire [7:0] rep_node;
+	wire [15:0] SPI_CTRL;
+	wire nc_ready;
+	wire [15:0] data_in_tmp;
+	wire [15:0] data_in_tmp1;
+	wire invalid_cmd;
+	wire up_cs_b;
+	wire up_rw_b;
+	wire [wb_nb_bit:0] up_data_out;
+	wire [7:0] mem0;
+	wire [7:0] mem1;
+	wire [7:0] mem2;
+	wire [7:0] mem3;
+	wire [7:0] mem4;
+	wire [7:0] mem5;
+	wire [7:0] mem6;
+	wire [7:0] mem7;
+	wire [7:0] mem8;
+	wire [7:0] mem9;
+	wire [7:0] mem10;
+	wire [7:0] mem11;
+	wire [7:0] mem12;
+	wire [7:0] mem13;
+	wire [7:0] mem14;
+	wire [7:0] mem15;
+	wire [7:0] mem16;
+	wire [7:0] mem17;
+	wire [7:0] mem18;
+	wire [7:0] mem19;
+	wire [7:0] mem20;
+	wire [7:0] mem21;
+	wire [6:0] visual_RST_ST_current;
+	
+	
+	// (output)\W*?(\[\w+:\w+\])*\W*?(\w+)(_o);  => .\3\4(\3o_2),
+	// (input)\W*?(\[\w+:\w+\])*\W*?(\w+)(_i);  => .\3\4(\3_1),
+	// (input)\W*?(\[\w+:\w+\])*\W*?(\w+);      => .\3\4(\3_1),
+
+	nctrl_iostate nctrl_iostate_1   (.clock(clock_1), .reset(reset_1), .up_rw_b_i(up_rw_b_1), .up_rw_b_o(up_rw_b_2), .up_data_out_i(up_data_out_1), .up_data_out_o(up_data_out_2), .up_data_in(up_data_in_1), .up_addr_i(up_addr_1), .up_addr_o(up_addr_2), .up_cs_b_i(up_cs_b_1), .up_cs_b_o(up_cs_b_2),
+              .tx_ena_i(tx_ena_1), .tx_ena_o(tx_ena_2), .tx_dav(tx_dav_1), .nc_ready_i(nc_ready_1), .nc_ready_o(nc_ready_2), .rx_dav_i(rx_dav_1), .rx_dav_o(rx_dav_2), .rx_ena(rx_ena_1), .dataw_in(dataw_in_1), .dataw_out_i(dataw_out_1), .dataw_out_o(dataw_out_2),
+              .Int_arb_in(Int_arb_in_1), .up_busy_in(up_busy_in_1), .CRE_i(CRE_1), .CRE_o(CRE_2), .SRA_i(SRA_1), .SRA_o(SRA_2), .SRB_i(SRB_1), .SRB_o(SRB_2), .CRA_i(CRA_1), .CRA_o(CRA_2), .CRB_i(CRB_1), .CRB_o(CRB_2), .CRC_i(CRC_1), .CRC_o(CRC_2), .CRD_i(CRD_1), .CRD_o(CRD_2), .EN_ch_reg_i(EN_ch_reg_1), .EN_ch_reg_o(EN_ch_reg_2), .AckByte_i(AckByte_1), .AckByte_o(AckByte_2), .LenRep_i(LenRep_1), .LenRep_o(LenRep_2), .TR_i(TR_1), .TR_o(TR_2), .CH_i(CH_1), .CH_o(CH_2), .CMD_i(CMD_1), .CMD_o(CMD_2), .LEN_i(LEN_1), .LEN_o(LEN_2), .rep_node_i(rep_node_1), .rep_node_o(rep_node_2), .SPI_CTRL_i(SPI_CTRL_1), .SPI_CTRL_o(SPI_CTRL_2), .data_in_tmp_i(data_in_tmp_1), .data_in_tmp_o(data_in_tmp_2), .data_in_tmp1_i(data_in_tmp1_1), .data_in_tmp1_o(data_in_tmp1_2), .invalid_cmd_i(invalid_cmd_1), .invalid_cmd_o(invalid_cmd_2), .mem0_i(mem0_1), .mem0_o(mem0_2), .mem1_i(mem1_1), .mem1_o(mem1_2), .mem2_i(mem2_1), .mem2_o(mem2_2), .mem3_i(mem3_1), .mem3_o(mem3_2), .mem4_i(mem4_1), .mem4_o(mem4_2), .mem5_i(mem5_1), .mem5_o(mem5_2), .mem6_i(mem6_1), .mem6_o(mem6_2), .mem7_i(mem7_1), .mem7_o(mem7_2), .mem8_i(mem8_1), .mem8_o(mem8_2), .mem9_i(mem9_1), .mem9_o(mem9_2), .mem10_i(mem10_1), .mem10_o(mem10_2), .mem11_i(mem11_1), .mem11_o(mem11_2), .mem12_i(mem12_1), .mem12_o(mem12_2), .mem13_i(mem13_1), .mem13_o(mem13_2), .mem14_i(mem14_1), .mem14_o(mem14_2), .mem15_i(mem15_1), .mem15_o(mem15_2), .mem16_i(mem16_1), .mem16_o(mem16_2), .mem17_i(mem17_1), .mem17_o(mem17_2), .mem18_i(mem18_1), .mem18_o(mem18_2), .mem19_i(mem19_1), .mem19_o(mem19_2), .mem20_i(mem20_1), .mem20_o(mem20_2), .mem21_i(mem21_1), .mem21_o(mem21_2), .visual_RST_ST_current_i(visual_RST_ST_current_1), .visual_RST_ST_current_o(visual_RST_ST_current_2));
+
+	nctrl_iostate nctrl_iostate_2   (.clock(clock_2), .reset(reset_2), .up_rw_b_i(up_rw_b_2), .up_rw_b_o(up_rw_b_3), .up_data_out_i(up_data_out_2), .up_data_out_o(up_data_out_3), .up_data_in(up_data_in_2), .up_addr_i(up_addr_2), .up_addr_o(up_addr_3), .up_cs_b_i(up_cs_b_2), .up_cs_b_o(up_cs_b_3),
+              .tx_ena_i(tx_ena_2), .tx_ena_o(tx_ena_3), .tx_dav(tx_dav_2), .nc_ready_i(nc_ready_2), .nc_ready_o(nc_ready_3), .rx_dav_i(rx_dav_2), .rx_dav_o(rx_dav_3), .rx_ena(rx_ena_2), .dataw_in(dataw_in_2), .dataw_out_i(dataw_out_2), .dataw_out_o(dataw_out_3),
+              .Int_arb_in(Int_arb_in_2), .up_busy_in(up_busy_in_2), .CRE_i(CRE_2), .CRE_o(CRE_3), .SRA_i(SRA_2), .SRA_o(SRA_3), .SRB_i(SRB_2), .SRB_o(SRB_3), .CRA_i(CRA_2), .CRA_o(CRA_3), .CRB_i(CRB_2), .CRB_o(CRB_3), .CRC_i(CRC_2), .CRC_o(CRC_3), .CRD_i(CRD_2), .CRD_o(CRD_3), .EN_ch_reg_i(EN_ch_reg_2), .EN_ch_reg_o(EN_ch_reg_3), .AckByte_i(AckByte_2), .AckByte_o(AckByte_3), .LenRep_i(LenRep_2), .LenRep_o(LenRep_3), .TR_i(TR_2), .TR_o(TR_3), .CH_i(CH_2), .CH_o(CH_3), .CMD_i(CMD_2), .CMD_o(CMD_3), .LEN_i(LEN_2), .LEN_o(LEN_3), .rep_node_i(rep_node_2), .rep_node_o(rep_node_3), .SPI_CTRL_i(SPI_CTRL_2), .SPI_CTRL_o(SPI_CTRL_3), .data_in_tmp_i(data_in_tmp_2), .data_in_tmp_o(data_in_tmp_3), .data_in_tmp1_i(data_in_tmp1_2), .data_in_tmp1_o(data_in_tmp1_3), .invalid_cmd_i(invalid_cmd_2), .invalid_cmd_o(invalid_cmd_3), .mem0_i(mem0_2), .mem0_o(mem0_3), .mem1_i(mem1_2), .mem1_o(mem1_3), .mem2_i(mem2_2), .mem2_o(mem2_3), .mem3_i(mem3_2), .mem3_o(mem3_3), .mem4_i(mem4_2), .mem4_o(mem4_3), .mem5_i(mem5_2), .mem5_o(mem5_3), .mem6_i(mem6_2), .mem6_o(mem6_3), .mem7_i(mem7_2), .mem7_o(mem7_3), .mem8_i(mem8_2), .mem8_o(mem8_3), .mem9_i(mem9_2), .mem9_o(mem9_3), .mem10_i(mem10_2), .mem10_o(mem10_3), .mem11_i(mem11_2), .mem11_o(mem11_3), .mem12_i(mem12_2), .mem12_o(mem12_3), .mem13_i(mem13_2), .mem13_o(mem13_3), .mem14_i(mem14_2), .mem14_o(mem14_3), .mem15_i(mem15_2), .mem15_o(mem15_3), .mem16_i(mem16_2), .mem16_o(mem16_3), .mem17_i(mem17_2), .mem17_o(mem17_3), .mem18_i(mem18_2), .mem18_o(mem18_3), .mem19_i(mem19_2), .mem19_o(mem19_3), .mem20_i(mem20_2), .mem20_o(mem20_3), .mem21_i(mem21_2), .mem21_o(mem21_3), .visual_RST_ST_current_i(visual_RST_ST_current_2), .visual_RST_ST_current_o(visual_RST_ST_current_3));
+
+	nctrl_iostate nctrl_iostate_3   (.clock(clock_3), .reset(reset_3), .up_rw_b_i(up_rw_b_3), .up_rw_b_o(up_rw_b), .up_data_out_i(up_data_out_3), .up_data_out_o(up_data_out), .up_data_in(up_data_in_3), .up_addr_i(up_addr_3), .up_addr_o(up_addr), .up_cs_b_i(up_cs_b_3), .up_cs_b_o(up_cs_b),
+              .tx_ena_i(tx_ena_3), .tx_ena_o(tx_ena), .tx_dav(tx_dav_3), .nc_ready_i(nc_ready_3), .nc_ready_o(nc_ready), .rx_dav_i(rx_dav_3), .rx_dav_o(rx_dav), .rx_ena(rx_ena_3), .dataw_in(dataw_in_3), .dataw_out_i(dataw_out_3), .dataw_out_o(dataw_out),
+              .Int_arb_in(Int_arb_in_3), .up_busy_in(up_busy_in_3), .CRE_i(CRE_3), .CRE_o(CRE), .SRA_i(SRA_3), .SRA_o(SRA), .SRB_i(SRB_3), .SRB_o(SRB), .CRA_i(CRA_3), .CRA_o(CRA), .CRB_i(CRB_3), .CRB_o(CRB), .CRC_i(CRC_3), .CRC_o(CRC), .CRD_i(CRD_3), .CRD_o(CRD), .EN_ch_reg_i(EN_ch_reg_3), .EN_ch_reg_o(EN_ch_reg), .AckByte_i(AckByte_3), .AckByte_o(AckByte), .LenRep_i(LenRep_3), .LenRep_o(LenRep), .TR_i(TR_3), .TR_o(TR), .CH_i(CH_3), .CH_o(CH), .CMD_i(CMD_3), .CMD_o(CMD), .LEN_i(LEN_3), .LEN_o(LEN), .rep_node_i(rep_node_3), .rep_node_o(rep_node), .SPI_CTRL_i(SPI_CTRL_3), .SPI_CTRL_o(SPI_CTRL), .data_in_tmp_i(data_in_tmp_3), .data_in_tmp_o(data_in_tmp), .data_in_tmp1_i(data_in_tmp1_3), .data_in_tmp1_o(data_in_tmp1), .invalid_cmd_i(invalid_cmd_3), .invalid_cmd_o(invalid_cmd), .mem0_i(mem0_3), .mem0_o(mem0), .mem1_i(mem1_3), .mem1_o(mem1), .mem2_i(mem2_3), .mem2_o(mem2), .mem3_i(mem3_3), .mem3_o(mem3), .mem4_i(mem4_3), .mem4_o(mem4), .mem5_i(mem5_3), .mem5_o(mem5), .mem6_i(mem6_3), .mem6_o(mem6), .mem7_i(mem7_3), .mem7_o(mem7), .mem8_i(mem8_3), .mem8_o(mem8), .mem9_i(mem9_3), .mem9_o(mem9), .mem10_i(mem10_3), .mem10_o(mem10), .mem11_i(mem11_3), .mem11_o(mem11), .mem12_i(mem12_3), .mem12_o(mem12), .mem13_i(mem13_3), .mem13_o(mem13), .mem14_i(mem14_3), .mem14_o(mem14), .mem15_i(mem15_3), .mem15_o(mem15), .mem16_i(mem16_3), .mem16_o(mem16), .mem17_i(mem17_3), .mem17_o(mem17), .mem18_i(mem18_3), .mem18_o(mem18), .mem19_i(mem19_3), .mem19_o(mem19), .mem20_i(mem20_3), .mem20_o(mem20), .mem21_i(mem21_3), .mem21_o(mem21), .visual_RST_ST_current_i(visual_RST_ST_current_3), .visual_RST_ST_current_o(visual_RST_ST_current));
+	
+
+	majority_voter #(.WIDTH(384+atlantic_nb_bit+wb_nb_bit+wb_nb_bit)) mv (
+		.in1({rx_dav_2, tx_ena_2, dataw_out_2, SRA_2, SRB_2, CRA_2, CRB_2, CRC_2, CRD_2, CRE_2, EN_ch_reg_2, AckByte_2, LenRep_2, TR_2, CH_2, CMD_2, LEN_2, up_addr_2, rep_node_2, SPI_CTRL_2, nc_ready_2, data_in_tmp_2, data_in_tmp1_2, invalid_cmd_2, up_cs_b_2, up_rw_b_2, up_data_out_2, mem0_2, mem1_2, mem2_2, mem3_2, mem4_2, mem5_2, mem6_2, mem7_2, mem8_2, mem9_2, mem10_2, mem11_2, mem12_2, mem13_2, mem14_2, mem15_2, mem16_2, mem17_2, mem18_2, mem19_2, mem20_2, mem21_2, visual_RST_ST_current_2 }),
+		.in2({rx_dav_3, tx_ena_3, dataw_out_3, SRA_3, SRB_3, CRA_3, CRB_3, CRC_3, CRD_3, CRE_3, EN_ch_reg_3, AckByte_3, LenRep_3, TR_3, CH_3, CMD_3, LEN_3, up_addr_3, rep_node_3, SPI_CTRL_3, nc_ready_3, data_in_tmp_3, data_in_tmp1_3, invalid_cmd_3, up_cs_b_3, up_rw_b_3, up_data_out_3, mem0_3, mem1_3, mem2_3, mem3_3, mem4_3, mem5_3, mem6_3, mem7_3, mem8_3, mem9_3, mem10_3, mem11_3, mem12_3, mem13_3, mem14_3, mem15_3, mem16_3, mem17_3, mem18_3, mem19_3, mem20_3, mem21_3, visual_RST_ST_current_3 }),
+		.in3({rx_dav,   tx_ena,   dataw_out,   SRA,   SRB,   CRA,   CRB,   CRC,   CRD,   CRE,   EN_ch_reg,   AckByte,   LenRep,   TR,   CH,   CMD,   LEN,   up_addr,   rep_node,   SPI_CTRL,   nc_ready,   data_in_tmp,   data_in_tmp1,   invalid_cmd,   up_cs_b,   up_rw_b,   up_data_out,   mem0,   mem1,   mem2,   mem3,   mem4,   mem5,   mem6,   mem7,   mem8,   mem9,   mem10,   mem11,   mem12,   mem13,   mem14,   mem15,   mem16,   mem17,   mem18,   mem19,   mem20,   mem21,   visual_RST_ST_current   }),
+		.out({rx_dav_1, tx_ena_1, dataw_out_1, SRA_1, SRB_1, CRA_1, CRB_1, CRC_1, CRD_1, CRE_1, EN_ch_reg_1, AckByte_1, LenRep_1, TR_1, CH_1, CMD_1, LEN_1, up_addr_1, rep_node_1, SPI_CTRL_1, nc_ready_1, data_in_tmp_1, data_in_tmp1_1, invalid_cmd_1, up_cs_b_1, up_rw_b_1, up_data_out_1, mem0_1, mem1_1, mem2_1, mem3_1, mem4_1, mem5_1, mem6_1, mem7_1, mem8_1, mem9_1, mem10_1, mem11_1, mem12_1, mem13_1, mem14_1, mem15_1, mem16_1, mem17_1, mem18_1, mem19_1, mem20_1, mem21_1, visual_RST_ST_current_1 }),		
+		.err()
+	);
+	
+`ifdef WithSEUcounter
+	majority_error err_identif1 (
+		.in1({rx_dav_2, tx_ena_2, dataw_out_2, SRA_2, SRB_2, CRA_2, CRB_2, CRC_2, CRD_2, CRE_2, EN_ch_reg_2, AckByte_2, LenRep_2, TR_2, CH_2, CMD_2, LEN_2, up_addr_2, rep_node_2, SPI_CTRL_2, nc_ready_2, data_in_tmp_2, data_in_tmp1_2, invalid_cmd_2, up_cs_b_2, up_rw_b_2, up_data_out_2, mem0_2, mem1_2, mem2_2, mem3_2, mem4_2, mem5_2, mem6_2, mem7_2, mem8_2, mem9_2, mem10_2, mem11_2, mem12_2, mem13_2, mem14_2, mem15_2, mem16_2, mem17_2, mem18_2, mem19_2, mem20_2, mem21_2, visual_RST_ST_current_2 }),
+		.in2({rx_dav_3, tx_ena_3, dataw_out_3, SRA_3, SRB_3, CRA_3, CRB_3, CRC_3, CRD_3, CRE_3, EN_ch_reg_3, AckByte_3, LenRep_3, TR_3, CH_3, CMD_3, LEN_3, up_addr_3, rep_node_3, SPI_CTRL_3, nc_ready_3, data_in_tmp_3, data_in_tmp1_3, invalid_cmd_3, up_cs_b_3, up_rw_b_3, up_data_out_3, mem0_3, mem1_3, mem2_3, mem3_3, mem4_3, mem5_3, mem6_3, mem7_3, mem8_3, mem9_3, mem10_3, mem11_3, mem12_3, mem13_3, mem14_3, mem15_3, mem16_3, mem17_3, mem18_3, mem19_3, mem20_3, mem21_3, visual_RST_ST_current_3 }),
+		.in3({rx_dav,   tx_ena,   dataw_out,   SRA,   SRB,   CRA,   CRB,   CRC,   CRD,   CRE,   EN_ch_reg,   AckByte,   LenRep,   TR,   CH,   CMD,   LEN,   up_addr,   rep_node,   SPI_CTRL,   nc_ready,   data_in_tmp,   data_in_tmp1,   invalid_cmd,   up_cs_b,   up_rw_b,   up_data_out,   mem0,   mem1,   mem2,   mem3,   mem4,   mem5,   mem6,   mem7,   mem8,   mem9,   mem10,   mem11,   mem12,   mem13,   mem14,   mem15,   mem16,   mem17,   mem18,   mem19,   mem20,   mem21,   visual_RST_ST_current   }),
+		.err(SEU_NCTRLflag1)
+	);		
+	assign SEU_NCTRLflag2 = SEU_NCTRLflag1; //an error here can be considered as part of the sensitivity logic to SEUs
+	assign SEU_NCTRLflag3 = SEU_NCTRLflag1;
+`endif	
+	
+/*	
+`ifdef WithSEUcounter
+	majority_error err_identif1 (
+		.in1({rx_dav_2, tx_ena_2, dataw_out_2, SRA_2, SRB_2, CRA_2, CRB_2, CRC_2, CRD_2, CRE_2, EN_ch_reg_2, AckByte_2, LenRep_2, TR_2, CH_2, CMD_2, LEN_2, up_addr_2, rep_node_2, SPI_CTRL_2, nc_ready_2, data_in_tmp_2, data_in_tmp1_2, invalid_cmd_2, up_cs_b_2, up_rw_b_2, up_data_out_2, mem0_2, mem1_2, mem2_2, mem3_2, mem4_2, mem5_2, mem6_2, mem7_2, mem8_2, mem9_2, mem10_2, mem11_2, mem12_2, mem13_2, mem14_2, mem15_2, mem16_2, mem17_2, mem18_2, mem19_2, mem20_2, mem21_2, visual_RST_ST_current_2 }),
+		.in2({rx_dav_3, tx_ena_3, dataw_out_3, SRA_3, SRB_3, CRA_3, CRB_3, CRC_3, CRD_3, CRE_3, EN_ch_reg_3, AckByte_3, LenRep_3, TR_3, CH_3, CMD_3, LEN_3, up_addr_3, rep_node_3, SPI_CTRL_3, nc_ready_3, data_in_tmp_3, data_in_tmp1_3, invalid_cmd_3, up_cs_b_3, up_rw_b_3, up_data_out_3, mem0_3, mem1_3, mem2_3, mem3_3, mem4_3, mem5_3, mem6_3, mem7_3, mem8_3, mem9_3, mem10_3, mem11_3, mem12_3, mem13_3, mem14_3, mem15_3, mem16_3, mem17_3, mem18_3, mem19_3, mem20_3, mem21_3, visual_RST_ST_current_3 }),
+		.in3({rx_dav,   tx_ena,   dataw_out,   SRA,   SRB,   CRA,   CRB,   CRC,   CRD,   CRE,   EN_ch_reg,   AckByte,   LenRep,   TR,   CH,   CMD,   LEN,   up_addr,   rep_node,   SPI_CTRL,   nc_ready,   data_in_tmp,   data_in_tmp1,   invalid_cmd,   up_cs_b,   up_rw_b,   up_data_out,   mem0,   mem1,   mem2,   mem3,   mem4,   mem5,   mem6,   mem7,   mem8,   mem9,   mem10,   mem11,   mem12,   mem13,   mem14,   mem15,   mem16,   mem17,   mem18,   mem19,   mem20,   mem21,   visual_RST_ST_current   }),
+		.err(SEU_NCTRLflag1)
+	);
+	majority_error err_identif2 (
+		.in2({rx_dav_2, tx_ena_2, dataw_out_2, SRA_2, SRB_2, CRA_2, CRB_2, CRC_2, CRD_2, CRE_2, EN_ch_reg_2, AckByte_2, LenRep_2, TR_2, CH_2, CMD_2, LEN_2, up_addr_2, rep_node_2, SPI_CTRL_2, nc_ready_2, data_in_tmp_2, data_in_tmp1_2, invalid_cmd_2, up_cs_b_2, up_rw_b_2, up_data_out_2, mem0_2, mem1_2, mem2_2, mem3_2, mem4_2, mem5_2, mem6_2, mem7_2, mem8_2, mem9_2, mem10_2, mem11_2, mem12_2, mem13_2, mem14_2, mem15_2, mem16_2, mem17_2, mem18_2, mem19_2, mem20_2, mem21_2, visual_RST_ST_current_2 }),
+		.in3({rx_dav_3, tx_ena_3, dataw_out_3, SRA_3, SRB_3, CRA_3, CRB_3, CRC_3, CRD_3, CRE_3, EN_ch_reg_3, AckByte_3, LenRep_3, TR_3, CH_3, CMD_3, LEN_3, up_addr_3, rep_node_3, SPI_CTRL_3, nc_ready_3, data_in_tmp_3, data_in_tmp1_3, invalid_cmd_3, up_cs_b_3, up_rw_b_3, up_data_out_3, mem0_3, mem1_3, mem2_3, mem3_3, mem4_3, mem5_3, mem6_3, mem7_3, mem8_3, mem9_3, mem10_3, mem11_3, mem12_3, mem13_3, mem14_3, mem15_3, mem16_3, mem17_3, mem18_3, mem19_3, mem20_3, mem21_3, visual_RST_ST_current_3 }),
+		.in1({rx_dav,   tx_ena,   dataw_out,   SRA,   SRB,   CRA,   CRB,   CRC,   CRD,   CRE,   EN_ch_reg,   AckByte,   LenRep,   TR,   CH,   CMD,   LEN,   up_addr,   rep_node,   SPI_CTRL,   nc_ready,   data_in_tmp,   data_in_tmp1,   invalid_cmd,   up_cs_b,   up_rw_b,   up_data_out,   mem0,   mem1,   mem2,   mem3,   mem4,   mem5,   mem6,   mem7,   mem8,   mem9,   mem10,   mem11,   mem12,   mem13,   mem14,   mem15,   mem16,   mem17,   mem18,   mem19,   mem20,   mem21,   visual_RST_ST_current   }),
+		.err(SEU_NCTRLflag2)
+	);
+	majority_error err_identif3 (
+		.in3({rx_dav_2, tx_ena_2, dataw_out_2, SRA_2, SRB_2, CRA_2, CRB_2, CRC_2, CRD_2, CRE_2, EN_ch_reg_2, AckByte_2, LenRep_2, TR_2, CH_2, CMD_2, LEN_2, up_addr_2, rep_node_2, SPI_CTRL_2, nc_ready_2, data_in_tmp_2, data_in_tmp1_2, invalid_cmd_2, up_cs_b_2, up_rw_b_2, up_data_out_2, mem0_2, mem1_2, mem2_2, mem3_2, mem4_2, mem5_2, mem6_2, mem7_2, mem8_2, mem9_2, mem10_2, mem11_2, mem12_2, mem13_2, mem14_2, mem15_2, mem16_2, mem17_2, mem18_2, mem19_2, mem20_2, mem21_2, visual_RST_ST_current_2 }),
+		.in1({rx_dav_3, tx_ena_3, dataw_out_3, SRA_3, SRB_3, CRA_3, CRB_3, CRC_3, CRD_3, CRE_3, EN_ch_reg_3, AckByte_3, LenRep_3, TR_3, CH_3, CMD_3, LEN_3, up_addr_3, rep_node_3, SPI_CTRL_3, nc_ready_3, data_in_tmp_3, data_in_tmp1_3, invalid_cmd_3, up_cs_b_3, up_rw_b_3, up_data_out_3, mem0_3, mem1_3, mem2_3, mem3_3, mem4_3, mem5_3, mem6_3, mem7_3, mem8_3, mem9_3, mem10_3, mem11_3, mem12_3, mem13_3, mem14_3, mem15_3, mem16_3, mem17_3, mem18_3, mem19_3, mem20_3, mem21_3, visual_RST_ST_current_3 }),
+		.in2({rx_dav,   tx_ena,   dataw_out,   SRA,   SRB,   CRA,   CRB,   CRC,   CRD,   CRE,   EN_ch_reg,   AckByte,   LenRep,   TR,   CH,   CMD,   LEN,   up_addr,   rep_node,   SPI_CTRL,   nc_ready,   data_in_tmp,   data_in_tmp1,   invalid_cmd,   up_cs_b,   up_rw_b,   up_data_out,   mem0,   mem1,   mem2,   mem3,   mem4,   mem5,   mem6,   mem7,   mem8,   mem9,   mem10,   mem11,   mem12,   mem13,   mem14,   mem15,   mem16,   mem17,   mem18,   mem19,   mem20,   mem21,   visual_RST_ST_current   }),
+		.err(SEU_NCTRLflag3)
+	);
+`endif	
+*/		
+endmodule
+
+
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  ARBITER
+//      Library Name  :  node_ctrl
+//  
+//      Creation Date :  Mon Jun 24 09:42:12 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         IF for state selection         :  No
+//         Error (default) state          :  Yes
+//         String typed state variable    :  No
+//         Next state assignments         :  Non blocking
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  node_ctrl
+//  Unit    Name :  ARBITER
+//  Unit    Type :  State Machine
+//  
+//----------------------------------------------------
+ 
+
+
+module ARBITER_iostate(clock, reset, CH_int_iv, CH_int_ov, IE_CH, canal_iv, canal_ov, visual_Repos_current_iv, visual_Repos_current_ov);
+
+`include "Table_Commande.v"
+
+
+  input clock;
+  input [2:0] visual_Repos_current_iv;
+  input [5:0] canal_iv;
+  input [20:0] IE_CH;
+  input reset;
+  output [5:0] CH_int_ov;
+  output [2:0] visual_Repos_current_ov;
+  output [5:0] canal_ov;
+  input [5:0] CH_int_iv;
+  
+  wire clock;
+  wire reset;
+  wire [20:0] IE_CH;
+
+  reg [5:0] CH_int_ov;
+  reg [5:0] canal_ov;
+  reg [2:0] visual_Repos_current_ov;
+  
+  parameter Repos      = 3'b000,
+            Clr_int    = 3'b001,
+            Int_Activ  = 3'b010,
+            Next_canal = 3'b011,
+            fin        = 3'b100,
+            start      = 3'b101;
+
+  always  @(posedge clock or posedge reset)
+  begin : ARBITER_Repos
+ 
+    if (reset === 1'b1)
+    begin
+      CH_int_ov <=   6'h0;  
+      canal_ov <=   6'b0;
+      visual_Repos_current_ov <=   Repos;
+    end
+    else
+    begin
+      CH_int_ov <=   CH_int_iv;  
+      canal_ov <=   canal_iv;
+      visual_Repos_current_ov <=   visual_Repos_current_iv;
+
+      case (visual_Repos_current_iv)
+        Repos:
+          begin
+            visual_Repos_current_ov <=   start;
+          end
+ 
+        Clr_int:
+          begin
+            canal_ov <=   canal_iv + 6'h1;
+            visual_Repos_current_ov <=   Next_canal;
+          end
+ 
+        Int_Activ:
+          begin
+            if (IE_CH[canal_iv] == 1'b1)
+            begin
+              visual_Repos_current_ov <=   Int_Activ;
+            end
+            else if (IE_CH[canal_iv] == 1'b0)
+            begin
+              CH_int_ov <=   6'h0;
+              visual_Repos_current_ov <=   Clr_int;
+            end
+            else
+              visual_Repos_current_ov <=   Int_Activ;
+          end
+ 
+        Next_canal:
+          begin
+            visual_Repos_current_ov <=   fin;
+          end
+ 
+        fin:
+          begin
+            if (canal_iv[5:0] >= Num_Max_CH[5:0])
+            begin
+              CH_int_ov <=   6'h0;  
+              canal_ov <=   6'b0;
+              visual_Repos_current_ov <=   Repos;
+            end
+            else if (Num_Max_CH[5:0] >= canal_iv[5:0])
+            begin
+              visual_Repos_current_ov <=   start;
+            end
+            else
+              visual_Repos_current_ov <=   fin;
+          end
+ 
+        start:
+          begin
+            if (IE_CH[canal_iv] == 1'b1)
+            begin
+              CH_int_ov <=   canal_iv;
+              visual_Repos_current_ov <=   Int_Activ;
+            end
+            else if (IE_CH[canal_iv] == 1'b0)
+            begin
+              canal_ov <=   canal_iv + 6'h1;
+              visual_Repos_current_ov <=   Next_canal;
+            end
+            else
+              visual_Repos_current_ov <=   start;
+          end
+ 
+        default:
+          begin
+            CH_int_ov <=   6'h0;  
+            canal_ov <=   6'b0;
+            visual_Repos_current_ov <=   Repos;
+          end
+      endcase
+    end
+  end
+ 
+ 
+ 
+endmodule
+
+
+
+//  Design Unit:
+//  ------------
+//      Unit    Name  :  ARBITER
+//      Library Name  :  node_ctrl
+//  
+//      Creation Date :  Mon Jun 24 09:42:12 2013
+//      Version       :  2012.09 v4.4.1 build 33. Date: Nov  1 2012. License: 2012.11
+//  
+//  Options Used:
+//  -------------
+//      Target
+//         Language   :  As Is
+//         Purpose    :  Synthesis
+//         Vendor     :  BuildGates
+//  
+//      Style
+//         Use tasks                      :  No
+//         Code Destination               :  1 File per Unit
+//         Attach Directives              :  Yes
+//         Structural                     :  No
+//         IF for state selection         :  No
+//         Error (default_1, default_2, default_3) state          :  Yes
+//         String typed state variable    :  No
+//         Next state assignments         :  Non blocking
+//         Free text style                :  / / ...
+//         Preserve spacing for free text :  Yes
+//         Declaration alignment          :  No
+//         Sort Ports by mode             :  No
+//         New line for each Port         :  No
+//         Attach comment to Port         :  No
+//
+//--------------------------------------------------
+//--------------------------------------------------
+//  
+//  Library Name :  node_ctrl
+//  Unit    Name :  ARBITER
+//  Unit    Type :  State Machine
+//  
+//----------------------------------------------------
+
+module ARBITER_tri(clock_1, clock_2, clock_3, reset_1, reset_2, reset_3, CH_int_1, CH_int_2, CH_int_3, IE_CH_1, IE_CH_2, IE_CH_3
+                );
+
+`include "Table_Commande.v"
+
+  input clock_1, clock_2, clock_3;
+  input reset_1, reset_2, reset_3;
+  output [5:0] CH_int_1, CH_int_2, CH_int_3;
+  input [20:0] IE_CH_1, IE_CH_2, IE_CH_3;
+
+	wire [5:0] CH_int_1, CH_int_2, CH_int_3;
+	wire [5:0] canal_1, canal_2, canal_3;
+	wire [2:0] visual_Repos_current_1, visual_Repos_current_2, visual_Repos_current_3;
+	wire [5:0] CH_int;
+	wire [5:0] canal;
+	wire [2:0] visual_Repos_current;
+
+	ARBITER_iostate ARBITER_iostate_1  (.clock(clock_1), .reset(reset_1), .CH_int_iv(CH_int_1), .CH_int_ov(CH_int_2), .IE_CH(IE_CH_1), .canal_iv(canal_1), .canal_ov(canal_2), .visual_Repos_current_iv(visual_Repos_current_1), .visual_Repos_current_ov(visual_Repos_current_2));
+
+	ARBITER_iostate ARBITER_iostate_2  (.clock(clock_2), .reset(reset_2), .CH_int_iv(CH_int_2), .CH_int_ov(CH_int_3), .IE_CH(IE_CH_2), .canal_iv(canal_2), .canal_ov(canal_3), .visual_Repos_current_iv(visual_Repos_current_2), .visual_Repos_current_ov(visual_Repos_current_3));
+
+	ARBITER_iostate ARBITER_iostate_3  (.clock(clock_3), .reset(reset_3), .CH_int_iv(CH_int_3), .CH_int_ov(CH_int), .IE_CH(IE_CH_3), .canal_iv(canal_3), .canal_ov(canal), .visual_Repos_current_iv(visual_Repos_current_3), .visual_Repos_current_ov(visual_Repos_current));
+
+	majority_voter #(.WIDTH(15)) mv (
+		.in1({CH_int_2, canal_2, visual_Repos_current_2}),
+		.in2({CH_int_3, canal_3, visual_Repos_current_3}),
+		.in3({CH_int, canal, visual_Repos_current}),
+		.out({CH_int_1, canal_1, visual_Repos_current_1}),
+		.err()
+	);
+endmodule
+
diff --git a/vldb/code/Testbench/SCA-model/SCA_TRI_PAD.v b/vldb/code/Testbench/SCA-model/SCA_TRI_PAD.v
new file mode 100644
index 0000000..3723ca9
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/SCA_TRI_PAD.v
@@ -0,0 +1,1739 @@
+//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Design:................GBT-SCA                              //
+//  File name:.............SCA_TRI_PAD.v                        //
+//  Description:...........GBT-SCA top module                   //
+//                                                              //
+//  Authors:...............Christian Paillard CERN PH-ESE-ME    //
+//          ...............Alessandro Caratelli CERN PH-ESE-ME  //
+//                                                              //
+//  Version 1.0:                                                //
+//    Creation date:.......01 July 2013                         //
+//    Last modification:...02 June 2014                         //
+//                                                              //
+//  Version 2.0:                                                //
+//    Creation date:.......25 September 2015                    //
+//    Last modification:...16 November 2015 11.06               //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+module SCA_TOP(
+	// Elink HDLC 
+	input          link_clk_pad2core,
+	input          link_clk_aux_pad2core,
+	input          disable_Elink_aux,
+	output         tx_sd_core2pad,
+	output         tx_sd_aux_core2pad,
+	input          rx_sd_pad2core,
+	input          rx_sd_aux_pad2core,
+	output  [7:0]  CRE,
+	// JTAG 
+	output         TCK_core2pad,
+	output         TMS_core2pad,
+	output         TDO_core2pad,
+	input          TDI_pad2core,
+	output         RST_pad_o,      
+	// SPI 
+	output         SPI_sclk_core2pad,
+	output  [7:0]  ss_pad_o,
+	input          SPI_miso_pad2core,
+	output         SPI_mosi_core2pad,    
+	// GPIO 
+	output  [31:0] GPIO_out_core2pad,
+	output  [31:0] GPIO_oe_core2pad,
+	input          gpio_clk_pad2core,
+	input   [31:0] GPIO_pad2core,            
+	//I2C 
+	output  [15:0] SCL_core2pad,
+	input   [15:0] SDA_IN_pad2core,
+	output  [15:0] SDA_OUT_core2pad, 
+	output  [15:0] SCLEN_core2pad, 
+	// Auxiliary i2c Port 
+	input          auxPort_TestEn,
+	input          auxPort_SCL, 
+	input          auxPort_SDA_in,    
+	output         auxPort_SDA_out,
+	output         auxPort_SDA_oEn,
+	// Analog Pads 
+	input          FuseProgramPulse,  //EFuses program pulse
+	input          reset_b_pad2core,  //reset pad
+	input   [30:0] ADC_analog_in,     //ADC analog input
+	output  [3:0]  analog2pad,        //DAC analog output
+	output  [30:0] Pad_current_out,
+	inout          VDD33     
+	);
+	     
+	wire    [3:0]  adc_CalibrRegI_1;  
+	wire    [3:0]  adc_CalibrRegI_2;  
+	wire    [3:0]  adc_CalibrRegI_3; 
+	wire    [7:0]  DAC0;
+	wire    [7:0]  DAC1;
+	wire    [7:0]  DAC2;
+	wire    [7:0]  DAC3;
+	wire           CLK; 
+	wire    [3:0]  DAC_out;
+	wire    [31:0] ADC_in;
+	wire           PowerUpReset_1;
+	wire           PowerUpReset_2;
+	wire           PowerUpReset_3;
+	wire           ADC_wb_RES;
+	wire           ADC_wb_CLK;
+	wire    [7:0]  ADC_wb_SEL;
+	wire           ADC_wb_WE;
+	wire           ADC_wb_STB;
+	wire           ADC_wb_CYC;
+	wire    [3:0]  ADC_wb_ADR;
+	wire    [31:0] ADC_wb_DATi;
+	wire    [31:0] ADC_wb_DATo;
+	wire           ADC_wb_ACK;
+	wire           ADC_wb_INT;
+                                      
+	TOP_core_sca_tri_r2g  TOP_core_sca_tri_r2g (
+	   
+		// Elink HDLC 
+		.link_clk_1(link_clk_pad2core),              .link_clk_2(link_clk_pad2core),         .link_clk_3(link_clk_pad2core),
+		.link_clk_aux_1(link_clk_aux_pad2core),      .link_clk_aux_2(link_clk_aux_pad2core), .link_clk_aux_3(link_clk_aux_pad2core),
+		.rx_sd_1(rx_sd_pad2core),                    .rx_sd_2(rx_sd_pad2core),               .rx_sd_3(rx_sd_pad2core),
+		.rx_sd_aux_1(rx_sd_aux_pad2core),            .rx_sd_aux_2(rx_sd_aux_pad2core),       .rx_sd_aux_3(rx_sd_aux_pad2core),
+		.tx_sd_1(tx_sd_core2pad),                    .tx_sd_2(),                             .tx_sd_3(),
+		.tx_sd_aux_1(tx_sd_aux_core2pad),            .tx_sd_aux_2(),                         .tx_sd_aux_3(),
+		.tx_adr_1(8'h00),                            .tx_adr_2(8'h00),                       .tx_adr_3(8'h00),
+		.CRE_1(CRE[7:0]),                            .CRE_2(),                               .CRE_3(),
+		.disable_aux_1(disable_Elink_aux),           .disable_aux_2(disable_Elink_aux),      .disable_aux_3(disable_Elink_aux),
+		 
+		 // Reset Logic 
+		.PowerUpReset_1(PowerUpReset_1),             .PowerUpReset_2(PowerUpReset_2),        .PowerUpReset_3(PowerUpReset_3),
+		.PromtReset_1(1'b0),                         .PromtReset_2(1'b0),
+		.Reset_BG_1(Reset_BG),                       .Reset_BG_2(),                          .Reset_BG_3(),
+
+		// Auxiliary i2c port //
+		.auxPort_TestEn_1(auxPort_TestEn),           .auxPort_TestEn_2(auxPort_TestEn),      .auxPort_TestEn_3(auxPort_TestEn),
+		.auxPort_SCL_1(auxPort_SCL),                 .auxPort_SCL_2(auxPort_SCL),            .auxPort_SCL_3(auxPort_SCL),
+		.auxPort_SDA_in_1(auxPort_SDA_in),           .auxPort_SDA_in_2(auxPort_SDA_in),      .auxPort_SDA_in_3(auxPort_SDA_in),
+		.auxPort_SDA_out_1(auxPort_SDA_out),         .auxPort_SDA_out_2(),                   .auxPort_SDA_out_3(),
+		.auxPort_SDA_oEn_1(auxPort_SDA_oEn),         .auxPort_SDA_oEn_2(),                   .auxPort_SDA_oEn_3(),
+		 
+		// I2C 
+		.SDA_in_1(SDA_IN_pad2core[15:0]),            .SDA_in_2(SDA_IN_pad2core[15:0]),       .SDA_in_3(SDA_IN_pad2core[15:0]),
+		.SDA_out_inv_1(SDA_OUT_core2pad[15:0]),      .SDA_out_inv_2(),                       .SDA_out_inv_3(),
+		.SCL_1(SCL_core2pad[15:0]),                  .SCL_2(),                               .SCL_3(),
+		.SCLEN_1(SCLEN_core2pad[15:0]),              .SCLEN_2(),                             .SCLEN_3(),
+
+		// JTAG 
+		.JTAG_TMS_pad_o_1(TMS_core2pad),             .JTAG_TMS_pad_o_2(),                    .JTAG_TMS_pad_o_3(),
+		.JTAG_TCK_pad_o_1(TCK_core2pad),             .JTAG_TCK_pad_o_2(),                    .JTAG_TCK_pad_o_3(),
+		.JTAG_TDO_pad_o_1(TDO_core2pad),             .JTAG_TDO_pad_o_2(),                    .JTAG_TDO_pad_o_3(),
+		.JTAG_TDI_pad_i_1(TDI_pad2core),             .JTAG_TDI_pad_i_2(TDI_pad2core),        .JTAG_TDI_pad_i_3(TDI_pad2core),
+		.JTAG_RST_pad_o_1(RST_pad_o),                .JTAG_RST_pad_o_2(),                    .JTAG_RST_pad_o_3(),
+
+		// SPI 
+		.SPI_miso_pad_i_1(SPI_miso_pad2core),        .SPI_miso_pad_i_2(SPI_miso_pad2core),   .SPI_miso_pad_i_3(SPI_miso_pad2core),
+		.SPI_mosi_pad_o_1(SPI_mosi_core2pad),        .SPI_mosi_pad_o_2(),                    .SPI_mosi_pad_o_3(),
+		.SPI_sclk_pad_o_1(SPI_sclk_core2pad),        .SPI_sclk_pad_o_2(),                    .SPI_sclk_pad_o_3(),
+		.SPI_ss_pad_o_1(ss_pad_o[7:0]),              .SPI_ss_pad_o_2(),                      .SPI_ss_pad_o_3(),
+
+		// GPIO 
+		.GPIO_clk_pad_i_1(gpio_clk_pad2core),        .GPIO_clk_pad_i_2(gpio_clk_pad2core),   .GPIO_clk_pad_i_3(gpio_clk_pad2core),
+		.GPIO_ext_pad_i_1(GPIO_pad2core[31:0]),      .GPIO_ext_pad_i_2(GPIO_pad2core[31:0]), .GPIO_ext_pad_i_3(GPIO_pad2core[31:0]),
+		.GPIO_ext_padOE_o_1(GPIO_oe_core2pad[31:0]), .GPIO_ext_padOE_o_2(),                  .GPIO_ext_padOE_o_3(),
+		.GPIO_ext_pad_o_1(GPIO_out_core2pad[31:0]),  .GPIO_ext_pad_o_2(),                    .GPIO_ext_pad_o_3(),
+
+		// DAC
+		.anaDAC_A_1(DAC0),                           .anaDAC_A_2(),                          .anaDAC_A_3(),
+		.anaDAC_B_1(DAC1),                           .anaDAC_B_2(),                          .anaDAC_B_3(),
+		.anaDAC_C_1(DAC2),                           .anaDAC_C_2(),                          .anaDAC_C_3(),
+		.anaDAC_D_1(DAC3),                           .anaDAC_D_2(),                          .anaDAC_D_3(),  
+
+		// ADC 
+		.ADC_wb_RES_1(ADC_wb_RES),                   .ADC_wb_RES_2(),                        .ADC_wb_RES_3(),
+		.ADC_wb_CLK_1(ADC_wb_CLK),                   .ADC_wb_CLK_2(),                        .ADC_wb_CLK_3(),
+		.ADC_wb_SEL_1(),                             .ADC_wb_SEL_2(),                        .ADC_wb_SEL_3(),
+		.ADC_wb_WE_1(ADC_wb_WE),                     .ADC_wb_WE_2(),                         .ADC_wb_WE_3(),
+		.ADC_wb_STB_1(ADC_wb_STB),                   .ADC_wb_STB_2(),                        .ADC_wb_STB_3(),
+		.ADC_wb_CYC_1(ADC_wb_CYC),                   .ADC_wb_CYC_2(),                        .ADC_wb_CYC_3(),
+		.ADC_wb_ADR_1(ADC_wb_ADR),                   .ADC_wb_ADR_2(),                        .ADC_wb_ADR_3(),
+		.ADC_wb_DATi_1(ADC_wb_DATi),                 .ADC_wb_DATi_2(),                       .ADC_wb_DATi_3(),
+		.ADC_wb_DATo_1(ADC_wb_DATo),                 .ADC_wb_DATo_2(ADC_wb_DATo),            .ADC_wb_DATo_3(ADC_wb_DATo),
+		.ADC_wb_ACK_1(ADC_wb_ACK),                   .ADC_wb_ACK_2(ADC_wb_ACK),              .ADC_wb_ACK_3(ADC_wb_ACK),
+		.ADC_wb_INT_1(ADC_wb_INT),                   .ADC_wb_INT_2(ADC_wb_INT),              .ADC_wb_INT_3(ADC_wb_INT)  
+	);
+          
+	OC_PONtop Power_on_rst (
+		.globalReset(reset_b_pad2core),
+		.globalResetA(PowerUpReset_1), 
+		.globalResetB(PowerUpReset_2), 
+		.globalResetC(PowerUpReset_3)  
+	);
+        
+	anaBlock analog_block1 (        
+		.Clk_I(ADC_wb_CLK),
+		.Reset_I(ADC_wb_RES),
+		.ADR_I(ADC_wb_ADR),
+		.CYC_I(ADC_wb_CYC),
+		.DAT_I(ADC_wb_DATi),  
+		.STB_I(ADC_wb_STB),
+		.WE_I(ADC_wb_WE),
+		.ACK_O(ADC_wb_ACK),
+		.DAT_O(ADC_wb_DATo),
+		.DoneConv(ADC_wb_INT),
+		.DAC0(DAC0),                      // to logic
+		.DAC1(DAC1),                      // to logic
+		.DAC2(DAC2),                      // to logic
+		.DAC3(DAC3),                      // to logic                
+		.Reset_BG(Reset_BG),              // reset band gap  negatif  doit etre present 2015
+		.AVDD33(VDD33),                   // to PAD 
+		.ADC_in(ADC_analog_in[30:0]),     // to PAD 
+		.DAC_out(analog2pad[3:0]),        // to PAD
+		.CURR_out(Pad_current_out[30:0]), // to PAD
+		.FuseProgramPulse(FuseProgramPulse)
+	);
+
+
+endmodule 
+
+
+
+
+`timescale 1ns / 1ps
+module top_pad (SPI_ss_pad, TMS_pad, TDO_pad, SPI_clk_pad, RESET_B_pad,
+                SPI_mosi_pad,  DAC_out_pad, TCK_pad,
+                SPI_miso_pad, SCL_pad, rx_sd_aux, tx_sd_aux, tx_sd_aux_n,link_clk_n, tx_sd,
+                rx_sd_n, link_clk, pwr3_3pad, ADC_in_pad, link_clk_aux_n,
+                tx_sd_n, rx_sd_aux_n, link_clk_aux, SDA_pad,
+                rx_sd, TDI_pad, JTAG_reset_pad, GPIO_pad, link_aux_disable_pad, FuseProgramPulse_pad,
+                pad_GPIO_EXTCLK,  
+                auxPortSDA_pad, auxPortSCL_pad, auxPortTestEn_pad 
+                //SCAN_EN_pad,SCAN_MODE_pad,SCAN_IN_pad
+                );
+ 
+  output [7:0] SPI_ss_pad;
+  wire [7:0] SPI_ss_pad;
+  output TMS_pad;
+  wire TMS_pad;
+  output TDO_pad;
+  wire TDO_pad;
+  output SPI_clk_pad;
+  wire SPI_clk_pad;
+  input RESET_B_pad;
+  wire RESET_B_pad;
+  output SPI_mosi_pad;
+  wire SPI_mosi_pad; 
+  output [3:0] DAC_out_pad;
+  wire [3:0] DAC_out_pad;
+  output TCK_pad;
+  wire TCK_pad;
+  input SPI_miso_pad;
+  wire SPI_miso_pad;
+  output [15:0] SCL_pad;
+  wire [15:0] SCL_pad;
+  input rx_sd_aux;
+  wire rx_sd_aux;
+  output tx_sd_aux;
+  wire tx_sd_aux;
+  output tx_sd_aux_n;
+  wire tx_sd_aux_n;
+  input pad_GPIO_EXTCLK;
+  wire pad_GPIO_EXTCLK;
+  input link_aux_disable_pad;
+  wire link_aux_disable_pad;
+  input FuseProgramPulse_pad;
+  wire FuseProgramPulse_pad;
+  input link_clk_n;
+  wire link_clk_n;
+  output tx_sd;
+  wire tx_sd;
+  input rx_sd_n;
+  wire rx_sd_n;
+  input link_clk;
+  wire link_clk;
+  input pwr3_3pad;
+  wire pwr3_3pad;
+  input [30:0] ADC_in_pad;
+  wire [30:0] ADC_in_pad;
+  input link_clk_aux_n;
+  wire link_clk_aux_n;
+  output tx_sd_n;
+  wire tx_sd_n;
+  input rx_sd_aux_n;
+  wire rx_sd_aux_n;
+  input link_clk_aux;
+  wire link_clk_aux;
+  inout [15:0] SDA_pad;
+  wire [15:0] SDA_pad;
+  input rx_sd;
+  wire rx_sd;
+  input TDI_pad;
+  wire TDI_pad;
+  output JTAG_reset_pad;
+  wire JTAG_reset_pad;
+  inout [31:0] GPIO_pad;
+  wire [31:0] GPIO_pad;
+  wire [15:0] SDA_OUT_core2pad;
+  wire [15:0] SDA_IN_pad2core;
+  wire [15:0] SCL_core2pad;
+  wire SPI_miso_pad2core;
+  wire [31:0] GPIO_oe_core2pad;
+  wire TCK_core2pad;
+  wire [3:0] analog2pad;
+  wire TDI_pad2core;
+  wire rx_sd_pad2core;
+  wire TDO_core2pad;
+  wire pad_GPIO_EXTCLK_pad2core;
+  wire link_clk_pad2core;
+  wire rx_sd_aux_pad2core;
+  wire [31:0] GPIO_pad2core;
+  wire reset_b_pad2core;
+  wire [7:0] CRE;
+  wire SPI_mosi_core2pad;
+  wire TMS_core2pad;
+  wire RST_pad_o;
+  wire [7:0] ss_pad_o;
+  wire SPI_sclk_core2pad;
+  wire [31:0] GPIO_out_core2pad;
+  wire tx_sd_aux_core2pad;
+  wire tx_sd_core2pad;
+  wire [30:0] ADC_analog_in;
+  wire [30:0] Pad_current_out;  //------------------------2015
+  wire link_clk_aux_pad2core;
+  wire DVDD;  
+  wire DVSS;
+  wire AGND;
+  wire AVDD;
+  wire GND;
+  wire VDD33;
+  wire auxPort_TestEn_pad2core;
+  wire auxPort_SCL_pad2core;
+  wire auxPort_SDA_in_pad2core;   
+  wire auxPort_SDA_out_core2pad;
+  wire auxPort_SDA_oEn_core2pad; 
+  inout auxPortSDA_pad;
+  wire  auxPortSDA_pad;
+  input auxPortSCL_pad;
+  wire  auxPortSCL_pad;
+  input auxPortTestEn_pad;
+  wire  auxPortTestEn_pad;
+  wire  [15:0] SCLEN_core2pad;
+     
+     
+      
+SCA_TOP SCA_TOP(
+        // Elink HDLC //////////////////////////
+        .link_clk_pad2core(link_clk_pad2core),
+        .link_clk_aux_pad2core(link_clk_aux_pad2core),
+        .disable_Elink_aux(disable_Elink_aux),
+        .tx_sd_core2pad(tx_sd_core2pad),
+        .tx_sd_aux_core2pad(tx_sd_aux_core2pad),
+        .rx_sd_pad2core(rx_sd_pad2core),
+        .rx_sd_aux_pad2core(rx_sd_aux_pad2core),
+        .CRE(CRE),
+        // JTAG ////////////////////////////////
+        .TCK_core2pad(TCK_core2pad),
+        .TMS_core2pad(TMS_core2pad),
+        .TDO_core2pad(TDO_core2pad),
+        .TDI_pad2core(TDI_pad2core),
+        .RST_pad_o(RST_pad_o),      
+        // SPI /////////////////////////////////
+        .SPI_sclk_core2pad(SPI_sclk_core2pad),
+        .ss_pad_o(ss_pad_o),
+        .SPI_miso_pad2core(SPI_miso_pad2core),
+        .SPI_mosi_core2pad(SPI_mosi_core2pad),    
+        // GPIO ////////////////////////////////
+        .GPIO_out_core2pad(GPIO_out_core2pad),
+        .GPIO_oe_core2pad(GPIO_oe_core2pad),
+        .gpio_clk_pad2core(pad_GPIO_EXTCLK_pad2core),
+        .GPIO_pad2core(GPIO_pad2core),       
+        //I2C //////////////////////////////////
+        .SCL_core2pad(SCL_core2pad),
+        .SDA_IN_pad2core(SDA_IN_pad2core),
+        .SDA_OUT_core2pad(SDA_OUT_core2pad), 
+	.SCLEN_core2pad(SCLEN_core2pad), 
+        // Analog Pads /////////////////////////
+        .FuseProgramPulse(FuseProgramPulse),//EFuses program pulse
+	.VDD33(VDD33),   // 2015
+        .reset_b_pad2core(reset_b_pad2core),//reset pad
+        .ADC_analog_in(ADC_analog_in),//ADC analog input
+	.Pad_current_out(Pad_current_out),    //---------------2015
+        .analog2pad(analog2pad),
+        // Auxiliary i2c port /////////////////
+        .auxPort_TestEn(auxPort_TestEn_pad2core),  
+        .auxPort_SCL(auxPort_SCL_pad2core),        
+        .auxPort_SDA_in(auxPort_SDA_in_pad2core),  
+        .auxPort_SDA_out(auxPort_SDA_out_core2pad),
+        .auxPort_SDA_oEn(auxPort_SDA_oEn_core2pad)
+  );
+
+
+  
+  SIOB04_B  PAD_AUX_SDA //inout
+    (
+     .PAD(auxPortSDA_pad),
+     .Z(),
+     .ZH(auxPort_SDA_in_pad2core),
+     .A(auxPort_SDA_out_core2pad),
+     .RG(1'b1),
+     .TS(auxPort_SDA_oEn_core2pad)
+     );
+ 
+   SIOB04_B  PAD_AUX_SCL //in
+    (
+     .PAD(auxPortSCL_pad),
+     .Z(),
+     .ZH(auxPort_SCL_pad2core),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(1'b0)
+     );
+ 
+    SIOB04_B  PAD_AUX_EN //in
+    (
+     .PAD(auxPortTestEn_pad),
+     .Z(),
+     .ZH(auxPort_TestEn_pad2core),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(1'b0)
+     );
+
+   
+   
+   
+   
+   
+   
+   SIOB08_B  PAD_I2C_CLK15//modif 26october2015
+    (
+     .PAD(SCL_pad[15]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[15]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[15])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK14//modif 26october2015
+    (
+     .PAD(SCL_pad[14]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[14]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[14])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK13//modif 26october2015
+    (
+     .PAD(SCL_pad[13]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[13]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[13])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK12//modif 26october2015
+    (
+     .PAD(SCL_pad[12]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[12]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[12])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK11//modif 26october2015
+    (
+     .PAD(SCL_pad[11]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[11]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[11])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK10//modif 26october2015
+    (
+     .PAD(SCL_pad[10]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[10]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[10])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK9//modif 26october2015
+    (
+     .PAD(SCL_pad[9]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[9]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[9])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK8//modif 26october2015
+    (
+     .PAD(SCL_pad[8]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[8]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[8])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK7//modif 26october2015
+    (
+     .PAD(SCL_pad[7]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[7]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[7])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK6//modif 26october2015
+    (
+     .PAD(SCL_pad[6]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[6]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[6])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK5//modif 26october2015
+    (
+     .PAD(SCL_pad[5]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[5]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[5])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK4//modif 26october2015
+    (
+     .PAD(SCL_pad[4]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[4]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[4])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK3//modif 26october2015
+    (
+     .PAD(SCL_pad[3]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[3]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[3])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK2//modif 26october2015
+    (
+     .PAD(SCL_pad[2]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[2]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[2])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK1//modif 26october2015
+    (
+     .PAD(SCL_pad[1]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[1]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[1])
+     );
+ 
+  SIOB08_B  PAD_I2C_CLK0  //modif 26october2015
+    (
+     .PAD(SCL_pad[0]),
+     .Z(),
+     .ZH(),
+     .A(SCL_core2pad[0]),
+     .RG(1'b0),
+     .TS(SCLEN_core2pad[0])
+     ); 
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+
+  SIOB04_B  PAD_GPIO31
+    (
+     .PAD(GPIO_pad[31]),
+     .Z(),
+     .ZH(GPIO_pad2core[31]),
+     .A(GPIO_out_core2pad[31]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[31])
+     );
+ 
+  SIOB04_B  PAD_GPIO30
+    (
+     .PAD(GPIO_pad[30]),
+     .Z(),
+     .ZH(GPIO_pad2core[30]),
+     .A(GPIO_out_core2pad[30]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[30])
+     );
+ 
+  SIOB04_B  PAD_GPIO29
+    (
+     .PAD(GPIO_pad[29]),
+     .Z(),
+     .ZH(GPIO_pad2core[29]),
+     .A(GPIO_out_core2pad[29]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[29])
+     );
+ 
+  SIOB04_B  PAD_GPIO28
+    (
+     .PAD(GPIO_pad[28]),
+     .Z(),
+     .ZH(GPIO_pad2core[28]),
+     .A(GPIO_out_core2pad[28]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[28])
+     );
+ 
+  SIOB04_B  PAD_GPIO27
+    (
+     .PAD(GPIO_pad[27]),
+     .Z(),
+     .ZH(GPIO_pad2core[27]),
+     .A(GPIO_out_core2pad[27]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[27])
+     );
+ 
+  SIOB04_B  PAD_GPIO26
+    (
+     .PAD(GPIO_pad[26]),
+     .Z(),
+     .ZH(GPIO_pad2core[26]),
+     .A(GPIO_out_core2pad[26]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[26])
+     );
+ 
+  SIOB04_B  PAD_GPIO25
+    (
+     .PAD(GPIO_pad[25]),
+     .Z(),
+     .ZH(GPIO_pad2core[25]),
+     .A(GPIO_out_core2pad[25]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[25])
+     );
+ 
+  SIOB04_B  PAD_GPIO24
+    (
+     .PAD(GPIO_pad[24]),
+     .Z(),
+     .ZH(GPIO_pad2core[24]),
+     .A(GPIO_out_core2pad[24]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[24])
+     );
+ 
+  SIOB04_B  PAD_GPIO23
+    (
+     .PAD(GPIO_pad[23]),
+     .Z(),
+     .ZH(GPIO_pad2core[23]),
+     .A(GPIO_out_core2pad[23]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[23])
+     );
+ 
+  SIOB04_B  PAD_GPIO22
+    (
+     .PAD(GPIO_pad[22]),
+     .Z(),
+     .ZH(GPIO_pad2core[22]),
+     .A(GPIO_out_core2pad[22]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[22])
+     );
+ 
+  SIOB04_B  PAD_GPIO21
+    (
+     .PAD(GPIO_pad[21]),
+     .Z(),
+     .ZH(GPIO_pad2core[21]),
+     .A(GPIO_out_core2pad[21]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[21])
+     );
+ 
+  SIOB04_B  PAD_GPIO20
+    (
+     .PAD(GPIO_pad[20]),
+     .Z(),
+     .ZH(GPIO_pad2core[20]),
+     .A(GPIO_out_core2pad[20]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[20])
+     );
+ 
+  SIOB04_B  PAD_GPIO19
+    (
+     .PAD(GPIO_pad[19]),
+     .Z(),
+     .ZH(GPIO_pad2core[19]),
+     .A(GPIO_out_core2pad[19]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[19])
+     );
+ 
+  SIOB04_B  PAD_GPIO18
+    (
+     .PAD(GPIO_pad[18]),
+     .Z(),
+     .ZH(GPIO_pad2core[18]),
+     .A(GPIO_out_core2pad[18]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[18])
+     );
+ 
+  SIOB04_B  PAD_GPIO17
+    (
+     .PAD(GPIO_pad[17]),
+     .Z(),
+     .ZH(GPIO_pad2core[17]),
+     .A(GPIO_out_core2pad[17]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[17])
+     );
+ 
+  SIOB04_B  PAD_GPIO16
+    (
+     .PAD(GPIO_pad[16]),
+     .Z(),
+     .ZH(GPIO_pad2core[16]),
+     .A(GPIO_out_core2pad[16]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[16])
+     );
+ 
+  SIOB04_B  PAD_GPIO15
+    (
+     .PAD(GPIO_pad[15]),
+     .Z(),
+     .ZH(GPIO_pad2core[15]),
+     .A(GPIO_out_core2pad[15]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[15])
+     );
+ 
+  SIOB04_B  PAD_GPIO14
+    (
+     .PAD(GPIO_pad[14]),
+     .Z(),
+     .ZH(GPIO_pad2core[14]),
+     .A(GPIO_out_core2pad[14]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[14])
+     );
+ 
+  SIOB04_B  PAD_GPIO13
+    (
+     .PAD(GPIO_pad[13]),
+     .Z(),
+     .ZH(GPIO_pad2core[13]),
+     .A(GPIO_out_core2pad[13]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[13])
+     );
+ 
+  SIOB04_B  PAD_GPIO12
+    (
+     .PAD(GPIO_pad[12]),
+     .Z(),
+     .ZH(GPIO_pad2core[12]),
+     .A(GPIO_out_core2pad[12]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[12])
+     );
+ 
+  SIOB04_B  PAD_GPIO11
+    (
+     .PAD(GPIO_pad[11]),
+     .Z(),
+     .ZH(GPIO_pad2core[11]),
+     .A(GPIO_out_core2pad[11]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[11])
+     );
+ 
+  SIOB04_B  PAD_GPIO10
+    (
+     .PAD(GPIO_pad[10]),
+     .Z(),
+     .ZH(GPIO_pad2core[10]),
+     .A(GPIO_out_core2pad[10]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[10])
+     );
+ 
+  SIOB04_B  PAD_GPIO9
+    (
+     .PAD(GPIO_pad[9]),
+     .Z(),
+     .ZH(GPIO_pad2core[9]),
+     .A(GPIO_out_core2pad[9]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[9])
+     );
+ 
+  SIOB04_B  PAD_GPIO8
+    ( 
+     .PAD(GPIO_pad[8]),
+     .Z(),
+     .ZH(GPIO_pad2core[8]),
+     .A(GPIO_out_core2pad[8]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[8])
+     );
+ 
+  SIOB04_B  PAD_GPIO7
+    (
+     .PAD(GPIO_pad[7]),
+     .Z(),
+     .ZH(GPIO_pad2core[7]),
+     .A(GPIO_out_core2pad[7]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[7])
+     );
+ 
+  SIOB04_B  PAD_GPIO6
+    (
+     .PAD(GPIO_pad[6]),
+     .Z(),
+     .ZH(GPIO_pad2core[6]),
+     .A(GPIO_out_core2pad[6]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[6])
+     );
+ 
+  SIOB04_B  PAD_GPIO5
+    (
+     .PAD(GPIO_pad[5]),
+     .Z(),
+     .ZH(GPIO_pad2core[5]),
+     .A(GPIO_out_core2pad[5]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[5])
+     );
+ 
+  SIOB04_B  PAD_GPIO4
+    (
+     .PAD(GPIO_pad[4]),
+     .Z(),
+     .ZH(GPIO_pad2core[4]),
+     .A(GPIO_out_core2pad[4]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[4])
+     );
+ 
+  SIOB04_B  PAD_GPIO3
+    (
+     .PAD(GPIO_pad[3]),
+     .Z(),
+     .ZH(GPIO_pad2core[3]),
+     .A(GPIO_out_core2pad[3]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[3])
+     );
+ 
+  SIOB04_B  PAD_GPIO2
+    (
+     .PAD(GPIO_pad[2]),
+     .Z(),
+     .ZH(GPIO_pad2core[2]),
+     .A(GPIO_out_core2pad[2]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[2])
+     );
+ 
+  SIOB04_B  PAD_GPIO1
+    (
+     .PAD(GPIO_pad[1]),
+     .Z(),
+     .ZH(GPIO_pad2core[1]),
+     .A(GPIO_out_core2pad[1]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[1])
+     );
+ 
+  SIOB04_B  PAD_GPIO0
+    (
+     .PAD(GPIO_pad[0]),
+     .Z(),
+     .ZH(GPIO_pad2core[0]),
+     .A(GPIO_out_core2pad[0]),
+     .RG(1'b1),
+     .TS(GPIO_oe_core2pad[0])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA15
+    (
+     .PAD(SDA_pad[15]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[15]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[15])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA14
+    (
+     .PAD(SDA_pad[14]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[14]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[14])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA13
+    (
+     .PAD(SDA_pad[13]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[13]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[13])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA12
+    (
+     .PAD(SDA_pad[12]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[12]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[12])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA11
+    (
+     .PAD(SDA_pad[11]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[11]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[11])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA10
+    (
+     .PAD(SDA_pad[10]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[10]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[10])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA9
+    (
+     .PAD(SDA_pad[9]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[9]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[9])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA8
+    (
+     .PAD(SDA_pad[8]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[8]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[8])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA7
+    (
+     .PAD(SDA_pad[7]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[7]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[7])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA6
+    (
+     .PAD(SDA_pad[6]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[6]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[6])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA5
+    (
+     .PAD(SDA_pad[5]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[5]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[5])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA4
+    (
+     .PAD(SDA_pad[4]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[4]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[4])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA3
+    (
+     .PAD(SDA_pad[3]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[3]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[3])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA2
+    (
+     .PAD(SDA_pad[2]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[2]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[2])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA1
+    (
+     .PAD(SDA_pad[1]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[1]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[1])
+     );
+ 
+  SIOB08_B  PAD_I2C_SDA0
+    (
+     .PAD(SDA_pad[0]),
+     .Z(),
+     .ZH(SDA_IN_pad2core[0]),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(SDA_OUT_core2pad[0])
+     );
+ 
+  SIOB12_B  PAD_JTAG_TMS
+    (
+     .PAD(TMS_pad),
+     .Z(),
+     .ZH(),
+     .A(TMS_core2pad),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+  SIOB12_B  PAD_JTAG_TCK
+    (
+     .PAD(TCK_pad),
+     .Z(),
+     .ZH(),
+     .A(TCK_core2pad),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+  SIOB12_B  PAD_JTAG_TDO
+    (
+     .PAD(TDO_pad),
+     .Z(),
+     .ZH(),
+     .A(TDO_core2pad),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+  SIOB12_B  PAD_SPI_clk /////////////////////////// 18nov
+    (
+     .PAD(SPI_clk_pad),
+     .Z(),
+     .ZH(),
+     .A(SPI_sclk_core2pad),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+  SIOB12_B  PAD_SPI_mosi
+    (
+     .PAD(SPI_mosi_pad),
+     .Z(),
+     .ZH(),
+     .A(SPI_mosi_core2pad),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+  SIOB12_B  PAD_SPI_miso
+    (
+     .PAD(SPI_miso_pad),
+     .Z(),
+     .ZH(SPI_miso_pad2core),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(1'b0)
+     );
+ 
+  SIOB04_B  PAD_SPI_ss7
+    (
+     .PAD(SPI_ss_pad[7]),
+     .Z(),
+     .ZH(),
+     .A(ss_pad_o[7]),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+  SIOB04_B  PAD_SPI_ss6
+    (
+     .PAD(SPI_ss_pad[6]),
+     .Z(),
+     .ZH(),
+     .A(ss_pad_o[6]),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+  SIOB04_B  PAD_SPI_ss5
+    (
+     .PAD(SPI_ss_pad[5]),
+     .Z(),
+     .ZH(),
+     .A(ss_pad_o[5]),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+  SIOB04_B  PAD_SPI_ss4
+    (
+     .PAD(SPI_ss_pad[4]),
+     .Z(),
+     .ZH(),
+     .A(ss_pad_o[4]),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+  SIOB04_B  PAD_SPI_ss3
+    (
+     .PAD(SPI_ss_pad[3]),
+     .Z(),
+     .ZH(),
+     .A(ss_pad_o[3]),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+  SIOB04_B  PAD_SPI_ss2
+    (
+     .PAD(SPI_ss_pad[2]),
+     .Z(),
+     .ZH(),
+     .A(ss_pad_o[2]),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+  SIOB04_B  PAD_SPI_ss1
+    (
+     .PAD(SPI_ss_pad[1]),
+     .Z(),
+     .ZH(),
+     .A(ss_pad_o[1]),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+  SIOB04_B  PAD_SPI_ss0
+    (
+     .PAD(SPI_ss_pad[0]),
+     .Z(),
+     .ZH(),
+     .A(ss_pad_o[0]),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+  SIOB12_B  PAD_JTAG_TDI
+    (
+     .PAD(TDI_pad),
+     .Z(),
+     .ZH(TDI_pad2core),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(1'b0)
+     );
+ 
+  Eport_TX  PAD_TX_SD
+    (
+     .outp(tx_sd),
+     .in(tx_sd_core2pad),
+     .cset(CRE[3:0]),
+     .off(),
+     .outn(tx_sd_n),
+     .DVSS(DVSS),
+     .DVDD(DVDD)
+     );
+ 
+  Eport_TX  PAD_TX_SD_AUX
+    (
+     .outp(tx_sd_aux),
+     .in(tx_sd_aux_core2pad),
+     .cset(CRE[3:0]),
+     .off(),
+     .outn(tx_sd_aux_n),
+     .DVSS(DVSS),
+     .DVDD(DVDD)
+     );
+ 
+  wire term_clk_ctrl;
+  NAND2_B test_term_clk_nand(.A (disable_Elink_aux), .B (auxPort_TestEn_pad2core), .Z (term_clk_ctrl)); 
+   
+  Eport_RX  PAD_LINK_CLK
+    (
+     .inn(link_clk_n),
+     .term(term_clk_ctrl),
+     .inp(link_clk),
+     .DVDD(DVDD),
+     .off(1'b0),
+     .DVSS(DVSS),
+     .out(link_clk_pad2core)
+     );
+ 
+  Eport_RX  PAD_LINK_CLK_AUX
+    (
+     .inn(link_clk_aux_n),
+     .term(1'b1),
+     .inp(link_clk_aux),
+     .DVDD(DVDD),
+     .off(1'b0),
+     .DVSS(DVSS),
+     .out(link_clk_aux_pad2core)
+     );
+ 
+  Eport_RX  PAD_RX_SD
+    (
+     .inn(rx_sd_n),
+     .term(1'b1),
+     .inp(rx_sd),
+     .DVDD(DVDD),
+     .off(1'b0),
+     .DVSS(DVSS),
+     .out(rx_sd_pad2core)
+     );
+
+   SIOB04_B  PAD_LINK_AUX_DISABLE
+    (
+     .PAD(link_aux_disable_pad),
+     .Z(),
+     .ZH(disable_Elink_aux),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(1'b0)
+     );
+
+   SIOB04_B  PAD_FUSE_PRG
+    (
+     .PAD(FuseProgramPulse_pad),
+     .Z(),
+     .ZH(FuseProgramPulse),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(1'b0)
+     );
+
+
+  SIOVDD  PAD_VDD3
+    (
+ 
+     );
+ 
+  SIOVDD  PAD_VDD2
+    (
+ 
+     );
+ 
+  SIOVDD  PAD_VDD1
+    (
+ 
+     );
+ 
+  SIOVDD  PAD_VDD0
+    (
+ 
+     );
+ 
+  SIOGND  PAD_GND3
+    (
+ 
+     );
+ 
+  SIOGND  PAD_GND2
+    (
+ 
+     );
+ 
+  SIOGND  PAD_GND1
+    (
+ 
+     );
+ 
+  SIOGND  PAD_GND0
+    (
+ 
+     );
+ 
+  SIOWIRE_ESD_CDM_SB  PAD_DAC_OUT3
+    (
+     .PT(analog2pad[3]),
+     .PAD(DAC_out_pad[3])
+     );
+ 
+ 
+  SIOWIRE_ESD_CDM_SB  PAD_DAC_OUT2
+    (
+     .PT(analog2pad[2]),
+     .PAD(DAC_out_pad[2])
+     );
+ 
+  SIOWIRE_ESD_CDM_SB  PAD_DAC_OUT1
+    (
+     .PT(analog2pad[1]),
+     .PAD(DAC_out_pad[1])
+     );
+ 
+  SIOWIRE_ESD_CDM_SB  PAD_DAC_OUT0
+    (
+     .PT(analog2pad[0]),
+     .PAD(DAC_out_pad[0])
+     );
+ 
+  SIODVDD  PAD_DVDD5
+    (
+ 
+     );
+ 
+  SIODVDD  PAD_DVDD4
+    (
+ 
+     );
+ 
+  SIODVDD  PAD_DVDD3
+    (
+ 
+     );
+ 
+  SIODVDD  PAD_DVDD2
+    (
+ 
+     );
+ 
+  SIODVDD  PAD_DVDD1
+    (
+ 
+     );
+ 
+  SIODVDD  PAD_DVDD0
+    (
+ 
+     );
+ 
+  SIODVSS  PAD_DVSS5
+    (
+ 
+     );
+ 
+  SIODVSS  PAD_DVSS4
+    (
+ 
+     );
+ 
+  SIODVSS  PAD_DVSS3
+    (
+ 
+     );
+ 
+  SIODVSS  PAD_DVSS2
+    (
+ 
+     );
+ 
+  SIODVSS  PAD_DVSS1
+    (
+ 
+     );
+ 
+  SIODVSS  PAD_DVSS0
+    (
+ 
+     );
+ 
+   SIOAGND_SB  PAD_AGND2
+    (
+     .GND(AGND),
+     .DVSS(AGND)
+     );
+ 
+//  SIOWIRE_ESD_CDM_SB  PAD_ADC_EXTRES
+//    (
+//     .PT(resOut_pad2core),
+//     .PAD(pad_resOut)
+//     );
+ 
+SIO_ANALOG_INPAD   PAD_ADC_IN30
+    (
+     .PT(ADC_analog_in[30]),
+     .PAD(ADC_in_pad[30]),
+     .CurrentOut(Pad_current_out[30])     
+     );
+ 
+SIO_ANALOG_INPAD   PAD_ADC_IN29
+    (
+     .PT(ADC_analog_in[29]),
+     .PAD(ADC_in_pad[29]),
+     .CurrentOut(Pad_current_out[29])       
+     );
+ 
+SIO_ANALOG_INPAD   PAD_ADC_IN28
+    (
+     .PT(ADC_analog_in[28]),
+     .PAD(ADC_in_pad[28]),
+     .CurrentOut(Pad_current_out[28])      
+     );
+ 
+SIO_ANALOG_INPAD   PAD_ADC_IN27
+    (
+     .PT(ADC_analog_in[27]),
+     .PAD(ADC_in_pad[27]),
+     .CurrentOut(Pad_current_out[27])     
+     );
+ 
+SIO_ANALOG_INPAD   PAD_ADC_IN26
+    (
+     .PT(ADC_analog_in[26]),
+     .PAD(ADC_in_pad[26]),
+     .CurrentOut(Pad_current_out[26])      
+     );
+ 
+SIO_ANALOG_INPAD    PAD_ADC_IN25
+    (
+     .PT(ADC_analog_in[25]),
+     .PAD(ADC_in_pad[25]),
+     .CurrentOut(Pad_current_out[25])       
+     );
+ 
+SIO_ANALOG_INPAD    PAD_ADC_IN24
+    (
+     .PT(ADC_analog_in[24]),
+     .PAD(ADC_in_pad[24]),
+     .CurrentOut(Pad_current_out[24])      
+     );
+ 
+SIO_ANALOG_INPAD    PAD_ADC_IN23
+    (
+     .PT(ADC_analog_in[23]),
+     .PAD(ADC_in_pad[23]),
+     .CurrentOut(Pad_current_out[23])        
+     );
+ 
+SIO_ANALOG_INPAD   PAD_ADC_IN22
+    (
+     .PT(ADC_analog_in[22]),
+     .PAD(ADC_in_pad[22]),
+     .CurrentOut(Pad_current_out[22])        
+     );
+ 
+SIO_ANALOG_INPAD   PAD_ADC_IN21
+    (
+     .PT(ADC_analog_in[21]),
+     .PAD(ADC_in_pad[21]),
+     .CurrentOut(Pad_current_out[21])      
+     );
+ 
+SIO_ANALOG_INPAD   PAD_ADC_IN20
+    (
+     .PT(ADC_analog_in[20]),
+     .PAD(ADC_in_pad[20]),
+     .CurrentOut(Pad_current_out[20])      
+     );
+ 
+SIO_ANALOG_INPAD  PAD_ADC_IN19
+    (
+     .PT(ADC_analog_in[19]),
+     .PAD(ADC_in_pad[19]),
+     .CurrentOut(Pad_current_out[19])       
+     );
+ 
+SIO_ANALOG_INPAD  PAD_ADC_IN18
+    (
+     .PT(ADC_analog_in[18]),
+     .PAD(ADC_in_pad[18]),
+     .CurrentOut(Pad_current_out[18])      
+     );
+ 
+SIO_ANALOG_INPAD    PAD_ADC_IN17
+    (
+     .PT(ADC_analog_in[17]),
+     .PAD(ADC_in_pad[17]),
+     .CurrentOut(Pad_current_out[17])       
+     );
+ 
+SIO_ANALOG_INPAD      PAD_ADC_IN16
+    (
+     .PT(ADC_analog_in[16]),
+     .PAD(ADC_in_pad[16]),
+     .CurrentOut(Pad_current_out[16])       
+     );
+ 
+SIO_ANALOG_INPAD     PAD_ADC_IN15
+    (
+     .PT(ADC_analog_in[15]),
+     .PAD(ADC_in_pad[15]),
+     .CurrentOut(Pad_current_out[15])     
+     );
+ 
+SIO_ANALOG_INPAD      PAD_ADC_IN14
+    (
+     .PT(ADC_analog_in[14]),
+     .PAD(ADC_in_pad[14]),
+     .CurrentOut(Pad_current_out[14])      
+     );
+ 
+SIO_ANALOG_INPAD     PAD_ADC_IN13
+    (
+     .PT(ADC_analog_in[13]),
+     .PAD(ADC_in_pad[13]),
+     .CurrentOut(Pad_current_out[13])      
+     );
+ 
+SIO_ANALOG_INPAD    PAD_ADC_IN12
+    (
+     .PT(ADC_analog_in[12]),
+     .PAD(ADC_in_pad[12]),
+     .CurrentOut(Pad_current_out[12])       
+     );
+ 
+SIO_ANALOG_INPAD    PAD_ADC_IN11
+    (
+     .PT(ADC_analog_in[11]),
+     .PAD(ADC_in_pad[11]),
+     .CurrentOut(Pad_current_out[11])      
+     );
+ 
+SIO_ANALOG_INPAD     PAD_ADC_IN10
+    (
+     .PT(ADC_analog_in[10]),
+     .PAD(ADC_in_pad[10]),
+     .CurrentOut(Pad_current_out[10])      
+     );
+ 
+SIO_ANALOG_INPAD      PAD_ADC_IN9
+    (
+     .PT(ADC_analog_in[9]),
+     .PAD(ADC_in_pad[9]),
+     .CurrentOut(Pad_current_out[9])         
+     );
+ 
+SIO_ANALOG_INPAD     PAD_ADC_IN8
+    (
+     .PT(ADC_analog_in[8]),
+     .PAD(ADC_in_pad[8]),
+     .CurrentOut(Pad_current_out[8])       
+     );
+ 
+SIO_ANALOG_INPAD     PAD_ADC_IN7
+    (
+     .PT(ADC_analog_in[7]),
+     .PAD(ADC_in_pad[7]),
+     .CurrentOut(Pad_current_out[7])       
+     );
+ 
+SIO_ANALOG_INPAD    PAD_ADC_IN6
+    (
+     .PT(ADC_analog_in[6]),
+     .PAD(ADC_in_pad[6]),
+     .CurrentOut(Pad_current_out[6])          
+     );
+ 
+SIO_ANALOG_INPAD    PAD_ADC_IN5
+    (
+     .PT(ADC_analog_in[5]),
+     .PAD(ADC_in_pad[5]),
+     .CurrentOut(Pad_current_out[5])       
+     );
+ 
+SIO_ANALOG_INPAD    PAD_ADC_IN4
+    (
+     .PT(ADC_analog_in[4]),
+     .PAD(ADC_in_pad[4]),
+     .CurrentOut(Pad_current_out[4])      
+     );
+ 
+SIO_ANALOG_INPAD     PAD_ADC_IN3
+    (
+     .PT(ADC_analog_in[3]),
+     .PAD(ADC_in_pad[3]),
+     .CurrentOut(Pad_current_out[3])      
+     );
+ 
+SIO_ANALOG_INPAD     PAD_ADC_IN2
+    (
+     .PT(ADC_analog_in[2]),
+     .PAD(ADC_in_pad[2]),
+     .CurrentOut(Pad_current_out[2])     
+     );
+ 
+SIO_ANALOG_INPAD     PAD_ADC_IN1
+    (
+     .PT(ADC_analog_in[1]),
+     .PAD(ADC_in_pad[1]),
+     .CurrentOut(Pad_current_out[1])     
+     );
+ 
+/*  SIOWIRE_ESD_CDM_SB  PAD_ADC_IN0
+    (
+     .PT(ADC_analog_in[0]),
+     .PAD(ADC_in_pad[0])
+     );
+------------------------2015---------------*/
+ 
+SIO_ANALOG_INPAD  PAD_ADC_IN0
+    (
+     .PT(ADC_analog_in[0]),
+     .PAD(ADC_in_pad[0]),
+     .CurrentOut(Pad_current_out[0])
+     ); 
+
+ 
+ 
+   SIOB04_B  PAD_GPIO_EXTCLK
+    (
+     .PAD(pad_GPIO_EXTCLK),
+     .Z(),
+     .ZH(pad_GPIO_EXTCLK_pad2core),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(1'b0)
+     );       
+
+  SIOVDD  PAD_AVDD1
+    (
+      .VDD(AVDD)
+     );
+ 
+  SIOVDD  PAD_AVDD0
+    (
+      .VDD(AVDD)
+     );
+ 
+  SIOAGND_SB  PAD_AGND1
+    (
+      .GND(AGND),
+     .DVSS(AGND)
+     );
+ 
+  SIOAGND_SB  PAD_AGND0
+    (
+     .GND(AGND),
+     .DVSS(AGND) 
+     );
+ 
+  SIOB04_B  PAD_RESET_B
+    (
+     .PAD(RESET_B_pad),
+     .Z(),
+     .ZH(reset_b_pad2core),
+     .A(1'b0),
+     .RG(1'b1),
+     .TS(1'b0)
+     );
+ 
+  SIOWIRE_ESD33  PAD_3_3V
+    (
+     .PT(VDD33),  //.PT(pwr_3_3pad2core),
+     .PAD(pwr3_3pad),
+     .DVSS(DVSS)
+     );
+ 
+  SIOB12_B  PAD_JTAG_RST
+    (
+     .PAD(JTAG_reset_pad),
+     .Z(),
+     .ZH(),
+     .A(RST_pad_o),
+     .RG(1'b0),
+     .TS(1'b1)
+     );
+ 
+
+    
+  Eport_RX  PAD_RX_SD_AUX
+    (
+     .inn(rx_sd_aux_n),
+     .term(1'b1),
+     .inp(rx_sd_aux),
+     .DVDD(DVDD),
+     .off(1'b0),
+     .DVSS(DVSS),
+     .out(rx_sd_aux_pad2core)
+     );
+ 
+  SIOBREAK_SB  BREAK1
+    (
+     .DVSS(DVSS),
+     .DVSS_R(AGND)
+     );
+ 
+  SIOBREAK_SB  BREAK2
+    (
+     .DVSS(DVSS),
+     .DVSS_R(AGND)
+     );
+ 
+SIOFILL_AGND_AVDD_SB FILL_agnd0();
+SIOFILL_AGND_AVDD_SB FILL_agnd1();
+
+ 
+endmodule
+
+
+
+
diff --git a/vldb/code/Testbench/SCA-model/SEU_counter.v b/vldb/code/Testbench/SCA-model/SEU_counter.v
new file mode 100644
index 0000000..c94bcfb
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/SEU_counter.v
@@ -0,0 +1,517 @@
+
+/////////////////////////////////////////////////////////////////////////////
+// Design Name:....GBT_SCA                                                 //
+// Module Name:....SEU_counter + NCTR_majority_voter (TRI Version)         //
+// Description:....- Counter of Single event upset                         //
+//                 - Specific Majority Voter for reducing critical path    //
+// Company:........CERN (PH-ESE)                                           //
+// Made by:........Alessandro Caratelli                                    //
+//                                                                         //
+// Date:...........17/October/2013  - Created                              //
+//                 10/December/2013 - Changed                              //
+/////////////////////////////////////////////////////////////////////////////
+
+//`define cnt_TB
+//`define mjv_TB
+
+`include "global_defines.v"
+`define log4(N) ((N<4)?1:((N<16)?2:((N<64)?3:((N<256)?4:5)))) 
+
+`timescale 1ns/1ps
+module SEU_count_mono (
+
+	input  clk,
+	input  res,
+	input  clear,
+	input  err,
+	
+	output reg [15:0] SEU_count_o,
+	input      [15:0] SEU_count_i,
+	output reg [1:0]  cnt_o,
+	input      [1:0]  cnt_i,
+	output wire       inc_o,
+	input             inc_i
+	);
+	
+	always @(posedge clk or posedge res) begin
+            if(res)           SEU_count_o <= {16{1'b0}};
+            else if (clear)   SEU_count_o <= {16{1'b0}};
+            else if (inc_i)   SEU_count_o <= SEU_count_i + 16'h1;
+            else              SEU_count_o <= SEU_count_i;
+      end   
+	
+	always @(posedge clk or posedge res) begin
+		if(res) cnt_o <= 1'b0;           
+		else 	if(err) cnt_o <= (&cnt_i) ? 2'b01 : (cnt_i + 2'b01);   
+			else    cnt_o <= 2'b00;
+	end
+	
+	assign inc_o = (cnt_i == 2'b01);
+	
+endmodule
+
+`timescale 1ns/1ps		
+module SEU_voter # (
+	parameter  WIDTH = 1
+ 	)(
+	input      [(WIDTH-1):0] in1, in2, in3,
+	output reg [(WIDTH-1):0] out
+	);
+	
+	// synopsys template
+	
+	always @(*) out = vote (in1,in2,in3);	
+	
+	function vote_atom;
+		input in1,in2,in3;
+	begin
+		if (in1 != in2) vote_atom = in3;
+		else            vote_atom = in1;
+	end
+	endfunction
+	
+	function [(WIDTH-1):0] vote;
+		input   [(WIDTH-1):0]   in1, in2, in3;
+		integer i;
+	begin
+		for (i=0; i<WIDTH; i=i+1)
+			vote[i] = vote_atom( in1[i], in2[i], in3[i] );
+	end
+	endfunction
+    
+endmodule	
+
+`timescale 1ns/1ps	
+module SEU_counter(
+      input  clk_1,   clk_2,   clk_3,
+      input  res_1,   res_2,   res_3,
+      input  clear_1, clear_2, clear_3,
+      input  err_1,   err_2,   err_3, 
+      
+      output wire [15:0] SEU_count_1, 
+      output wire [15:0] SEU_count_2,
+      output wire [15:0] SEU_count_3
+      );  
+      
+	wire [15:0] SEU_count_1v, SEU_count_2v, SEU_count_3v;
+	wire  [1:0] cnt_1,        cnt_2,        cnt_3;
+	wire  [1:0] cnt_1v,       cnt_2v,       cnt_3v;
+	wire        inc_1,        inc_2,        inc_3;
+	wire        inc_1v,       inc_2v,       inc_3v;
+      
+	SEU_count_mono SEU_cnt_1 (
+ 		.clk(clk_1),
+		.res(res_1),
+		.clear(clear_1),
+		.err(err_1),
+		.SEU_count_o(SEU_count_1),
+		.SEU_count_i(SEU_count_1v),
+		.cnt_o(cnt_1),
+		.cnt_i(cnt_1v),
+		.inc_o(inc_1),
+		.inc_i(inc_1v)     
+      );
+      
+	SEU_count_mono SEU_cnt_2 (
+ 		.clk(clk_2),
+		.res(res_2),
+		.clear(clear_2),
+		.err(err_2),
+		.SEU_count_o(SEU_count_2),
+		.SEU_count_i(SEU_count_2v),
+		.cnt_o(cnt_2),
+		.cnt_i(cnt_2v),
+		.inc_o(inc_2),
+		.inc_i(inc_2v)     
+      );  
+          
+	SEU_count_mono SEU_cnt_3 (
+ 		.clk(clk_3),
+		.res(res_3),
+		.clear(clear_3),
+		.err(err_3),
+		.SEU_count_o(SEU_count_3),
+		.SEU_count_i(SEU_count_3v),
+		.cnt_o(cnt_3),
+		.cnt_i(cnt_3v),
+		.inc_o(inc_3),
+		.inc_i(inc_3v)     
+      ); 
+          
+      SEU_voter # (1+16+2) SEU_voter_1 (
+      	.in1({cnt_1[1:0],  inc_1,  SEU_count_1[15:0] }),
+      	.in2({cnt_2[1:0],  inc_2,  SEU_count_2[15:0] }),
+      	.in3({cnt_3[1:0],  inc_3,  SEU_count_3[15:0] }),
+      	.out({cnt_1v[1:0], inc_1v, SEU_count_1v[15:0]})
+      );
+      
+      SEU_voter # (1+16+2) SEU_voter_2 (
+      	.in1({cnt_2[1:0],  inc_2,  SEU_count_2[15:0] }),
+      	.in2({cnt_3[1:0],  inc_3,  SEU_count_3[15:0] }),
+      	.in3({cnt_1[1:0],  inc_1,  SEU_count_1[15:0] }),
+      	.out({cnt_2v[1:0], inc_2v, SEU_count_2v[15:0]})
+      );
+      
+      SEU_voter # (1+16+2) SEU_voter_3 (
+      	.in1({cnt_3[1:0],  inc_3,  SEU_count_3[15:0] }),
+      	.in2({cnt_1[1:0],  inc_1,  SEU_count_1[15:0] }),
+      	.in3({cnt_2[1:0],  inc_2,  SEU_count_2[15:0] }),
+      	.out({cnt_3v[1:0], inc_3v, SEU_count_3v[15:0]})
+      );
+
+
+endmodule
+
+`timescale 1ns/1ps
+module majority_error (
+	input  [460:0] in1, in2, in3,
+	output wire     err
+	);
+	reg  [459:0]   err0;
+	wire [114:0]   err1;
+	wire [28:0]    err2;
+	wire [6:0]     err3;
+	wire [1:0]     err4;
+	integer        i;
+	
+	function err_atom;
+		input in1,in2,in3;
+    	   begin
+		if (in1 != in2) err_atom = 1'b1;
+		else if (in2 != in3) err_atom = 1'b1;
+		     else err_atom = 1'b0;
+    	   end
+	endfunction
+
+	always @(*) for (i=0; i<460; i=i+1) err0[i] = err_atom(in1[i],in2[i],in3[i]);
+	
+	mvor4 me_or_0[114:0] (.Z(err1[114:0]), .A(err0[114:0]), .B(err0[229:115]), .C(err0[344:230]), .D(err0[459:345]));	
+	mvor4 me_or_1[27:0]  (.Z(err2[27:0]),  .A(err1[27:0]),  .B(err1[55:28]),   .C(err1[83:56]),   .D(err1[111:84]));
+	mvor3 me_or_1b       (.Z(err2[28]),    .A(err1[112]),   .B(err1[113]),     .C(err1[114]));	
+	mvor4 me_or_2[6:0]   (.Z(err3[6:0]),   .A(err2[6:0]),   .B(err2[13:7]),    .C(err2[20:14]),   .D(err2[27:21]));	
+	mvor4 me_or_3a       (.Z(err4[0]),     .A(err3[0]),     .B(err3[1]),       .C(err3[2]),       .D(err3[3]));
+	mvor4 me_or_3b       (.Z(err4[1]),     .A(err3[4]),     .B(err3[5]),       .C(err3[6]),       .D(err2[28]));
+	mvor2 me_or_4        (.Z(err),         .A(err4[0]),     .B(err4[1]));
+ 
+endmodule
+
+module mvor4(
+	input A,B,C,D,
+	output wire Z
+	);
+	// cadence dc::set_dont_touch or4b_inst
+	OR4_B or4b_inst (.Z(Z),.A(A),.B(B),.C(C),.D(D));
+endmodule
+module mvor3(
+	input A,B,C,
+	output wire Z
+	);
+	// cadence dc::set_dont_touch or3b_inst
+	OR3_B or3b_inst (.Z(Z),.A(A),.B(B),.C(C));
+endmodule
+module mvor2(
+	input A,B,
+	output wire Z
+	);
+	// cadence dc::set_dont_touch or2b_inst
+	OR2_B or2b_inst (.Z(Z),.A(A),.B(B));
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+	
+	
+/////////////////////////// TB //////////////////////////////	
+	
+`ifdef cnt_TB
+`timescale 1ps / 1ps
+module SEU_cnt_TB();	
+	//`define clk_skew
+      reg     res, clear, err;
+      reg     clk_1, clk_2, clk_3;
+      wire    [15:0] SEU_count_1, SEU_count_2, SEU_count_3; 
+      reg     [15:0] cnt_TB;
+	integer ran;	
+	initial begin
+		clk_1 = 1'b0; clk_2 = 1'b0; clk_3 = 1'b0; 
+		forever #(12500) clk_1 = ~clk_1;
+	end
+	
+	always @(clk_1) begin
+		`ifdef clk_skew
+			clk_2 = #({$random}%2000) clk_1;
+			clk_3 = #({$random}%2000) clk_1;
+		`else
+			clk_2 = clk_1; clk_3 = clk_1;
+		`endif
+	end
+	
+	initial begin
+		clear = 1'b0; err = 1'b0; ran = 1'b0;
+		#1000000;
+		forever #(50000+{$random}%500000) begin
+			err = 1'b1;
+			ran = (25000+{$random}%125000);
+			err = #ran 1'b0;
+		end
+	
+	end	
+	integer i;
+	always @ (posedge err) begin
+		@(posedge clk_1) cnt_TB = cnt_TB + 1;
+		if(err) @(posedge clk_1);
+		if(err) @(posedge clk_1);
+		if(err) @(posedge clk_1) if(err) cnt_TB = cnt_TB + 1;
+	end
+
+	
+	always @(negedge err) begin
+		#100;@(posedge clk_1)#100;
+		if (SEU_count_1 != cnt_TB) $display("@%d: Error_1! [%d][%d]",$time,SEU_count_1,cnt_TB);
+		if (SEU_count_1 != cnt_TB) $display("@%d: Error_1! [%d][%d]",$time,SEU_count_1,cnt_TB);
+		if (SEU_count_1 != cnt_TB) $display("@%d: Error_1! [%d][%d]",$time,SEU_count_1,cnt_TB);		
+	end
+	
+	initial begin
+		res = 1'b1;
+		cnt_TB = 0;
+		#200000; res = 1'b0;
+	end	
+      SEU_counter SEU_TB(
+		.clk_1(clk_1),
+		.clk_2(clk_2),
+		.clk_3(clk_3),
+		.res_1(res),
+		.res_2(res),
+		.res_3(res),
+		.clear_1(clear),
+		.clear_2(clear),
+		.clear_3(clear),
+		.err_1(err),
+		.err_2(err),
+		.err_3(err),
+		.SEU_count_1(SEU_count_1),
+		.SEU_count_2(SEU_count_2),
+		.SEU_count_3(SEU_count_3)
+      ); 
+endmodule
+`endif	
+
+`ifdef mjv_TB
+module TB();
+
+	parameter WIDTH = 445;
+	
+	reg   [(WIDTH-1):0]  in1, in2, in3;
+	wire  [(WIDTH-1):0]  out;
+	wire                 err;
+	
+ 	NodeCtrl_MajorityVoter # (
+		.WIDTH(445)
+	)MV_test(
+		.in1(in1), .in2(in2), .in3(in3),
+		.out(out), .err(err)
+	);	
+	
+	
+	initial begin
+		in1 = 0; 
+		in2 = 0; 
+		in3 = 0;
+	end
+	
+	initial forever #1000 begin
+			in1 = 1;
+			#100; in1 = 0;
+	end
+	
+	initial forever #1000 begin
+			in2 = 1;
+			#100; in2 = 0;
+	end	
+	initial forever #1000 begin
+			in3 = 1;
+			#100; in3 = 0;
+	end		
+endmodule	
+`endif	
+
+	
+	
+	
+	
+	
+	
+
+
+
+
+	
+////////////////// old version (monostable) //////////////////////////	
+	
+/*
+module SEU_counter(
+      input  clk_1,   clk_2,   clk_3,
+      input  res_1,   res_2,   res_3,
+      input  clear_1, clear_2, clear_3,
+      input  err_1,   err_2,   err_3, 
+      
+      output wire [15:0]  SEU_count_1, 
+      output reg  [15:0]  SEU_count_2,
+      output reg  [15:0]  SEU_count_3
+      );  
+      
+      reg  [15:0]  SEU_count;
+      wire inc, inc_1, inc_2, inc_3; 
+      
+      SEUmonostable SEU_mon1(.clk(clk_1), .res(res_1), .in(err_1), .out(inc_2));
+      SEUmonostable SEU_mon2(.clk(clk_2), .res(res_2), .in(err_2), .out(inc_3));
+      SEUmonostable SEU_mon3(.clk(clk_3), .res(res_3), .in(err_3), .out(inc)  );     
+      	
+      always @(posedge clk_1 or posedge res_1) begin
+            if(res_1)           SEU_count_2 <= {16{1'b0}};
+            else if (clear_1)   SEU_count_2 <= {16{1'b0}};
+            else if (inc_1)     SEU_count_2 <= SEU_count_1 + 16'h1;
+            else                SEU_count_2 <= SEU_count_1;
+      end   
+      always @(posedge clk_2 or posedge res_2) begin
+            if(res_2)           SEU_count_3 <= {16{1'b0}};
+            else if (clear_2)   SEU_count_3 <= {16{1'b0}};
+            else if (inc_2)     SEU_count_3 <= SEU_count_2 + 16'h1;
+            else                SEU_count_3 <= SEU_count_2;
+      end
+      always @(posedge clk_3 or posedge res_3) begin
+            if(res_3)           SEU_count <= {16{1'b0}};
+            else if (clear_3)   SEU_count <= {16{1'b0}};
+            else if (inc_3)     SEU_count <= SEU_count_3 + 16'h1;
+            else                SEU_count <= SEU_count_3;
+      end
+      
+      majority_voter #(.WIDTH(1)) mvMonostable (
+		.in1(inc_2),
+		.in2(inc_3),
+		.in3(inc),
+		.out(inc_1),
+		.err()
+	);	
+      majority_voter #(.WIDTH(16)) mv_SEUount (
+		.in1(SEU_count_2),
+		.in2(SEU_count_3),
+		.in3(SEU_count),
+		.out(SEU_count_1),
+		.err()
+	);	   
+endmodule
+
+module SEUmonostable(
+      input       clk,
+      input       res,
+      input       in,
+      output reg  out
+      ); 
+      wire areset;
+      reg  intq;
+      always@ (posedge in or posedge areset) 
+            if(areset)  intq <= 1'b0; 
+            else        intq <= 1'b1;
+      always@ (posedge clk or posedge res) 
+            if(res) out <= 1'b0;
+            else    out <= intq;
+      assign areset = (~clk & out)|res;     
+endmodule
+
+*/
+
+
+
+/*
+module single_vote (
+	input  i1, i2, i3,
+	output reg er
+	);
+	always @(*) begin
+		if (i1 != i2) er = 1'b1;
+		else 	if (i2 != i3) er = 1'b1;
+			else er = 1'b0;
+	end
+endmodule
+
+module or_mv # (
+	parameter dim = 445
+	)(
+	input  [dim-1:0] in,
+	output wire [dim/4:0] out
+);
+	genvar i;
+	or or1[dim/4-1:0] (
+		out[dim/4-1:0], 
+		in[(dim/4)-1:0],
+		in[(dim/4)*2-1:(dim/4)],
+		in[(dim/4)*3-1:(dim/4)*2],
+		in[(dim/4)*4-1:(dim/4*3)]
+	);
+	generate 
+	case (dim % 4) 
+		0: assign out[dim/4] = 1'b0;
+		1: assign out[dim/4] = in[dim-1];
+		2: or(out[dim/4],in[dim-1],in[dim-2]);
+		3: or(out[dim/4],in[dim-1],in[dim-2],in[dim-3]);
+	endcase 
+	endgenerate 
+endmodule	
+
+
+module NodeCtrl_ErrCnt 
+	input  [(WIDTH-1):0]  in1, in2, in3,
+	output                err
+	);
+	wire [(WIDTH-1):0]  vect0;
+	wire [WIDTH/4-1:0]  vect1;
+	wire [WIDTH/16-1:0] vect2;
+	wire [WIDTH/64-1:0] vect3;
+	genvar lev;
+		
+	single_vote svote[(WIDTH-1):0] (
+		.i1(in1[(WIDTH-1):0]),
+		.i2(in2[(WIDTH-1):0]),
+		.i3(in3[(WIDTH-1):0]),
+		.er(vect0[(WIDTH-1):0])
+	); 	
+
+	generate 
+		if(`log4(WIDTH)<2) assign err = (|vect0); 
+		else begin
+			or_mv #(.dim(WIDTH)) or_lev0 (.in(vect0[(WIDTH-1):0]) );	   
+			if(`log4(WIDTH)<3) assign err = (|vect1); 
+			else begin
+				or_mv #(.dim(WIDTH/4)) or_lev1 (.in(vect1[WIDTH/4-1:0]));
+				if(`log4(WIDTH)<4) assign err = (|vect2); 
+				else begin
+					or_mv #(.dim(WIDTH/16)) or_lev2 (.in(vect2[WIDTH/16-1:0]));
+					assign err = (|vect3);
+				end	
+			end
+		end	   		
+	endgenerate
+
+endmodule
+*/
+
+
diff --git a/vldb/code/Testbench/SCA-model/SPI_channel.v b/vldb/code/Testbench/SCA-model/SPI_channel.v
new file mode 100644
index 0000000..1239d20
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/SPI_channel.v
@@ -0,0 +1,914 @@
+
+`include "spi_defines.v"
+module spi_top_tri (
+
+input                             wb_clk_i_1,         
+input                             wb_clk_i_2,         
+input                             wb_clk_i_3,         
+input                             wb_rst_i_1,         
+input                             wb_rst_i_2,         
+input                             wb_rst_i_3,         
+input [4:0]                       wb_adr_i_1,         
+input [4:0]                       wb_adr_i_2,         
+input [4:0]                       wb_adr_i_3,         
+input [32-1:0]                    wb_dat_i_1,         
+input [32-1:0]                    wb_dat_i_2,         
+input [32-1:0]                    wb_dat_i_3,         
+output [32-1:0]                   wb_dat_o_1,         
+output [32-1:0]                   wb_dat_o_2,         
+output [32-1:0]                   wb_dat_o_3,         
+input [3:0]                       wb_sel_i_1,         
+input [3:0]                       wb_sel_i_2,         
+input [3:0]                       wb_sel_i_3,         
+input                             wb_we_i_1 ,         
+input                             wb_we_i_2 ,         
+input                             wb_we_i_3 ,         
+input                             wb_stb_i_1,         
+input                             wb_stb_i_2,         
+input                             wb_stb_i_3,         
+input                             wb_cyc_i_1,         
+input                             wb_cyc_i_2,         
+input                             wb_cyc_i_3,         
+output                            wb_ack_o_1,         
+output                            wb_ack_o_2,         
+output                            wb_ack_o_3,         
+output                            wb_err_o_1,         
+output                            wb_err_o_2,         
+output                            wb_err_o_3,         
+output                            wb_int_o_1,                               
+output                            wb_int_o_2,                               
+output                            wb_int_o_3,                               
+output [`SPI_SS_NB-1:0]           ss_pad_o_1,       
+output [`SPI_SS_NB-1:0]           ss_pad_o_2,       
+output [`SPI_SS_NB-1:0]           ss_pad_o_3,       
+output                            sclk_pad_o_1,       
+output                            sclk_pad_o_2,       
+output                            sclk_pad_o_3,       
+output                            mosi_pad_o_1,       
+output                            mosi_pad_o_2,       
+output                            mosi_pad_o_3,       
+input                             miso_pad_i_1,
+input                             miso_pad_i_2,
+input                             miso_pad_i_3 
+);
+
+wire [`SPI_DIVIDER_LEN-1:0]        divider_1;
+wire [`SPI_DIVIDER_LEN-1:0]        divider_2;
+wire [`SPI_DIVIDER_LEN-1:0]        divider_3;
+wire [`SPI_CTRL_BIT_NB-1:0]        ctrl_1;
+wire [`SPI_CTRL_BIT_NB-1:0]        ctrl_2;
+wire [`SPI_CTRL_BIT_NB-1:0]        ctrl_3;
+wire [`SPI_SS_NB-1:0]              ss_1;
+wire [`SPI_SS_NB-1:0]              ss_2;
+wire [`SPI_SS_NB-1:0]              ss_3;
+wire [`SPI_MAX_CHAR-1:0]          rx_1;
+wire [`SPI_MAX_CHAR-1:0]          rx_2;
+wire [`SPI_MAX_CHAR-1:0]          rx_3;
+wire                              rx_negedge_1;
+wire                              rx_negedge_2;
+wire                              rx_negedge_3;
+wire                              tx_negedge_1;
+wire                              tx_negedge_2;
+wire                              tx_negedge_3;
+wire [`SPI_CHAR_LEN_BITS-1:0]     char_len_1;
+wire [`SPI_CHAR_LEN_BITS-1:0]     char_len_2;
+wire [`SPI_CHAR_LEN_BITS-1:0]     char_len_3;
+wire                              go_1;
+wire                              go_2;
+wire                              go_3;
+wire                              lsb_1;
+wire                              lsb_2;
+wire                              lsb_3;
+wire                              ie_1;
+wire                              ie_2;
+wire                              ie_3;
+wire                              ass_1;
+wire                              ass_2;
+wire                              ass_3;
+wire 				     inv_sclk_1;
+wire 				     inv_sclk_2;
+wire 				     inv_sclk_3;
+wire                              spi_divider_sel_1;
+wire                              spi_divider_sel_2;
+wire                              spi_divider_sel_3;
+wire                              spi_ctrl_sel_1;
+wire                              spi_ctrl_sel_2;
+wire                              spi_ctrl_sel_3;
+wire [3:0]                        spi_tx_sel_1;
+wire [3:0]                        spi_tx_sel_2;
+wire [3:0]                        spi_tx_sel_3;
+wire                              spi_ss_sel_1;
+wire                              spi_ss_sel_2;
+wire                              spi_ss_sel_3;
+wire                              tip_1;
+wire                              tip_2;
+wire                              tip_3;
+wire                              pos_edge_1;
+wire                              pos_edge_2;
+wire                              pos_edge_3;
+wire                              neg_edge_1;
+wire                              neg_edge_2;
+wire                              neg_edge_3;
+wire                              last_bit_1;
+wire                              last_bit_2;
+wire                              last_bit_3;
+wire                              sclk_o_1;
+wire                              sclk_o_2;
+wire                              sclk_o_3;
+
+assign inv_sclk_1   = ctrl_1[`SPI_CTRL_INV_SCLK];
+assign inv_sclk_2   = ctrl_2[`SPI_CTRL_INV_SCLK];
+assign inv_sclk_3   = ctrl_3[`SPI_CTRL_INV_SCLK];
+
+assign go_1         = ctrl_1[`SPI_CTRL_GO];
+assign go_2         = ctrl_2[`SPI_CTRL_GO];
+assign go_3         = ctrl_3[`SPI_CTRL_GO];
+
+assign char_len_1   = ctrl_1[`SPI_CTRL_CHAR_LEN];
+assign char_len_2   = ctrl_2[`SPI_CTRL_CHAR_LEN];
+assign char_len_3   = ctrl_3[`SPI_CTRL_CHAR_LEN];
+
+assign lsb_1        = ctrl_1[`SPI_CTRL_LSB];
+assign lsb_2        = ctrl_2[`SPI_CTRL_LSB];
+assign lsb_3        = ctrl_3[`SPI_CTRL_LSB];
+
+//assign ie_1         = ctrl_1[`SPI_CTRL_IE]; //change 1-Oct-2015
+//assign ie_2         = ctrl_2[`SPI_CTRL_IE]; //change 1-Oct-2015
+//assign ie_3         = ctrl_3[`SPI_CTRL_IE]; //change 1-Oct-2015
+
+assign ie_1         = 1'b1; //change 1-Oct-2015
+assign ie_2         = 1'b1; //change 1-Oct-2015
+assign ie_3         = 1'b1; //change 1-Oct-2015
+
+assign ass_1        = ctrl_1[`SPI_CTRL_ASS];
+assign ass_2        = ctrl_2[`SPI_CTRL_ASS];
+assign ass_3        = ctrl_3[`SPI_CTRL_ASS];
+
+assign rx_negedge_1 = (~inv_sclk_1) ? ctrl_1[`SPI_CTRL_RX_NEGEDGE] : ~ctrl_1[`SPI_CTRL_RX_NEGEDGE];
+assign rx_negedge_2 = (~inv_sclk_2) ? ctrl_2[`SPI_CTRL_RX_NEGEDGE] : ~ctrl_2[`SPI_CTRL_RX_NEGEDGE];
+assign rx_negedge_3 = (~inv_sclk_3) ? ctrl_3[`SPI_CTRL_RX_NEGEDGE] : ~ctrl_3[`SPI_CTRL_RX_NEGEDGE];
+
+assign tx_negedge_1 = (~inv_sclk_1) ? ctrl_1[`SPI_CTRL_TX_NEGEDGE] : ~ctrl_1[`SPI_CTRL_TX_NEGEDGE];
+assign tx_negedge_2 = (~inv_sclk_2) ? ctrl_2[`SPI_CTRL_TX_NEGEDGE] : ~ctrl_2[`SPI_CTRL_TX_NEGEDGE];
+assign tx_negedge_3 = (~inv_sclk_3) ? ctrl_3[`SPI_CTRL_TX_NEGEDGE] : ~ctrl_3[`SPI_CTRL_TX_NEGEDGE];
+
+assign ss_pad_o_1 = ~((ss_1 & {`SPI_SS_NB{tip_1 & ass_1}}) | (ss_1 & {`SPI_SS_NB{!ass_1}}));
+assign ss_pad_o_2 = ~((ss_2 & {`SPI_SS_NB{tip_2 & ass_2}}) | (ss_2 & {`SPI_SS_NB{!ass_2}}));
+assign ss_pad_o_3 = ~((ss_3 & {`SPI_SS_NB{tip_3 & ass_3}}) | (ss_3 & {`SPI_SS_NB{!ass_3}}));
+
+assign sclk_pad_o_1 = (~inv_sclk_1) ? sclk_o_1 : ~sclk_o_1;
+assign sclk_pad_o_2 = (~inv_sclk_2) ? sclk_o_2 : ~sclk_o_2;
+assign sclk_pad_o_3 = (~inv_sclk_3) ? sclk_o_3 : ~sclk_o_3;
+
+spi_clgen_tri clgen (
+		.clk_in_1(wb_clk_i_1), 
+		.rst_1(wb_rst_i_1), 
+		.go_1(go_1), 
+		.enable_1(tip_1), 
+		.last_clk_1(last_bit_1),
+		.divider_1(divider_1), 
+		.clk_out_1(sclk_o_1), 
+		.pos_edge_1(pos_edge_1),                    
+		.neg_edge_1(neg_edge_1),
+		.clk_in_2(wb_clk_i_2), 
+		.rst_2(wb_rst_i_2), 
+		.go_2(go_2), 
+		.enable_2(tip_2), 
+		.last_clk_2(last_bit_2),
+		.divider_2(divider_2), 
+		.clk_out_2(sclk_o_2), 
+		.pos_edge_2(pos_edge_2),                    
+		.neg_edge_2(neg_edge_2),
+		.clk_in_3(wb_clk_i_3), 
+		.rst_3(wb_rst_i_3), 
+		.go_3(go_3), 
+		.enable_3(tip_3), 
+		.last_clk_3(last_bit_3),
+		.divider_3(divider_3), 
+		.clk_out_3(sclk_o_3), 
+		.pos_edge_3(pos_edge_3),                    
+		.neg_edge_3(neg_edge_3)
+	);
+
+
+spi_shift_tri shift (
+		.clk_1(wb_clk_i_1), 
+		.rst_1(wb_rst_i_1), 
+		.len_1(char_len_1[`SPI_CHAR_LEN_BITS-1:0]),                   
+		.latch_1(spi_tx_sel_1[3:0] & {4{wb_we_i_1}}), 
+		.byte_sel_1(wb_sel_i_1), 
+		.lsb_1(lsb_1),                 
+		.go_1(go_1), 
+		.pos_edge_1(pos_edge_1),
+		.neg_edge_1(neg_edge_1), 
+		.rx_negedge_1(rx_negedge_1), 
+		.tx_negedge_1(tx_negedge_1),
+		.tip_1(tip_1), 
+		.last_1(last_bit_1), 
+		.p_in_1(wb_dat_i_1), 
+		.p_out_1(rx_1), 
+		.s_clk_1(sclk_o_1), 
+		.s_in_1(miso_pad_i_1), 
+		.s_out_1(mosi_pad_o_1),
+		.clk_2(wb_clk_i_2), 
+		.rst_2(wb_rst_i_2), 
+		.len_2(char_len_2[`SPI_CHAR_LEN_BITS-1:0]),                   
+		.latch_2(spi_tx_sel_2[3:0] & {4{wb_we_i_2}}), 
+		.byte_sel_2(wb_sel_i_2), 
+		.lsb_2(lsb_2),                 
+		.go_2(go_2), 
+		.pos_edge_2(pos_edge_2),
+		.neg_edge_2(neg_edge_2), 
+		.rx_negedge_2(rx_negedge_2), 
+		.tx_negedge_2(tx_negedge_2),
+		.tip_2(tip_2), 
+		.last_2(last_bit_2), 
+		.p_in_2(wb_dat_i_2), 
+		.p_out_2(rx_2), 
+		.s_clk_2(sclk_o_2), 
+		.s_in_2(miso_pad_i_2), 
+		.s_out_2(mosi_pad_o_2),
+		.clk_3(wb_clk_i_3), 
+		.rst_3(wb_rst_i_3), 
+		.len_3(char_len_3[`SPI_CHAR_LEN_BITS-1:0]),                   
+		.latch_3(spi_tx_sel_3[3:0] & {4{wb_we_i_3}}), 
+		.byte_sel_3(wb_sel_i_3), 
+		.lsb_3(lsb_3),                 
+		.go_3(go_3), 
+		.pos_edge_3(pos_edge_3),
+		.neg_edge_3(neg_edge_3), 
+		.rx_negedge_3(rx_negedge_3), 
+		.tx_negedge_3(tx_negedge_3),
+		.tip_3(tip_3), 
+		.last_3(last_bit_3), 
+		.p_in_3(wb_dat_i_3), 
+		.p_out_3(rx_3), 
+		.s_clk_3(sclk_o_3), 
+		.s_in_3(miso_pad_i_3), 
+		.s_out_3(mosi_pad_o_3)
+	);
+
+
+spi_wb_interface_tri wb_interface ( 
+		.wb_clk_in_1(wb_clk_i_1), 
+		.wb_rst_in_1(wb_rst_i_1), 
+		.wb_adr_in_1(wb_adr_i_1), 
+		.wb_dat_in_1(wb_dat_i_1), 
+		.wb_dat_out_1(wb_dat_o_1),
+		.wb_sel_in_1(wb_sel_i_1), 
+		.wb_we_in_1(wb_we_i_1), 
+		.wb_stb_in_1(wb_stb_i_1), 
+		.wb_cyc_in_1(wb_cyc_i_1),            
+		.wb_ack_out_1(wb_ack_o_1), 
+		.wb_err_out_1(wb_err_o_1), 
+		.wb_int_out_1(wb_int_o_1),
+		.divider_1(divider_1), 
+		.ctrl_1(ctrl_1), 
+		.ss_1(ss_1),
+		.rx_1(rx_1),
+		.ie_1(ie_1),
+		.spi_divider_sel_1(spi_divider_sel_1), 
+		.spi_ctrl_sel_1(spi_ctrl_sel_1), 
+		.spi_tx_sel_1(spi_tx_sel_1), 
+		.spi_ss_sel_1(spi_ss_sel_1),
+		.tip_1(tip_1),
+		.last_bit_1(last_bit_1),
+		.pos_edge_1(pos_edge_1),
+		.wb_clk_in_2(wb_clk_i_2), 
+		.wb_rst_in_2(wb_rst_i_2), 
+		.wb_adr_in_2(wb_adr_i_2), 
+		.wb_dat_in_2(wb_dat_i_2), 
+		.wb_dat_out_2(wb_dat_o_2),
+		.wb_sel_in_2(wb_sel_i_2), 
+		.wb_we_in_2(wb_we_i_2), 
+		.wb_stb_in_2(wb_stb_i_2), 
+		.wb_cyc_in_2(wb_cyc_i_2),            
+		.wb_ack_out_2(wb_ack_o_2), 
+		.wb_err_out_2(wb_err_o_2), 
+		.wb_int_out_2(wb_int_o_2),
+		.divider_2(divider_2), 
+		.ctrl_2(ctrl_2), 
+		.ss_2(ss_2),
+		.rx_2(rx_2),
+		.ie_2(ie_2),
+		.spi_divider_sel_2(spi_divider_sel_2), 
+		.spi_ctrl_sel_2(spi_ctrl_sel_2), 
+		.spi_tx_sel_2(spi_tx_sel_2), 
+		.spi_ss_sel_2(spi_ss_sel_2),
+		.tip_2(tip_2),
+		.last_bit_2(last_bit_2),
+		.pos_edge_2(pos_edge_2),
+		.wb_clk_in_3(wb_clk_i_3), 
+		.wb_rst_in_3(wb_rst_i_3), 
+		.wb_adr_in_3(wb_adr_i_3), 
+		.wb_dat_in_3(wb_dat_i_3), 
+		.wb_dat_out_3(wb_dat_o_3),
+		.wb_sel_in_3(wb_sel_i_3), 
+		.wb_we_in_3(wb_we_i_3), 
+		.wb_stb_in_3(wb_stb_i_3), 
+		.wb_cyc_in_3(wb_cyc_i_3),            
+		.wb_ack_out_3(wb_ack_o_3), 
+		.wb_err_out_3(wb_err_o_3), 
+		.wb_int_out_3(wb_int_o_3),
+		.divider_3(divider_3), 
+		.ctrl_3(ctrl_3), 
+		.ss_3(ss_3),
+		.rx_3(rx_3),
+		.ie_3(ie_3),
+		.spi_divider_sel_3(spi_divider_sel_3), 
+		.spi_ctrl_sel_3(spi_ctrl_sel_3), 
+		.spi_tx_sel_3(spi_tx_sel_3), 
+		.spi_ss_sel_3(spi_ss_sel_3),
+		.tip_3(tip_3),
+		.last_bit_3(last_bit_3),
+		.pos_edge_3(pos_edge_3)
+	);
+
+
+endmodule
+
+`timescale 1ns / 1ps
+module spi_clgen_iostate (clk_in, rst, go, enable, last_clk, divider, clk_out_i, clk_out_o, pos_edge_i, pos_edge_o, neg_edge_i, neg_edge_o, cnt_i, cnt_o); 
+  
+  input                            clk_in;   
+  input                            neg_edge_i;                          
+  input                            pos_edge_i; 
+  input                            clk_out_i;  
+  input     [`SPI_DIVIDER_LEN-1:0] cnt_i;     
+ 
+  input                            rst;      
+  input                            enable;   
+  input                            go;       
+  input                            last_clk; 
+  input     [`SPI_DIVIDER_LEN-1:0] divider;  
+  output                           clk_out_o;
+  output       [`SPI_DIVIDER_LEN-1:0] cnt_o;
+  output                           pos_edge_o;
+  output                           neg_edge_o;
+  
+  reg                              clk_out_o;
+  reg                              pos_edge_o;
+  reg                              neg_edge_o;                        
+  reg       [`SPI_DIVIDER_LEN-1:0] cnt_o;
+  wire                             cnt_zero; 
+  wire                             cnt_one;  
+  
+  
+  assign cnt_zero = cnt_i == {`SPI_DIVIDER_LEN{1'b0}};
+  assign cnt_one  = cnt_i == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
+  
+  
+  always @(posedge clk_in or posedge rst)
+  begin
+    if(rst)
+      cnt_o <=#1   {`SPI_DIVIDER_LEN{1'b1}};
+    else
+      begin
+	  cnt_o <=#1   cnt_i;
+        if(!enable || cnt_zero)
+          cnt_o <=#1   divider;
+        else
+          cnt_o <=#1   cnt_i - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
+      end
+  end
+  
+  
+  always @(posedge clk_in or posedge rst)
+  begin
+    if(rst)
+      clk_out_o <=#1   1'b0;
+    else
+      clk_out_o <=#1   (enable && cnt_zero && (!last_clk || clk_out_i)) ? ~clk_out_i : clk_out_i;
+  end
+   
+  
+  always @(posedge clk_in or posedge rst)
+  begin
+    if(rst)
+      begin
+        pos_edge_o  <=#1   1'b0;
+        neg_edge_o  <=#1   1'b0;
+      end
+    else
+      begin
+        pos_edge_o  <=#1   (enable && !clk_out_i && cnt_one) || (!(|divider) && clk_out_i) || (!(|divider) && go && !enable);
+        neg_edge_o  <=#1   (enable && clk_out_i && cnt_one) || (!(|divider) && !clk_out_i && enable);
+      end
+  end
+
+endmodule
+
+
+
+module spi_clgen_tri (clk_in_1, clk_in_2, clk_in_3, rst_1, rst_2, rst_3, go_1, go_2, go_3, enable_1, enable_2, enable_3, last_clk_1, last_clk_2, last_clk_3, divider_1, divider_2, divider_3, clk_out_1, clk_out_2, clk_out_3, pos_edge_1, pos_edge_2, pos_edge_3, neg_edge_1, neg_edge_2, neg_edge_3);
+
+  input                            clk_in_1, clk_in_2, clk_in_3;   
+  input                            rst_1, rst_2, rst_3;      
+  input                            enable_1, enable_2, enable_3;   
+  input                            go_1, go_2, go_3;       
+  input                            last_clk_1, last_clk_2, last_clk_3; 
+  input     [`SPI_DIVIDER_LEN-1:0] divider_1, divider_2, divider_3;  
+  output                           clk_out_1, clk_out_2, clk_out_3;  
+  output                           pos_edge_1, pos_edge_2, pos_edge_3; 
+  output                           neg_edge_1, neg_edge_2, neg_edge_3; 
+
+	wire [`SPI_DIVIDER_LEN-1:0] cnt_1, cnt_2, cnt_3;
+	wire clk_out_1, clk_out_2, clk_out_3;
+	wire pos_edge_1, pos_edge_2, pos_edge_3;
+	wire neg_edge_1, neg_edge_2, neg_edge_3;
+	wire [`SPI_DIVIDER_LEN-1:0] cnt;
+	wire clk_out;
+	wire pos_edge;
+	wire neg_edge;
+
+	spi_clgen_iostate spi_clgen_iostate_1   (.clk_in(clk_in_1), .rst(rst_1), .go(go_1), .enable(enable_1), .last_clk(last_clk_1), .divider(divider_1), .clk_out_i(clk_out_1), .clk_out_o(clk_out_2), .pos_edge_i(pos_edge_1), .pos_edge_o(pos_edge_2), .neg_edge_i(neg_edge_1), .neg_edge_o(neg_edge_2), .cnt_i(cnt_1), .cnt_o(cnt_2));
+
+	spi_clgen_iostate spi_clgen_iostate_2   (.clk_in(clk_in_2), .rst(rst_2), .go(go_2), .enable(enable_2), .last_clk(last_clk_2), .divider(divider_2), .clk_out_i(clk_out_2), .clk_out_o(clk_out_3), .pos_edge_i(pos_edge_2), .pos_edge_o(pos_edge_3), .neg_edge_i(neg_edge_2), .neg_edge_o(neg_edge_3), .cnt_i(cnt_2), .cnt_o(cnt_3));
+
+	spi_clgen_iostate spi_clgen_iostate_3   (.clk_in(clk_in_3), .rst(rst_3), .go(go_3), .enable(enable_3), .last_clk(last_clk_3), .divider(divider_3), .clk_out_i(clk_out_3), .clk_out_o(clk_out), .pos_edge_i(pos_edge_3), .pos_edge_o(pos_edge), .neg_edge_i(neg_edge_3), .neg_edge_o(neg_edge), .cnt_i(cnt_3), .cnt_o(cnt));
+
+	majority_voter #(.WIDTH(4+`SPI_DIVIDER_LEN-1)) mv (
+		.in1({cnt_2, clk_out_2, pos_edge_2, neg_edge_2}),
+		.in2({cnt_3, clk_out_3, pos_edge_3, neg_edge_3}),
+		.in3({cnt, clk_out, pos_edge, neg_edge}),
+		.out({cnt_1, clk_out_1, pos_edge_1, neg_edge_1}),
+		.err()
+	);
+endmodule
+
+
+// missing: s_out_o <=#1  s_out_i;
+
+`timescale 1ns / 1ps
+module spi_shift_iostate (clk, rst, latch, byte_sel, len, lsb, go,
+                  pos_edge, neg_edge, rx_negedge, tx_negedge,
+                  tip_i, tip_o, last, 
+                  p_in, p_out, s_clk, s_in, s_out_i, s_out_o, cnt_i, cnt_o, data_i, data_o);
+ 
+  input                          clk;          
+  input        [`SPI_MAX_CHAR-1:0] data_i;  
+ 
+      
+  input                          s_clk;        
+  input                          s_in;         
+  input     [`SPI_CHAR_LEN_BITS:0] cnt_i;          
+  input                          rst;          
+  input                    [3:0] latch;        
+  input                    [3:0] byte_sel;     
+  input [`SPI_CHAR_LEN_BITS-1:0] len;          
+  input                          lsb;          
+  input                          go;           
+  input                          pos_edge;     
+  input                          neg_edge;     
+  input                          rx_negedge;   
+  input                          tx_negedge;   
+  output                         tip_o;
+  output        [`SPI_MAX_CHAR-1:0] data_o;
+  output     [`SPI_MAX_CHAR-1:0] p_out;        
+  output                         s_out_o;
+  input                         s_out_i;  
+      
+                                               
+  input                          tip_i;          
+  output  [`SPI_CHAR_LEN_BITS:0] cnt_o;
+  output                         last;         
+  input                   [31:0] p_in;         
+  reg                            s_out_o;        
+  reg                            tip_o;                             
+  reg     [`SPI_CHAR_LEN_BITS:0] cnt_o;
+  reg        [`SPI_MAX_CHAR-1:0] data_o;
+  wire    [`SPI_CHAR_LEN_BITS:0] tx_bit_pos;   
+  wire    [`SPI_CHAR_LEN_BITS:0] rx_bit_pos;   
+  wire                           rx_clk;       
+  wire                           tx_clk;       
+  
+  assign p_out = data_i;
+  
+  assign tx_bit_pos = lsb ? {!(|len), len} - cnt_i : cnt_i - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
+  assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt_i + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt_i) : 
+                            (rx_negedge ? cnt_i : cnt_i - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
+  
+  assign last = !(|cnt_i);
+  
+  assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
+  assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
+  
+  
+  always @(posedge clk or posedge rst)
+  begin
+    if(rst)
+      cnt_o <=#1   {`SPI_CHAR_LEN_BITS+1{1'b0}};
+    else
+      begin
+	  cnt_o <=#1   cnt_i;
+        if(tip_i)
+          cnt_o <=#1   pos_edge ? (cnt_i - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt_i;
+        else
+          cnt_o <=#1   !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
+      end
+  end
+  
+  
+  always @(posedge clk or posedge rst)
+  begin
+    	if(rst)
+      	tip_o <=#1   1'b0;
+  	else if(go && ~tip_i)
+    		tip_o <=#1   1'b1;
+  	else if(tip_i && last && pos_edge)
+    		tip_o <=#1   1'b0;
+	else 
+		tip_o <=#1   tip_i;
+  end
+  
+  
+  always @(posedge clk or posedge rst)
+  begin
+    if (rst)
+      s_out_o   <=#1   1'b0;
+    else
+      s_out_o <=#1   (tx_clk || !tip_i) ? data_i[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out_i;
+  end
+  
+  
+  always @(posedge clk or posedge rst)
+  begin
+    if (rst)
+      data_o   <=#1   {`SPI_MAX_CHAR{1'b0}};
+    else begin
+		data_o <=#1   data_i;
+		if (latch[0] && !tip_i)
+			begin
+			  if (byte_sel[3])
+				 data_o[31:24] <=#1   p_in[31:24];
+			  if (byte_sel[2])
+				 data_o[23:16] <=#1   p_in[23:16];
+			  if (byte_sel[1])
+				 data_o[15:8] <=#1   p_in[15:8];
+			  if (byte_sel[0])
+				 data_o[7:0] <=#1   p_in[7:0];
+			end
+		 else if (latch[1] && !tip_i)
+			begin
+			  if (byte_sel[3])
+				 data_o[63:56] <=#1   p_in[31:24];
+			  if (byte_sel[2])
+				 data_o[55:48] <=#1   p_in[23:16];
+			  if (byte_sel[1])
+				 data_o[47:40] <=#1   p_in[15:8];
+			  if (byte_sel[0])
+				 data_o[39:32] <=#1   p_in[7:0];
+			end
+		 else if (latch[2] && !tip_i)
+			begin
+			  if (byte_sel[3])
+				 data_o[95:88] <=#1   p_in[31:24];
+			  if (byte_sel[2])
+				 data_o[87:80] <=#1   p_in[23:16];
+			  if (byte_sel[1])
+				 data_o[79:72] <=#1   p_in[15:8];
+			  if (byte_sel[0])
+				 data_o[71:64] <=#1   p_in[7:0];
+			end
+		 else if (latch[3] && !tip_i)
+			begin
+			  if (byte_sel[3])
+				 data_o[127:120] <=#1   p_in[31:24];
+			  if (byte_sel[2])
+				 data_o[119:112] <=#1   p_in[23:16];
+			  if (byte_sel[1])
+				 data_o[111:104] <=#1   p_in[15:8];
+			  if (byte_sel[0])
+				 data_o[103:96] <=#1   p_in[7:0];
+			end
+		 else
+			data_o[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <=#1   rx_clk ? s_in : data_i[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
+   end
+  end
+  
+endmodule
+
+
+
+module spi_shift_tri (clk_1, clk_2, clk_3, rst_1, rst_2, rst_3, latch_1, latch_2, latch_3, byte_sel_1, byte_sel_2, byte_sel_3, len_1, len_2, len_3, lsb_1, lsb_2, lsb_3, go_1, go_2, go_3,
+                  pos_edge_1, pos_edge_2, pos_edge_3, neg_edge_1, neg_edge_2, neg_edge_3, rx_negedge_1, rx_negedge_2, rx_negedge_3, tx_negedge_1, tx_negedge_2, tx_negedge_3,
+                  tip_1, tip_2, tip_3, last_1, last_2, last_3, 
+                  p_in_1, p_in_2, p_in_3, p_out_1, p_out_2, p_out_3, s_clk_1, s_clk_2, s_clk_3, s_in_1, s_in_2, s_in_3, s_out_1, s_out_2, s_out_3);
+
+  input                          clk_1, clk_2, clk_3;          
+  input                          rst_1, rst_2, rst_3;          
+  input                    [3:0] latch_1, latch_2, latch_3;        
+  input                    [3:0] byte_sel_1, byte_sel_2, byte_sel_3;     
+  input [`SPI_CHAR_LEN_BITS-1:0] len_1, len_2, len_3;          
+  input                          lsb_1, lsb_2, lsb_3;          
+  input                          go_1, go_2, go_3;           
+  input                          pos_edge_1, pos_edge_2, pos_edge_3;     
+  input                          neg_edge_1, neg_edge_2, neg_edge_3;     
+  input                          rx_negedge_1, rx_negedge_2, rx_negedge_3;   
+  input                          tx_negedge_1, tx_negedge_2, tx_negedge_3;   
+  output                         tip_1, tip_2, tip_3;          
+  output                         last_1, last_2, last_3;         
+  input                   [31:0] p_in_1, p_in_2, p_in_3;         
+  output     [`SPI_MAX_CHAR-1:0] p_out_1, p_out_2, p_out_3;        
+  input                          s_clk_1, s_clk_2, s_clk_3;        
+  input                          s_in_1, s_in_2, s_in_3;         
+  output                         s_out_1, s_out_2, s_out_3;  
+
+	wire [`SPI_CHAR_LEN_BITS:0] cnt_1, cnt_2, cnt_3;
+	wire tip_1, tip_2, tip_3;
+	wire s_out_1, s_out_2, s_out_3;
+	wire [`SPI_MAX_CHAR-1:0] data_1, data_2, data_3;
+	wire [`SPI_CHAR_LEN_BITS:0] cnt;
+	wire tip;
+	wire s_out;
+	wire [`SPI_MAX_CHAR-1:0] data;
+
+	spi_shift_iostate spi_shift_iostate_1   (.clk(clk_1), .rst(rst_1), .latch(latch_1), .byte_sel(byte_sel_1), .len(len_1), .lsb(lsb_1), .go(go_1),
+                  .pos_edge(pos_edge_1), .neg_edge(neg_edge_1), .rx_negedge(rx_negedge_1), .tx_negedge(tx_negedge_1),
+                  .tip_i(tip_1), .tip_o(tip_2), .last(last_1), 
+                  .p_in(p_in_1), .p_out(p_out_1), .s_clk(s_clk_1), .s_in(s_in_1), .s_out_i(s_out_1), .s_out_o(s_out_2), .cnt_i(cnt_1), .cnt_o(cnt_2), .data_i(data_1), .data_o(data_2));
+
+	spi_shift_iostate spi_shift_iostate_2   (.clk(clk_2), .rst(rst_2), .latch(latch_2), .byte_sel(byte_sel_2), .len(len_2), .lsb(lsb_2), .go(go_2),
+                  .pos_edge(pos_edge_2), .neg_edge(neg_edge_2), .rx_negedge(rx_negedge_2), .tx_negedge(tx_negedge_2),
+                  .tip_i(tip_2), .tip_o(tip_3), .last(last_2), 
+                  .p_in(p_in_2), .p_out(p_out_2), .s_clk(s_clk_2), .s_in(s_in_2), .s_out_i(s_out_2), .s_out_o(s_out_3), .cnt_i(cnt_2), .cnt_o(cnt_3), .data_i(data_2), .data_o(data_3));
+
+	spi_shift_iostate spi_shift_iostate_3   (.clk(clk_3), .rst(rst_3), .latch(latch_3), .byte_sel(byte_sel_3), .len(len_3), .lsb(lsb_3), .go(go_3),
+                  .pos_edge(pos_edge_3), .neg_edge(neg_edge_3), .rx_negedge(rx_negedge_3), .tx_negedge(tx_negedge_3),
+                  .tip_i(tip_3), .tip_o(tip), .last(last_3), 
+                  .p_in(p_in_3), .p_out(p_out_3), .s_clk(s_clk_3), .s_in(s_in_3), .s_out_i(s_out_3), .s_out_o(s_out), .cnt_i(cnt_3), .cnt_o(cnt), .data_i(data_3), .data_o(data));
+
+	majority_voter #(.WIDTH(4+`SPI_CHAR_LEN_BITS+`SPI_MAX_CHAR-1)) mv (
+		.in1({cnt_2, tip_2, s_out_2, data_2}),
+		.in2({cnt_3, tip_3, s_out_3, data_3}),
+		.in3({cnt, tip, s_out, data}),
+		.out({cnt_1, tip_1, s_out_1, data_1}),
+		.err()
+	);
+endmodule
+
+
+`timescale 1ns / 1ps
+ module spi_wb_interface_iostate (
+		wb_clk_in, wb_rst_in, wb_adr_in, wb_dat_in, wb_dat_out_i, wb_dat_out_o,
+		wb_sel_in, wb_we_in, wb_stb_in, wb_cyc_in,
+            wb_ack_out_i, wb_ack_out_o, wb_err_out, wb_int_out_i, wb_int_out_o,
+  		divider_i, divider_o, ctrl_i, ctrl_o, ss_i, ss_o, rx, ie, tip, last_bit, pos_edge,
+		spi_divider_sel, spi_ctrl_sel, spi_tx_sel, spi_ss_sel
+	);
+
+
+  input                            wb_clk_in;         
+  input				     ie; 
+  input     [`SPI_CTRL_BIT_NB-1:0] ctrl_i;             
+  input     [`SPI_DIVIDER_LEN-1:0] divider_i;          
+  input				     tip;
+  input				     last_bit;
+  input				     pos_edge;
+  input                            wb_rst_in;         
+  input                      [4:0] wb_adr_in;         
+  input                   [32-1:0] wb_dat_in;         
+  output                  [32-1:0] wb_dat_out_o; 
+  output    [`SPI_CTRL_BIT_NB-1:0] ctrl_o;
+  output          [`SPI_SS_NB-1:0] ss_o;
+  input           [`SPI_SS_NB-1:0] ss_i;               
+
+  output                           spi_divider_sel;  
+  output                           spi_ctrl_sel;      
+  output                     [3:0] spi_tx_sel;       
+  output                           spi_ss_sel;  
+
+
+  input                  [32-1:0] wb_dat_out_i;         
+  input                      [3:0] wb_sel_in;         
+  input                            wb_we_in;          
+  input                            wb_stb_in;         
+  input                            wb_cyc_in;        
+  output                           wb_ack_out_o;
+  input                            wb_ack_out_i;         
+  output                           wb_err_out;         
+  output                           wb_int_out_o;
+  input                            wb_int_out_i;
+  
+  input	   [`SPI_MAX_CHAR-1:0] rx;
+  output    [`SPI_DIVIDER_LEN-1:0] divider_o;
  reg                     [32-1:0] wb_dat_out_o;
+  reg                              wb_ack_out_o;
+  reg                              wb_int_out_o;
+  reg       [`SPI_DIVIDER_LEN-1:0] divider_o;          
+  reg       [`SPI_CTRL_BIT_NB-1:0] ctrl_o;             
+  reg             [`SPI_SS_NB-1:0] ss_o;               
+  reg                     [32-1:0] wb_datM; 
+  wire  				     spi_go_sel;
+
+  assign spi_divider_sel = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `SPI_DEVIDE);
+  assign spi_ctrl_sel    = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `SPI_CTRL);
+  assign spi_tx_sel[0]   = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `SPI_TX_0);
+  assign spi_tx_sel[1]   = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `SPI_TX_1);
+  assign spi_tx_sel[2]   = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `SPI_TX_2);
+  assign spi_tx_sel[3]   = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `SPI_TX_3);
+  assign spi_ss_sel      = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `SPI_SS);  
+  assign spi_go_sel      = wb_cyc_in & wb_stb_in & (wb_adr_in[`SPI_OFS_BITS] == `SPI_GO_REG);
+  assign wb_err_out = 1'b0;
+	
+  always @(wb_adr_in or rx or ctrl_i or divider_i or ss_i)
+  begin
+    case (wb_adr_in[`SPI_OFS_BITS])
+      `SPI_RX_0:    wb_datM = rx[31:0];
+      `SPI_RX_1:    wb_datM = rx[63:32];
+      `SPI_RX_2:    wb_datM = rx[95:64];
+      `SPI_RX_3:    wb_datM = {{128-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:96]};
+      `SPI_CTRL:    wb_datM = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl_i};
+      `SPI_DEVIDE:  wb_datM = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider_i};
+      `SPI_SS:      wb_datM = {{32-`SPI_SS_NB{1'b0}}, ss_i};
+	`SPI_GO_REG:  wb_datM = {31'h0,ctrl_i[`SPI_CTRL_GO]};
+      default:      wb_datM = 32'bx;
+    endcase
+  end
+  
+  
+  always @(posedge wb_clk_in or posedge wb_rst_in)
+  begin
+    if (wb_rst_in)
+      wb_dat_out_o <=#1   32'b0;
+    else
+      wb_dat_out_o <=#1   wb_datM;
+  end
+  
+  
+  always @(posedge wb_clk_in or posedge wb_rst_in)
+  begin
+    if (wb_rst_in)
+      wb_ack_out_o <=#1   1'b0;
+    else
+      wb_ack_out_o <=#1   wb_cyc_in & wb_stb_in & ~wb_ack_out_i;
+  end
+  
+
+  always @(posedge wb_clk_in or posedge wb_rst_in)
+  begin
+    if (wb_rst_in)
+      wb_int_out_o <=#1   1'b0;
+    else if (ie && tip && last_bit && pos_edge)
+      wb_int_out_o <=#1   1'b1;
+    else if (wb_ack_out_i)
+      wb_int_out_o <=#1   1'b0;
+    else 
+	wb_int_out_o <=#1   wb_int_out_i;
+  end
+  
+  
+  always @(posedge wb_clk_in or posedge wb_rst_in)
+  begin
+    if (wb_rst_in)
+        divider_o <=#1   {`SPI_DIVIDER_LEN{1'b0}};
+    else begin
+	divider_o <=#1   divider_i;
+	if (spi_divider_sel && wb_we_in && !tip)
+      begin
+        if (wb_sel_in[0])
+          divider_o[7:0] <=#1   wb_dat_in[7:0];
+        if (wb_sel_in[1])
+          divider_o[`SPI_DIVIDER_LEN-1:8] <=#1   wb_dat_in[`SPI_DIVIDER_LEN-1:8];
+      end
+    end
+  end
+  
+  
+	always @(posedge wb_clk_in or posedge wb_rst_in) begin
+		if (wb_rst_in) begin
+			ctrl_o <=#1   {`SPI_CTRL_BIT_NB{1'b0}};
+			ctrl_o[`SPI_CTRL_GO]         <=#1   1'b0;                            
+			ctrl_o[`SPI_CTRL_IE]         <=#1   1'b1;                            
+			ctrl_o[`SPI_CTRL_RX_NEGEDGE] <=#1   1'b0;
+			ctrl_o[`SPI_CTRL_TX_NEGEDGE] <=#1   1'b0;
+			ctrl_o[`SPI_CTRL_LSB]        <=#1   1'b0;
+			ctrl_o[`SPI_CTRL_ASS]        <=#1   1'b0;
+			ctrl_o[`SPI_CTRL_CHAR_LEN]   <=#1   7'h0;
+			ctrl_o[`SPI_CTRL_INV_SCLK]   <=#1   1'b0;
+		end
+		else begin
+			ctrl_o <=#1   ctrl_i;
+			if(spi_go_sel && wb_we_in && !tip) begin
+				if (wb_sel_in[0])
+					ctrl_o[`SPI_CTRL_GO] <=#1   1'b1;
+					ctrl_o[`SPI_CTRL_IE] <=#1   1'b1; //change 1-Oct-2015
+			end
+			else if(spi_ctrl_sel && wb_we_in && !tip) begin
+				if (wb_sel_in[0])
+					ctrl_o[`SPI_CTRL_CHAR_LEN] <=#1   wb_dat_in[`SPI_CTRL_CHAR_LEN];     //change 1-Oct-2015
+					ctrl_o[`SPI_CTRL_INV_SCLK] <=#1   wb_dat_in[`SPI_CTRL_INV_SCLK];     //change 1-Oct-2015
+				if (wb_sel_in[1]) begin					
+					ctrl_o[`SPI_CTRL_GO]         <=#1   1'b0;                            //change 1-Oct-2015
+					ctrl_o[`SPI_CTRL_IE]         <=#1   1'b1;                            //change 1-Oct-2015
+					ctrl_o[`SPI_CTRL_RX_NEGEDGE] <=#1   wb_dat_in[`SPI_CTRL_RX_NEGEDGE]; //change 1-Oct-2015
+					ctrl_o[`SPI_CTRL_TX_NEGEDGE] <=#1   wb_dat_in[`SPI_CTRL_TX_NEGEDGE]; //change 1-Oct-2015
+					ctrl_o[`SPI_CTRL_LSB]        <=#1   wb_dat_in[`SPI_CTRL_LSB];        //change 1-Oct-2015
+					ctrl_o[`SPI_CTRL_ASS]        <=#1   wb_dat_in[`SPI_CTRL_ASS];        //change 1-Oct-2015
+				end					
+			end
+			else if(tip && last_bit && pos_edge) begin
+				ctrl_o[`SPI_CTRL_GO] <=#1   1'b0;
+			end
+		end
+	end
+  
+  
+  
+  
+
+  always @(posedge wb_clk_in or posedge wb_rst_in)
+  begin
+    if (wb_rst_in)
+      ss_o <=#1   {`SPI_SS_NB{1'b0}};
+    else begin
+	ss_o <=#1   ss_i;
+	if(spi_ss_sel && wb_we_in && !tip)
+      begin
+         if (wb_sel_in[0])
+          ss_o <=#1   wb_dat_in[`SPI_SS_NB-1:0];
+      end
+    end
+  end
+
+endmodule
+
+
+
+ module spi_wb_interface_tri (
+		wb_clk_in_1, wb_clk_in_2, wb_clk_in_3, wb_rst_in_1, wb_rst_in_2, wb_rst_in_3, wb_adr_in_1, wb_adr_in_2, wb_adr_in_3, wb_dat_in_1, wb_dat_in_2, wb_dat_in_3, wb_dat_out_1, wb_dat_out_2, wb_dat_out_3,
+		wb_sel_in_1, wb_sel_in_2, wb_sel_in_3, wb_we_in_1, wb_we_in_2, wb_we_in_3, wb_stb_in_1, wb_stb_in_2, wb_stb_in_3, wb_cyc_in_1, wb_cyc_in_2, wb_cyc_in_3,
+            wb_ack_out_1, wb_ack_out_2, wb_ack_out_3, wb_err_out_1, wb_err_out_2, wb_err_out_3, wb_int_out_1, wb_int_out_2, wb_int_out_3,
+  		divider_1, divider_2, divider_3, ctrl_1, ctrl_2, ctrl_3, ss_1, ss_2, ss_3, rx_1, rx_2, rx_3, ie_1, ie_2, ie_3, tip_1, tip_2, tip_3, last_bit_1, last_bit_2, last_bit_3, pos_edge_1, pos_edge_2, pos_edge_3,
+		spi_divider_sel_1, spi_divider_sel_2, spi_divider_sel_3, spi_ctrl_sel_1, spi_ctrl_sel_2, spi_ctrl_sel_3, spi_tx_sel_1, spi_tx_sel_2, spi_tx_sel_3, spi_ss_sel_1, spi_ss_sel_2, spi_ss_sel_3
+	);
+
+  input                            wb_clk_in_1, wb_clk_in_2, wb_clk_in_3;         
+  input                            wb_rst_in_1, wb_rst_in_2, wb_rst_in_3;         
+  input                      [4:0] wb_adr_in_1, wb_adr_in_2, wb_adr_in_3;         
+  input                   [32-1:0] wb_dat_in_1, wb_dat_in_2, wb_dat_in_3;         
+  output                  [32-1:0] wb_dat_out_1, wb_dat_out_2, wb_dat_out_3;         
+  input                      [3:0] wb_sel_in_1, wb_sel_in_2, wb_sel_in_3;         
+  input                            wb_we_in_1, wb_we_in_2, wb_we_in_3;          
+  input                            wb_stb_in_1, wb_stb_in_2, wb_stb_in_3;         
+  input                            wb_cyc_in_1, wb_cyc_in_2, wb_cyc_in_3;        
+  output                           wb_ack_out_1, wb_ack_out_2, wb_ack_out_3;         
+  output                           wb_err_out_1, wb_err_out_2, wb_err_out_3;         
+  output                           wb_int_out_1, wb_int_out_2, wb_int_out_3;
+
+  input	   [`SPI_MAX_CHAR-1:0] rx_1, rx_2, rx_3;
+  input				     ie_1, ie_2, ie_3;
+  input				     tip_1, tip_2, tip_3;
+  input				     last_bit_1, last_bit_2, last_bit_3;
+  input				     pos_edge_1, pos_edge_2, pos_edge_3;
+  output    [`SPI_DIVIDER_LEN-1:0] divider_1, divider_2, divider_3;          
+  output    [`SPI_CTRL_BIT_NB-1:0] ctrl_1, ctrl_2, ctrl_3;             
+  output          [`SPI_SS_NB-1:0] ss_1, ss_2, ss_3;               
+
+  output                           spi_divider_sel_1, spi_divider_sel_2, spi_divider_sel_3;  
+  output                           spi_ctrl_sel_1, spi_ctrl_sel_2, spi_ctrl_sel_3;     
+  output                     [3:0] spi_tx_sel_1, spi_tx_sel_2, spi_tx_sel_3;       
+  output                           spi_ss_sel_1, spi_ss_sel_2, spi_ss_sel_3;  
+
+	wire [32-1:0] wb_dat_out_1, wb_dat_out_2, wb_dat_out_3;
+	wire wb_ack_out_1, wb_ack_out_2, wb_ack_out_3;
+	wire wb_int_out_1, wb_int_out_2, wb_int_out_3;
+	wire [`SPI_DIVIDER_LEN-1:0] divider_1, divider_2, divider_3;
+	wire [`SPI_CTRL_BIT_NB-1:0] ctrl_1, ctrl_2, ctrl_3;
+	wire [`SPI_SS_NB-1:0] ss_1, ss_2, ss_3;
+	wire [32-1:0] wb_dat_out;
+	wire wb_ack_out;
+	wire wb_int_out;
+	wire [`SPI_DIVIDER_LEN-1:0] divider;
+	wire [`SPI_CTRL_BIT_NB-1:0] ctrl;
+	wire [`SPI_SS_NB-1:0] ss;
+
+ 	spi_wb_interface_iostate spi_wb_interface_iostate_1   (
+		.wb_clk_in(wb_clk_in_1), .wb_rst_in(wb_rst_in_1), .wb_adr_in(wb_adr_in_1), .wb_dat_in(wb_dat_in_1), .wb_dat_out_i(wb_dat_out_1), .wb_dat_out_o(wb_dat_out_2),
+		.wb_sel_in(wb_sel_in_1), .wb_we_in(wb_we_in_1), .wb_stb_in(wb_stb_in_1), .wb_cyc_in(wb_cyc_in_1),
+            .wb_ack_out_i(wb_ack_out_1), .wb_ack_out_o(wb_ack_out_2), .wb_err_out(wb_err_out_1), .wb_int_out_i(wb_int_out_1), .wb_int_out_o(wb_int_out_2),
+  		.divider_i(divider_1), .divider_o(divider_2), .ctrl_i(ctrl_1), .ctrl_o(ctrl_2), .ss_i(ss_1), .ss_o(ss_2), .rx(rx_1), .ie(ie_1), .tip(tip_1), .last_bit(last_bit_1), .pos_edge(pos_edge_1),
+		.spi_divider_sel(spi_divider_sel_1), .spi_ctrl_sel(spi_ctrl_sel_1), .spi_tx_sel(spi_tx_sel_1), .spi_ss_sel(spi_ss_sel_1));
+
+ 	spi_wb_interface_iostate spi_wb_interface_iostate_2   (
+		.wb_clk_in(wb_clk_in_2), .wb_rst_in(wb_rst_in_2), .wb_adr_in(wb_adr_in_2), .wb_dat_in(wb_dat_in_2), .wb_dat_out_i(wb_dat_out_2), .wb_dat_out_o(wb_dat_out_3),
+		.wb_sel_in(wb_sel_in_2), .wb_we_in(wb_we_in_2), .wb_stb_in(wb_stb_in_2), .wb_cyc_in(wb_cyc_in_2),
+            .wb_ack_out_i(wb_ack_out_2), .wb_ack_out_o(wb_ack_out_3), .wb_err_out(wb_err_out_2), .wb_int_out_i(wb_int_out_2), .wb_int_out_o(wb_int_out_3),
+  		.divider_i(divider_2), .divider_o(divider_3), .ctrl_i(ctrl_2), .ctrl_o(ctrl_3), .ss_i(ss_2), .ss_o(ss_3), .rx(rx_2), .ie(ie_2), .tip(tip_2), .last_bit(last_bit_2), .pos_edge(pos_edge_2),
+		.spi_divider_sel(spi_divider_sel_2), .spi_ctrl_sel(spi_ctrl_sel_2), .spi_tx_sel(spi_tx_sel_2), .spi_ss_sel(spi_ss_sel_2));
+
+ 	spi_wb_interface_iostate spi_wb_interface_iostate_3   (
+		.wb_clk_in(wb_clk_in_3), .wb_rst_in(wb_rst_in_3), .wb_adr_in(wb_adr_in_3), .wb_dat_in(wb_dat_in_3), .wb_dat_out_i(wb_dat_out_3), .wb_dat_out_o(wb_dat_out),
+		.wb_sel_in(wb_sel_in_3), .wb_we_in(wb_we_in_3), .wb_stb_in(wb_stb_in_3), .wb_cyc_in(wb_cyc_in_3),
+            .wb_ack_out_i(wb_ack_out_3), .wb_ack_out_o(wb_ack_out), .wb_err_out(wb_err_out_3), .wb_int_out_i(wb_int_out_3), .wb_int_out_o(wb_int_out),
+  		.divider_i(divider_3), .divider_o(divider), .ctrl_i(ctrl_3), .ctrl_o(ctrl), .ss_i(ss_3), .ss_o(ss), .rx(rx_3), .ie(ie_3), .tip(tip_3), .last_bit(last_bit_3), .pos_edge(pos_edge_3),
+		.spi_divider_sel(spi_divider_sel_3), .spi_ctrl_sel(spi_ctrl_sel_3), .spi_tx_sel(spi_tx_sel_3), .spi_ss_sel(spi_ss_sel_3));
+
+	majority_voter #(.WIDTH(6+32-1+`SPI_DIVIDER_LEN-1+`SPI_CTRL_BIT_NB-1+`SPI_SS_NB-1)) mv (
+		.in1({wb_dat_out_2, wb_ack_out_2, wb_int_out_2, divider_2, ctrl_2, ss_2}),
+		.in2({wb_dat_out_3, wb_ack_out_3, wb_int_out_3, divider_3, ctrl_3, ss_3}),
+		.in3({wb_dat_out, wb_ack_out, wb_int_out, divider, ctrl, ss}),
+		.out({wb_dat_out_1, wb_ack_out_1, wb_int_out_1, divider_1, ctrl_1, ss_1}),
+		.err()
+	);
+endmodule
+
diff --git a/vldb/code/Testbench/SCA-model/TOP_core_sca_tri.v b/vldb/code/Testbench/SCA-model/TOP_core_sca_tri.v
new file mode 100644
index 0000000..35c86d7
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/TOP_core_sca_tri.v
@@ -0,0 +1,1034 @@
+//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Top module name:.......TOP_core_sca_tri.v                   //
+//  Description:...........SCA top digital core (TMR)           //
+//                                                              //
+//  Authors:...............Alessandro Caratelli CERN PH-ESE-ME  //
+//  .......................Christian Paillard CERN PH-ESE-ME    //
+//                                                              //
+//  Version 1.0:                                                //
+//    Creation date:.......01 JULY 2013                         //
+//    Last modification:...09 JAN 2014                          //
+//                                                              //
+//  Version 2.0:                                                //
+//    Creation date:.......25 SEPT 2015                         //
+//    Last modification:...28 SEPT 2015                         //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+`define WithSEUcounter
+`define ClkGate_channels 
+        
+         
+module TOP_core_sca_tri ( 
+        `ifdef WithScanPath
+		 input         SCAN_MODE,         SCAN_ENABLE,
+         input         SCAN_IN1,          SCAN_IN2,          SCAN_IN3,
+        `endif
+         // Elink HDLC 
+         input         link_clk_1,    
+         input         link_clk_aux_1,
+         input         disable_aux_1, 
+         output        tx_sd_1,       
+         output        tx_sd_aux_1,   
+         input         rx_sd_1,       
+         input         rx_sd_aux_1,   
+         input  [7:0]  tx_adr_1,      
+         output [7:0]  CRE_1,         
+         output        active_aux_1,  
+		 
+         // JTAG 
+         output        JTAG_TCK_pad_o_1,
+         output        JTAG_TMS_pad_o_1,
+         output        JTAG_TDO_pad_o_1,
+         input         JTAG_TDI_pad_i_1,
+         output        JTAG_RST_pad_o_1,
+		 
+         // SPI 
+         output        SPI_sclk_pad_o_1,
+         output [7:0]  SPI_ss_pad_o_1,  
+         input         SPI_miso_pad_i_1,
+         output        SPI_mosi_pad_o_1,
+		 
+         // GPIO 
+         output [31:0] GPIO_ext_pad_o_1,  
+         output [31:0] GPIO_ext_padOE_o_1,
+         input         GPIO_clk_pad_i_1,  
+         input  [31:0] GPIO_ext_pad_i_1,  
+		 
+         // I2C 
+         output [15:0] SCL_1,        
+		 output [15:0] SCLEN_1,      
+         input  [15:0] SDA_in_1,     
+         output [15:0] SDA_out_inv_1,
+		 
+         // ADC  
+         output        ADC_wb_RES_1, 
+         output        ADC_wb_CLK_1, 
+         output        ADC_wb_SEL_1, 
+         output        ADC_wb_WE_1,  
+         output        ADC_wb_STB_1, 
+         output        ADC_wb_CYC_1, 
+         output [3:0]  ADC_wb_ADR_1, 
+         output [31:0] ADC_wb_DATi_1,
+         input  [31:0] ADC_wb_DATo_1,
+         input         ADC_wb_ACK_1, 
+         input         ADC_wb_INT_1, 
+
+         // DAC 
+         output [7:0]  anaDAC_A_1,
+         output [7:0]  anaDAC_B_1,
+         output [7:0]  anaDAC_C_1,
+         output [7:0]  anaDAC_D_1,
+		 
+         // Reset Logic //
+         input         PowerUpReset_1,
+         input         PromtReset_1,  
+         output        Reset_BG_1,    
+		 
+         // Auxiliary Port I2C //
+         input         auxPort_TestEn_1,
+         input         auxPort_SCL_1,   
+         input         auxPort_SDA_in_1,
+         output        auxPort_SDA_out_1,
+         output        auxPort_SDA_oEn_1
+	);
+	
+	`include "Table_Commande.v"
+		
+		
+         wire         	link_clk_2;
+         wire         	link_clk_aux_2;
+         wire         	disable_aux_2;
+         wire        	tx_sd_2;
+         wire        	tx_sd_aux_2;
+         wire         	rx_sd_2;
+         wire         	rx_sd_aux_2;
+         wire [7:0]  	tx_adr_2;
+         wire [7:0]  	CRE_2;
+         wire        	active_aux_2;
+         wire         	link_clk_3;
+         wire         	link_clk_aux_3;
+         wire         	disable_aux_3;
+         wire        	tx_sd_3;
+         wire        	tx_sd_aux_3;
+         wire         	rx_sd_3;
+         wire         	rx_sd_aux_3;
+         wire [7:0]  	tx_adr_3;
+         wire [7:0]  	CRE_3;
+         wire        	active_aux_3;
+		 
+		 wire 			JTAG_TCK_pad_o_2;
+		 wire 			JTAG_TMS_pad_o_2;
+		 wire 			JTAG_TDO_pad_o_2;
+		 wire 			JTAG_TDI_pad_i_2;
+		 wire 			JTAG_RST_pad_o_2;
+		 wire 			JTAG_TCK_pad_o_3;
+		 wire 			JTAG_TMS_pad_o_3;
+		 wire 			JTAG_TDO_pad_o_3;
+		 wire 			JTAG_TDI_pad_i_3;
+		 wire 			JTAG_RST_pad_o_3;
+		 
+		 wire			SPI_sclk_pad_o_2;
+		 wire [7:0]		SPI_ss_pad_o_2;
+		 wire			SPI_miso_pad_i_2;
+		 wire			SPI_mosi_pad_o_2;
+		 wire			SPI_sclk_pad_o_3;
+		 wire [7:0]		SPI_ss_pad_o_3;
+		 wire			SPI_miso_pad_i_3;
+		 wire			SPI_mosi_pad_o_3;
+		 
+		 wire [31:0]	GPIO_ext_pad_o_2;
+		 wire [31:0]	GPIO_ext_padOE_o_2;
+		 wire			GPIO_clk_pad_i_2;
+		 wire [31:0]	GPIO_ext_pad_i_2;
+		 wire [31:0]	GPIO_ext_pad_o_3;
+		 wire [31:0]	GPIO_ext_padOE_o_3;
+		 wire			GPIO_clk_pad_i_3;
+		 wire [31:0]	GPIO_ext_pad_i_3;
+		 
+		 wire [15:0]	SCL_2;
+		 wire [15:0]	SCLEN_2;
+		 wire [15:0]	SDA_in_2;
+		 wire [15:0]	SDA_out_inv_2;
+		 wire [15:0]	SCL_3;
+		 wire [15:0]	SCLEN_3;
+		 wire [15:0]	SDA_in_3;
+		 wire [15:0]	SDA_out_inv_3;
+		 
+		 
+		 wire        	ADC_wb_RES_2;
+		 wire        	ADC_wb_CLK_2;
+		 wire        	ADC_wb_SEL_2;
+		 wire        	ADC_wb_WE_2;
+		 wire        	ADC_wb_STB_2;
+		 wire        	ADC_wb_CYC_2;
+		 wire [3:0]  	ADC_wb_ADR_2;
+		 wire [31:0] 	ADC_wb_DATi_2;
+		 wire [31:0] 	ADC_wb_DATo_2;
+		 wire        	ADC_wb_ACK_2;
+		 wire        	ADC_wb_INT_2;
+		 wire        	ADC_wb_RES_3;
+		 wire        	ADC_wb_CLK_3;
+		 wire        	ADC_wb_SEL_3;
+		 wire        	ADC_wb_WE_3;
+		 wire        	ADC_wb_STB_3;
+		 wire        	ADC_wb_CYC_3;
+		 wire [3:0]  	ADC_wb_ADR_3;
+		 wire [31:0] 	ADC_wb_DATi_3;
+		 wire [31:0] 	ADC_wb_DATo_3;
+		 wire        	ADC_wb_ACK_3;
+		 wire        	ADC_wb_INT_3;
+		 
+		 wire [7:0]  	anaDAC_A_2;
+		 wire [7:0]  	anaDAC_B_2;
+		 wire [7:0]  	anaDAC_C_2;
+		 wire [7:0]  	anaDAC_D_2;
+		 wire [7:0]  	anaDAC_A_3;
+		 wire [7:0]  	anaDAC_B_3;
+		 wire [7:0]  	anaDAC_C_3;
+		 wire [7:0]  	anaDAC_D_3;
+		 
+		 wire        	PowerUpReset_2;
+		 wire        	PromtReset_2;  
+		 wire        	Reset_BG_2;  
+		 wire        	PowerUpReset_3;
+		 wire        	PromtReset_3;  
+		 wire        	Reset_BG_3;  
+		 
+		 wire	        auxPort_TestEn_2;
+		 wire	        auxPort_SCL_2;  
+		 wire	        auxPort_SDA_in_2;
+		 wire	        auxPort_SDA_out_2;
+		 wire	        auxPort_SDA_oEn_2;
+		 wire	        auxPort_TestEn_3;
+		 wire	        auxPort_SCL_3;  
+		 wire	        auxPort_SDA_in_3;
+		 wire	        auxPort_SDA_out_3;
+		 wire	        auxPort_SDA_oEn_3;
+		 
+		 
+         assign link_clk_2 = link_clk_1;
+         assign link_clk_aux_2 = link_clk_aux_1;
+         assign disable_aux_2 = disable_aux_1;
+         assign rx_sd_2 = rx_sd_1;
+         assign rx_sd_aux_2 = rx_sd_aux_1;
+         assign tx_adr_2 = tx_adr_1;
+         assign link_clk_3 = link_clk_1;
+         assign link_clk_aux_3 = link_clk_aux_1;
+         assign disable_aux_3 = disable_aux_1;
+         assign rx_sd_3 = rx_sd_1;
+         assign rx_sd_aux_3 = rx_sd_aux_1;
+         assign tx_adr_3 = tx_adr_1;
+		 
+		 assign JTAG_TDI_pad_i_2 = JTAG_TDI_pad_i_1;
+		 assign JTAG_TDI_pad_i_3 = JTAG_TDI_pad_i_1;
+		 
+		 assign SPI_miso_pad_i_2 = SPI_miso_pad_i_1;
+		 assign SPI_miso_pad_i_3 = SPI_miso_pad_i_1;
+		 
+		 assign GPIO_clk_pad_i_2 = GPIO_clk_pad_i_1;
+		 assign GPIO_ext_pad_i_2 = GPIO_ext_pad_i_1;
+		 assign GPIO_clk_pad_i_3 = GPIO_clk_pad_i_1;
+		 assign GPIO_ext_pad_i_3 = GPIO_ext_pad_i_1;
+		 
+		 assign SDA_in_2 = SDA_in_1;
+		 assign SDA_in_3 = SDA_in_1;
+		 
+		 assign ADC_wb_DATo_2 = ADC_wb_DATo_1;
+		 assign ADC_wb_ACK_2 = ADC_wb_ACK_1;
+		 assign ADC_wb_INT_2 = ADC_wb_INT_1;
+		 assign ADC_wb_DATo_3 = ADC_wb_DATo_1;
+		 assign ADC_wb_ACK_3 = ADC_wb_ACK_1;
+		 assign ADC_wb_INT_3 = ADC_wb_INT_1;
+		 		 
+		 assign PowerUpReset_2 = PowerUpReset_1;
+		 assign PromtReset_2 = PromtReset_1;  
+		 assign PowerUpReset_3 = PowerUpReset_1;
+		 assign PromtReset_3 = PromtReset_1;
+		 
+		 assign auxPort_TestEn_2 = auxPort_TestEn_1;
+		 assign auxPort_SCL_2 = auxPort_SCL_1;  
+		 assign auxPort_SDA_in_2 = auxPort_SDA_in_1;
+		 assign auxPort_TestEn_3 = auxPort_TestEn_1;
+		 assign auxPort_SCL_3 = auxPort_SCL_1;  
+		 assign auxPort_SDA_in_3 = auxPort_SDA_in_1;	 
+		 
+	 wire	[31:0]  wb_dat_o10_1;
+	 wire	[31:0]  wb_dat_o10_2;
+	 wire	[31:0]  wb_dat_o10_3;
+	 wire	[31:0]  wb_dat_o11_1;
+	 wire	[31:0]  wb_dat_o11_2;
+	 wire	[31:0]  wb_dat_o11_3;
+	 wire	[31:0]  wb_dat_o12_1;
+	 wire	[31:0]  wb_dat_o12_2;
+	 wire	[31:0]  wb_dat_o12_3;
+	 wire	[31:0]  wb_dat_o13_1;
+	 wire	[31:0]  wb_dat_o13_2;
+	 wire	[31:0]  wb_dat_o13_3;
+	 wire	[31:0]  wb_dat_o14_1;
+	 wire	[31:0]  wb_dat_o14_2;
+	 wire	[31:0]  wb_dat_o14_3;
+	 wire	[31:0]  wb_dat_o15_1;
+	 wire	[31:0]  wb_dat_o15_2;
+	 wire	[31:0]  wb_dat_o15_3;
+	 wire	[31:0]  wb_con_data_o_1;
+	 wire	[31:0]  wb_con_data_o_2;
+	 wire	[31:0]  wb_con_data_o_3;
+	 wire	[15:0]  rx_dat_1;
+	 wire	[15:0]  rx_dat_2;
+	 wire	[15:0]  rx_dat_3;
+	 wire		wb_we_o_1;
+	 wire		wb_we_o_2;
+	 wire		wb_we_o_3;
+	 wire		rx_dav_1;
+	 wire		rx_dav_2;
+	 wire		rx_dav_3;
+	 wire		wb_stb_o_1;
+	 wire		wb_stb_o_2;
+	 wire		wb_stb_o_3;
+	 wire		clock_1;
+	 wire		clock_2;
+	 wire		clock_3;
+	 wire	[31:0]  wb_dat_spi_1;
+	 wire	[31:0]  wb_dat_spi_2;
+	 wire	[31:0]  wb_dat_spi_3;
+	 wire		rx_ena_1;
+	 wire		rx_ena_2;
+	 wire		rx_ena_3;
+	 wire		tx_dav_1;
+	 wire		tx_dav_2;
+	 wire		tx_dav_3;
+	 wire		wb_err_out_1;
+	 wire		wb_err_out_2;
+	 wire		wb_err_out_3;
+	 wire	[15:0]  dataw_out_1;
+	 wire	[15:0]  dataw_out_2;
+	 wire	[15:0]  dataw_out_3;
+	 wire		tx_ena_1;
+	 wire		tx_ena_2;
+	 wire		tx_ena_3;
+	 wire		wb_err_o_1;
+	 wire		wb_err_o_2;
+	 wire		wb_err_o_3;
+	 wire	[31:0]  wb_dat_o0_1;
+	 wire	[31:0]  wb_dat_o0_2;
+	 wire	[31:0]  wb_dat_o0_3;
+	 wire	[31:0]  wb_dat_o1_1;
+	 wire	[31:0]  wb_dat_o1_2;
+	 wire	[31:0]  wb_dat_o1_3;
+	 wire	[31:0]  wb_dat_o2_1;
+	 wire	[31:0]  wb_dat_o2_2;
+	 wire	[31:0]  wb_dat_o2_3;
+	 wire	[31:0]  wb_dat_o3_1;
+	 wire	[31:0]  wb_dat_o3_2;
+	 wire	[31:0]  wb_dat_o3_3;
+	 wire	[31:0]  wb_dat_o4_1;
+	 wire	[31:0]  wb_dat_o4_2;
+	 wire	[31:0]  wb_dat_o4_3;
+	 wire	[31:0]  wb_addr_o_1;
+	 wire	[31:0]  wb_addr_o_2;
+	 wire	[31:0]  wb_addr_o_3;
+	 wire	[31:0]  wb_dat_o5_1;
+	 wire	[31:0]  wb_dat_o5_2;
+	 wire	[31:0]  wb_dat_o5_3;
+	 wire	[31:0]  wb_dat_o6_1;
+	 wire	[31:0]  wb_dat_o6_2;
+	 wire	[31:0]  wb_dat_o6_3;
+	 wire	[31:0]  wb_data_1;
+	 wire	[31:0]  wb_data_2;
+	 wire	[31:0]  wb_data_3;
+	 wire	[31:0]  wb_dat_o7_1;
+	 wire	[31:0]  wb_dat_o7_2;
+	 wire	[31:0]  wb_dat_o7_3;
+	 wire	[31:0]  wb_dat_o8_1;
+	 wire	[31:0]  wb_dat_o8_2;
+	 wire	[31:0]  wb_dat_o8_3;
+	 wire	[31:0]  wb_dat_o9_1;
+	 wire	[31:0]  wb_dat_o9_2;
+	 wire	[31:0]  wb_dat_o9_3;
+	 wire	[5:0]	CH_int_1;
+	 wire	[5:0]	CH_int_2;
+	 wire	[5:0]	CH_int_3;
+	 wire	[31:0]  wb_dat_gpio_1;
+	 wire	[31:0]  wb_dat_gpio_2;
+	 wire	[31:0]  wb_dat_gpio_3;
+	 wire	[3:0]	SN_1;
+	 wire	[3:0]	SN_2;
+	 wire	[3:0]	SN_3;
+	 wire		CONV_STEP_1;
+	 wire		CONV_STEP_2;
+	 wire		CONV_STEP_3;
+	 wire	[31:0]  wb_con_19_1;
+	 wire	[31:0]  wb_con_19_2;
+	 wire	[31:0]  wb_con_19_3;
+	 wire	[31:0]  wb_stb_slave_1;
+	 wire	[31:0]  wb_stb_slave_2;
+	 wire	[31:0]  wb_stb_slave_3;
+	 wire	[20:0]  IE_CH_1;
+	 wire	[20:0]  IE_CH_2;
+	 wire	[20:0]  IE_CH_3;
+	 reg	[31:0]  wb_con_20_1, wb_con_20_2, wb_con_20_3;
+	 reg            ADC_ack_1,   ADC_ack_2,   ADC_ack_3;
+	 reg            ADC_int_1,   ADC_int_2,   ADC_int_3;
+	 wire	[5:0]	ack_in_1;
+	 wire	[5:0]	ack_in_2;
+	 wire	[5:0]	ack_in_3;
+	 wire		ack_out_1;
+	 wire		ack_out_2;
+	 wire		ack_out_3;
+	 wire	[3:0]	wb_sel_o_1;
+	 wire	[3:0]	wb_sel_o_2;
+	 wire	[3:0]	wb_sel_o_3;
+	 wire		rst_el_s_1;
+	 wire		rst_el_s_2;
+	 wire		rst_el_s_3;
+	 wire	[31:0]  wb_dat_o_1;
+	 wire	[31:0]  wb_dat_o_2;
+	 wire	[31:0]  wb_dat_o_3;
+	 wire		wb_cyc_o_1;
+	 wire		wb_cyc_o_2;
+	 wire		wb_cyc_o_3;
+	 wire		FCLRN_1;
+	 wire		FCLRN_2;
+	 wire		FCLRN_3;
+	 wire		FSETP_1;
+	 wire	        FSETP_2;
+	 wire	        FSETP_3;
+	 wire   [15:0]  SDA_OUT_1;
+	 wire   [15:0]  SDA_OUT_2;
+	 wire   [15:0]  SDA_OUT_3;
+	 wire	        ElinkReset_1;
+	 wire	        ElinkReset_2;
+	 wire	        ElinkReset_3;	    
+	 wire	        reset_1;
+	 wire	        reset_2;
+	 wire	        reset_3;
+	 wire	        nctrl_tx_dav_1,     nctrl_tx_dav_2,     nctrl_tx_dav_3;
+	 wire	[15:0]  nctrl_tx_dat_1,     nctrl_tx_dat_2,     nctrl_tx_dat_3;  
+	 wire	        nctrl_rx_ena_1,     nctrl_rx_ena_2,     nctrl_rx_ena_3;
+	 wire	        nctrl_rx_dav_1,     nctrl_rx_dav_2,     nctrl_rx_dav_3;
+	 wire	[15:0]  nctrl_rx_dat_1,     nctrl_rx_dat_2,     nctrl_rx_dat_3;
+	 wire	        nctrl_tx_ena_1,     nctrl_tx_ena_2,     nctrl_tx_ena_3; 
+	 wire   [15:0]  SCL_inv_1,          SCL_inv_2,          SCL_inv_3;         
+	 wire	        anaEXT_CLK; 
+
+	`ifdef WithSEUcounter
+	 wire  SEU_NCTRLflag;						  
+	 wire  SEUclear_1,SEUclear_2,SEUclear_3;
+	 wire  [15:0] SEU_cnt_1, SEU_cnt_2, SEU_cnt_3;
+	`endif 
+	`ifdef ClkGate_channels
+	 wire  [31:0] EN_ch_reg_1, EN_ch_reg_2, EN_ch_reg_3;
+	 wire  [21:0] ch_clk_g_1,  ch_clk_g_2,  ch_clk_g_3;
+	 wire  [21:0] ch_res_1,    ch_res_2,    ch_res_3;
+	`endif 
+
+
+
+	// RESET LOGIC ///////////////////////////////////////////////
+	// cadence dc::set_dont_touch ResetLogicV
+
+	ResetLogicVoted ResetLogicV(
+		.ElinkReset_1(ElinkReset_1),	  .ElinkReset_2(ElinkReset_2),     .ElinkReset_3(ElinkReset_3),
+		.PowerUpReset_1(PowerUpReset_1),  .PowerUpReset_2(PowerUpReset_2), .PowerUpReset_3(PowerUpReset_3),
+		.PromtReset_1(PromtReset_1),	  .PromtReset_2(PromtReset_2),        
+		.SystemReset_1(reset_1),	  .SystemReset_2(reset_2),	   .SystemReset_3(reset_3),
+		.clk_1(clock_1),		  .clk_2(clock_2),		   .clk_3(clock_3)
+	);
+
+	// SEU COUNTER ///////////////////////////////////////////////
+	`ifdef WithSEUcounter	
+	SEU_counter SEU_cnt(
+		.clk_1(clock_1),		  .clk_2(clock_2),		   .clk_3(clock_3),
+		.res_1(reset_1),		  .res_2(reset_2),		   .res_3(reset_3),
+		.clear_1(SEUclear_1),		  .clear_2(SEUclear_2),            .clear_3(SEUclear_3),
+		.err_1(SEU_NCTRLflag1), 	  .err_2(SEU_NCTRLflag2),	   .err_3(SEU_NCTRLflag3), 
+		.SEU_count_1(SEU_cnt_1),	  .SEU_count_2(SEU_cnt_2),	   .SEU_count_3(SEU_cnt_3)
+	); 
+	`endif
+
+	// CLOCK CONTROL ///////////////////////////////////////////////   
+	`ifdef ClkGate_channels
+	ClkGate_Reset_channels_tri # (
+		.n_ch(22)
+	)ch_clk_gating(
+		.clk_1(clock_1),		  .clk_2(clock_2),		   .clk_3(clock_3),	  
+		.reset_1(reset_1),		  .reset_2(reset_2),		   .reset_3(reset_3),	
+		.ch_enable_1(EN_ch_reg_1[21:0]),  .ch_enable_2(EN_ch_reg_2[21:0]), .ch_enable_3(EN_ch_reg_3[21:0]),  
+		.ch_clk_1(ch_clk_g_1[21:0]),	  .ch_clk_2(ch_clk_g_2[21:0]),     .ch_clk_3(ch_clk_g_3[21:0]),  
+		.ch_res_1(ch_res_1),		  .ch_res_2(ch_res_2),  	   .ch_res_3(ch_res_3)
+	);
+	`endif 
+
+	// SWITCH INPUT PORT ///////////////////////////////////////////////	 
+	SwitchPort_tri SwitchPort(
+		.clk_1(clock_1),		       .clk_2(clock_2),  		      .clk_3(clock_3),
+		.resetB_1(~PowerUpReset_1),	       .resetB_2(~PowerUpReset_2),	      .resetB_3(~PowerUpReset_3),
+		.auxPort_TestEn_1(auxPort_TestEn_1),   .auxPort_TestEn_2(auxPort_TestEn_2),   .auxPort_TestEn_3(auxPort_TestEn_3),
+		.auxPort_SCL_1(auxPort_SCL_1),         .auxPort_SCL_2(auxPort_SCL_2),	      .auxPort_SCL_3(auxPort_SCL_3),
+		.auxPort_SDA_in_1(auxPort_SDA_in_1),   .auxPort_SDA_in_2(auxPort_SDA_in_2),   .auxPort_SDA_in_3(auxPort_SDA_in_3),      
+		.auxPort_SDA_out_1(auxPort_SDA_out_1), .auxPort_SDA_out_2(auxPort_SDA_out_2), .auxPort_SDA_out_3(auxPort_SDA_out_3),
+		.auxPort_SDA_oEn_1(auxPort_SDA_oEn_1), .auxPort_SDA_oEn_2(auxPort_SDA_oEn_2), .auxPort_SDA_oEn_3(auxPort_SDA_oEn_3),
+		.nctrl_tx_dav_1(nctrl_tx_dav_1),       .nctrl_tx_dav_2(nctrl_tx_dav_2),       .nctrl_tx_dav_3(nctrl_tx_dav_3),
+		.nctrl_tx_dat_1(nctrl_tx_dat_1),       .nctrl_tx_dat_2(nctrl_tx_dat_2),       .nctrl_tx_dat_3(nctrl_tx_dat_3),  
+		.nctrl_rx_ena_1(nctrl_rx_ena_1),       .nctrl_rx_ena_2(nctrl_rx_ena_2),       .nctrl_rx_ena_3(nctrl_rx_ena_3),
+		.nctrl_rx_dav_1(nctrl_rx_dav_1),       .nctrl_rx_dav_2(nctrl_rx_dav_2),       .nctrl_rx_dav_3(nctrl_rx_dav_3),
+		.nctrl_rx_dat_1(nctrl_rx_dat_1),       .nctrl_rx_dat_2(nctrl_rx_dat_2),       .nctrl_rx_dat_3(nctrl_rx_dat_3),
+		.nctrl_tx_ena_1(nctrl_tx_ena_1),       .nctrl_tx_ena_2(nctrl_tx_ena_2),       .nctrl_tx_ena_3(nctrl_tx_ena_3),
+		.elink_tx_dav_1(tx_dav_1),	       .elink_tx_dav_2(tx_dav_2),	      .elink_tx_dav_3(tx_dav_3),
+		.elink_tx_dat_1(dataw_out_1),	       .elink_tx_dat_2(dataw_out_2),	      .elink_tx_dat_3(dataw_out_3),
+		.elink_rx_ena_1(rx_ena_1),	       .elink_rx_ena_2(rx_ena_2),	      .elink_rx_ena_3(rx_ena_3),
+		.elink_rx_dav_1(rx_dav_1),	       .elink_rx_dav_2(rx_dav_2),	      .elink_rx_dav_3(rx_dav_3),
+		.elink_rx_dat_1(rx_dat_1),	       .elink_rx_dat_2(rx_dat_2),	      .elink_rx_dat_3(rx_dat_3),
+		.elink_tx_ena_1(tx_ena_1),	       .elink_tx_ena_2(tx_ena_2),	      .elink_tx_ena_3(tx_ena_3)
+	);
+
+	// ARBITER ///////////////////////////////////////////////   
+	ARBITER_tri  arbiter (                
+		.clock_1(clock_1),            .clock_2(clock_2),	  .clock_3(clock_3),
+		.reset_1(reset_1),            .reset_2(reset_2),	  .reset_3(reset_3),
+		.CH_int_1(CH_int_1[5:0]),     .CH_int_2(CH_int_2[5:0]),   .CH_int_3(CH_int_3[5:0]),
+		.IE_CH_1(IE_CH_1[20:0]),      .IE_CH_2(IE_CH_2[20:0]),    .IE_CH_3(IE_CH_3[20:0])
+	);
+
+	// NODE CONTROLLER  ///////////////////////////////////////////////
+
+	sca_node_ctrl_tri  node_ctrl (
+		`ifdef WithSEUcounter
+		.SEU_NCTRLflag1(SEU_NCTRLflag1),    .SEU_NCTRLflag2(SEU_NCTRLflag2),    .SEU_NCTRLflag3(SEU_NCTRLflag3),
+		`endif
+		`ifdef ClkGate_channels
+		.EN_ch_reg_1(EN_ch_reg_1),          .EN_ch_reg_2(EN_ch_reg_2),          .EN_ch_reg_3(EN_ch_reg_3),
+		`endif 
+		.tx_dav_1(nctrl_tx_dav_1),          .tx_dav_2(nctrl_tx_dav_2),          .tx_dav_3(nctrl_tx_dav_3),
+		.rx_dav_1(nctrl_rx_dav_1),          .rx_dav_2(nctrl_rx_dav_2),          .rx_dav_3(nctrl_rx_dav_3), 
+		.dataw_in_1(nctrl_rx_dat_1),        .dataw_in_2(nctrl_rx_dat_2),        .dataw_in_3(nctrl_rx_dat_3),
+		.dataw_out_1(nctrl_tx_dat_1),       .dataw_out_2(nctrl_tx_dat_2),       .dataw_out_3(nctrl_tx_dat_3),
+		.tx_ena_1(nctrl_tx_ena_1),          .tx_ena_2(nctrl_tx_ena_2),          .tx_ena_3(nctrl_tx_ena_3),
+		.rx_ena_1(nctrl_rx_ena_1),          .rx_ena_2(nctrl_rx_ena_2),          .rx_ena_3(nctrl_rx_ena_3),
+		                                                                      
+		.wb_cyc_o_1(wb_cyc_o_1),            .wb_cyc_o_2(wb_cyc_o_2),            .wb_cyc_o_3(wb_cyc_o_3),
+		.clock_1(clock_1),                  .clock_2(clock_2),                  .clock_3(clock_3),
+		.wb_stb_o_1(wb_stb_o_1),            .wb_stb_o_2(wb_stb_o_2),            .wb_stb_o_3(wb_stb_o_3),
+		.wb_addr_o_1(wb_addr_o_1[31:0]),    .wb_addr_o_2(wb_addr_o_2[31:0]),    .wb_addr_o_3(wb_addr_o_3[31:0]),
+		.wb_ack_i_1(ack_out_1),             .wb_ack_i_2(ack_out_2),             .wb_ack_i_3(ack_out_3),
+		.wb_err_in_1(wb_err_o_1),           .wb_err_in_2(wb_err_o_2),           .wb_err_in_3(wb_err_o_3),
+		.Int_arb_in_1(CH_int_1[5:0]),       .Int_arb_in_2(CH_int_2[5:0]),       .Int_arb_in_3(CH_int_3[5:0]),
+		.CRE_1(CRE_1[7:0]),                 .CRE_2(CRE_2[7:0]),                 .CRE_3(CRE_3[7:0]),
+		.wb_dat_i_1(wb_con_data_o_1[31:0]), .wb_dat_i_2(wb_con_data_o_2[31:0]), .wb_dat_i_3(wb_con_data_o_3[31:0]),
+		.wb_dat_o_1(wb_data_1[31:0]),       .wb_dat_o_2(wb_data_2[31:0]),       .wb_dat_o_3(wb_data_3[31:0]),
+		.wb_sel_o_1(wb_sel_o_1[3:0]),       .wb_sel_o_2(wb_sel_o_2[3:0]),       .wb_sel_o_3(wb_sel_o_3[3:0]),
+		.wb_we_o_1(wb_we_o_1),              .wb_we_o_2(wb_we_o_2),              .wb_we_o_3(wb_we_o_3),
+		.reset_1(reset_1),                  .reset_2(reset_2),                  .reset_3(reset_3)    
+	);
+
+
+	// WHISHBONE CONNECT FABRIC ///////////////////////////////////////////////
+	ack_and_tri  C54_ack_and(
+		.ack_in_1(ack_in_1[5:0]), .ack_in_2(ack_in_2[5:0]),  .ack_in_3(ack_in_3[5:0]),
+		.ack_out_1(ack_out_1),    .ack_out_2(ack_out_2),     .ack_out_3(ack_out_3) 
+	);
+
+	wb_addr_decod_tri  WB_intercon(
+		.wb_addr_1(wb_addr_o_1[11:7]),		  .wb_addr_2(wb_addr_o_2[11:7]),	   .wb_addr_3(wb_addr_o_3[11:7]),
+		.wb_stb_slave_1(wb_stb_slave_1[31:0]),	  .wb_stb_slave_2(wb_stb_slave_2[31:0]),   .wb_stb_slave_3(wb_stb_slave_3[31:0]),
+		.wb_stb_1(wb_stb_o_1),			  .wb_stb_2(wb_stb_o_2),		   .wb_stb_3(wb_stb_o_3),
+		.wb_con_in_1_1(wb_dat_spi_1[31:0]),	  .wb_con_in_1_2(wb_dat_spi_2[31:0]),	   .wb_con_in_1_3(wb_dat_spi_3[31:0]),
+		.wb_con_in_3_1(wb_dat_o0_1[31:0]),	  .wb_con_in_3_2(wb_dat_o0_2[31:0]),	   .wb_con_in_3_3(wb_dat_o0_3[31:0]),
+		.wb_con_in_2_1(wb_dat_gpio_1[31:0]),	  .wb_con_in_2_2(wb_dat_gpio_2[31:0]),	   .wb_con_in_2_3(wb_dat_gpio_3[31:0]),
+		.wb_con_in_4_1(wb_dat_o1_1[31:0]),	  .wb_con_in_4_2(wb_dat_o1_2[31:0]),	   .wb_con_in_4_3(wb_dat_o1_3[31:0]),
+		.wb_con_in_5_1(wb_dat_o2_1[31:0]),	  .wb_con_in_5_2(wb_dat_o2_2[31:0]),	   .wb_con_in_5_3(wb_dat_o2_3[31:0]),
+		.wb_con_in_6_1(wb_dat_o3_1[31:0]),	  .wb_con_in_6_2(wb_dat_o3_2[31:0]),	   .wb_con_in_6_3(wb_dat_o3_3[31:0]),
+		.wb_con_in_7_1(wb_dat_o4_1[31:0]),	  .wb_con_in_7_2(wb_dat_o4_2[31:0]),	   .wb_con_in_7_3(wb_dat_o4_3[31:0]),
+		.wb_con_in_8_1(wb_dat_o5_1[31:0]),	  .wb_con_in_8_2(wb_dat_o5_2[31:0]),	   .wb_con_in_8_3(wb_dat_o5_3[31:0]),
+		.wb_con_in_9_1(wb_dat_o6_1[31:0]),	  .wb_con_in_9_2(wb_dat_o6_2[31:0]),	   .wb_con_in_9_3(wb_dat_o6_3[31:0]),
+		.wb_con_in_10_1(wb_dat_o7_1[31:0]),	  .wb_con_in_10_2(wb_dat_o7_2[31:0]),	   .wb_con_in_10_3(wb_dat_o7_3[31:0]),
+		.wb_con_in_11_1(wb_dat_o8_1[31:0]),	  .wb_con_in_11_2(wb_dat_o8_2[31:0]),	   .wb_con_in_11_3(wb_dat_o8_3[31:0]),
+		.wb_con_in_12_1(wb_dat_o9_1[31:0]),	  .wb_con_in_12_2(wb_dat_o9_2[31:0]),	   .wb_con_in_12_3(wb_dat_o9_3[31:0]),
+		.wb_con_in_13_1(wb_dat_o10_1[31:0]),	  .wb_con_in_13_2(wb_dat_o10_2[31:0]),	   .wb_con_in_13_3(wb_dat_o10_3[31:0]),
+		.wb_con_in_14_1(wb_dat_o11_1[31:0]),	  .wb_con_in_14_2(wb_dat_o11_2[31:0]),	   .wb_con_in_14_3(wb_dat_o11_3[31:0]),
+		.wb_con_in_15_1(wb_dat_o12_1[31:0]),	  .wb_con_in_15_2(wb_dat_o12_2[31:0]),	   .wb_con_in_15_3(wb_dat_o12_3[31:0]),
+		.wb_con_in_16_1(wb_dat_o13_1[31:0]),	  .wb_con_in_16_2(wb_dat_o13_2[31:0]),	   .wb_con_in_16_3(wb_dat_o13_3[31:0]),
+		.wb_con_in_17_1(wb_dat_o14_1[31:0]),	  .wb_con_in_17_2(wb_dat_o14_2[31:0]),	   .wb_con_in_17_3(wb_dat_o14_3[31:0]),
+		.wb_con_in_18_1(wb_dat_o15_1[31:0]),	  .wb_con_in_18_2(wb_dat_o15_2[31:0]),	   .wb_con_in_18_3(wb_dat_o15_3[31:0]),
+		.wb_con_in_19_1(wb_con_19_1[31:0]),	  .wb_con_in_19_2(wb_con_19_2[31:0]),	   .wb_con_in_19_3(wb_con_19_3[31:0]),
+		.wb_con_in_20_1(wb_con_20_1[31:0]),	  .wb_con_in_20_2(wb_con_20_2[31:0]),	   .wb_con_in_20_3(wb_con_20_3[31:0]),
+		.wb_con_in_21_1(wb_dat_o_1[31:0]),	  .wb_con_in_21_2(wb_dat_o_2[31:0]),	   .wb_con_in_21_3(wb_dat_o_3[31:0]),
+		.wb_con_data_o_1(wb_con_data_o_1[31:0]),  .wb_con_data_o_2(wb_con_data_o_2[31:0]), .wb_con_data_o_3(wb_con_data_o_3[31:0])	
+	);
+
+
+
+	// ELINK PORT  ///////////////////////////////////////////////
+	elink_tri #(0, 1)  elink_slave(
+		.tx_dat_1(dataw_out_1[15:0]),	  .tx_dat_2(dataw_out_2[15:0]),     .tx_dat_3(dataw_out_3[15:0]),
+		.rx_dat_1(rx_dat_1[15:0]),	  .rx_dat_2(rx_dat_2[15:0]),	    .rx_dat_3(rx_dat_3[15:0]),
+		.tx_sd_1(tx_sd_1),		  .tx_sd_2(tx_sd_2),		    .tx_sd_3(tx_sd_3),
+		.tx_sd_aux_1(tx_sd_aux_1),	  .tx_sd_aux_2(tx_sd_aux_2),	    .tx_sd_aux_3(tx_sd_aux_3),
+		.tx_ena_1(tx_ena_1),		  .tx_ena_2(tx_ena_2),		    .tx_ena_3(tx_ena_3),
+		.rx_sd_1(rx_sd_1),		  .rx_sd_2(rx_sd_2),		    .rx_sd_3(rx_sd_3),
+		.rx_sd_aux_1(rx_sd_aux_1),	  .rx_sd_aux_2(rx_sd_aux_2),	    .rx_sd_aux_3(rx_sd_aux_3),
+		.link_clk_1(link_clk_1),	  .link_clk_2(link_clk_2),	    .link_clk_3(link_clk_3),
+		.link_clk_aux_1(link_clk_aux_1),  .link_clk_aux_2(link_clk_aux_2),  .link_clk_aux_3(link_clk_aux_3),
+		.user_clk_1(clock_1),		  .user_clk_2(clock_2), 	    .user_clk_3(clock_3),
+		.rx_ena_1(rx_ena_1),		  .rx_ena_2(rx_ena_2),		    .rx_ena_3(rx_ena_3),
+		.rx_dav_1(rx_dav_1),		  .rx_dav_2(rx_dav_2),		    .rx_dav_3(rx_dav_3),
+		.resetb_1(rst_el_s_1),		  .resetb_2(rst_el_s_2),	    .resetb_3(rst_el_s_3),
+		.rx_eop_1(),			  .rx_eop_2(),			    .rx_eop_3(),
+		.rx_err_1(),			  .rx_err_2(),			    .rx_err_3(),
+		.tx_dav_1(tx_dav_1),		  .tx_dav_2(tx_dav_2),		    .tx_dav_3(tx_dav_3),
+		.rx_sop_1(),			  .rx_sop_2(),			    .rx_sop_3(),
+		.tx_adr_1(tx_adr_1[7:0]),	  .tx_adr_2(tx_adr_2[7:0]),	    .tx_adr_3(tx_adr_3[7:0]),
+		.rx_adr_1(),			  .rx_adr_2(),			    .rx_adr_3(),
+		.tx_cmd_reset_1(1'b0),		  .tx_cmd_reset_2(1'b0),	    .tx_cmd_reset_3(1'b0),
+		.rx_cmd_reset_1(ElinkReset_1),	  .rx_cmd_reset_2(ElinkReset_2),    .rx_cmd_reset_3(ElinkReset_3),
+		.tx_cmd_test_1(1'b0),		  .tx_cmd_test_2(1'b0), 	    .tx_cmd_test_3(1'b0),
+		.rx_cmd_test_1(),		  .rx_cmd_test_2(),		    .rx_cmd_test_3(),
+		.tx_cset_1(CRE_1[3:0]), 	  .tx_cset_2(CRE_2[3:0]),	    .tx_cset_3(CRE_3[3:0]),
+		.tx_ns_1(),			  .tx_ns_2(),			    .tx_ns_3(),
+		.rx_nr_1(),			  .rx_nr_2(),			    .rx_nr_3(),
+		.rx_cmd_srej_1(),		  .rx_cmd_srej_2(),		    .rx_cmd_srej_3(),
+		.cmd_busy_1(),			  .cmd_busy_2(),		    .cmd_busy_3(),
+		.tx_cmd_sabm_1(1'b0),		  .tx_cmd_sabm_2(1'b0), 	    .tx_cmd_sabm_3(1'b0),
+		.rx_cmd_ua_1(), 		  .rx_cmd_ua_2(),		    .rx_cmd_ua_3(),
+		.rx_ns_1(),			  .rx_ns_2(),			    .rx_ns_3(),
+		.active_aux_1(active_aux_1),	  .active_aux_2(active_aux_2),	    .active_aux_3(active_aux_3),
+		.disable_aux_1(disable_aux_1),	  .disable_aux_2(disable_aux_2),    .disable_aux_3(disable_aux_3)		
+	);
+
+
+	// ADC ///////////////////////////////////////////////
+	assign  ADC_wb_RES_1      = ch_res_1[CH_ADC];
+	assign  ADC_wb_RES_2      = ch_res_2[CH_ADC];
+	assign  ADC_wb_RES_3      = ch_res_3[CH_ADC];
+	assign  ADC_wb_RES_1      = ch_res_1[CH_ADC];
+	assign  ADC_wb_RES_2      = ch_res_2[CH_ADC];
+	assign  ADC_wb_RES_3      = ch_res_3[CH_ADC];
+	assign  ADC_wb_CLK_1      = clock_1;
+	assign  ADC_wb_CLK_2      = clock_2;
+	assign  ADC_wb_CLK_3      = clock_3;
+	assign  ADC_wb_SEL_1      = wb_sel_o_1[3:0];
+	assign  ADC_wb_SEL_2      = wb_sel_o_2[3:0];
+	assign  ADC_wb_SEL_3      = wb_sel_o_3[3:0];
+	assign  ADC_wb_WE_1       = wb_we_o_1;
+	assign  ADC_wb_WE_2       = wb_we_o_2;
+	assign  ADC_wb_WE_3       = wb_we_o_3;
+	assign  ADC_wb_STB_1      = wb_stb_slave_1[19];
+	assign  ADC_wb_STB_2      = wb_stb_slave_2[19];
+	assign  ADC_wb_STB_3      = wb_stb_slave_3[19];
+	assign  ADC_wb_CYC_1      = wb_cyc_o_1;
+	assign  ADC_wb_CYC_2      = wb_cyc_o_2;
+	assign  ADC_wb_CYC_3      = wb_cyc_o_3;
+	assign  ADC_wb_ADR_1[3:0] = wb_addr_o_1[5:2];
+	assign  ADC_wb_ADR_2[3:0] = wb_addr_o_2[5:2];
+	assign  ADC_wb_ADR_3[3:0] = wb_addr_o_3[5:2];
+	assign  ADC_wb_DATi_1     = wb_data_1[31:0];
+	assign  ADC_wb_DATi_2     = wb_data_2[31:0];
+	assign  ADC_wb_DATi_3     = wb_data_3[31:0];
+	assign  ack_in_1[5]       = ADC_ack_1;
+	assign  ack_in_2[5]       = ADC_ack_2;
+	assign  ack_in_3[5]       = ADC_ack_3;
+	assign  IE_CH_1[20]	  = ADC_int_1;
+	assign  IE_CH_2[20]	  = ADC_int_2;
+	assign  IE_CH_3[20]	  = ADC_int_3;  
+	
+	always @(posedge clock_1 or posedge ch_res_1[CH_ADC]) begin
+		if (ch_res_1[CH_ADC]) begin
+			ADC_ack_1    <= 1'b0;
+			ADC_ack_2    <= 1'b0;
+			ADC_ack_3    <= 1'b0;
+			ADC_int_1    <= 1'b0;
+			ADC_int_2    <= 1'b0;
+			ADC_int_3    <= 1'b0;
+			wb_con_20_1  <= 32'h0;
+			wb_con_20_2  <= 32'h0;
+			wb_con_20_3  <= 32'h0;
+		end 
+		else begin
+			ADC_ack_1    <= ADC_wb_ACK_1;
+			ADC_ack_2    <= ADC_wb_ACK_2;
+			ADC_ack_3    <= ADC_wb_ACK_3;
+			ADC_int_1    <= ADC_wb_INT_1;
+			ADC_int_2    <= ADC_wb_INT_2;
+			ADC_int_3    <= ADC_wb_INT_3;
+			wb_con_20_1  <= ADC_wb_DATo_1;
+			wb_con_20_2  <= ADC_wb_DATo_2;
+			wb_con_20_3  <= ADC_wb_DATo_3;
+		end
+	end
+
+	// I2C 0 TO 15  ///////////////////////////////////////////////
+	i2c_gener_tri  I2C_16x(
+		.reset_1(ch_res_1[CH_I2C15:CH_I2C0]),
+		.clock_1(ch_clk_g_1[CH_I2C15:CH_I2C0]),
+		.wb_stb_i_1(wb_stb_slave_1[31:0]),
+		.wb_dat_i_1(wb_data_1[31:0]),
+		.wb_adr_i_1(wb_addr_o_1[4:0]),
+		.wb_dat_o0_1(wb_dat_o0_1[31:0]),
+		.wb_dat_o1_1(wb_dat_o1_1[31:0]),
+		.wb_dat_o2_1(wb_dat_o2_1[31:0]),
+		.wb_dat_o3_1(wb_dat_o3_1[31:0]),
+		.wb_dat_o4_1(wb_dat_o4_1[31:0]),
+		.wb_dat_o5_1(wb_dat_o5_1[31:0]),
+		.wb_dat_o6_1(wb_dat_o6_1[31:0]),
+		.wb_dat_o7_1(wb_dat_o7_1[31:0]),
+		.wb_dat_o8_1(wb_dat_o8_1[31:0]),
+		.wb_dat_o9_1(wb_dat_o9_1[31:0]),
+		.wb_dat_o10_1(wb_dat_o10_1[31:0]),
+		.wb_dat_o11_1(wb_dat_o11_1[31:0]),
+		.wb_dat_o12_1(wb_dat_o12_1[31:0]),
+		.wb_dat_o13_1(wb_dat_o13_1[31:0]),
+		.wb_dat_o14_1(wb_dat_o14_1[31:0]),
+		.wb_dat_o15_1(wb_dat_o15_1[31:0]),
+		.wb_ack_out_1(ack_in_1[2]),
+		.wb_we_1(wb_we_o_1),
+		.wb_sel_1(wb_sel_o_1[3:0]),
+		.SCL_1(SCL_inv_1[15:0]),
+		.SDA_in_1(SDA_in_1[15:0]),
+		.SDA_OUT_1(SDA_OUT_1[15:0]),
+		.wb_i2c_int_1(IE_CH_1[18:3]),
+		.wb_cyc_1(wb_cyc_o_1),
+		.SCLEN_1(SCLEN_1),
+		       .reset_2(ch_res_2[CH_I2C15:CH_I2C0]),
+		.clock_2(ch_clk_g_2[CH_I2C15:CH_I2C0]),
+		.wb_stb_i_2(wb_stb_slave_2[31:0]),
+		.wb_dat_i_2(wb_data_2[31:0]),
+		.wb_adr_i_2(wb_addr_o_2[4:0]),
+		.wb_dat_o0_2(wb_dat_o0_2[31:0]),
+		.wb_dat_o1_2(wb_dat_o1_2[31:0]),
+		.wb_dat_o2_2(wb_dat_o2_2[31:0]),
+		.wb_dat_o3_2(wb_dat_o3_2[31:0]),
+		.wb_dat_o4_2(wb_dat_o4_2[31:0]),
+		.wb_dat_o5_2(wb_dat_o5_2[31:0]),
+		.wb_dat_o6_2(wb_dat_o6_2[31:0]),
+		.wb_dat_o7_2(wb_dat_o7_2[31:0]),
+		.wb_dat_o8_2(wb_dat_o8_2[31:0]),
+		.wb_dat_o9_2(wb_dat_o9_2[31:0]),
+		.wb_dat_o10_2(wb_dat_o10_2[31:0]),
+		.wb_dat_o11_2(wb_dat_o11_2[31:0]),
+		.wb_dat_o12_2(wb_dat_o12_2[31:0]),
+		.wb_dat_o13_2(wb_dat_o13_2[31:0]),
+		.wb_dat_o14_2(wb_dat_o14_2[31:0]),
+		.wb_dat_o15_2(wb_dat_o15_2[31:0]),
+		.wb_ack_out_2(ack_in_2[2]),
+		.wb_we_2(wb_we_o_2),
+		.wb_sel_2(wb_sel_o_2[3:0]),
+		.SCL_2(SCL_inv_2[15:0]),
+		.SDA_in_2(SDA_in_2[15:0]),
+		.SDA_OUT_2(SDA_OUT_2[15:0]),
+		.wb_i2c_int_2(IE_CH_2[18:3]),
+		.wb_cyc_2(wb_cyc_o_2),
+		.SCLEN_2(SCLEN_2),
+		       .reset_3(ch_res_3[CH_I2C15:CH_I2C0]),
+		.clock_3(ch_clk_g_3[CH_I2C15:CH_I2C0]),
+		.wb_stb_i_3(wb_stb_slave_3[31:0]),
+		.wb_dat_i_3(wb_data_3[31:0]),
+		.wb_adr_i_3(wb_addr_o_3[4:0]),
+		.wb_dat_o0_3(wb_dat_o0_3[31:0]),
+		.wb_dat_o1_3(wb_dat_o1_3[31:0]),
+		.wb_dat_o2_3(wb_dat_o2_3[31:0]),
+		.wb_dat_o3_3(wb_dat_o3_3[31:0]),
+		.wb_dat_o4_3(wb_dat_o4_3[31:0]),
+		.wb_dat_o5_3(wb_dat_o5_3[31:0]),
+		.wb_dat_o6_3(wb_dat_o6_3[31:0]),
+		.wb_dat_o7_3(wb_dat_o7_3[31:0]),
+		.wb_dat_o8_3(wb_dat_o8_3[31:0]),
+		.wb_dat_o9_3(wb_dat_o9_3[31:0]),
+		.wb_dat_o10_3(wb_dat_o10_3[31:0]),
+		.wb_dat_o11_3(wb_dat_o11_3[31:0]),
+		.wb_dat_o12_3(wb_dat_o12_3[31:0]),
+		.wb_dat_o13_3(wb_dat_o13_3[31:0]),
+		.wb_dat_o14_3(wb_dat_o14_3[31:0]),
+		.wb_dat_o15_3(wb_dat_o15_3[31:0]),
+		.wb_ack_out_3(ack_in_3[2]),
+		.wb_we_3(wb_we_o_3),
+		.wb_sel_3(wb_sel_o_3[3:0]),
+		.SCL_3(SCL_inv_3[15:0]),
+		.SDA_in_3(SDA_in_3[15:0]),
+		.SDA_OUT_3(SDA_OUT_3[15:0]),
+		.wb_i2c_int_3(IE_CH_3[18:3]),
+		.wb_cyc_3(wb_cyc_o_3),
+		.SCLEN_3(SCLEN_3)
+	);
+
+
+	// SPI  ///////////////////////////////////////////////
+	spi_top_tri  SPI_mast(
+		.wb_clk_i_1(ch_clk_g_1[CH_SPI]),
+		.wb_rst_i_1(ch_res_1[CH_SPI]),
+		.wb_adr_i_1(wb_addr_o_1[4:0]),
+		.wb_dat_i_1(wb_data_1[31:0]),
+		.wb_dat_o_1(wb_dat_spi_1[31:0]),
+		.wb_sel_i_1(wb_sel_o_1[3:0]),
+		.wb_we_i_1(wb_we_o_1),
+		.wb_stb_i_1(wb_stb_slave_1[0]),
+		.wb_cyc_i_1(wb_cyc_o_1),
+		.wb_ack_o_1(ack_in_1[0]),
+		.wb_err_o_1(),
+		.wb_int_o_1(IE_CH_1[1]),
+		.ss_pad_o_1(SPI_ss_pad_o_1[7:0]),
+		.sclk_pad_o_1(SPI_sclk_pad_o_1),
+		.mosi_pad_o_1(SPI_mosi_pad_o_1),
+		.miso_pad_i_1(SPI_miso_pad_i_1),
+		       .wb_clk_i_2(ch_clk_g_2[CH_SPI]),
+		.wb_rst_i_2(ch_res_2[CH_SPI]),
+		.wb_adr_i_2(wb_addr_o_2[4:0]),
+		.wb_dat_i_2(wb_data_2[31:0]),
+		.wb_dat_o_2(wb_dat_spi_2[31:0]),
+		.wb_sel_i_2(wb_sel_o_2[3:0]),
+		.wb_we_i_2(wb_we_o_2),
+		.wb_stb_i_2(wb_stb_slave_2[0]),
+		.wb_cyc_i_2(wb_cyc_o_2),
+		.wb_ack_o_2(ack_in_2[0]),
+		.wb_err_o_2(),
+		.wb_int_o_2(IE_CH_2[1]),
+		.ss_pad_o_2(SPI_ss_pad_o_2[7:0]),
+		.sclk_pad_o_2(SPI_sclk_pad_o_2),
+		.mosi_pad_o_2(SPI_mosi_pad_o_2),
+		.miso_pad_i_2(SPI_miso_pad_i_2),
+		       .wb_clk_i_3(ch_clk_g_3[CH_SPI]),
+		.wb_rst_i_3(ch_res_3[CH_SPI]),
+		.wb_adr_i_3(wb_addr_o_3[4:0]),
+		.wb_dat_i_3(wb_data_3[31:0]),
+		.wb_dat_o_3(wb_dat_spi_3[31:0]),
+		.wb_sel_i_3(wb_sel_o_3[3:0]),
+		.wb_we_i_3(wb_we_o_3),
+		.wb_stb_i_3(wb_stb_slave_3[0]),
+		.wb_cyc_i_3(wb_cyc_o_3),
+		.wb_ack_o_3(ack_in_3[0]),
+		.wb_err_o_3(),
+		.wb_int_o_3(IE_CH_3[1]),
+		.ss_pad_o_3(SPI_ss_pad_o_3[7:0]),
+		.sclk_pad_o_3(SPI_sclk_pad_o_3),
+		.mosi_pad_o_3(SPI_mosi_pad_o_3),
+		.miso_pad_i_3(SPI_miso_pad_i_3)
+	);
+
+	// DAC  ///////////////////////////////////////////////
+	DAC_wb_interf_tri  DAC_CH(
+		.wb_clk_in_1(ch_clk_g_1[CH_DAC]),
+		.wb_rst_in_1(ch_res_1[CH_DAC]),
+		.wb_adr_in_1(wb_addr_o_1[4:0]),
+		.wb_dat_in_1(wb_data_1[31:0]),
+		.wb_sel_in_1(wb_sel_o_1[3:0]),
+		.wb_we_in_1(wb_we_o_1),
+		.wb_stb_in_1(wb_stb_slave_1[20]),
+		.wb_cyc_in_1(wb_cyc_o_1),
+		.wb_dat_out_1(wb_dat_o_1[31:0]),
+		.wb_ack_out_1(ack_in_1[3]),
+		.wb_err_out_1(),
+		.wb_int_out_1(),
+		.dac_out_1_1(anaDAC_A_1[7:0]),
+		.dac_out_2_1(anaDAC_B_1[7:0]),
+		.dac_out_3_1(anaDAC_C_1[7:0]),
+		.dac_out_4_1(anaDAC_D_1[7:0]),
+		 
+		.wb_clk_in_2(ch_clk_g_2[CH_DAC]),
+		.wb_rst_in_2(ch_res_2[CH_DAC]),
+		.wb_adr_in_2(wb_addr_o_2[4:0]),
+		.wb_dat_in_2(wb_data_2[31:0]),
+		.wb_sel_in_2(wb_sel_o_2[3:0]),
+		.wb_we_in_2(wb_we_o_2),
+		.wb_stb_in_2(wb_stb_slave_2[20]),
+		.wb_cyc_in_2(wb_cyc_o_2),
+		.wb_dat_out_2(wb_dat_o_2[31:0]),
+		.wb_ack_out_2(ack_in_2[3]),
+		.wb_err_out_2(),
+		.wb_int_out_2(),
+		.dac_out_1_2(anaDAC_A_2[7:0]),
+		.dac_out_2_2(anaDAC_B_2[7:0]),
+		.dac_out_3_2(anaDAC_C_2[7:0]),
+		.dac_out_4_2(anaDAC_D_2[7:0]),
+
+		.wb_clk_in_3(ch_clk_g_3[CH_DAC]),
+		.wb_rst_in_3(ch_res_3[CH_DAC]),
+		.wb_adr_in_3(wb_addr_o_3[4:0]),
+		.wb_dat_in_3(wb_data_3[31:0]),
+		.wb_sel_in_3(wb_sel_o_3[3:0]),
+		.wb_we_in_3(wb_we_o_3),
+		.wb_stb_in_3(wb_stb_slave_3[20]),
+		.wb_cyc_in_3(wb_cyc_o_3),
+		.wb_dat_out_3(wb_dat_o_3[31:0]),
+		.wb_ack_out_3(ack_in_3[3]),
+		.wb_err_out_3(),
+		.wb_int_out_3(),
+		.dac_out_1_3(anaDAC_A_3[7:0]),
+		.dac_out_2_3(anaDAC_B_3[7:0]),
+		.dac_out_3_3(anaDAC_C_3[7:0]),
+		.dac_out_4_3(anaDAC_D_3[7:0])
+	);
+
+	// JTAG  ///////////////////////////////////////////////     
+	JTAG_Master_Top_tri  C67_JTAG(
+		`ifdef WithSEUcounter
+		.SEUclear_1(SEUclear_1),
+		.SEUclear_2(SEUclear_2),
+		.SEUclear_3(SEUclear_3),
+		.SEU_cnt_1(SEU_cnt_1), 
+		.SEU_cnt_2(SEU_cnt_2), 
+		.SEU_cnt_3(SEU_cnt_3),
+		`endif
+		.TCK_pad_o_1(JTAG_TCK_pad_o_1),
+		.TDI_pad_i_1(JTAG_TDI_pad_i_1),
+		.TDO_pad_o_1(JTAG_TDO_pad_o_1),
+		.TMS_pad_o_1(JTAG_TMS_pad_o_1),
+		.RST_pad_o_1(JTAG_RST_pad_o_1),
+		.wb_clk_i_1(ch_clk_g_1[CH_JTAG]),
+		.wb_rst_i_1(ch_res_1[CH_JTAG]),
+		.wb_adr_i_1(wb_addr_o_1[5:0]),
+		.wb_dat_i_1(wb_data_1[31:0]),
+		.wb_dat_o_1(wb_con_19_1[31:0]),
+		.wb_sel_i_1(wb_sel_o_1[3:0]),
+		.wb_we_i_1(wb_we_o_1),
+		.wb_stb_i_1(wb_stb_slave_1[18]),
+		.wb_cyc_i_1(wb_cyc_o_1),
+		.wb_ack_o_1(ack_in_1[4]),
+		.wb_err_o_1(),
+		.wb_int_o_1(IE_CH_1[19]),
+
+		.TCK_pad_o_2(JTAG_TCK_pad_o_2),
+		.TDI_pad_i_2(JTAG_TDI_pad_i_2),
+		.TDO_pad_o_2(JTAG_TDO_pad_o_2),
+		.TMS_pad_o_2(JTAG_TMS_pad_o_2),
+		.RST_pad_o_2(JTAG_RST_pad_o_2),
+		.wb_clk_i_2(ch_clk_g_2[CH_JTAG]),
+		.wb_rst_i_2(ch_res_2[CH_JTAG]),
+		.wb_adr_i_2(wb_addr_o_2[5:0]),
+		.wb_dat_i_2(wb_data_2[31:0]),
+		.wb_dat_o_2(wb_con_19_2[31:0]),
+		.wb_sel_i_2(wb_sel_o_2[3:0]),
+		.wb_we_i_2(wb_we_o_2),
+		.wb_stb_i_2(wb_stb_slave_2[18]),
+		.wb_cyc_i_2(wb_cyc_o_2),
+		.wb_ack_o_2(ack_in_2[4]),
+		.wb_err_o_2(),
+		.wb_int_o_2(IE_CH_2[19]),
+
+		.TCK_pad_o_3(JTAG_TCK_pad_o_3),
+		.TDI_pad_i_3(JTAG_TDI_pad_i_3),
+		.TDO_pad_o_3(JTAG_TDO_pad_o_3),
+		.TMS_pad_o_3(JTAG_TMS_pad_o_3),
+		.RST_pad_o_3(JTAG_RST_pad_o_3),
+		.wb_clk_i_3(ch_clk_g_3[CH_JTAG]),
+		.wb_rst_i_3(ch_res_3[CH_JTAG]),
+		.wb_adr_i_3(wb_addr_o_3[5:0]),
+		.wb_dat_i_3(wb_data_3[31:0]),
+		.wb_dat_o_3(wb_con_19_3[31:0]),
+		.wb_sel_i_3(wb_sel_o_3[3:0]),
+		.wb_we_i_3(wb_we_o_3),
+		.wb_stb_i_3(wb_stb_slave_3[18]),
+		.wb_cyc_i_3(wb_cyc_o_3),
+		.wb_ack_o_3(ack_in_3[4]),
+		.wb_err_o_3(),
+		.wb_int_o_3(IE_CH_3[19])
+	 );
+			 
+	 // GPIO  ///////////////////////////////////////////////     
+	 gpio_top_tri  GPIO(
+		.wb_clk_i_1(ch_clk_g_1[CH_GPIO]),
+		.wb_rst_i_1(ch_res_1[CH_GPIO]),
+		.wb_cyc_i_1(wb_cyc_o_1),
+		.wb_adr_i_1(wb_addr_o_1[7:0]),
+		.wb_dat_i_1(wb_data_1[31:0]),
+		.wb_sel_i_1(wb_sel_o_1[3:0]),
+		.wb_we_i_1(wb_we_o_1),
+		.wb_stb_i_1(wb_stb_slave_1[1]),
+		.wb_dat_o_1(wb_dat_gpio_1[31:0]),
+		.wb_ack_o_1(ack_in_1[1]),
+		.wb_err_o_1(),
+		.wb_inta_o_1(IE_CH_1[2]),
+		.GPIO_ext_pad_i_1(GPIO_ext_pad_i_1[31:0]),
+		.GPIO_ext_pad_o_1(GPIO_ext_pad_o_1[31:0]),
+		.GPIO_ext_padOE_o_1(GPIO_ext_padOE_o_1[31:0]),
+		.GPIO_clk_pad_i_1(GPIO_clk_pad_i_1),
+
+		.wb_clk_i_2(ch_clk_g_2[CH_GPIO]),
+		.wb_rst_i_2(ch_res_2[CH_GPIO]),
+		.wb_cyc_i_2(wb_cyc_o_2),
+		.wb_adr_i_2(wb_addr_o_2[7:0]),
+		.wb_dat_i_2(wb_data_2[31:0]),
+		.wb_sel_i_2(wb_sel_o_2[3:0]),
+		.wb_we_i_2(wb_we_o_2),
+		.wb_stb_i_2(wb_stb_slave_2[1]),
+		.wb_dat_o_2(wb_dat_gpio_2[31:0]),
+		.wb_ack_o_2(ack_in_2[1]),
+		.wb_err_o_2(),
+		.wb_inta_o_2(IE_CH_2[2]),
+		.GPIO_ext_pad_i_2(GPIO_ext_pad_i_2[31:0]),
+		.GPIO_ext_pad_o_2(GPIO_ext_pad_o_2[31:0]),
+		.GPIO_ext_padOE_o_2(GPIO_ext_padOE_o_2[31:0]),
+		.GPIO_clk_pad_i_2(GPIO_clk_pad_i_2),
+
+		.wb_clk_i_3(ch_clk_g_3[CH_GPIO]),
+		.wb_rst_i_3(ch_res_3[CH_GPIO]),
+		.wb_cyc_i_3(wb_cyc_o_3),
+		.wb_adr_i_3(wb_addr_o_3[7:0]),
+		.wb_dat_i_3(wb_data_3[31:0]),
+		.wb_sel_i_3(wb_sel_o_3[3:0]),
+		.wb_we_i_3(wb_we_o_3),
+		.wb_stb_i_3(wb_stb_slave_3[1]),
+		.wb_dat_o_3(wb_dat_gpio_3[31:0]),
+		.wb_ack_o_3(ack_in_3[1]),
+		.wb_err_o_3(),
+		.wb_inta_o_3(IE_CH_3[2]),
+		.GPIO_ext_pad_i_3(GPIO_ext_pad_i_3[31:0]),
+		.GPIO_ext_pad_o_3(GPIO_ext_pad_o_3[31:0]),
+		.GPIO_ext_padOE_o_3(GPIO_ext_padOE_o_3[31:0]),
+		.GPIO_clk_pad_i_3(GPIO_clk_pad_i_3)
+	 );
+
+	   assign IE_CH_1[0] = 1'b0;
+	   assign IE_CH_2[0] = 1'b0;
+	   assign IE_CH_3[0] = 1'b0;
+
+	   assign rst_el_s_1 = ~PowerUpReset_1;
+	   assign rst_el_s_2 = ~PowerUpReset_2;
+	   assign rst_el_s_3 = ~PowerUpReset_3;
+
+	   assign wb_err_o_1 = 1'b0;
+	   assign wb_err_o_2 = 1'b0;
+	   assign wb_err_o_3 = 1'b0;
+	   
+	   assign Reset_BG_1 = ~reset_1;
+	   assign Reset_BG_2 = ~reset_2;
+	   assign Reset_BG_3 = ~reset_3;
+	   
+	   assign SDA_out_inv_1 = ~SDA_OUT_1;	 
+	   assign SDA_out_inv_2 = ~SDA_OUT_2;	 
+	   assign SDA_out_inv_3 = ~SDA_OUT_3;
+	   
+	   assign SCL_1 = SCL_inv_1; //26oct2015
+	   assign SCL_2 = SCL_inv_2; //26oct2015
+	   assign SCL_3 = SCL_inv_3; //26oct2015
+	  
+	   assign anaEXT_CLK_1 = anaEXT_CLK;
+	   assign anaEXT_CLK_2 = anaEXT_CLK;	 
+	   assign anaEXT_CLK_3 = anaEXT_CLK; 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/vldb/code/Testbench/SCA-model/Table_Commande.v b/vldb/code/Testbench/SCA-model/Table_Commande.v
new file mode 100644
index 0000000..1733cce
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/Table_Commande.v
@@ -0,0 +1,183 @@
+///////////////////////////////////////
+//                                   //
+// Table of commands                 //
+// Last modification: 29 sept 2015   //
+//                                   //
+//                                   //
+///////////////////////////////////////
+
+//------------ GLobal -------------
+localparam wb_nb_bit       = 31;    
+localparam atlantic_nb_bit = 15;    
+localparam CH_NODE = 8'h00;  
+localparam CH_SPI  = 8'h01;  
+localparam CH_GPIO = 8'h02;  
+localparam CH_I2C0 = 8'h03;  
+localparam CH_I2C1 = 8'h04;  
+localparam CH_I2C2 = 8'h05;  
+localparam CH_I2C3 = 8'h06;  
+localparam CH_I2C4 = 8'h07;  
+localparam CH_I2C5 = 8'h08;  
+localparam CH_I2C6 = 8'h09;  
+localparam CH_I2C7 = 8'h0a;  
+localparam CH_I2C8 = 8'h0b;  
+localparam CH_I2C9 = 8'h0c;  
+localparam CH_I2C10 = 8'h0d; 
+localparam CH_I2C11 = 8'h0e; 
+localparam CH_I2C12 = 8'h0f; 
+localparam CH_I2C13 = 8'h10; 
+localparam CH_I2C14 = 8'h11; 
+localparam CH_I2C15 = 8'h12; 
+localparam CH_JTAG  = 8'h13; 
+localparam CH_ADC   = 8'h14; 
+localparam CH_DAC   = 8'h15; 
+
+//--------------Err flags----------
+localparam Err_bit  = 0;   
+localparam Inv_CH   = 1;
+localparam Inv_Cmd  = 2;
+localparam Inv_TR   = 3;  
+localparam Inv_LEN  = 4;    
+localparam CH_dis   = 5;  
+localparam CH_Busy  = 6;
+localparam Num_Max_CH = 8'h15;  
+
+//--------------Node Ctrl----------
+localparam NC_Write_CRA = 8'h00;    
+localparam NC_Read_CRA  = 8'h01;    
+localparam NC_Write_CRB = 8'h02;
+localparam NC_Read_CRB  = 8'h03;
+localparam NC_Write_CRC = 8'h04;
+localparam NC_Read_CRC  = 8'h05;
+localparam NC_Write_CRD = 8'h06;
+localparam NC_Read_CRD  = 8'h07;
+localparam NC_Write_CRE = 8'h08;    
+localparam NC_Read_CRE  = 8'h09;
+
+//-----------------SPI--------------
+localparam SPI_wrt_TX0   = 8'h00;   
+localparam SPI_rea_RX0   = 8'h01;   
+localparam SPI_wrt_TX1   = 8'h10;   
+localparam SPI_rea_RX1   = 8'h11;   
+localparam SPI_wrt_TX2   = 8'h20;   
+localparam SPI_rea_RX2   = 8'h21;   
+localparam SPI_wrt_TX3   = 8'h30;   
+localparam SPI_rea_RX3   = 8'h31;   
+localparam SPI_wrt_ctrl  = 8'h40;   
+localparam SPI_rea_ctrl  = 8'h41;   
+localparam SPI_wrt_DIV   = 8'h50;   
+localparam SPI_rea_DIV   = 8'h51;   
+localparam SPI_wrt_SS    = 8'h60;   
+localparam SPI_rea_SS    = 8'h61;   
+localparam SPI_go        = 8'h72;   
+
+//--------------JTAG----------------
+localparam JTG_w_TDO_tx0   = 8'h00;
+localparam JTG_r_TDI_rx0   = 8'h01;
+localparam JTG_w_TDO_tx1   = 8'h10;
+localparam JTG_r_TDI_rx1   = 8'h11;
+localparam JTG_w_TDO_tx2   = 8'h20;
+localparam JTG_r_TDI_rx2   = 8'h21;
+localparam JTG_w_TDO_tx3   = 8'h30;
+localparam JTG_r_TDI_rx3   = 8'h31;
+localparam JTG_w_TMS_tx0   = 8'h40;
+localparam JTG_r_TMS_tx0   = 8'h41;
+localparam JTG_w_TMS_tx1   = 8'h50;
+localparam JTG_r_TMS_tx1   = 8'h51;
+localparam JTG_w_TMS_tx2   = 8'h60;
+localparam JTG_r_TMS_tx2   = 8'h61;
+localparam JTG_w_TMS_tx3   = 8'h70;
+localparam JTG_r_TMS_tx3   = 8'h71;
+localparam JTG_w_ctrl      = 8'h80;
+localparam JTG_r_crtl      = 8'h81;
+localparam JTG_w_div       = 8'h90;
+localparam JTG_r_div       = 8'h91;
+localparam JTG_go_auto     = 8'ha2;
+localparam JTG_go_manual   = 8'hb0;
+localparam JTAG_RES        = 8'hc0;
+localparam JTAG_status     = 8'hd1;
+localparam SEU_read        = 8'hf1;
+localparam SEU_clear       = 8'hf0;
+
+
+//--------------------------
+
+
+
+//------------I2C------------------
+localparam I2C_WRITE_CRA   = 8'h30;   
+localparam I2C_READ_CRA    = 8'h31;   
+localparam I2C_READ_SRA    = 8'h11;
+localparam I2C_WRITE_MSK   = 8'h20;
+localparam I2C_READ_MSK    = 8'h21;   
+localparam I2C_1BYTE_WRITE = 8'h82;   
+localparam I2C_1BYTE_READ  = 8'h86;
+localparam I2C_1BYTE_WRITE_EXT = 8'h8A;   
+localparam I2C_1byte_READ_EXT  = 8'h8E;   
+localparam I2C_1byte_rmw_OR    = 8'hC6;   
+localparam I2C_1byte_rmw_XOR   = 8'hCA;
+localparam I2C_W_multi_4byte0  = 8'h40;   
+localparam I2C_W_multi_4byte1  = 8'h50;   
+localparam I2C_W_multi_4byte2  = 8'h60;   
+localparam I2C_W_multi_4byte3  = 8'h70;   
+localparam I2C_R_multi_4byte0  = 8'h41;   
+localparam I2C_R_multi_4byte1  = 8'h51;   
+localparam I2C_R_multi_4byte2  = 8'h61;   
+localparam I2C_R_multi_4byte3  = 8'h71;  
+localparam I2C_write_multi     = 8'hDA;   
+localparam I2C_read_multi      = 8'hDE;   
+localparam I2C_write_multi_ext = 8'hE2;   
+localparam I2C_read_multi_ext  = 8'hE6;   
+
+
+//-------------GPIO---------------------
+localparam GPIO_R_DAT_IN        = 8'h01;     
+localparam GPIO_W_DAT_OUT       = 8'h10;     
+localparam GPIO_R_DAT_OUT       = 8'h11;     
+localparam GPIO_W_OE            = 8'h20;     
+localparam GPIO_R_WE            = 8'h21;     
+localparam GPIO_W_INTE          = 8'h30;     
+localparam GPIO_R_INTE          = 8'h31;     
+localparam GPIO_W_PTRIG         = 8'h40;     
+localparam GPIO_R_PTRIG         = 8'h41;     
+localparam GPIO_W_AUX           = 8'h50;     
+localparam GPIO_R_AUX           = 8'h51;     
+localparam GPIO_W_CTRL          = 8'h60;     
+localparam GPIO_R_CTRL          = 8'h61;     
+localparam GPIO_W_INTS          = 8'h70;     
+localparam GPIO_R_INTS          = 8'h71;     
+localparam GPIO_W_ECLK          = 8'h80;
+localparam GPIO_R_ECLK          = 8'h81;
+localparam GPIO_W_NEC           = 8'h90;
+localparam GPIO_R_NEC           = 8'h91;
+
+//--------------DAC--------------------
+localparam DAC_W_CTRL          = 8'h00;
+localparam DAC_R_CTRL          = 8'h01;
+localparam DAC_W_CH1           = 8'h10;
+localparam DAC_R_CH1           = 8'h11;
+localparam DAC_W_CH2           = 8'h20;
+localparam DAC_R_CH2           = 8'h21;
+localparam DAC_W_CH3           = 8'h30;
+localparam DAC_R_CH3           = 8'h31;
+localparam DAC_W_CH4           = 8'h40;
+localparam DAC_R_CH4           = 8'h41;
+
+//--------------ADC-------------------
+localparam ADC_GO              = 8'h02; 
+localparam ADC_W_MUX           = 8'h50;
+localparam ADC_R_MUX           = 8'h51;
+localparam ADC_W_GAIN          = 8'h10;
+localparam ADC_R_GAIN	       = 8'h11;
+localparam ADC_R_ID            = 8'hd1;
+localparam ADC_W_CURR          = 8'h60;
+localparam ADC_R_CURR          = 8'h61;
+localparam ADC_R_DATA          = 8'h21;
+localparam ADC_R_CTRL          = 8'h71;
+localparam ADC_R_CWD           = 8'h31;
+localparam ADC_R_OFFSET        = 8'h41;
+localparam FUSE_W_ID           = 8'hf0;
+localparam FUSE_R_ID           = 8'hf1;
+localparam FUSE_W_GAIN         = 8'he0;
+localparam FUSE_R_GAIN         = 8'he1;
+
diff --git a/vldb/code/Testbench/SCA-model/cadence.v b/vldb/code/Testbench/SCA-model/cadence.v
new file mode 100644
index 0000000..ded4b0d
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/cadence.v
@@ -0,0 +1,169 @@
+//-----------------------------------------------------
+// Design Name : DFFR_E
+// File Name   : cadence.v
+// Function    : D flip-flop async reset
+// Coder       : J. Mendez
+//-----------------------------------------------------
+
+module DFFR_E (
+	RN  , // Reset input
+	CLK , // Clock Input
+	D   , // Data Input
+	Q   , // Q output
+	QBAR  // QBAR output
+);
+
+	//-----------Input Ports---------------
+	input D, CLK, RN ; 
+
+	//-----------Output Ports---------------
+	output Q, QBAR;
+
+	//------------Internal Variables--------
+	reg q, qbar;
+
+	//-------------Code Starts Here---------
+	always @ ( posedge CLK or negedge RN)
+		if (~RN) begin
+		  q <= 1'b0;
+		  qbar <= 1'b1;
+		end  else begin
+		  q <= D;
+		  qbar <= ~D;
+		end
+		
+	assign Q = q;
+	assign QBAR = qbar;
+	
+endmodule //End Of Module dff_sync_reset
+
+//-----------------------------------------------------
+// Design Name : DELAY6_C
+// File Name   : cadence.v
+// Function    : Delay
+// Coder       : J. Mendez
+//-----------------------------------------------------
+
+`timescale 1ns / 1ps
+
+module DELAY6_C(
+    input A,
+    output Z
+    );
+	assign #0.5 Z = A;
+ endmodule
+
+//-----------------------------------------------------
+// Design Name : INVERT_A
+// File Name   : cadence.v
+// Function    : Inverter
+// Coder       : J. Mendez
+//-----------------------------------------------------
+module INVERT_A (
+    input A,
+    output Z
+);
+	assign Z = ~A;	
+endmodule
+
+//-----------------------------------------------------
+// Design Name : OR3_B
+// File Name   : cadence.v
+// Function    : Oring
+// Coder       : J. Mendez
+//-----------------------------------------------------
+module OR3_B (
+    input A,
+    input B,
+    input C,
+    output Z
+);
+	assign Z = A | B | C;	
+endmodule
+
+//-----------------------------------------------------
+// Design Name : BUFFER_F
+// File Name   : cadence.v
+// Function    : Buffer
+// Coder       : J. Mendez
+//-----------------------------------------------------
+module BUFFER_F (
+    input A,
+    output Z
+);
+	assign Z = A;	
+endmodule
+
+//-----------------------------------------------------
+// Design Name : BUFFER_C
+// File Name   : cadence.v
+// Function    : Buffer
+// Coder       : J. Mendez
+//-----------------------------------------------------
+module BUFFER_C (
+    input A,
+    output Z
+);
+	assign Z = A;	
+endmodule
+
+//-----------------------------------------------------
+// Design Name : AND2_B
+// File Name   : cadence.v
+// Function    : Oring
+// Coder       : J. Mendez
+//-----------------------------------------------------
+module AND2_B (
+    input A,
+    input B,
+    output Z
+);
+	assign Z = A & B;	
+endmodule
+
+//-----------------------------------------------------
+// Design Name : ADDF_F
+// File Name   : cadence.v
+// Function    : Adder
+// Coder       : J. Mendez
+//-----------------------------------------------------
+module ADDF_F (
+    input A,
+    input B,
+    input CIN,
+    output COUT,
+	output SUM
+);
+	assign SUM = A ^ B ^ CIN;	
+	assign COUT = ((A ^ B) & CIN) | (A & B);	
+endmodule
+
+//-----------------------------------------------------
+// Design Name : OR4_B
+// File Name   : cadence.v
+// Function    : Oring
+// Coder       : J. Mendez
+//-----------------------------------------------------
+module OR4_B (
+    input A,
+    input B,
+    input C,
+    input D,
+    output Z
+);
+	assign Z = A | B | C | D;	
+endmodule
+
+//-----------------------------------------------------
+// Design Name : OR2_B
+// File Name   : cadence.v
+// Function    : Oring
+// Coder       : J. Mendez
+//-----------------------------------------------------
+module OR2_B (
+    input A,
+    input B,
+    output Z
+);
+	assign Z = A | B;	
+endmodule
\ No newline at end of file
diff --git a/vldb/code/Testbench/SCA-model/elink_super.v b/vldb/code/Testbench/SCA-model/elink_super.v
new file mode 100644
index 0000000..9dd507a
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/elink_super.v
@@ -0,0 +1,4029 @@
+
+
+
+////////////////////////////////////////////////////////////////////
+//                                                                //
+//                      E-LINK - triplicated                      //
+//                      by Sandro Bonacini                        //
+//                                                                //
+////////////////////////////////////////////////////////////////////
+`include "global_defines.v"
+`timescale 1ns/1ps
+
+module elink_tri 
+#(
+	parameter MASTER = 0,
+	 HEADER_FIELD = 1,
+	 ADDR_WIDTH = 5,
+	 MAX_PACKET_LENGTH = 16, 
+	 THRESHOLD = 2**ADDR_WIDTH -MAX_PACKET_LENGTH-1
+)
+ (
+input [15:0]  tx_dat_1,
+input [15:0]  tx_dat_2,
+input [15:0]  tx_dat_3,
+output [15:0]  rx_dat_1,
+output [15:0]  rx_dat_2,
+output [15:0]  rx_dat_3,
+input  rx_sd_1, rx_sd_aux_1, link_clk_1, link_clk_aux_1, rx_dav_1, 
+input  rx_sd_2, rx_sd_aux_2, link_clk_2, link_clk_aux_2, rx_dav_2, 
+input  rx_sd_3, rx_sd_aux_3, link_clk_3, link_clk_aux_3, rx_dav_3, 
+output  tx_sd_1, tx_sd_aux_1, rx_ena_1, rx_eop_1, tx_dav_1, rx_sop_1, rx_err_1,
+output  tx_sd_2, tx_sd_aux_2, rx_ena_2, rx_eop_2, tx_dav_2, rx_sop_2, rx_err_2,
+output  tx_sd_3, tx_sd_aux_3, rx_ena_3, rx_eop_3, tx_dav_3, rx_sop_3, rx_err_3,
+input  resetb_1, tx_ena_1,
+input  resetb_2, tx_ena_2,
+input  resetb_3, tx_ena_3,
+output  user_clk_1,
+output  user_clk_2,
+output  user_clk_3,
+input [7:0]  tx_adr_1,
+input [7:0]  tx_adr_2,
+input [7:0]  tx_adr_3,
+output [7:0]  rx_adr_1,
+output [7:0]  rx_adr_2,
+output [7:0]  rx_adr_3,
+input  tx_cmd_reset_1, tx_cmd_test_1, tx_cmd_sabm_1, disable_aux_1,
+input  tx_cmd_reset_2, tx_cmd_test_2, tx_cmd_sabm_2, disable_aux_2,
+input  tx_cmd_reset_3, tx_cmd_test_3, tx_cmd_sabm_3, disable_aux_3,
+output  rx_cmd_reset_1, rx_cmd_test_1, rx_cmd_ua_1,
+output  rx_cmd_reset_2, rx_cmd_test_2, rx_cmd_ua_2,
+output  rx_cmd_reset_3, rx_cmd_test_3, rx_cmd_ua_3,
+input [3:0]  tx_cset_1,
+input [3:0]  tx_cset_2,
+input [3:0]  tx_cset_3,
+output [2:0]  tx_ns_1, rx_nr_1,rx_ns_1,
+output [2:0]  tx_ns_2, rx_nr_2,rx_ns_2,
+output [2:0]  tx_ns_3, rx_nr_3,rx_ns_3,
+output [6:0]  rx_cmd_srej_1,
+output [6:0]  rx_cmd_srej_2,
+output [6:0]  rx_cmd_srej_3,
+output  cmd_busy_1,
+output  cmd_busy_2,
+output  cmd_busy_3,
+output  active_aux_1,
+output  active_aux_2,
+output  active_aux_3
+);
+wire [1:0]  rx_sdr_pri_1, rx_sdr_aux_1, tx_sdr_1;
+wire [1:0]  rx_sdr_pri_2, rx_sdr_aux_2, tx_sdr_2;
+wire [1:0]  rx_sdr_pri_3, rx_sdr_aux_3, tx_sdr_3;
+wire [2:0]  rx_vr_1;
+wire [2:0]  rx_vr_2;
+wire [2:0]  rx_vr_3;
+wire [6:0]  tx_cmd_srej_1;
+wire [6:0]  tx_cmd_srej_2;
+wire [6:0]  tx_cmd_srej_3;
+wire [7:0]  rx_dat_pri_1,rx_dat_aux_1,tx_dat__1;
+wire [7:0]  rx_dat_pri_2,rx_dat_aux_2,tx_dat__2;
+wire [7:0]  rx_dat_pri_3,rx_dat_aux_3,tx_dat__3;
+
+HDLC_tri #(.MASTER(MASTER),.HEADER_FIELD(HEADER_FIELD), .ADDR_WIDTH(ADDR_WIDTH),.MAX_PACKET_LENGTH(MAX_PACKET_LENGTH)) HDLC (
+		.user_clk_pri_1(user_clk_pri_1), 
+		.user_clk_aux_1(user_clk_aux_1),
+		.user_clk_1(user_clk_1),
+		.rx_dat_1(rx_dat_1),
+		.rx_sdr_1(rx_sdr_pri_1),
+		.rx_sdr_aux_1(rx_sdr_aux_1),
+		.rx_ena_1(rx_ena_1),
+		.rx_dav_1(rx_dav_1),
+		.rx_eop_1(rx_eop_1),
+		.rx_sop_1(rx_sop_1),
+		.rx_adr_1(rx_adr_1),
+		.rx_err_1(rx_err_1),
+		.rx_nr_1(rx_nr_1),
+		.rx_ns_1(rx_ns_1),
+		.rx_cmd_ua_1(rx_cmd_ua_1),
+		.rx_cmd_srej_1(rx_cmd_srej_1),
+		.resetb_1(resetb_1),
+		.rx_cmd_reset_1(rx_cmd_reset_1),
+		.rx_cmd_test_1(rx_cmd_test_1),
+		.tx_dat_1(tx_dat_1),
+		.tx_sdr_1(tx_sdr_1),
+		.tx_ena_1(tx_ena_1),
+		.tx_dav_1(tx_dav_1),
+		.tx_adr_1(tx_adr_1),
+		.tx_ns_1(tx_ns_1),
+		.cmd_busy_1(cmd_busy_1),
+		.tx_cmd_sabm_1(tx_cmd_sabm_1),
+		.tx_cmd_reset_1(tx_cmd_reset_1),
+		.tx_cmd_test_1(tx_cmd_test_1),
+		.active_aux_1(active_aux_1),
+		.disable_aux_1(disable_aux_1),
+		.user_clk_pri_2(user_clk_pri_2), 
+		.user_clk_aux_2(user_clk_aux_2),
+		.user_clk_2(user_clk_2),
+		.rx_dat_2(rx_dat_2),
+		.rx_sdr_2(rx_sdr_pri_2),
+		.rx_sdr_aux_2(rx_sdr_aux_2),
+		.rx_ena_2(rx_ena_2),
+		.rx_dav_2(rx_dav_2),
+		.rx_eop_2(rx_eop_2),
+		.rx_sop_2(rx_sop_2),
+		.rx_adr_2(rx_adr_2),
+		.rx_err_2(rx_err_2),
+		.rx_nr_2(rx_nr_2),
+		.rx_ns_2(rx_ns_2),
+		.rx_cmd_ua_2(rx_cmd_ua_2),
+		.rx_cmd_srej_2(rx_cmd_srej_2),
+		.resetb_2(resetb_2),
+		.rx_cmd_reset_2(rx_cmd_reset_2),
+		.rx_cmd_test_2(rx_cmd_test_2),
+		.tx_dat_2(tx_dat_2),
+		.tx_sdr_2(tx_sdr_2),
+		.tx_ena_2(tx_ena_2),
+		.tx_dav_2(tx_dav_2),
+		.tx_adr_2(tx_adr_2),
+		.tx_ns_2(tx_ns_2),
+		.cmd_busy_2(cmd_busy_2),
+		.tx_cmd_sabm_2(tx_cmd_sabm_2),
+		.tx_cmd_reset_2(tx_cmd_reset_2),
+		.tx_cmd_test_2(tx_cmd_test_2),
+		.active_aux_2(active_aux_2),
+		.disable_aux_2(disable_aux_2),
+		.user_clk_pri_3(user_clk_pri_3), 
+		.user_clk_aux_3(user_clk_aux_3),
+		.user_clk_3(user_clk_3),
+		.rx_dat_3(rx_dat_3),
+		.rx_sdr_3(rx_sdr_pri_3),
+		.rx_sdr_aux_3(rx_sdr_aux_3),
+		.rx_ena_3(rx_ena_3),
+		.rx_dav_3(rx_dav_3),
+		.rx_eop_3(rx_eop_3),
+		.rx_sop_3(rx_sop_3),
+		.rx_adr_3(rx_adr_3),
+		.rx_err_3(rx_err_3),
+		.rx_nr_3(rx_nr_3),
+		.rx_ns_3(rx_ns_3),
+		.rx_cmd_ua_3(rx_cmd_ua_3),
+		.rx_cmd_srej_3(rx_cmd_srej_3),
+		.resetb_3(resetb_3),
+		.rx_cmd_reset_3(rx_cmd_reset_3),
+		.rx_cmd_test_3(rx_cmd_test_3),
+		.tx_dat_3(tx_dat_3),
+		.tx_sdr_3(tx_sdr_3),
+		.tx_ena_3(tx_ena_3),
+		.tx_dav_3(tx_dav_3),
+		.tx_adr_3(tx_adr_3),
+		.tx_ns_3(tx_ns_3),
+		.cmd_busy_3(cmd_busy_3),
+		.tx_cmd_sabm_3(tx_cmd_sabm_3),
+		.tx_cmd_reset_3(tx_cmd_reset_3),
+		.tx_cmd_test_3(tx_cmd_test_3),
+		.active_aux_3(active_aux_3),
+		.disable_aux_3(disable_aux_3)
+	);
+
+
+serdes_tri serdes_pri (
+		.rx_sd_1(rx_sd_1),
+		.tx_sd_1(tx_sd_1),
+		.rx_clk_1(link_clk_1),
+		.rx_dat_1(rx_dat_pri_1),
+		.tx_dat_1(tx_dat__1),
+		.clk40_1(user_clk_pri_1),
+		.clkdiv_skip_1(gnd_1),
+		.resetb_1(vdd_1),
+		.rx_off_1(gnd_1),
+		.tx_off_1(tx_off_1),
+		.rx_sd_2(rx_sd_2),
+		.tx_sd_2(tx_sd_2),
+		.rx_clk_2(link_clk_2),
+		.rx_dat_2(rx_dat_pri_2),
+		.tx_dat_2(tx_dat__2),
+		.clk40_2(user_clk_pri_2),
+		.clkdiv_skip_2(gnd_2),
+		.resetb_2(vdd_2),
+		.rx_off_2(gnd_2),
+		.tx_off_2(tx_off_2),
+		.rx_sd_3(rx_sd_3),
+		.tx_sd_3(tx_sd_3),
+		.rx_clk_3(link_clk_3),
+		.rx_dat_3(rx_dat_pri_3),
+		.tx_dat_3(tx_dat__3),
+		.clk40_3(user_clk_pri_3),
+		.clkdiv_skip_3(gnd_3),
+		.resetb_3(vdd_3),
+		.rx_off_3(gnd_3),
+		.tx_off_3(tx_off_3)
+	);
+
+
+serdes_tri serdes_aux (
+		.rx_sd_1(rx_sd_aux_1),
+		.tx_sd_1(tx_sd_aux_1),
+		.rx_clk_1(link_clk_aux_1),
+		.rx_dat_1(rx_dat_aux_1),
+		.tx_dat_1(tx_dat__1),
+		.clk40_1(user_clk_aux_1),
+		.clkdiv_skip_1(gnd_1),
+		.resetb_1(vdd_1),
+		.rx_off_1(gnd_1),
+		.tx_off_1(tx_off_1),
+		.rx_sd_2(rx_sd_aux_2),
+		.tx_sd_2(tx_sd_aux_2),
+		.rx_clk_2(link_clk_aux_2),
+		.rx_dat_2(rx_dat_aux_2),
+		.tx_dat_2(tx_dat__2),
+		.clk40_2(user_clk_aux_2),
+		.clkdiv_skip_2(gnd_2),
+		.resetb_2(vdd_2),
+		.rx_off_2(gnd_2),
+		.tx_off_2(tx_off_2),
+		.rx_sd_3(rx_sd_aux_3),
+		.tx_sd_3(tx_sd_aux_3),
+		.rx_clk_3(link_clk_aux_3),
+		.rx_dat_3(rx_dat_aux_3),
+		.tx_dat_3(tx_dat__3),
+		.clk40_3(user_clk_aux_3),
+		.clkdiv_skip_3(gnd_3),
+		.resetb_3(vdd_3),
+		.rx_off_3(gnd_3),
+		.tx_off_3(tx_off_3)
+	);
+
+
+assign link_clkb_1= ~link_clk_1;
+assign link_clkb_2= ~link_clk_2;
+assign link_clkb_3= ~link_clk_3;
+
+assign rx_sdr_pri_1 = rx_dat_pri_1[1:0];
+assign rx_sdr_pri_2 = rx_dat_pri_2[1:0];
+assign rx_sdr_pri_3 = rx_dat_pri_3[1:0];
+
+assign tx_dat__1 = {6'b0,tx_sdr_1};
+assign tx_dat__2 = {6'b0,tx_sdr_2};
+assign tx_dat__3 = {6'b0,tx_sdr_3};
+
+assign tx_off_1 = tx_cset_1==4'b1111;
+assign tx_off_2 = tx_cset_2==4'b1111;
+assign tx_off_3 = tx_cset_3==4'b1111;
+
+assign gnd_1 = 1'b0;
+assign gnd_2 = 1'b0;
+assign gnd_3 = 1'b0;
+
+assign vdd_1=1'b1;
+assign vdd_2=1'b1;
+assign vdd_3=1'b1;
+
+assign link_clk_auxb_1= ~link_clk_aux_1;
+assign link_clk_auxb_2= ~link_clk_aux_2;
+assign link_clk_auxb_3= ~link_clk_aux_3;
+
+assign rx_sdr_aux_1 = rx_dat_aux_1[1:0];
+assign rx_sdr_aux_2 = rx_dat_aux_2[1:0];
+assign rx_sdr_aux_3 = rx_dat_aux_3[1:0];
+endmodule
+
+
+
+
+
+
+
+
+module rx_tri 
+#(
+	 parameter 	HEADER_FIELD = 1,
+	 			ADDR_WIDTH = 8
+)
+ (
+output [15:0]  rx_dat_1,
+output [15:0]  rx_dat_2,
+output [15:0]  rx_dat_3,
+output  rx_ena_1, rx_eop_1, rx_sop_1, rx_err_1,
+output  rx_ena_2, rx_eop_2, rx_sop_2, rx_err_2,
+output  rx_ena_3, rx_eop_3, rx_sop_3, rx_err_3,
+output [7:0]  rx_adr_1,
+output [7:0]  rx_adr_2,
+output [7:0]  rx_adr_3,
+output  rx_cmd_reset_1, rx_cmd_test_1,rx_cmd_ua_1, active_aux_1, tx_cmd_ua_1,
+output  rx_cmd_reset_2, rx_cmd_test_2,rx_cmd_ua_2, active_aux_2, tx_cmd_ua_2,
+output  rx_cmd_reset_3, rx_cmd_test_3,rx_cmd_ua_3, active_aux_3, tx_cmd_ua_3,
+output [6:0]  rx_cmd_srej_1,
+output [6:0]  rx_cmd_srej_2,
+output [6:0]  rx_cmd_srej_3,
+output [6:0]  tx_cmd_srej_1,
+output [6:0]  tx_cmd_srej_2,
+output [6:0]  tx_cmd_srej_3,
+output [2:0]  rx_vr_1, rx_nr_1, rx_ns_1,
+output [2:0]  rx_vr_2, rx_nr_2, rx_ns_2,
+output [2:0]  rx_vr_3, rx_nr_3, rx_ns_3,
+input  clk_pri_1, rx_dav_1, clk_aux_1, clk_active_1,
+input  clk_pri_2, rx_dav_2, clk_aux_2, clk_active_2,
+input  clk_pri_3, rx_dav_3, clk_aux_3, clk_active_3,
+input [1:0]  rx_sdr_pri_1, rx_sdr_aux_1,
+input [1:0]  rx_sdr_pri_2, rx_sdr_aux_2,
+input [1:0]  rx_sdr_pri_3, rx_sdr_aux_3,
+input  resetb_1, disable_aux_1,
+input  resetb_2, disable_aux_2,
+input  resetb_3, disable_aux_3,
+input  cmd_busy_1, tx_cmd_reset_1,
+input  cmd_busy_2, tx_cmd_reset_2,
+input  cmd_busy_3, tx_cmd_reset_3
+);
+wire [7:0]  phy_data_pri_1, phy_data_aux_1;
+wire [7:0]  phy_data_pri_2, phy_data_aux_2;
+wire [7:0]  phy_data_pri_3, phy_data_aux_3;
+wire [16:0]  fifo_data_w_pri_1, fifo_data_w_aux_1;
+wire [16:0]  fifo_data_w_pri_2, fifo_data_w_aux_2;
+wire [16:0]  fifo_data_w_pri_3, fifo_data_w_aux_3;
+wire [16:0]  fifo_data_r_1;
+wire [16:0]  fifo_data_r_2;
+wire [16:0]  fifo_data_r_3;
+wire [ADDR_WIDTH-1:0]  fifo_addr_r_pri_1, fifo_addr_w_pri_1, fifo_addr_w_1;
+wire [ADDR_WIDTH-1:0]  fifo_addr_r_pri_2, fifo_addr_w_pri_2, fifo_addr_w_2;
+wire [ADDR_WIDTH-1:0]  fifo_addr_r_pri_3, fifo_addr_w_pri_3, fifo_addr_w_3;
+wire [ADDR_WIDTH-1:0]  fifo_addr_r_aux_1, fifo_addr_w_aux_1, fifo_addr_r_1;
+wire [ADDR_WIDTH-1:0]  fifo_addr_r_aux_2, fifo_addr_w_aux_2, fifo_addr_r_2;
+wire [ADDR_WIDTH-1:0]  fifo_addr_r_aux_3, fifo_addr_w_aux_3, fifo_addr_r_3;
+wire [16:0]  fifo_data_w_1 = active_aux_1 ? fifo_data_w_aux_1 : fifo_data_w_pri_1;
+wire [16:0]  fifo_data_w_2 = active_aux_2 ? fifo_data_w_aux_2 : fifo_data_w_pri_2;
+wire [16:0]  fifo_data_w_3 = active_aux_3 ? fifo_data_w_aux_3 : fifo_data_w_pri_3;
+wire [6:0]  rx_cmd_srej_pri_1, rx_cmd_srej_aux_1;
+wire [6:0]  rx_cmd_srej_pri_2, rx_cmd_srej_aux_2;
+wire [6:0]  rx_cmd_srej_pri_3, rx_cmd_srej_aux_3;
+wire [6:0]  tx_cmd_srej_pri_1, tx_cmd_srej_aux_1;
+wire [6:0]  tx_cmd_srej_pri_2, tx_cmd_srej_aux_2;
+wire [6:0]  tx_cmd_srej_pri_3, tx_cmd_srej_aux_3;
+wire [2:0]  rx_vr_pri_1, rx_nr_pri_1, rx_ns_pri_1;
+wire [2:0]  rx_vr_pri_2, rx_nr_pri_2, rx_ns_pri_2;
+wire [2:0]  rx_vr_pri_3, rx_nr_pri_3, rx_ns_pri_3;
+wire [2:0]  rx_vr_aux_1, rx_nr_aux_1, rx_ns_aux_1;
+wire [2:0]  rx_vr_aux_2, rx_nr_aux_2, rx_ns_aux_2;
+wire [2:0]  rx_vr_aux_3, rx_nr_aux_3, rx_ns_aux_3;
+wire [15:0]  rx_dat_pri_1, rx_dat_aux_1;
+wire [15:0]  rx_dat_pri_2, rx_dat_aux_2;
+wire [15:0]  rx_dat_pri_3, rx_dat_aux_3;
+wire [7:0]  rx_adr_pri_1, rx_adr_aux_1;
+wire [7:0]  rx_adr_pri_2, rx_adr_aux_2;
+wire [7:0]  rx_adr_pri_3, rx_adr_aux_3;
+wire [23:0]  dec_in_1, enc_out_1;
+wire [23:0]  dec_in_2, enc_out_2;
+wire [23:0]  dec_in_3, enc_out_3;
+wire [15:0]  crc_pri_1, crc_aux_1;
+wire [15:0]  crc_pri_2, crc_aux_2;
+wire [15:0]  crc_pri_3, crc_aux_3;
+wire  rx_cmd_reset_aux_1;
+wire  rx_cmd_reset_aux_2;
+wire  rx_cmd_reset_aux_3;
+wire [24:0]  SRAM_data_r_1, SRAM_data_w_1;
+wire [24:0]  SRAM_data_r_2, SRAM_data_w_2;
+wire [24:0]  SRAM_data_r_3, SRAM_data_w_3;
+
+MAC_rx_tri #(.HEADER_FIELD(HEADER_FIELD), .ADDR_WIDTH(ADDR_WIDTH)) MAC_rx_pri (
+		.clk_1(clk_pri_1),
+		.resetb_1(resetb_1),
+		.rx_dav_1(rx_dav_1),
+		.fifo_data_r_1(fifo_data_r_1),
+		.cmd_busy_1(cmd_busy_1),
+		.rx_dat_1(rx_dat_pri_1),
+		.rx_ena_1(rx_ena_pri_1),
+		.rx_ena_pre_1(rx_ena_pre_pri_1),
+		.rx_eop_1(rx_eop_pri_1),
+		.rx_sop_1(rx_sop_pri_1),
+		.rx_adr_1(rx_adr_pri_1),
+		.rx_err_1(rx_err_pri_1),
+		.rx_vr_1(rx_vr_pri_1),
+		.rx_ns_1(rx_ns_pri_1),
+		.rx_nr_1(rx_nr_pri_1),
+		.rx_cmd_reset_1(),
+		.rx_cmd_test_1(rx_cmd_test_pri_1),
+		.rx_cmd_ua_1(rx_cmd_ua_pri_1),
+		.rx_cmd_sabm_1(rx_cmd_sabm_pri_1),
+		.rx_cmd_srej_1(rx_cmd_srej_pri_1),
+		.tx_cmd_srej_1(tx_cmd_srej_pri_1),
+		.tx_cmd_reset_1(tx_cmd_reset_1),
+		.phy_data_1(phy_data_pri_1),
+		.phy_dvalid_1(phy_dvalid_pri_1),
+		.phy_dstrobe_1(phy_dstrobe_pri_1),
+		.crc_zero_1(crc_zero_pri_1),
+		.fifo_data_w_1(fifo_data_w_pri_1),
+		.fifo_addr_w_1(fifo_addr_w_pri_1),
+		.fifo_addr_r_1(fifo_addr_r_pri_1),
+		.fifo_w_1(fifo_w_pri_1),
+		.active_1(active_pri_1),
+		.disconnect_1(disconnect_pri_dis_1),
+		.tx_cmd_ua_1(tx_cmd_ua_pri_1),
+		.clk_2(clk_pri_2),
+		.resetb_2(resetb_2),
+		.rx_dav_2(rx_dav_2),
+		.fifo_data_r_2(fifo_data_r_2),
+		.cmd_busy_2(cmd_busy_2),
+		.rx_dat_2(rx_dat_pri_2),
+		.rx_ena_2(rx_ena_pri_2),
+		.rx_ena_pre_2(rx_ena_pre_pri_2),
+		.rx_eop_2(rx_eop_pri_2),
+		.rx_sop_2(rx_sop_pri_2),
+		.rx_adr_2(rx_adr_pri_2),
+		.rx_err_2(rx_err_pri_2),
+		.rx_vr_2(rx_vr_pri_2),
+		.rx_ns_2(rx_ns_pri_2),
+		.rx_nr_2(rx_nr_pri_2),
+		.rx_cmd_reset_2(rx_cmd_reset_pri_2),
+		.rx_cmd_test_2(rx_cmd_test_pri_2),
+		.rx_cmd_ua_2(rx_cmd_ua_pri_2),
+		.rx_cmd_sabm_2(rx_cmd_sabm_pri_2),
+		.rx_cmd_srej_2(rx_cmd_srej_pri_2),
+		.tx_cmd_srej_2(tx_cmd_srej_pri_2),
+		.tx_cmd_reset_2(tx_cmd_reset_2),
+		.phy_data_2(phy_data_pri_2),
+		.phy_dvalid_2(phy_dvalid_pri_2),
+		.phy_dstrobe_2(phy_dstrobe_pri_2),
+		.crc_zero_2(crc_zero_pri_2),
+		.fifo_data_w_2(fifo_data_w_pri_2),
+		.fifo_addr_w_2(fifo_addr_w_pri_2),
+		.fifo_addr_r_2(fifo_addr_r_pri_2),
+		.fifo_w_2(fifo_w_pri_2),
+		.active_2(active_pri_2),
+		.disconnect_2(disconnect_pri_dis_2),
+		.tx_cmd_ua_2(tx_cmd_ua_pri_2),
+		.clk_3(clk_pri_3),
+		.resetb_3(resetb_3),
+		.rx_dav_3(rx_dav_3),
+		.fifo_data_r_3(fifo_data_r_3),
+		.cmd_busy_3(cmd_busy_3),
+		.rx_dat_3(rx_dat_pri_3),
+		.rx_ena_3(rx_ena_pri_3),
+		.rx_ena_pre_3(rx_ena_pre_pri_3),
+		.rx_eop_3(rx_eop_pri_3),
+		.rx_sop_3(rx_sop_pri_3),
+		.rx_adr_3(rx_adr_pri_3),
+		.rx_err_3(rx_err_pri_3),
+		.rx_vr_3(rx_vr_pri_3),
+		.rx_ns_3(rx_ns_pri_3),
+		.rx_nr_3(rx_nr_pri_3),
+		.rx_cmd_reset_3(rx_cmd_reset_pri_3),
+		.rx_cmd_test_3(rx_cmd_test_pri_3),
+		.rx_cmd_ua_3(rx_cmd_ua_pri_3),
+		.rx_cmd_sabm_3(rx_cmd_sabm_pri_3),
+		.rx_cmd_srej_3(rx_cmd_srej_pri_3),
+		.tx_cmd_srej_3(tx_cmd_srej_pri_3),
+		.tx_cmd_reset_3(tx_cmd_reset_3),
+		.phy_data_3(phy_data_pri_3),
+		.phy_dvalid_3(phy_dvalid_pri_3),
+		.phy_dstrobe_3(phy_dstrobe_pri_3),
+		.crc_zero_3(crc_zero_pri_3),
+		.fifo_data_w_3(fifo_data_w_pri_3),
+		.fifo_addr_w_3(fifo_addr_w_pri_3),
+		.fifo_addr_r_3(fifo_addr_r_pri_3),
+		.fifo_w_3(fifo_w_pri_3),
+		.active_3(active_pri_3),
+		.disconnect_3(disconnect_pri_dis_3),
+		.tx_cmd_ua_3(tx_cmd_ua_pri_3),
+		.rx_cmd_reset(rx_cmd_reset_pri_1)
+	);
+
+MAC_rx_tri #(.HEADER_FIELD(HEADER_FIELD), .ADDR_WIDTH(ADDR_WIDTH)) MAC_rx_aux (
+		.rx_cmd_reset(rx_cmd_reset_aux_1),
+		.clk_1(clk_aux_dis_1),
+		.resetb_1(resetb_dis_1),
+		.rx_dav_1(rx_dav_1),
+		.fifo_data_r_1(fifo_data_r_1),
+		.cmd_busy_1(cmd_busy_1),
+		.rx_dat_1(rx_dat_aux_1),
+		.rx_ena_1(rx_ena_aux_1),
+		.rx_ena_pre_1(rx_ena_pre_aux_1),
+		.rx_eop_1(rx_eop_aux_1),
+		.rx_sop_1(rx_sop_aux_1),
+		.rx_adr_1(rx_adr_aux_1),
+		.rx_err_1(rx_err_aux_1),
+		.rx_vr_1(rx_vr_aux_1),
+		.rx_ns_1(rx_ns_aux_1),
+		.rx_nr_1(rx_nr_aux_1),
+		.rx_cmd_reset_1(),
+		.rx_cmd_test_1(rx_cmd_test_aux_1),
+		.rx_cmd_ua_1(rx_cmd_ua_aux_1),
+		.rx_cmd_sabm_1(rx_cmd_sabm_aux_1),
+		.rx_cmd_srej_1(rx_cmd_srej_aux_1),
+		.tx_cmd_srej_1(tx_cmd_srej_aux_1),
+		.tx_cmd_reset_1(tx_cmd_reset_1),
+		.phy_data_1(phy_data_aux_1),
+		.phy_dvalid_1(phy_dvalid_aux_1),
+		.phy_dstrobe_1(phy_dstrobe_aux_1),
+		.crc_zero_1(crc_zero_aux_1),
+		.fifo_data_w_1(fifo_data_w_aux_1),
+		.fifo_addr_w_1(fifo_addr_w_aux_1),
+		.fifo_addr_r_1(fifo_addr_r_aux_1),
+		.fifo_w_1(fifo_w_aux_1),
+		.active_1(active_aux_1),
+		.disconnect_1(disconnect_aux_1),
+		.tx_cmd_ua_1(tx_cmd_ua_aux_1),
+		.clk_2(clk_aux_dis_2),
+		.resetb_2(resetb_dis_2),
+		.rx_dav_2(rx_dav_2),
+		.fifo_data_r_2(fifo_data_r_2),
+		.cmd_busy_2(cmd_busy_2),
+		.rx_dat_2(rx_dat_aux_2),
+		.rx_ena_2(rx_ena_aux_2),
+		.rx_ena_pre_2(rx_ena_pre_aux_2),
+		.rx_eop_2(rx_eop_aux_2),
+		.rx_sop_2(rx_sop_aux_2),
+		.rx_adr_2(rx_adr_aux_2),
+		.rx_err_2(rx_err_aux_2),
+		.rx_vr_2(rx_vr_aux_2),
+		.rx_ns_2(rx_ns_aux_2),
+		.rx_nr_2(rx_nr_aux_2),
+		.rx_cmd_reset_2(rx_cmd_reset_aux_2),
+		.rx_cmd_test_2(rx_cmd_test_aux_2),
+		.rx_cmd_ua_2(rx_cmd_ua_aux_2),
+		.rx_cmd_sabm_2(rx_cmd_sabm_aux_2),
+		.rx_cmd_srej_2(rx_cmd_srej_aux_2),
+		.tx_cmd_srej_2(tx_cmd_srej_aux_2),
+		.tx_cmd_reset_2(tx_cmd_reset_2),
+		.phy_data_2(phy_data_aux_2),
+		.phy_dvalid_2(phy_dvalid_aux_2),
+		.phy_dstrobe_2(phy_dstrobe_aux_2),
+		.crc_zero_2(crc_zero_aux_2),
+		.fifo_data_w_2(fifo_data_w_aux_2),
+		.fifo_addr_w_2(fifo_addr_w_aux_2),
+		.fifo_addr_r_2(fifo_addr_r_aux_2),
+		.fifo_w_2(fifo_w_aux_2),
+		.active_2(active_aux_2),
+		.disconnect_2(disconnect_aux_2),
+		.tx_cmd_ua_2(tx_cmd_ua_aux_2),
+		.clk_3(clk_aux_dis_3),
+		.resetb_3(resetb_dis_3),
+		.rx_dav_3(rx_dav_3),
+		.fifo_data_r_3(fifo_data_r_3),
+		.cmd_busy_3(cmd_busy_3),
+		.rx_dat_3(rx_dat_aux_3),
+		.rx_ena_3(rx_ena_aux_3),
+		.rx_ena_pre_3(rx_ena_pre_aux_3),
+		.rx_eop_3(rx_eop_aux_3),
+		.rx_sop_3(rx_sop_aux_3),
+		.rx_adr_3(rx_adr_aux_3),
+		.rx_err_3(rx_err_aux_3),
+		.rx_vr_3(rx_vr_aux_3),
+		.rx_ns_3(rx_ns_aux_3),
+		.rx_nr_3(rx_nr_aux_3),
+		.rx_cmd_reset_3(rx_cmd_reset_aux_3),
+		.rx_cmd_test_3(rx_cmd_test_aux_3),
+		.rx_cmd_ua_3(rx_cmd_ua_aux_3),
+		.rx_cmd_sabm_3(rx_cmd_sabm_aux_3),
+		.rx_cmd_srej_3(rx_cmd_srej_aux_3),
+		.tx_cmd_srej_3(tx_cmd_srej_aux_3),
+		.tx_cmd_reset_3(tx_cmd_reset_3),
+		.phy_data_3(phy_data_aux_3),
+		.phy_dvalid_3(phy_dvalid_aux_3),
+		.phy_dstrobe_3(phy_dstrobe_aux_3),
+		.crc_zero_3(crc_zero_aux_3),
+		.fifo_data_w_3(fifo_data_w_aux_3),
+		.fifo_addr_w_3(fifo_addr_w_aux_3),
+		.fifo_addr_r_3(fifo_addr_r_aux_3),
+		.fifo_w_3(fifo_w_aux_3),
+		.active_3(active_aux_3),
+		.disconnect_3(disconnect_aux_3),
+		.tx_cmd_ua_3(tx_cmd_ua_aux_3)
+	);
+
+
+
+DELAY6_C delay_disconnect_pri_1 (.Z(disconnect_pri_del1_1),.A(disconnect_pri_1)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_pri_2 (.Z(disconnect_pri_del1_2),.A(disconnect_pri_2)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_pri_3 (.Z(disconnect_pri_del1_3),.A(disconnect_pri_3)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+
+
+DELAY6_C delay_disconnect_pri1_1 (.Z(disconnect_pri_del2_1),.A(disconnect_pri_del1_1)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_pri1_2 (.Z(disconnect_pri_del2_2),.A(disconnect_pri_del1_2)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_pri1_3 (.Z(disconnect_pri_del2_3),.A(disconnect_pri_del1_3)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+
+
+DELAY6_C delay_disconnect_pri2_1 (.Z(disconnect_pri_del3_1),.A(disconnect_pri_del2_1)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_pri2_2 (.Z(disconnect_pri_del3_2),.A(disconnect_pri_del2_2)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_pri2_3 (.Z(disconnect_pri_del3_3),.A(disconnect_pri_del2_3)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+
+
+DELAY6_C delay_disconnect_pri3_1 (.Z(disconnect_pri_del4_1),.A(disconnect_pri_del3_1)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_pri3_2 (.Z(disconnect_pri_del4_2),.A(disconnect_pri_del3_2)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_pri3_3 (.Z(disconnect_pri_del4_3),.A(disconnect_pri_del3_3)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+
+
+DELAY6_C delay_disconnect_pri4_1 (.Z(disconnect_pri_del_1),.A(disconnect_pri_del4_1)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_pri4_2 (.Z(disconnect_pri_del_2),.A(disconnect_pri_del4_2)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_pri4_3 (.Z(disconnect_pri_del_3),.A(disconnect_pri_del4_3)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+
+
+DELAY6_C delay_disconnect_aux_1 (.Z(disconnect_aux_del1_1),.A(disconnect_aux_1)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_aux_2 (.Z(disconnect_aux_del1_2),.A(disconnect_aux_2)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_aux_3 (.Z(disconnect_aux_del1_3),.A(disconnect_aux_3)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+
+
+DELAY6_C delay_disconnect_aux1_1 (.Z(disconnect_aux_del2_1),.A(disconnect_aux_del1_1)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_aux1_2 (.Z(disconnect_aux_del2_2),.A(disconnect_aux_del1_2)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_aux1_3 (.Z(disconnect_aux_del2_3),.A(disconnect_aux_del1_3)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+
+
+DELAY6_C delay_disconnect_aux2_1 (.Z(disconnect_aux_del3_1),.A(disconnect_aux_del2_1)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_aux2_2 (.Z(disconnect_aux_del3_2),.A(disconnect_aux_del2_2)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_aux2_3 (.Z(disconnect_aux_del3_3),.A(disconnect_aux_del2_3)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+
+
+DELAY6_C delay_disconnect_aux3_1 (.Z(disconnect_aux_del4_1),.A(disconnect_aux_del3_1)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_aux3_2 (.Z(disconnect_aux_del4_2),.A(disconnect_aux_del3_2)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_aux3_3 (.Z(disconnect_aux_del4_3),.A(disconnect_aux_del3_3)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+
+
+DELAY6_C delay_disconnect_aux4_1 (.Z(disconnect_aux_del_1),.A(disconnect_aux_del4_1)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_aux4_2 (.Z(disconnect_aux_del_2),.A(disconnect_aux_del4_2)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+DELAY6_C delay_disconnect_aux4_3 (.Z(disconnect_aux_del_3),.A(disconnect_aux_del4_3)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+
+
+Hamming16_24 Hamming16_24_1 (
+		.enc_in(fifo_data_w_1[15:0]),
+		.enc_out(enc_out_1),
+		.dec_in(dec_in_1),
+		.dec_out(fifo_data_r_1[15:0])
+	);
+Hamming16_24 Hamming16_24_2 (
+		.enc_in(fifo_data_w_2[15:0]),
+		.enc_out(enc_out_2),
+		.dec_in(dec_in_2),
+		.dec_out(fifo_data_r_2[15:0])
+	);
+Hamming16_24 Hamming16_24_3 (
+		.enc_in(fifo_data_w_3[15:0]),
+		.enc_out(enc_out_3),
+		.dec_in(dec_in_3),
+		.dec_out(fifo_data_r_3[15:0])
+	);
+
+
+SRAM_tri #(.DATA_WIDTH(25),.ADDR_WIDTH(ADDR_WIDTH)) fifo (
+		.data_w_1(SRAM_data_w_1),
+		.data_r_1(SRAM_data_r_1),
+		.addr_w_1(fifo_addr_w_1),
+		.addr_r_1(fifo_addr_r_1),
+		.w_enable_1(fifo_w_1),
+		.clk_w_1(clk_activeb_1),
+		.data_w_2(SRAM_data_w_2),
+		.data_r_2(SRAM_data_r_2),
+		.addr_w_2(fifo_addr_w_2),
+		.addr_r_2(fifo_addr_r_2),
+		.w_enable_2(fifo_w_2),
+		.clk_w_2(clk_activeb_2),
+		.data_w_3(SRAM_data_w_3),
+		.data_r_3(SRAM_data_r_3),
+		.addr_w_3(fifo_addr_w_3),
+		.addr_r_3(fifo_addr_r_3),
+		.w_enable_3(fifo_w_3),
+		.clk_w_3(clk_activeb_3)
+	);
+
+
+crc_tri #(.DATA_WIDTH(8)) crc16_8_pri (
+		.d_1(phy_data_pri_1), 
+		.init_1(phy_dvalid_prib_1),
+		.reset_b_1(resetb_1),
+		.clk_1(clk_pri_1),
+		.d_valid_1(phy_dstrobe_pri_1),
+		.crc_1(crc_pri_1),
+		.d_2(phy_data_pri_2), 
+		.init_2(phy_dvalid_prib_2),
+		.reset_b_2(resetb_2),
+		.clk_2(clk_pri_2),
+		.d_valid_2(phy_dstrobe_pri_2),
+		.crc_2(crc_pri_2),
+		.d_3(phy_data_pri_3), 
+		.init_3(phy_dvalid_prib_3),
+		.reset_b_3(resetb_3),
+		.clk_3(clk_pri_3),
+		.d_valid_3(phy_dstrobe_pri_3),
+		.crc_3(crc_pri_3)
+	);
+
+
+crc_tri #(.DATA_WIDTH(8)) crc16_8_aux (
+		.d_1(phy_data_aux_1), 
+		.init_1(phy_dvalid_auxb_1),
+		.reset_b_1(resetb_dis_1),
+		.clk_1(clk_aux_dis_1),
+		.d_valid_1(phy_dstrobe_aux_1),
+		.crc_1(crc_aux_1),
+		.d_2(phy_data_aux_2), 
+		.init_2(phy_dvalid_auxb_2),
+		.reset_b_2(resetb_dis_2),
+		.clk_2(clk_aux_dis_2),
+		.d_valid_2(phy_dstrobe_aux_2),
+		.crc_2(crc_aux_2),
+		.d_3(phy_data_aux_3), 
+		.init_3(phy_dvalid_auxb_3),
+		.reset_b_3(resetb_dis_3),
+		.clk_3(clk_aux_dis_3),
+		.d_valid_3(phy_dstrobe_aux_3),
+		.crc_3(crc_aux_3)
+	);
+
+
+PHY_HDLC_rx_tri PHY_HDLC_rx_pri (
+		.rx_data_1(phy_data_pri_1),
+		.rx_sdr_1(rx_sdr_pri_1),
+		.rx_clk_1(clk_pri_1),
+		.rx_dvalid_1(phy_dvalid_pri_1),
+		.rx_dstrobe_1(phy_dstrobe_pri_1),
+		.resetb_1(resetb_1),
+		.rx_data_2(phy_data_pri_2),
+		.rx_sdr_2(rx_sdr_pri_2),
+		.rx_clk_2(clk_pri_2),
+		.rx_dvalid_2(phy_dvalid_pri_2),
+		.rx_dstrobe_2(phy_dstrobe_pri_2),
+		.resetb_2(resetb_2),
+		.rx_data_3(phy_data_pri_3),
+		.rx_sdr_3(rx_sdr_pri_3),
+		.rx_clk_3(clk_pri_3),
+		.rx_dvalid_3(phy_dvalid_pri_3),
+		.rx_dstrobe_3(phy_dstrobe_pri_3),
+		.resetb_3(resetb_3)
+	);
+
+
+PHY_HDLC_rx_tri PHY_HDLC_rx_aux (
+		.rx_data_1(phy_data_aux_1),
+		.rx_sdr_1(rx_sdr_aux_1),
+		.rx_clk_1(clk_aux_dis_1),
+		.rx_dvalid_1(phy_dvalid_aux_1),
+		.rx_dstrobe_1(phy_dstrobe_aux_1),
+		.resetb_1(resetb_dis_1),
+		.rx_data_2(phy_data_aux_2),
+		.rx_sdr_2(rx_sdr_aux_2),
+		.rx_clk_2(clk_aux_dis_2),
+		.rx_dvalid_2(phy_dvalid_aux_2),
+		.rx_dstrobe_2(phy_dstrobe_aux_2),
+		.resetb_2(resetb_dis_2),
+		.rx_data_3(phy_data_aux_3),
+		.rx_sdr_3(rx_sdr_aux_3),
+		.rx_clk_3(clk_aux_dis_3),
+		.rx_dvalid_3(phy_dvalid_aux_3),
+		.rx_dstrobe_3(phy_dstrobe_aux_3),
+		.resetb_3(resetb_dis_3)
+	);
+
+
+pri_aux_control_tri pri_aux_control (
+		.resetb_pri_1(resetb_1),
+		.resetb_aux_1(resetb_dis_1),
+		.disconnect_pri_1(disconnect_pri_1),
+		.disconnect_aux_1(disconnect_aux_1),
+		.activate_commands_pri_1(activate_commands_pri_1),
+		.activate_commands_aux_1(activate_commands_aux_1),
+		.active_aux_1(active_aux_int_1),
+		.active_pri_1(active_pri_1),
+		.clk_pri_1(clk_pri_1),
+		.clk_aux_1(clk_aux_dis_1),
+		.disable_aux_1(disable_aux_1),
+		.resetb_pri_2(resetb_2),
+		.resetb_aux_2(resetb_dis_2),
+		.disconnect_pri_2(disconnect_pri_2),
+		.disconnect_aux_2(disconnect_aux_2),
+		.activate_commands_pri_2(activate_commands_pri_2),
+		.activate_commands_aux_2(activate_commands_aux_2),
+		.active_aux_2(active_aux_int_2),
+		.active_pri_2(active_pri_2),
+		.clk_pri_2(clk_pri_2),
+		.clk_aux_2(clk_aux_dis_2),
+		.disable_aux_2(disable_aux_2),
+		.resetb_pri_3(resetb_3),
+		.resetb_aux_3(resetb_dis_3),
+		.disconnect_pri_3(disconnect_pri_3),
+		.disconnect_aux_3(disconnect_aux_3),
+		.activate_commands_pri_3(activate_commands_pri_3),
+		.activate_commands_aux_3(activate_commands_aux_3),
+		.active_aux_3(active_aux_int_3),
+		.active_pri_3(active_pri_3),
+		.clk_pri_3(clk_pri_3),
+		.clk_aux_3(clk_aux_dis_3),
+		.disable_aux_3(disable_aux_3)
+	);
+
+
+monostable ms_rx_cmd_reset_pri_1 (
+		.A(rx_cmd_reset_pri_1),
+		.Z(rx_cmd_reset_pri_monos_1)
+	);
+monostable ms_rx_cmd_reset_pri_2 (
+		.A(rx_cmd_reset_pri_2),
+		.Z(rx_cmd_reset_pri_monos_2)
+	);
+monostable ms_rx_cmd_reset_pri_3 (
+		.A(rx_cmd_reset_pri_3),
+		.Z(rx_cmd_reset_pri_monos_3)
+	);
+
+
+monostable ms_rx_cmd_reset_aux_1 (
+		.A(rx_cmd_reset_aux_1),
+		.Z(rx_cmd_reset_aux_monos_1)
+	);
+monostable ms_rx_cmd_reset_aux_2 (
+		.A(rx_cmd_reset_aux_2),
+		.Z(rx_cmd_reset_aux_monos_2)
+	);
+monostable ms_rx_cmd_reset_aux_3 (
+		.A(rx_cmd_reset_aux_3),
+		.Z(rx_cmd_reset_aux_monos_3)
+	);
+
+
+monostable ms_activate_commands_pri_1 (
+		.A(activate_commands_pri_1),
+		.Z(disconnect_aux_1)
+	);
+monostable ms_activate_commands_pri_2 (
+		.A(activate_commands_pri_2),
+		.Z(disconnect_aux_2)
+	);
+monostable ms_activate_commands_pri_3 (
+		.A(activate_commands_pri_3),
+		.Z(disconnect_aux_3)
+	);
+
+
+monostable ms_activate_commands_aux_1 (
+		.A(activate_commands_aux_1),
+		.Z(disconnect_pri_1)
+	);
+monostable ms_activate_commands_aux_2 (
+		.A(activate_commands_aux_2),
+		.Z(disconnect_pri_2)
+	);
+monostable ms_activate_commands_aux_3 (
+		.A(activate_commands_aux_3),
+		.Z(disconnect_pri_3)
+	);
+
+
+assign crc_zero_aux_1 = crc_aux_1==16'b0;
+assign crc_zero_aux_2 = crc_aux_2==16'b0;
+assign crc_zero_aux_3 = crc_aux_3==16'b0;
+
+assign	SRAM_data_w_1={fifo_data_w_1[16], enc_out_1};
+assign	SRAM_data_w_2={fifo_data_w_2[16], enc_out_2};
+assign	SRAM_data_w_3={fifo_data_w_3[16], enc_out_3};
+
+assign	fifo_data_r_1[16]=SRAM_data_r_1[24];
+assign	fifo_data_r_2[16]=SRAM_data_r_2[24];
+assign	fifo_data_r_3[16]=SRAM_data_r_3[24];
+
+assign  dec_in_1=SRAM_data_r_1[23:0];
+assign  dec_in_2=SRAM_data_r_2[23:0];
+assign  dec_in_3=SRAM_data_r_3[23:0];
+
+assign clk_activeb_1=~clk_active_1;
+assign clk_activeb_2=~clk_active_2;
+assign clk_activeb_3=~clk_active_3;
+
+assign phy_dvalid_prib_1=~phy_dvalid_pri_1;
+assign phy_dvalid_prib_2=~phy_dvalid_pri_2;
+assign phy_dvalid_prib_3=~phy_dvalid_pri_3;
+
+assign phy_dvalid_auxb_1=~phy_dvalid_aux_1;
+assign phy_dvalid_auxb_2=~phy_dvalid_aux_2;
+assign phy_dvalid_auxb_3=~phy_dvalid_aux_3;
+
+assign activate_commands_pri_1 = rx_cmd_reset_pri_1 || rx_cmd_sabm_pri_1 || tx_cmd_reset_1 || disable_aux_1;
+assign activate_commands_pri_2 = rx_cmd_reset_pri_2 || rx_cmd_sabm_pri_2 || tx_cmd_reset_2 || disable_aux_2;
+assign activate_commands_pri_3 = rx_cmd_reset_pri_3 || rx_cmd_sabm_pri_3 || tx_cmd_reset_3 || disable_aux_3;
+
+assign activate_commands_aux_1 = (rx_cmd_reset_aux_1 || rx_cmd_sabm_aux_1 || tx_cmd_reset_1) && (~disable_aux_1);
+assign activate_commands_aux_2 = (rx_cmd_reset_aux_2 || rx_cmd_sabm_aux_2 || tx_cmd_reset_2) && (~disable_aux_2);
+assign activate_commands_aux_3 = (rx_cmd_reset_aux_3 || rx_cmd_sabm_aux_3 || tx_cmd_reset_3) && (~disable_aux_3);
+
+assign active_aux_1 = active_aux_int_1 & (~disable_aux_1);
+assign active_aux_2 = active_aux_int_2 & (~disable_aux_2);
+assign active_aux_3 = active_aux_int_3 & (~disable_aux_3);
+
+assign clk_aux_dis_1 = clk_aux_1 & (~disable_aux_1);
+assign clk_aux_dis_2 = clk_aux_2 & (~disable_aux_2);
+assign clk_aux_dis_3 = clk_aux_3 & (~disable_aux_3);
+
+assign resetb_dis_1 = resetb_1 & (~disable_aux_1);
+assign resetb_dis_2 = resetb_2 & (~disable_aux_2);
+assign resetb_dis_3 = resetb_3 & (~disable_aux_3);
+
+assign fifo_addr_r_1 = active_aux_1 ? fifo_addr_r_aux_1 : fifo_addr_r_pri_1;
+assign fifo_addr_r_2 = active_aux_2 ? fifo_addr_r_aux_2 : fifo_addr_r_pri_2;
+assign fifo_addr_r_3 = active_aux_3 ? fifo_addr_r_aux_3 : fifo_addr_r_pri_3;
+
+assign fifo_addr_w_1 = active_aux_1 ? fifo_addr_w_aux_1 : fifo_addr_w_pri_1;
+assign fifo_addr_w_2 = active_aux_2 ? fifo_addr_w_aux_2 : fifo_addr_w_pri_2;
+assign fifo_addr_w_3 = active_aux_3 ? fifo_addr_w_aux_3 : fifo_addr_w_pri_3;
+
+assign fifo_w_1 = active_aux_1 ? fifo_w_aux_1 : fifo_w_pri_1;
+assign fifo_w_2 = active_aux_2 ? fifo_w_aux_2 : fifo_w_pri_2;
+assign fifo_w_3 = active_aux_3 ? fifo_w_aux_3 : fifo_w_pri_3;
+
+assign rx_dat_1 = active_aux_1 ? rx_dat_aux_1 : rx_dat_pri_1;
+assign rx_dat_2 = active_aux_2 ? rx_dat_aux_2 : rx_dat_pri_2;
+assign rx_dat_3 = active_aux_3 ? rx_dat_aux_3 : rx_dat_pri_3;
+
+assign rx_ena_1 = active_aux_1 ? rx_ena_aux_1 : rx_ena_pri_1;
+assign rx_ena_2 = active_aux_2 ? rx_ena_aux_2 : rx_ena_pri_2;
+assign rx_ena_3 = active_aux_3 ? rx_ena_aux_3 : rx_ena_pri_3;
+
+assign rx_eop_1 = active_aux_1 ? rx_eop_aux_1 : rx_eop_pri_1;
+assign rx_eop_2 = active_aux_2 ? rx_eop_aux_2 : rx_eop_pri_2;
+assign rx_eop_3 = active_aux_3 ? rx_eop_aux_3 : rx_eop_pri_3;
+
+assign rx_sop_1 = active_aux_1 ? rx_sop_aux_1 : rx_sop_pri_1;
+assign rx_sop_2 = active_aux_2 ? rx_sop_aux_2 : rx_sop_pri_2;
+assign rx_sop_3 = active_aux_3 ? rx_sop_aux_3 : rx_sop_pri_3;
+
+assign rx_err_1 = active_aux_1 ? rx_err_aux_1 : rx_err_pri_1;
+assign rx_err_2 = active_aux_2 ? rx_err_aux_2 : rx_err_pri_2;
+assign rx_err_3 = active_aux_3 ? rx_err_aux_3 : rx_err_pri_3;
+
+assign rx_adr_1 = active_aux_1 ? rx_adr_aux_1 : rx_adr_pri_1;
+assign rx_adr_2 = active_aux_2 ? rx_adr_aux_2 : rx_adr_pri_2;
+assign rx_adr_3 = active_aux_3 ? rx_adr_aux_3 : rx_adr_pri_3;
+
+assign rx_cmd_reset_1 = rx_cmd_reset_aux_monos_1 | rx_cmd_reset_pri_monos_1;
+assign rx_cmd_reset_2 = rx_cmd_reset_aux_monos_2 | rx_cmd_reset_pri_monos_2;
+assign rx_cmd_reset_3 = rx_cmd_reset_aux_monos_3 | rx_cmd_reset_pri_monos_3;
+
+assign rx_cmd_test_1 = active_aux_1 ? rx_cmd_test_aux_1 : rx_cmd_test_pri_1;
+assign rx_cmd_test_2 = active_aux_2 ? rx_cmd_test_aux_2 : rx_cmd_test_pri_2;
+assign rx_cmd_test_3 = active_aux_3 ? rx_cmd_test_aux_3 : rx_cmd_test_pri_3;
+
+assign rx_cmd_ua_1 = active_aux_1 ? rx_cmd_ua_aux_1 : rx_cmd_ua_pri_1;
+assign rx_cmd_ua_2 = active_aux_2 ? rx_cmd_ua_aux_2 : rx_cmd_ua_pri_2;
+assign rx_cmd_ua_3 = active_aux_3 ? rx_cmd_ua_aux_3 : rx_cmd_ua_pri_3;
+
+assign tx_cmd_ua_1 = (active_aux_1 ? tx_cmd_ua_aux_1 : tx_cmd_ua_pri_1);
+assign tx_cmd_ua_2 = (active_aux_2 ? tx_cmd_ua_aux_2 : tx_cmd_ua_pri_2);
+assign tx_cmd_ua_3 = (active_aux_3 ? tx_cmd_ua_aux_3 : tx_cmd_ua_pri_3);
+
+assign rx_cmd_srej_1 = active_aux_1 ? rx_cmd_srej_aux_1 : rx_cmd_srej_pri_1;
+assign rx_cmd_srej_2 = active_aux_2 ? rx_cmd_srej_aux_2 : rx_cmd_srej_pri_2;
+assign rx_cmd_srej_3 = active_aux_3 ? rx_cmd_srej_aux_3 : rx_cmd_srej_pri_3;
+
+assign tx_cmd_srej_1 = active_aux_1 ? tx_cmd_srej_aux_1 : tx_cmd_srej_pri_1;
+assign tx_cmd_srej_2 = active_aux_2 ? tx_cmd_srej_aux_2 : tx_cmd_srej_pri_2;
+assign tx_cmd_srej_3 = active_aux_3 ? tx_cmd_srej_aux_3 : tx_cmd_srej_pri_3;
+
+assign rx_vr_1 = active_aux_1 ? rx_vr_aux_1 : rx_vr_pri_1;
+assign rx_vr_2 = active_aux_2 ? rx_vr_aux_2 : rx_vr_pri_2;
+assign rx_vr_3 = active_aux_3 ? rx_vr_aux_3 : rx_vr_pri_3;
+
+assign rx_nr_1 = active_aux_1 ? rx_nr_aux_1 : rx_nr_pri_1;
+assign rx_nr_2 = active_aux_2 ? rx_nr_aux_2 : rx_nr_pri_2;
+assign rx_nr_3 = active_aux_3 ? rx_nr_aux_3 : rx_nr_pri_3;
+
+assign rx_ns_1 = active_aux_1 ? rx_ns_aux_1 : rx_ns_pri_1;
+assign rx_ns_2 = active_aux_2 ? rx_ns_aux_2 : rx_ns_pri_2;
+assign rx_ns_3 = active_aux_3 ? rx_ns_aux_3 : rx_ns_pri_3;
+
+assign crc_zero_pri_1 = crc_pri_1==16'b0;
+assign crc_zero_pri_2 = crc_pri_2==16'b0;
+assign crc_zero_pri_3 = crc_pri_3==16'b0;
+
+assign disconnect_pri_dis_1 = disconnect_pri_1 & (~disable_aux_1);
+assign disconnect_pri_dis_2 = disconnect_pri_2 & (~disable_aux_2);
+assign disconnect_pri_dis_3 = disconnect_pri_3 & (~disable_aux_3);
+endmodule
+`timescale 1ns/1ns
+module tx_tri 
+#(
+	parameter HEADER_FIELD = 1,
+	ADDR_WIDTH = 12,
+	THRESHOLD = 3072
+)
+ (
+input [15:0]  tx_dat_1,
+input [15:0]  tx_dat_2,
+input [15:0]  tx_dat_3,
+input  clk_1,tx_ena_1,
+input  clk_2,tx_ena_2,
+input  clk_3,tx_ena_3,
+input [7:0]  tx_adr_1,
+input [7:0]  tx_adr_2,
+input [7:0]  tx_adr_3,
+input  resetb_1,
+input  resetb_2,
+input  resetb_3,
+input  tx_cmd_reset_1, tx_cmd_test_1, rx_cmd_reset_1,
+input  tx_cmd_reset_2, tx_cmd_test_2, rx_cmd_reset_2,
+input  tx_cmd_reset_3, tx_cmd_test_3, rx_cmd_reset_3,
+output  tx_dav_1,
+output  tx_dav_2,
+output  tx_dav_3,
+output [1:0]  tx_sdr_1,
+output [1:0]  tx_sdr_2,
+output [1:0]  tx_sdr_3,
+output [2:0]  tx_ns_1,
+output [2:0]  tx_ns_2,
+output [2:0]  tx_ns_3,
+input [2:0]  tx_nr_1,
+input [2:0]  tx_nr_2,
+input [2:0]  tx_nr_3,
+input [6:0]  tx_cmd_srej_1,
+input [6:0]  tx_cmd_srej_2,
+input [6:0]  tx_cmd_srej_3,
+input  tx_cmd_sabm_1,
+input  tx_cmd_sabm_2,
+input  tx_cmd_sabm_3,
+input  tx_cmd_ua_1,
+input  tx_cmd_ua_2,
+input  tx_cmd_ua_3,
+output  cmd_busy_1,
+output  cmd_busy_2,
+output  cmd_busy_3
+);
+wire [7:0]  phy_tx_data_1;
+wire [7:0]  phy_tx_data_2;
+wire [7:0]  phy_tx_data_3;
+wire [15:0]  crc_1;
+wire [15:0]  crc_2;
+wire [15:0]  crc_3;
+wire [16:0]  fifo_data_w_1;
+wire [16:0]  fifo_data_w_2;
+wire [16:0]  fifo_data_w_3;
+wire [16:0]  fifo_data_r_1;
+wire [16:0]  fifo_data_r_2;
+wire [16:0]  fifo_data_r_3;
+wire [ADDR_WIDTH-1:0]  fifo_addr_r_1, fifo_addr_w_1;
+wire [ADDR_WIDTH-1:0]  fifo_addr_r_2, fifo_addr_w_2;
+wire [ADDR_WIDTH-1:0]  fifo_addr_r_3, fifo_addr_w_3;
+wire [23:0]  dec_in_1, enc_out_1;
+wire [23:0]  dec_in_2, enc_out_2;
+wire [23:0]  dec_in_3, enc_out_3;
+wire [24:0]  SRAM_data_r_1, SRAM_data_w_1;
+wire [24:0]  SRAM_data_r_2, SRAM_data_w_2;
+wire [24:0]  SRAM_data_r_3, SRAM_data_w_3;
+wire [7:0]  phy_tx_data_delayed_1;
+wire [7:0]  phy_tx_data_delayed_2;
+wire [7:0]  phy_tx_data_delayed_3;
+
+MAC_tx_tri #(.HEADER_FIELD(HEADER_FIELD), .ADDR_WIDTH(ADDR_WIDTH), .THRESHOLD(THRESHOLD)) MAC_tx (
+		.tx_dat_1(tx_dat_1),
+		.clk_1(clk_1),
+		.tx_ena_1(tx_ena_1),
+		.tx_dav_1(tx_dav_1),
+		.tx_adr_1(tx_adr_1),
+		.tx_cmd_reset_1(tx_cmd_reset_1),
+		.tx_cmd_test_1(tx_cmd_test_1),
+		.tx_cmd_sabm_1(tx_cmd_sabm_1),
+		.tx_cmd_ua_1(tx_cmd_ua_1),
+		.tx_cmd_srej_1(tx_cmd_srej_1),
+		.rx_cmd_reset_1(rx_cmd_reset_v_1),
+		.cmd_busy_1(cmd_busy_1),
+		.tx_ns_1(tx_ns_1),
+		.tx_nr_1(tx_nr_1),
+		.resetb_1(resetb_1),
+		.phy_tx_data_1(phy_tx_data_1),
+		.phy_bytesel_1(phy_bytesel_1),
+		.phy_dvalid_1(phy_dvalid_1),
+		.crc_1(crc_1),
+		.crc_strobe_1(crc_strobe_1),
+		.phy_dstrobe_1(phy_dstrobe_1),
+		.fifo_data_w_1(fifo_data_w_1),
+		.fifo_data_r_1(fifo_data_r_1),
+		.fifo_addr_w_1(fifo_addr_w_1),
+		.fifo_addr_r_1(fifo_addr_r_1),
+		.fifo_w_1(fifo_w_1),
+		.tx_dat_2(tx_dat_2),
+		.clk_2(clk_2),
+		.tx_ena_2(tx_ena_2),
+		.tx_dav_2(tx_dav_2),
+		.tx_adr_2(tx_adr_2),
+		.tx_cmd_reset_2(tx_cmd_reset_2),
+		.tx_cmd_test_2(tx_cmd_test_2),
+		.tx_cmd_sabm_2(tx_cmd_sabm_2),
+		.tx_cmd_ua_2(tx_cmd_ua_2),
+		.tx_cmd_srej_2(tx_cmd_srej_2),
+		.rx_cmd_reset_2(rx_cmd_reset_v_2),
+		.cmd_busy_2(cmd_busy_2),
+		.tx_ns_2(tx_ns_2),
+		.tx_nr_2(tx_nr_2),
+		.resetb_2(resetb_2),
+		.phy_tx_data_2(phy_tx_data_2),
+		.phy_bytesel_2(phy_bytesel_2),
+		.phy_dvalid_2(phy_dvalid_2),
+		.crc_2(crc_2),
+		.crc_strobe_2(crc_strobe_2),
+		.phy_dstrobe_2(phy_dstrobe_2),
+		.fifo_data_w_2(fifo_data_w_2),
+		.fifo_data_r_2(fifo_data_r_2),
+		.fifo_addr_w_2(fifo_addr_w_2),
+		.fifo_addr_r_2(fifo_addr_r_2),
+		.fifo_w_2(fifo_w_2),
+		.tx_dat_3(tx_dat_3),
+		.clk_3(clk_3),
+		.tx_ena_3(tx_ena_3),
+		.tx_dav_3(tx_dav_3),
+		.tx_adr_3(tx_adr_3),
+		.tx_cmd_reset_3(tx_cmd_reset_3),
+		.tx_cmd_test_3(tx_cmd_test_3),
+		.tx_cmd_sabm_3(tx_cmd_sabm_3),
+		.tx_cmd_ua_3(tx_cmd_ua_3),
+		.tx_cmd_srej_3(tx_cmd_srej_3),
+		.rx_cmd_reset_3(rx_cmd_reset_v_3),
+		.cmd_busy_3(cmd_busy_3),
+		.tx_ns_3(tx_ns_3),
+		.tx_nr_3(tx_nr_3),
+		.resetb_3(resetb_3),
+		.phy_tx_data_3(phy_tx_data_3),
+		.phy_bytesel_3(phy_bytesel_3),
+		.phy_dvalid_3(phy_dvalid_3),
+		.crc_3(crc_3),
+		.crc_strobe_3(crc_strobe_3),
+		.phy_dstrobe_3(phy_dstrobe_3),
+		.fifo_data_w_3(fifo_data_w_3),
+		.fifo_data_r_3(fifo_data_r_3),
+		.fifo_addr_w_3(fifo_addr_w_3),
+		.fifo_addr_r_3(fifo_addr_r_3),
+		.fifo_w_3(fifo_w_3)
+	);
+
+
+Hamming16_24 Hamming16_24_1 (
+		.enc_in(fifo_data_w_1[15:0]),
+		.enc_out(enc_out_1),
+		.dec_in(dec_in_1),
+		.dec_out(fifo_data_r_1[15:0])
+	);
+Hamming16_24 Hamming16_24_2 (
+		.enc_in(fifo_data_w_2[15:0]),
+		.enc_out(enc_out_2),
+		.dec_in(dec_in_2),
+		.dec_out(fifo_data_r_2[15:0])
+	);
+Hamming16_24 Hamming16_24_3 (
+		.enc_in(fifo_data_w_3[15:0]),
+		.enc_out(enc_out_3),
+		.dec_in(dec_in_3),
+		.dec_out(fifo_data_r_3[15:0])
+	);
+
+
+SRAM_tri #(.DATA_WIDTH(25),.ADDR_WIDTH(ADDR_WIDTH)) fifo (
+		.data_w_1(SRAM_data_w_1),
+		.data_r_1(SRAM_data_r_1),
+		.addr_w_1(fifo_addr_w_1),
+		.addr_r_1(fifo_addr_r_1),
+		.w_enable_1(fifo_w_1),
+		.clk_w_1(clkb_1),
+		.data_w_2(SRAM_data_w_2),
+		.data_r_2(SRAM_data_r_2),
+		.addr_w_2(fifo_addr_w_2),
+		.addr_r_2(fifo_addr_r_2),
+		.w_enable_2(fifo_w_2),
+		.clk_w_2(clkb_2),
+		.data_w_3(SRAM_data_w_3),
+		.data_r_3(SRAM_data_r_3),
+		.addr_w_3(fifo_addr_w_3),
+		.addr_r_3(fifo_addr_r_3),
+		.w_enable_3(fifo_w_3),
+		.clk_w_3(clkb_3)
+	);
+
+
+regbank regbank_1 (.D(phy_tx_data_1), .Q(phy_tx_data_delayed_1), 
+		.clk(clk_1), .RN(1'b1)
+	);
+regbank regbank_2 (.D(phy_tx_data_2), .Q(phy_tx_data_delayed_2), 
+		.clk(clk_2), .RN(1'b1)
+	);
+regbank regbank_3 (.D(phy_tx_data_3), .Q(phy_tx_data_delayed_3), 
+		.clk(clk_3), .RN(1'b1)
+	);
+
+
+crc_tri #(.DATA_WIDTH(8)) crc16_8 (
+		.d_1(phy_tx_data_delayed_1), 
+		.init_1(phy_dvalidb_1),
+		.reset_b_1(resetb_1),
+		.clk_1(clk_1),
+		.d_valid_1(crc_strobe_1),
+		.crc_1(crc_1),
+		.d_2(phy_tx_data_delayed_2), 
+		.init_2(phy_dvalidb_2),
+		.reset_b_2(resetb_2),
+		.clk_2(clk_2),
+		.d_valid_2(crc_strobe_2),
+		.crc_2(crc_2),
+		.d_3(phy_tx_data_delayed_3), 
+		.init_3(phy_dvalidb_3),
+		.reset_b_3(resetb_3),
+		.clk_3(clk_3),
+		.d_valid_3(crc_strobe_3),
+		.crc_3(crc_3)
+	);
+
+
+PHY_HDLC_tx_tri PHY_HDLC_tx (
+		.tx_data_1(phy_tx_data_1),
+		.tx_sdr_1(tx_sdr_1),
+		.rx_clk_1(clk_1),
+		.tx_dvalid_1(phy_dvalid_1),
+		.tx_dstrobe_1(phy_dstrobe_1),
+		.resetb_1(phy_resetb_1),
+		.tx_data_2(phy_tx_data_2),
+		.tx_sdr_2(tx_sdr_2),
+		.rx_clk_2(clk_2),
+		.tx_dvalid_2(phy_dvalid_2),
+		.tx_dstrobe_2(phy_dstrobe_2),
+		.resetb_2(phy_resetb_2),
+		.tx_data_3(phy_tx_data_3),
+		.tx_sdr_3(tx_sdr_3),
+		.rx_clk_3(clk_3),
+		.tx_dvalid_3(phy_dvalid_3),
+		.tx_dstrobe_3(phy_dstrobe_3),
+		.resetb_3(phy_resetb_3)
+	);
+
+
+majority_voter_placeholder_tri mv_rx_cmd_reset (
+		.in_1(rx_cmd_reset_1),
+		.out_1(rx_cmd_reset_v_1),
+		.err_1(err_cmd_reset_1),
+		.in_2(rx_cmd_reset_2),
+		.out_2(rx_cmd_reset_v_2),
+		.err_2(err_cmd_reset_2),
+		.in_3(rx_cmd_reset_3),
+		.out_3(rx_cmd_reset_v_3),
+		.err_3(err_cmd_reset_3)
+	);
+
+
+assign	SRAM_data_w_1={fifo_data_w_1[16], enc_out_1};
+assign	SRAM_data_w_2={fifo_data_w_2[16], enc_out_2};
+assign	SRAM_data_w_3={fifo_data_w_3[16], enc_out_3};
+
+assign	fifo_data_r_1[16]=SRAM_data_r_1[24];
+assign	fifo_data_r_2[16]=SRAM_data_r_2[24];
+assign	fifo_data_r_3[16]=SRAM_data_r_3[24];
+
+assign dec_in_1 = SRAM_data_r_1[23:0];
+assign dec_in_2 = SRAM_data_r_2[23:0];
+assign dec_in_3 = SRAM_data_r_3[23:0];
+
+assign clkb_1 = ~clk_1;
+assign clkb_2 = ~clk_2;
+assign clkb_3 = ~clk_3;
+
+assign phy_dvalidb_1=~phy_dvalid_1;
+assign phy_dvalidb_2=~phy_dvalid_2;
+assign phy_dvalidb_3=~phy_dvalid_3;
+
+assign phy_resetb_1 = resetb_1 && (~rx_cmd_reset_v_1);
+assign phy_resetb_2 = resetb_2 && (~rx_cmd_reset_v_2);
+assign phy_resetb_3 = resetb_3 && (~rx_cmd_reset_v_3);
+endmodule
+// missing: tx_ena_old_o <=#1 tx_ena_old_i;
+`timescale 1ns/1ns
+module MAC_tx_iostate (tx_dat, tx_ena, tx_dav, tx_adr, clk, tx_nr, tx_ns_i, tx_ns_o, tx_cmd_srej,
+				resetb, tx_cmd_reset, tx_cmd_test, phy_bytesel_i, phy_bytesel_o, phy_dvalid_i, phy_dvalid_o,
+				phy_tx_data, phy_dstrobe, crc, fifo_data_w, fifo_data_r,
+				fifo_addr_w_i, fifo_addr_w_o, fifo_addr_r_i, fifo_addr_r_o, fifo_w, crc_strobe, tx_cmd_sabm,
+				tx_cmd_ua, cmd_busy, rx_cmd_reset, tx_ena_old_i, tx_ena_old_o, tx_dat_old_i, tx_dat_old_o, overflow_i, overflow_o, fifo_addr_w_last_i, fifo_addr_w_last_o, state_i, state_o, issue_cmd_i, issue_cmd_o, cmd_in_progress_i, cmd_in_progress_o);
+
+	parameter ADDR_WIDTH = 12;
+	parameter THRESHOLD = 3072;
+	parameter HEADER_FIELD = 1; 
+
+	input [15:0] tx_dat;
+ 
+
+	input cmd_in_progress_i;
+	input [11:0] issue_cmd_i;
+	input [1:0] state_i;
+	input phy_dstrobe;
+	input [16:0] fifo_data_r;
+	input [ADDR_WIDTH-1:0] fifo_addr_r_i;
+
+	input [ADDR_WIDTH-1:0]   fifo_addr_w_last_i;
+	input overflow_i;
+	input [ADDR_WIDTH-1:0]  fifo_addr_w_i;
+	input [15:0] tx_dat_old_i;
+	input [1:0] tx_ena_old_i;
+	input [2:0] tx_nr;
+	input [15:0]  crc;
+	input tx_ena;
+
+	input  clk;
+	input [7:0] tx_adr;
+	input resetb;
+	input tx_cmd_reset;
+
+	input  tx_cmd_test;
+
+
+	input   rx_cmd_reset;
+	input [6:0] tx_cmd_srej;
+	input tx_cmd_sabm;
+	input tx_cmd_ua;
+	output cmd_busy;
+	output cmd_in_progress_o;
+	output [11:0] issue_cmd_o;
+	output [1:0] state_o;
+	output fifo_w;
+	output [16:0] fifo_data_w;
+	output [ADDR_WIDTH-1:0] fifo_addr_r_o;
+	output [ADDR_WIDTH-1:0]   fifo_addr_w_last_o;
+	output overflow_o;
+	output [ADDR_WIDTH-1:0]  fifo_addr_w_o;
+	output [15:0] tx_dat_old_o;
+	output [1:0] tx_ena_old_o;
+	output [2:0] tx_ns_o;
+	input [2:0] tx_ns_i;	
+
+	output tx_dav;
+
+	output  crc_strobe;
+	output [7:0] phy_tx_data;
+	output phy_bytesel_o;
+	input phy_bytesel_i;
+
+	output  phy_dvalid_o;
+	input  phy_dvalid_i;
+	reg [2:0] tx_ns_o;	
+	wire phy_dstrobe;
+	reg [ADDR_WIDTH-1:0] fifo_addr_r_o;
+
+	reg [ADDR_WIDTH-1:0]  fifo_addr_w_o;
+
+
+	reg [ADDR_WIDTH-1:0]   fifo_addr_w_last_o;
+	reg phy_bytesel_o;
+
+	reg  phy_dvalid_o;
+	reg [1:0] tx_ena_old_o;
+	reg [15:0] tx_dat_old_o;
+	reg [16:0] fifo_data_w;
+	reg fifo_w;
+	wire [15:0] crc;
+	reg crc_strobe;
+	//wire [15:0] header = {8'h03,tx_adr}; 
+	wire [ADDR_WIDTH-1:0] fifo_nItems = fifo_addr_w_i - fifo_addr_r_i;
+	
+	reg [11:0] issue_cmd_o;
+	reg cmd_in_progress_o;
+	reg [15:0] phy_tx_data16;
+	reg [7:0] phy_tx_data;
+	reg overflow_o;
+	wire cmd_busy = issue_cmd_i[0];
+	wire resetb_rx_cmd_resetb = resetb & (~rx_cmd_reset);
+
+	always @(posedge clk or negedge resetb_rx_cmd_resetb) begin
+		if (~resetb_rx_cmd_resetb) begin
+			fifo_addr_w_o <=#1 0;
+			tx_ena_old_o <=#1 0;
+			tx_dat_old_o <=#1 0;
+			tx_ns_o <=#1 0;
+			overflow_o <=#1 0;
+		end
+/*		else if (rx_cmd_reset) begin
+			fifo_addr_w_o <=#1 0;
+			tx_ena_old_o <=#1 0;
+			tx_dat_old_o <=#1 0;
+			tx_ns_o <=#1 0;
+			overflow_o <=#1 0;
+		end
+*/		else begin
+			tx_ns_o <=#1 tx_ns_i;
+			tx_dat_old_o <=#1 tx_dat_old_i;
+			fifo_addr_w_o <=#1 fifo_addr_w_i;
+			overflow_o <=#1 overflow_i;
+			fifo_addr_w_last_o <=#1 fifo_addr_w_last_i;
+			
+			
+			tx_ena_old_o <=#1 {tx_ena_old_i[0], tx_ena};
+
+			if (((tx_ena | (tx_ena_old_i[0])) && HEADER_FIELD) ||
+				((tx_ena) && (!HEADER_FIELD))) begin
+
+				tx_dat_old_o <=#1 tx_dat;
+				if ((fifo_nItems != {ADDR_WIDTH{1'b1}}) && (~overflow_i)) 
+					fifo_addr_w_o <=#1 fifo_addr_w_i + 1;
+				else begin
+					overflow_o <=#1 1;
+					fifo_addr_w_o <=#1 fifo_addr_w_last_i;
+				end
+			end
+
+			if ((~tx_ena) & (tx_ena_old_i[0])) tx_ns_o <=#1 tx_ns_i + 1;
+			if (tx_cmd_reset | tx_cmd_sabm) tx_ns_o <=#1 0;
+
+			if (!tx_ena_old_i[0]) fifo_addr_w_last_o <=#1 fifo_addr_w_i;
+
+
+			if ((~tx_ena)&&(fifo_nItems != {ADDR_WIDTH{1'b1}})) overflow_o <=#1 0;
+
+		end
+	end
+
+
+	assign tx_dav = ~((fifo_nItems >= THRESHOLD) || tx_ena || tx_ena_old_i[0] ||
+						(tx_ena_old_i[1] && HEADER_FIELD));
+
+	reg [1:0] state_o;
+	parameter [1:0] IDLE = 0,
+					START = 1,
+					DATA = 2,
+					END = 3;
+					
+	always @(posedge clk or negedge resetb_rx_cmd_resetb) begin
+		if (~resetb_rx_cmd_resetb) begin
+			fifo_addr_r_o <=#1 0;
+			phy_bytesel_o <=#1 0;
+			phy_dvalid_o <=#1 0;
+			state_o <=#1 0;
+			issue_cmd_o <=#1 0;
+		end
+/*		else if (rx_cmd_reset) begin
+			fifo_addr_r_o <=#1 0;
+			phy_bytesel_o <=#1 0;
+			phy_dvalid_o <=#1 0;
+			state_o <=#1 0;
+			issue_cmd_o <=#1 0;
+		end
+*/		else begin
+			state_o <=#1 state_i;
+			phy_dvalid_o <=#1 phy_dvalid_i;
+			phy_bytesel_o <=#1 phy_bytesel_i;
+			fifo_addr_r_o <=#1 fifo_addr_r_i;
+			issue_cmd_o <=#1 issue_cmd_i;
+			cmd_in_progress_o <=#1 cmd_in_progress_i;
+
+			if (!issue_cmd_i) begin
+				if (tx_cmd_ua && HEADER_FIELD) issue_cmd_o <=#1 8'h63;
+				if (tx_cmd_srej && HEADER_FIELD) issue_cmd_o <=#1 {tx_cmd_srej,5'h0d};
+				if (tx_cmd_sabm && HEADER_FIELD) issue_cmd_o <=#1 8'h2f;
+				if (tx_cmd_test && HEADER_FIELD) issue_cmd_o <=#1 8'he3;
+				if (tx_cmd_reset && HEADER_FIELD) issue_cmd_o <=#1 8'h8f;
+			end
+		
+			if (phy_dstrobe & phy_dvalid_i) begin
+				if (phy_bytesel_i) begin
+					phy_bytesel_o <=#1 0;
+				end
+				else begin
+					phy_bytesel_o <=#1 1;
+				end
+			end
+		
+			case (state_i) // synopsys parallel_case
+				IDLE: begin
+					phy_dvalid_o <=#1 0;
+					if ((~phy_dvalid_i) && ((fifo_nItems!=0) || issue_cmd_i)) begin
+						cmd_in_progress_o <=#1 issue_cmd_i[0];
+						phy_dvalid_o <=#1 1;
+						state_o <=#1 START;
+					end
+				end
+				
+				START: begin
+					phy_dvalid_o <=#1 1;
+					if (phy_dstrobe) begin
+						if (phy_bytesel_i) begin
+							state_o <=#1 DATA;
+							if (~cmd_in_progress_i) begin
+								fifo_addr_r_o <=#1 fifo_addr_r_i + 1;
+							end
+							else begin
+								if (!issue_cmd_i[11:8]) state_o <=#1 END;
+							end							
+						end
+					end
+				end
+			
+				DATA: begin
+					phy_dvalid_o <=#1 1;
+					if (phy_dstrobe) begin
+						if (phy_bytesel_i) begin
+							if (~cmd_in_progress_i) fifo_addr_r_o <=#1 fifo_addr_r_i + 1;
+							else state_o <=#1 END;
+						end
+					end
+
+					if ((~cmd_in_progress_i) && (fifo_data_r[16] || (fifo_nItems==0))) begin
+						state_o <=#1 END;
+					end	
+				end
+				
+				END: begin
+					if (phy_dstrobe) begin
+						if (phy_bytesel_i) begin
+							state_o <=#1 IDLE;
+							if (cmd_in_progress_i) begin
+								cmd_in_progress_o <=#1 0;
+								issue_cmd_o <=#1 0;
+							end
+						end
+					end
+				end
+			
+			endcase
+		end
+	end
+	
+	// COMBINATORIAL LOGIC
+	always @* begin
+		case (state_i)
+			START: begin
+				if (HEADER_FIELD) begin
+					phy_tx_data16 = {tx_nr,1'b0,fifo_data_r[11:9],1'b0,fifo_data_r[7:0]};
+					if (cmd_in_progress_i) phy_tx_data16 = {issue_cmd_i, 8'hff};
+				end
+				else phy_tx_data16 = fifo_data_r;
+			end
+			DATA: begin
+				phy_tx_data16 = fifo_data_r;
+				if (cmd_in_progress_i) phy_tx_data16 = {issue_cmd_i[10:8],1'b1,issue_cmd_i[7:5],1'b1};
+			end
+			END: phy_tx_data16 = crc;
+			default: phy_tx_data16 = fifo_data_r;
+		endcase
+
+		phy_tx_data = phy_bytesel_i ? phy_tx_data16[15:8] : phy_tx_data16[7:0];
+		crc_strobe = phy_dstrobe & phy_dvalid_i & (state_i!=END);
+	
+		fifo_w = 0;
+		fifo_data_w = tx_dat_old_i;
+		if (HEADER_FIELD) begin
+			if (tx_ena & (~tx_ena_old_i[0])) begin
+				fifo_data_w =  {1'b1,4'b0,tx_ns_i,1'b0,tx_adr};
+				fifo_w = 1;
+			end
+			if (tx_ena_old_i[0]) begin
+				fifo_w = 1;
+			end
+		end
+		else begin
+			if (tx_ena) begin
+				fifo_data_w = {~tx_ena_old_i[0], tx_dat};
+				fifo_w = 1;
+			end
+		end
+	end
+	
+
+endmodule
+
+`timescale 1ns/1ns
+module MAC_tx_tri (tx_dat_1, tx_dat_2, tx_dat_3, tx_ena_1, tx_ena_2, tx_ena_3, tx_dav_1, tx_dav_2, tx_dav_3, tx_adr_1, tx_adr_2, tx_adr_3, clk_1, clk_2, clk_3, tx_nr_1, tx_nr_2, tx_nr_3, tx_ns_1, tx_ns_2, tx_ns_3, tx_cmd_srej_1, tx_cmd_srej_2, tx_cmd_srej_3,
+				resetb_1, resetb_2, resetb_3, tx_cmd_reset_1, tx_cmd_reset_2, tx_cmd_reset_3, tx_cmd_test_1, tx_cmd_test_2, tx_cmd_test_3, phy_bytesel_1, phy_bytesel_2, phy_bytesel_3, phy_dvalid_1, phy_dvalid_2, phy_dvalid_3,
+				phy_tx_data_1, phy_tx_data_2, phy_tx_data_3, phy_dstrobe_1, phy_dstrobe_2, phy_dstrobe_3, crc_1, crc_2, crc_3, fifo_data_w_1, fifo_data_w_2, fifo_data_w_3, fifo_data_r_1, fifo_data_r_2, fifo_data_r_3,
+				fifo_addr_w_1, fifo_addr_w_2, fifo_addr_w_3, fifo_addr_r_1, fifo_addr_r_2, fifo_addr_r_3, fifo_w_1, fifo_w_2, fifo_w_3, crc_strobe_1, crc_strobe_2, crc_strobe_3, tx_cmd_sabm_1, tx_cmd_sabm_2, tx_cmd_sabm_3,
+				tx_cmd_ua_1, tx_cmd_ua_2, tx_cmd_ua_3, cmd_busy_1, cmd_busy_2, cmd_busy_3, rx_cmd_reset_1, rx_cmd_reset_2, rx_cmd_reset_3);
+
+	parameter ADDR_WIDTH = 12;
+	parameter THRESHOLD = 3072;
+	parameter HEADER_FIELD = 1; 
+
+	input [15:0] tx_dat_1, tx_dat_2, tx_dat_3;
+
+	input [15:0]  crc_1, crc_2, crc_3;
+	input tx_ena_1, tx_ena_2, tx_ena_3;
+
+	input  clk_1, clk_2, clk_3;
+	input [7:0] tx_adr_1, tx_adr_2, tx_adr_3;
+	input resetb_1, resetb_2, resetb_3;
+	input tx_cmd_reset_1, tx_cmd_reset_2, tx_cmd_reset_3;
+
+	input  tx_cmd_test_1, tx_cmd_test_2, tx_cmd_test_3;
+
+	input   rx_cmd_reset_1, rx_cmd_reset_2, rx_cmd_reset_3;
+	input [6:0] tx_cmd_srej_1, tx_cmd_srej_2, tx_cmd_srej_3;
+	input tx_cmd_sabm_1, tx_cmd_sabm_2, tx_cmd_sabm_3;
+	input tx_cmd_ua_1, tx_cmd_ua_2, tx_cmd_ua_3;
+	output cmd_busy_1, cmd_busy_2, cmd_busy_3;
+	output tx_dav_1, tx_dav_2, tx_dav_3;
+
+	output  crc_strobe_1, crc_strobe_2, crc_strobe_3;
+	output [7:0] phy_tx_data_1, phy_tx_data_2, phy_tx_data_3;
+	output phy_bytesel_1, phy_bytesel_2, phy_bytesel_3;
+
+	output  phy_dvalid_1, phy_dvalid_2, phy_dvalid_3;
+	input phy_dstrobe_1, phy_dstrobe_2, phy_dstrobe_3;
+	output fifo_w_1, fifo_w_2, fifo_w_3;
+	output [16:0] fifo_data_w_1, fifo_data_w_2, fifo_data_w_3;
+	input [16:0] fifo_data_r_1, fifo_data_r_2, fifo_data_r_3;
+	output [ADDR_WIDTH-1:0] fifo_addr_r_1, fifo_addr_r_2, fifo_addr_r_3;
+
+	output [ADDR_WIDTH-1:0]  fifo_addr_w_1, fifo_addr_w_2, fifo_addr_w_3;
+	input [2:0] tx_nr_1, tx_nr_2, tx_nr_3;
+	output [2:0] tx_ns_1, tx_ns_2, tx_ns_3;	
+
+	wire [ADDR_WIDTH-1:0] fifo_addr_w_1, fifo_addr_w_2, fifo_addr_w_3;
+	wire [1:0] tx_ena_old_1, tx_ena_old_2, tx_ena_old_3;
+	wire [15:0] tx_dat_old_1, tx_dat_old_2, tx_dat_old_3;
+	wire [2:0] tx_ns_1, tx_ns_2, tx_ns_3;
+	wire overflow_1, overflow_2, overflow_3;
+	wire [ADDR_WIDTH-1:0] fifo_addr_w_last_1, fifo_addr_w_last_2, fifo_addr_w_last_3;
+	wire [ADDR_WIDTH-1:0] fifo_addr_r_1, fifo_addr_r_2, fifo_addr_r_3;
+	wire phy_bytesel_1, phy_bytesel_2, phy_bytesel_3;
+	wire phy_dvalid_1, phy_dvalid_2, phy_dvalid_3;
+	wire [1:0] state_1, state_2, state_3;
+	wire [11:0] issue_cmd_1, issue_cmd_2, issue_cmd_3;
+	wire cmd_in_progress_1, cmd_in_progress_2, cmd_in_progress_3;
+	wire [ADDR_WIDTH-1:0] fifo_addr_w;
+	wire [1:0] tx_ena_old;
+	wire [15:0] tx_dat_old;
+	wire [2:0] tx_ns;
+	wire overflow;
+	wire [ADDR_WIDTH-1:0] fifo_addr_w_last;
+	wire [ADDR_WIDTH-1:0] fifo_addr_r;
+	wire phy_bytesel;
+	wire phy_dvalid;
+	wire [1:0] state;
+	wire [11:0] issue_cmd;
+	wire cmd_in_progress;
+	MAC_tx_iostate #(.ADDR_WIDTH(ADDR_WIDTH), .THRESHOLD(THRESHOLD), .HEADER_FIELD(HEADER_FIELD) ) MAC_tx_iostate_1 (.tx_dat(tx_dat_1), .tx_ena(tx_ena_1), .tx_dav(tx_dav_1), .tx_adr(tx_adr_1), .clk(clk_1), .tx_nr(tx_nr_1), .tx_ns_i(tx_ns_1), .tx_ns_o(tx_ns_2), .tx_cmd_srej(tx_cmd_srej_1),
+				.resetb(resetb_1), .tx_cmd_reset(tx_cmd_reset_1), .tx_cmd_test(tx_cmd_test_1), .phy_bytesel_i(phy_bytesel_1), .phy_bytesel_o(phy_bytesel_2), .phy_dvalid_i(phy_dvalid_1), .phy_dvalid_o(phy_dvalid_2),
+				.phy_tx_data(phy_tx_data_1), .phy_dstrobe(phy_dstrobe_1), .crc(crc_1), .fifo_data_w(fifo_data_w_1), .fifo_data_r(fifo_data_r_1),
+				.fifo_addr_w_i(fifo_addr_w_1), .fifo_addr_w_o(fifo_addr_w_2), .fifo_addr_r_i(fifo_addr_r_1), .fifo_addr_r_o(fifo_addr_r_2), .fifo_w(fifo_w_1), .crc_strobe(crc_strobe_1), .tx_cmd_sabm(tx_cmd_sabm_1),
+				.tx_cmd_ua(tx_cmd_ua_1), .cmd_busy(cmd_busy_1), .rx_cmd_reset(rx_cmd_reset_1), .tx_ena_old_i(tx_ena_old_1), .tx_ena_old_o(tx_ena_old_2), .tx_dat_old_i(tx_dat_old_1), .tx_dat_old_o(tx_dat_old_2), .overflow_i(overflow_1), .overflow_o(overflow_2), .fifo_addr_w_last_i(fifo_addr_w_last_1), .fifo_addr_w_last_o(fifo_addr_w_last_2), .state_i(state_1), .state_o(state_2), .issue_cmd_i(issue_cmd_1), .issue_cmd_o(issue_cmd_2), .cmd_in_progress_i(cmd_in_progress_1), .cmd_in_progress_o(cmd_in_progress_2));
+	MAC_tx_iostate #(.ADDR_WIDTH(ADDR_WIDTH), .THRESHOLD(THRESHOLD), .HEADER_FIELD(HEADER_FIELD) ) MAC_tx_iostate_2 (.tx_dat(tx_dat_2), .tx_ena(tx_ena_2), .tx_dav(tx_dav_2), .tx_adr(tx_adr_2), .clk(clk_2), .tx_nr(tx_nr_2), .tx_ns_i(tx_ns_2), .tx_ns_o(tx_ns_3), .tx_cmd_srej(tx_cmd_srej_2),
+				.resetb(resetb_2), .tx_cmd_reset(tx_cmd_reset_2), .tx_cmd_test(tx_cmd_test_2), .phy_bytesel_i(phy_bytesel_2), .phy_bytesel_o(phy_bytesel_3), .phy_dvalid_i(phy_dvalid_2), .phy_dvalid_o(phy_dvalid_3),
+				.phy_tx_data(phy_tx_data_2), .phy_dstrobe(phy_dstrobe_2), .crc(crc_2), .fifo_data_w(fifo_data_w_2), .fifo_data_r(fifo_data_r_2),
+				.fifo_addr_w_i(fifo_addr_w_2), .fifo_addr_w_o(fifo_addr_w_3), .fifo_addr_r_i(fifo_addr_r_2), .fifo_addr_r_o(fifo_addr_r_3), .fifo_w(fifo_w_2), .crc_strobe(crc_strobe_2), .tx_cmd_sabm(tx_cmd_sabm_2),
+				.tx_cmd_ua(tx_cmd_ua_2), .cmd_busy(cmd_busy_2), .rx_cmd_reset(rx_cmd_reset_2), .tx_ena_old_i(tx_ena_old_2), .tx_ena_old_o(tx_ena_old_3), .tx_dat_old_i(tx_dat_old_2), .tx_dat_old_o(tx_dat_old_3), .overflow_i(overflow_2), .overflow_o(overflow_3), .fifo_addr_w_last_i(fifo_addr_w_last_2), .fifo_addr_w_last_o(fifo_addr_w_last_3), .state_i(state_2), .state_o(state_3), .issue_cmd_i(issue_cmd_2), .issue_cmd_o(issue_cmd_3), .cmd_in_progress_i(cmd_in_progress_2), .cmd_in_progress_o(cmd_in_progress_3));
+	MAC_tx_iostate #(.ADDR_WIDTH(ADDR_WIDTH), .THRESHOLD(THRESHOLD), .HEADER_FIELD(HEADER_FIELD) ) MAC_tx_iostate_3 (.tx_dat(tx_dat_3), .tx_ena(tx_ena_3), .tx_dav(tx_dav_3), .tx_adr(tx_adr_3), .clk(clk_3), .tx_nr(tx_nr_3), .tx_ns_i(tx_ns_3), .tx_ns_o(tx_ns), .tx_cmd_srej(tx_cmd_srej_3),
+				.resetb(resetb_3), .tx_cmd_reset(tx_cmd_reset_3), .tx_cmd_test(tx_cmd_test_3), .phy_bytesel_i(phy_bytesel_3), .phy_bytesel_o(phy_bytesel), .phy_dvalid_i(phy_dvalid_3), .phy_dvalid_o(phy_dvalid),
+				.phy_tx_data(phy_tx_data_3), .phy_dstrobe(phy_dstrobe_3), .crc(crc_3), .fifo_data_w(fifo_data_w_3), .fifo_data_r(fifo_data_r_3),
+				.fifo_addr_w_i(fifo_addr_w_3), .fifo_addr_w_o(fifo_addr_w), .fifo_addr_r_i(fifo_addr_r_3), .fifo_addr_r_o(fifo_addr_r), .fifo_w(fifo_w_3), .crc_strobe(crc_strobe_3), .tx_cmd_sabm(tx_cmd_sabm_3),
+				.tx_cmd_ua(tx_cmd_ua_3), .cmd_busy(cmd_busy_3), .rx_cmd_reset(rx_cmd_reset_3), .tx_ena_old_i(tx_ena_old_3), .tx_ena_old_o(tx_ena_old), .tx_dat_old_i(tx_dat_old_3), .tx_dat_old_o(tx_dat_old), .overflow_i(overflow_3), .overflow_o(overflow), .fifo_addr_w_last_i(fifo_addr_w_last_3), .fifo_addr_w_last_o(fifo_addr_w_last), .state_i(state_3), .state_o(state), .issue_cmd_i(issue_cmd_3), .issue_cmd_o(issue_cmd), .cmd_in_progress_i(cmd_in_progress_3), .cmd_in_progress_o(cmd_in_progress));
+
+	majority_voter #(.WIDTH(42+ADDR_WIDTH-1+ADDR_WIDTH-1+ADDR_WIDTH-1)) mv (
+		.in1({fifo_addr_w_2, tx_ena_old_2, tx_dat_old_2, tx_ns_2, overflow_2, fifo_addr_w_last_2, fifo_addr_r_2, phy_bytesel_2, phy_dvalid_2, state_2, issue_cmd_2, cmd_in_progress_2}),
+		.in2({fifo_addr_w_3, tx_ena_old_3, tx_dat_old_3, tx_ns_3, overflow_3, fifo_addr_w_last_3, fifo_addr_r_3, phy_bytesel_3, phy_dvalid_3, state_3, issue_cmd_3, cmd_in_progress_3}),
+		.in3({fifo_addr_w, tx_ena_old, tx_dat_old, tx_ns, overflow, fifo_addr_w_last, fifo_addr_r, phy_bytesel, phy_dvalid, state, issue_cmd, cmd_in_progress}),
+		.out({fifo_addr_w_1, tx_ena_old_1, tx_dat_old_1, tx_ns_1, overflow_1, fifo_addr_w_last_1, fifo_addr_r_1, phy_bytesel_1, phy_dvalid_1, state_1, issue_cmd_1, cmd_in_progress_1}),
+		.err()
+	);
+endmodule
+
+// missing: rx_ns_o <=#1 rx_ns_i;
+// missing: rx_dat_o <=#1 rx_dat_i;
+// missing: rx_eop_o <=#1 rx_eop_i;
+// missing: rx_ena_o <=#1 rx_ena_i;
+// missing: rx_sop_o <=#1 rx_sop_i;
+// missing: rx_nr_o <=#1 rx_nr_i;
+// missing: header_o <=#1 header_i;
+// missing: rx_cmd_ua_o <=#1 rx_cmd_ua_i;
+// missing: rx_cmd_srej_o <=#1 rx_cmd_srej_i;
+// missing: tx_cmd_ua_o <=#1 tx_cmd_ua_i;
+// missing: tx_cmd_srej_o <=#1 tx_cmd_srej_i;
+// missing: rx_cmd_sabm_o <=#1 rx_cmd_sabm_i;
+// missing: rx_cmd_test_o <=#1 rx_cmd_test_i;
+// missing: rx_cmd_reset_o <=#1 rx_cmd_reset_i;
+// missing: phy_dvalid_old_o <=#1 phy_dvalid_old_i;
+
+`timescale 1ns/1ns
+module MAC_rx_iostate (rx_dat_i, rx_dat_o,  rx_ena_i, rx_ena_o, rx_ena_pre_i, rx_ena_pre_o,  rx_eop_i, rx_eop_o, rx_err, rx_vr_i, rx_vr_o, rx_nr_i, rx_nr_o,
+			rx_sop_i, rx_sop_o, rx_adr_i, rx_adr_o, clk, rx_dav, resetb, rx_cmd_reset_i, rx_cmd_reset_o, rx_cmd_test_i, rx_cmd_test_o,
+			phy_data, phy_dvalid, phy_dstrobe,  crc_zero,fifo_data_w,
+			fifo_data_r, fifo_addr_w, fifo_addr_r_i, fifo_addr_r_o, fifo_w, cmd_busy, active,
+			rx_cmd_ua_i, rx_cmd_ua_o, rx_cmd_srej_i, rx_cmd_srej_o, tx_cmd_srej_i, tx_cmd_srej_o, rx_ns_i, rx_ns_o, rx_cmd_sabm_i, rx_cmd_sabm_o,
+			disconnect, tx_cmd_ua_i, tx_cmd_ua_o, tx_cmd_reset , fifo_addr_w_int_i, fifo_addr_w_int_o, phy_bytesel_i, phy_bytesel_o, phy_dvalid_old_i, phy_dvalid_old_o, fifo_addr_w_last_i, fifo_addr_w_last_o, phy_data_old_i, phy_data_old_o, phy_data_lowbyte_i, phy_data_lowbyte_o, phy_data_old2_i, phy_data_old2_o, overflow_i, overflow_o, packet_length_i, packet_length_o, header_i, header_o);
+
+	parameter ADDR_WIDTH = 12;
+	parameter HEADER_FIELD = 1; 
+	parameter MAX_LENGTH = 1<<ADDR_WIDTH;
+
+	output [15:0] rx_dat_o;
+	output    rx_ena_pre_o;
+	output      rx_err;
+	input [15:0] rx_dat_i;
+	input [15:0] phy_data_old_i;
+
+	input [ADDR_WIDTH-1:0]  fifo_addr_w_last_i;
+	output [7:0] rx_adr_o;
+	output rx_cmd_reset_o;
+	output  rx_cmd_test_o;
+	output  rx_cmd_ua_o;
+	output  tx_cmd_ua_o;
+	output   rx_cmd_sabm_o;
+	output [6:0] rx_cmd_srej_o;
+	output [7:0] header_o;
+	output [15:0] packet_length_o;
+	output [6:0] tx_cmd_srej_o;
+	output fifo_w;
+	output overflow_o;
+	output [16:0] fifo_data_w;
+	output [ADDR_WIDTH-1:0] fifo_addr_r_o;
+	input [ADDR_WIDTH-1:0] fifo_addr_r_i;
+
+	input phy_dvalid_old_i;
+
+	input  phy_bytesel_i;
+	input [ADDR_WIDTH-1:0] fifo_addr_w_int_i;
+
+
+	input [2:0] rx_vr_i;
+
+	input disconnect;
+
+	
+	input  tx_cmd_reset;
+
+
+	
+	output [ADDR_WIDTH-1:0]  fifo_addr_w;
+	output [2:0] rx_vr_o;
+	output [2:0] rx_nr_o;
+	input [2:0] rx_nr_i;
+
+
+	input   active;
+	output [2:0]  rx_ns_o;
+	input [2:0]  rx_ns_i;
+	
+	output [15:0] phy_data_old2_o;
+	output [7:0] phy_data_lowbyte_o;
+	output [15:0] phy_data_old_o;
+	output [ADDR_WIDTH-1:0]  fifo_addr_w_last_o;
+	output phy_dvalid_old_o;
+	output  phy_bytesel_o;
+	output [ADDR_WIDTH-1:0] fifo_addr_w_int_o;
+	output rx_ena_o;
+	input rx_ena_i;
+
+	output  rx_eop_o;
+	input  rx_eop_i;
+
+
+	output   rx_sop_o;
+	input   rx_sop_i;
+
+
+
+	input    rx_ena_pre_i;
+
+
+
+
+	input [7:0] rx_adr_i;
+	input rx_cmd_reset_i;
+
+	input [7:0] header_i;
+
+	input [15:0] packet_length_i;
+	input clk;
+
+	input  rx_dav;
+	input overflow_i;
+	input resetb;
+	input [7:0] phy_data;
+	input phy_dvalid;
+	input crc_zero;
+
+	input  cmd_busy;
+	input [16:0] fifo_data_r;
+
+	input  rx_cmd_test_i;
+
+
+	input  rx_cmd_ua_i;
+
+
+
+	input  tx_cmd_ua_i;
+
+
+
+
+	input   rx_cmd_sabm_i;
+	input [6:0] rx_cmd_srej_i;
+	input [6:0] tx_cmd_srej_i;
+	input phy_dstrobe;
+	input [15:0] phy_data_old2_i;
+	input [7:0] phy_data_lowbyte_i;
+	reg [ADDR_WIDTH-1:0] fifo_addr_r_o;
+
+
+	reg [ADDR_WIDTH-1:0]  fifo_addr_w;
+	reg [16:0] fifo_data_w;
+	reg fifo_w;
+
+	reg [ADDR_WIDTH-1:0] fifo_addr_w_int_o;
+	reg [ADDR_WIDTH-1:0]  fifo_addr_w_last_o;
+	reg phy_dvalid_old_o;
+	reg  phy_bytesel_o;
+	wire phy_dstrobe, phy_dvalid;
+	wire [7:0] phy_data;
+	reg rx_sop_o;
+	reg [7:0] rx_adr_o;
+	reg overflow_o;
+	reg [15:0] rx_dat_o;
+	reg rx_eop_o;
+	wire rx_err = 1'b0;
+	reg [7:0] phy_data_lowbyte_o;
+	reg [15:0] phy_data_old_o;
+	reg [15:0] phy_data_old2_o;
+	reg [15:0] packet_length_o;
+	reg rx_ena_o;
+
+	reg  rx_ena_pre_o;
+
+
+	reg   rx_cmd_reset_o;
+
+
+
+	reg    rx_cmd_test_o;
+
+
+
+
+	reg     rx_cmd_sabm_o;
+
+
+
+
+
+	reg     rx_cmd_ua_o;
+
+
+
+
+
+
+	reg     tx_cmd_ua_o;
+	reg [6:0] rx_cmd_srej_o;
+	reg [6:0] tx_cmd_srej_o;
+	reg [2:0] rx_vr_o;
+
+	reg [2:0]  rx_nr_o;
+
+
+	reg [2:0]   rx_ns_o;
+	reg [7:0] header_o;
+	wire [ADDR_WIDTH-1:0] fifo_nItems = fifo_addr_w_int_i - fifo_addr_r_i;
+	wire [ADDR_WIDTH-1:0] fifo_nItems_complete = fifo_addr_w_last_i - fifo_addr_r_i;
+	wire fifo_full = (fifo_nItems==(MAX_LENGTH-1));
+	wire [2:0] rx_ns_minus_one = header_i[3:1]-1;
+	
+	wire disconnectb_resetb = resetb & (~disconnect);
+
+
+	always @(posedge clk or negedge disconnectb_resetb) begin
+		if (~disconnectb_resetb) begin
+			fifo_addr_w_int_o <=#1 0;
+			//phy_bytesel_o <=#1 0;
+			phy_dvalid_old_o <=#1 0;
+			fifo_addr_w_last_o <=#1 0;
+			//phy_data_old_o <=#1 0;
+			//phy_data_lowbyte_o <=#1 0;
+			//phy_data_old2_o <=#1 0;
+			rx_cmd_reset_o <=#1 0;
+			rx_cmd_test_o <=#1 0;
+			rx_vr_o <=#1 0;
+			rx_cmd_sabm_o <=#1 0;
+			tx_cmd_srej_o <=#1 0;
+			tx_cmd_ua_o <=#1 0;
+		end
+		else if (rx_cmd_reset_i) begin
+			fifo_addr_w_int_o <=#1 0;
+			phy_bytesel_o <=#1 0;
+			phy_dvalid_old_o <=#1 0;
+			fifo_addr_w_last_o <=#1 0;
+			phy_data_old_o <=#1 0;
+			phy_data_lowbyte_o <=#1 0;
+			phy_data_old2_o <=#1 0;
+			overflow_o <=#1 0;
+			rx_cmd_reset_o <=#1 0;
+			rx_cmd_test_o <=#1 0;
+			rx_vr_o <=#1 0;
+			rx_cmd_sabm_o <=#1 0;
+			tx_cmd_ua_o <=#1 1;
+		end
+		else begin
+			rx_cmd_reset_o <=#1 0;
+			rx_cmd_test_o <=#1 0;
+			tx_cmd_srej_o <=#1 0;
+			rx_cmd_srej_o <=#1 0;
+			rx_cmd_sabm_o <=#1 0;
+			rx_cmd_ua_o <=#1 0;
+			tx_cmd_ua_o <=#1 rx_cmd_sabm_i;
+			phy_data_old_o <=#1 phy_data_old_i;
+			fifo_addr_w_last_o <=#1 fifo_addr_w_last_i;
+			phy_bytesel_o <=#1 phy_bytesel_i;
+			fifo_addr_w_int_o <=#1 fifo_addr_w_int_i;
+			phy_data_lowbyte_o <=#1 phy_data_lowbyte_i;
+			phy_data_old2_o <=#1 phy_data_old2_i;
+			packet_length_o <=#1 packet_length_i;
+			phy_dvalid_old_o <=#1 phy_dvalid;
+			overflow_o <=#1 overflow_i;
+			rx_vr_o <=#1 rx_vr_i;
+			
+			if (tx_cmd_reset) rx_vr_o <=#1 0;
+			if (rx_cmd_sabm_i) rx_vr_o <=#1 0;
+			
+			if (phy_dvalid) begin
+				if (phy_dstrobe) begin
+					if (phy_bytesel_i) begin
+						if (fifo_full || overflow_i) begin 
+							overflow_o <=#1 1;
+						end 
+						else begin
+							fifo_addr_w_int_o <=#1 fifo_addr_w_int_i + 1;
+						end
+						phy_data_old_o <=#1 {phy_data,phy_data_lowbyte_i};
+						phy_data_old2_o <=#1 phy_data_old_i;
+						phy_bytesel_o <=#1 0;
+						packet_length_o <=#1 packet_length_i + 1;
+						if ((packet_length_i==0) && HEADER_FIELD) begin // HEADER
+							header_o <=#1 phy_data;
+						end
+					end
+					else begin
+						phy_data_lowbyte_o <=#1 phy_data;
+						phy_bytesel_o <=#1 1;
+					end
+				end
+			end
+			else begin
+				packet_length_o <=#1 0;
+				if (fifo_full); else overflow_o <=#1 0;
+				phy_bytesel_o <=#1 0;
+			end
+			
+			
+			if ((~phy_dvalid) && phy_dvalid_old_i) begin
+				if (crc_zero) begin
+					if (((packet_length_i)==2) && HEADER_FIELD) begin
+						// COMMAND FRAME
+						fifo_addr_w_int_o <=#1 fifo_addr_w_last_i;
+						if (phy_data_old2_i[15:8] == 8'h8f) rx_cmd_reset_o <=#1 1;
+						if (phy_data_old2_i[15:8] == 8'h2f) rx_cmd_sabm_o <=#1 1;
+						if (phy_data_old2_i[15:8] == 8'h63) rx_cmd_ua_o <=#1 1;
+						if (phy_data_old2_i[15:8] == 8'he3) rx_cmd_test_o <=#1 1;
+						//if (phy_data_old2_i[15:11] == 5'h0d) rx_cmd_srej_o[2:0] <=#1 phy_data_old2_i[10:8];
+					end
+					else begin
+						if ((!HEADER_FIELD) || (HEADER_FIELD && (!header_i[0]))) begin
+							// INFORMATION FRAME END
+							fifo_addr_w_last_o <=#1 fifo_addr_w_int_i-1;
+							fifo_addr_w_int_o <=#1 fifo_addr_w_int_i-1;
+							// Receive state variable:
+							rx_vr_o <=#1 header_i[3:1]+1;
+							if (header_i[3:1]!=rx_vr_i) begin
+								tx_cmd_srej_o <=#1 {1'b1,rx_ns_minus_one, rx_vr_i};
+							end
+
+							rx_nr_o <=#1 header_i[7:5];
+						end
+						else begin // SREJ FRAME END
+							fifo_addr_w_int_o <=#1 fifo_addr_w_last_i;
+							rx_cmd_srej_o <=#1 {1'b1,phy_data_old2_i[7:5],phy_data_old2_i[3:1]};
+						end
+					end
+				end
+				else begin // CRC FAILED
+					fifo_addr_w_int_o <=#1 fifo_addr_w_last_i;
+				end
+			end
+		end
+	end
+	
+	// COMBINATORIAL LOGIC
+	always @* begin
+		fifo_w = 0;
+		fifo_addr_w = fifo_addr_w_int_i;
+		fifo_data_w = {1'b0,phy_data,phy_data_lowbyte_i};
+		
+		if (phy_dstrobe && phy_dvalid && (~fifo_full)) begin
+			if (phy_bytesel_i) begin
+				fifo_w=1;
+			end
+		end
+
+		if ((~phy_dvalid) && phy_dvalid_old_i) begin
+			if (~(((fifo_addr_w_int_i-fifo_addr_w_last_i)==2) && HEADER_FIELD)) begin
+				fifo_addr_w = fifo_addr_w_int_i-2;
+				fifo_data_w = {1'b1,phy_data_old2_i};
+				fifo_w=1;
+			end
+		end
+	end
+	
+	
+	// FIFO READ INTERFACE 
+	always @(posedge clk or negedge disconnectb_resetb) begin
+		if (~disconnectb_resetb) begin
+			fifo_addr_r_o <=#1 0;
+			//rx_sop_o <=#1 0;
+			//rx_ena_o <=#1 0;
+			//rx_adr_o <=#1 0;
+			rx_ena_pre_o <=#1 0;
+		end
+		else if (rx_cmd_reset_i) begin
+			fifo_addr_r_o <=#1 0;
+			rx_sop_o <=#1 0;
+			rx_ena_o <=#1 0;
+			rx_adr_o <=#1 0;
+			rx_ena_pre_o <=#1 0;
+		end
+		else begin
+			rx_adr_o <=#1 rx_adr_i;
+			rx_ena_o <=#1 rx_ena_pre_i;
+			fifo_addr_r_o <=#1 fifo_addr_r_i;
+			rx_ena_pre_o <=#1 rx_ena_pre_i;
+
+			rx_sop_o <=#1 0;
+			rx_eop_o <=#1 fifo_data_r[16] & rx_ena_pre_i;
+
+			if ((~rx_ena_pre_i) && (fifo_nItems_complete!=0) && rx_dav) begin
+				rx_ena_pre_o <=#1 1;
+				rx_dat_o <=#1 fifo_data_r[15:0];				
+				fifo_addr_r_o <=#1 fifo_addr_r_i + 1;
+				if (HEADER_FIELD) begin
+					rx_adr_o <=#1 fifo_data_r[7:0];
+					rx_ns_o <=#1 fifo_data_r[11:9];
+				end
+				else begin
+					rx_sop_o <=#1 1;
+					rx_ena_o <=#1 1;
+					rx_eop_o <=#1 fifo_data_r[16];
+				end
+			end
+
+			if (rx_eop_i & rx_ena_i) begin
+				rx_ena_o <=#1 0;
+				rx_ena_pre_o <=#1 0;
+			end
+			
+			if (rx_ena_pre_i) begin
+				if (~rx_ena_i) rx_sop_o <=#1 1;
+				rx_dat_o <=#1 fifo_data_r[15:0];
+				if (~rx_eop_i) fifo_addr_r_o <=#1 fifo_addr_r_i + 1;
+			end
+			
+			if (fifo_nItems_complete==0) begin
+				fifo_addr_r_o <=#1 fifo_addr_r_i;
+				rx_ena_pre_o <=#1 0;
+				rx_ena_o <=#1 0;
+			end
+		end
+	end
+
+
+
+endmodule
+
+// Triplicate with:
+// python tri.py < MAC_rx.v > MAC_rx_tri.v
+
+
+`timescale 1ns/1ns
+module MAC_rx_tri (rx_cmd_reset,rx_dat_1, rx_dat_2, rx_dat_3,  rx_ena_1, rx_ena_2, rx_ena_3, rx_ena_pre_1, rx_ena_pre_2, rx_ena_pre_3,  rx_eop_1, rx_eop_2, rx_eop_3, rx_err_1, rx_err_2, rx_err_3, rx_vr_1, rx_vr_2, rx_vr_3, rx_nr_1, rx_nr_2, rx_nr_3,
+			rx_sop_1, rx_sop_2, rx_sop_3, rx_adr_1, rx_adr_2, rx_adr_3, clk_1, clk_2, clk_3, rx_dav_1, rx_dav_2, rx_dav_3, resetb_1, resetb_2, resetb_3, rx_cmd_reset_1, rx_cmd_reset_2, rx_cmd_reset_3, rx_cmd_test_1, rx_cmd_test_2, rx_cmd_test_3,
+			phy_data_1, phy_data_2, phy_data_3, phy_dvalid_1, phy_dvalid_2, phy_dvalid_3, phy_dstrobe_1, phy_dstrobe_2, phy_dstrobe_3,  crc_zero_1, crc_zero_2, crc_zero_3,fifo_data_w_1, fifo_data_w_2, fifo_data_w_3,
+			fifo_data_r_1, fifo_data_r_2, fifo_data_r_3, fifo_addr_w_1, fifo_addr_w_2, fifo_addr_w_3, fifo_addr_r_1, fifo_addr_r_2, fifo_addr_r_3, fifo_w_1, fifo_w_2, fifo_w_3, cmd_busy_1, cmd_busy_2, cmd_busy_3, active_1, active_2, active_3,
+			rx_cmd_ua_1, rx_cmd_ua_2, rx_cmd_ua_3, rx_cmd_srej_1, rx_cmd_srej_2, rx_cmd_srej_3, tx_cmd_srej_1, tx_cmd_srej_2, tx_cmd_srej_3, rx_ns_1, rx_ns_2, rx_ns_3, rx_cmd_sabm_1, rx_cmd_sabm_2, rx_cmd_sabm_3,
+			disconnect_1, disconnect_2, disconnect_3, tx_cmd_ua_1, tx_cmd_ua_2, tx_cmd_ua_3, tx_cmd_reset_1, tx_cmd_reset_2, tx_cmd_reset_3 );
+
+	parameter ADDR_WIDTH = 12;
+	parameter HEADER_FIELD = 1; 
+	parameter MAX_LENGTH = 1<<ADDR_WIDTH;
+
+	output [15:0] rx_dat_1, rx_dat_2, rx_dat_3;
+	output rx_ena_1, rx_ena_2, rx_ena_3;
+
+	output  rx_eop_1, rx_eop_2, rx_eop_3;
+
+	output   rx_sop_1, rx_sop_2, rx_sop_3;
+
+	output    rx_ena_pre_1, rx_ena_pre_2, rx_ena_pre_3;
+
+	output      rx_err_1, rx_err_2, rx_err_3;
+	output [7:0] rx_adr_1, rx_adr_2, rx_adr_3;
+	output rx_cmd_reset_1, rx_cmd_reset_2, rx_cmd_reset_3,rx_cmd_reset;
+
+	output  rx_cmd_test_1, rx_cmd_test_2, rx_cmd_test_3;
+
+	output  rx_cmd_ua_1, rx_cmd_ua_2, rx_cmd_ua_3;
+
+	output  tx_cmd_ua_1, tx_cmd_ua_2, tx_cmd_ua_3;
+
+	output   rx_cmd_sabm_1, rx_cmd_sabm_2, rx_cmd_sabm_3;
+	output [6:0] rx_cmd_srej_1, rx_cmd_srej_2, rx_cmd_srej_3;
+	output [6:0] tx_cmd_srej_1, tx_cmd_srej_2, tx_cmd_srej_3;
+	input phy_dstrobe_1, phy_dstrobe_2, phy_dstrobe_3;
+	output fifo_w_1, fifo_w_2, fifo_w_3;
+	output [16:0] fifo_data_w_1, fifo_data_w_2, fifo_data_w_3;
+	output [ADDR_WIDTH-1:0] fifo_addr_r_1, fifo_addr_r_2, fifo_addr_r_3;
+
+	output [ADDR_WIDTH-1:0]  fifo_addr_w_1, fifo_addr_w_2, fifo_addr_w_3;
+	output [2:0] rx_vr_1, rx_vr_2, rx_vr_3;
+
+	output [2:0] rx_nr_1, rx_nr_2, rx_nr_3;
+
+	output [2:0]  rx_ns_1, rx_ns_2, rx_ns_3;
+
+	input disconnect_1, disconnect_2, disconnect_3;
+
+	input  tx_cmd_reset_1, tx_cmd_reset_2, tx_cmd_reset_3;
+
+	input   active_1, active_2, active_3;
+	input clk_1, clk_2, clk_3;
+
+	input  rx_dav_1, rx_dav_2, rx_dav_3;
+	input resetb_1, resetb_2, resetb_3;
+	input [7:0] phy_data_1, phy_data_2, phy_data_3;
+	input phy_dvalid_1, phy_dvalid_2, phy_dvalid_3;
+	input crc_zero_1, crc_zero_2, crc_zero_3;
+
+	input  cmd_busy_1, cmd_busy_2, cmd_busy_3;
+	input [16:0] fifo_data_r_1, fifo_data_r_2, fifo_data_r_3;
+
+	wire [ADDR_WIDTH-1:0] fifo_addr_w_int_1, fifo_addr_w_int_2, fifo_addr_w_int_3;
+	wire phy_bytesel_1, phy_bytesel_2, phy_bytesel_3;
+	wire phy_dvalid_old_1, phy_dvalid_old_2, phy_dvalid_old_3;
+	wire [ADDR_WIDTH-1:0] fifo_addr_w_last_1, fifo_addr_w_last_2, fifo_addr_w_last_3;
+	wire [15:0] phy_data_old_1, phy_data_old_2, phy_data_old_3;
+	wire [7:0] phy_data_lowbyte_1, phy_data_lowbyte_2, phy_data_lowbyte_3;
+	wire [15:0] phy_data_old2_1, phy_data_old2_2, phy_data_old2_3;
+	wire rx_cmd_reset_1, rx_cmd_reset_2, rx_cmd_reset_3;
+	wire rx_cmd_test_1, rx_cmd_test_2, rx_cmd_test_3;
+	wire [2:0] rx_vr_1, rx_vr_2, rx_vr_3;
+	wire rx_cmd_sabm_1, rx_cmd_sabm_2, rx_cmd_sabm_3;
+	wire [6:0] tx_cmd_srej_1, tx_cmd_srej_2, tx_cmd_srej_3;
+	wire tx_cmd_ua_1, tx_cmd_ua_2, tx_cmd_ua_3;
+	wire overflow_1, overflow_2, overflow_3;
+	wire [6:0] rx_cmd_srej_1, rx_cmd_srej_2, rx_cmd_srej_3;
+	wire rx_cmd_ua_1, rx_cmd_ua_2, rx_cmd_ua_3;
+	wire [15:0] packet_length_1, packet_length_2, packet_length_3;
+	wire [7:0] header_1, header_2, header_3;
+	wire [2:0] rx_nr_1, rx_nr_2, rx_nr_3;
+	wire [ADDR_WIDTH-1:0] fifo_addr_r_1, fifo_addr_r_2, fifo_addr_r_3;
+	wire rx_sop_1, rx_sop_2, rx_sop_3;
+	wire rx_ena_1, rx_ena_2, rx_ena_3;
+	wire [7:0] rx_adr_1, rx_adr_2, rx_adr_3;
+	wire rx_ena_pre_1, rx_ena_pre_2, rx_ena_pre_3;
+	wire rx_eop_1, rx_eop_2, rx_eop_3;
+	wire [15:0] rx_dat_1, rx_dat_2, rx_dat_3;
+	wire [2:0] rx_ns_1, rx_ns_2, rx_ns_3;
+	wire [ADDR_WIDTH-1:0] fifo_addr_w_int;
+	wire phy_bytesel;
+	wire phy_dvalid_old;
+	wire [ADDR_WIDTH-1:0] fifo_addr_w_last;
+	wire [15:0] phy_data_old;
+	wire [7:0] phy_data_lowbyte;
+	wire [15:0] phy_data_old2;
+	wire rx_cmd_reset;
+	wire rx_cmd_test;
+	wire [2:0] rx_vr;
+	wire rx_cmd_sabm;
+	wire [6:0] tx_cmd_srej;
+	wire tx_cmd_ua;
+	wire overflow;
+	wire [6:0] rx_cmd_srej;
+	wire rx_cmd_ua;
+	wire [15:0] packet_length;
+	wire [7:0] header;
+	wire [2:0] rx_nr;
+	wire [ADDR_WIDTH-1:0] fifo_addr_r;
+	wire rx_sop;
+	wire rx_ena;
+	wire [7:0] rx_adr;
+	wire rx_ena_pre;
+	wire rx_eop;
+	wire [15:0] rx_dat;
+	wire [2:0] rx_ns;
+
+	MAC_rx_iostate #(.ADDR_WIDTH(ADDR_WIDTH), .HEADER_FIELD(HEADER_FIELD), .MAX_LENGTH(MAX_LENGTH) ) MAC_rx_iostate_1 (.rx_dat_i(rx_dat_1), .rx_dat_o(rx_dat_2),  .rx_ena_i(rx_ena_1), .rx_ena_o(rx_ena_2), .rx_ena_pre_i(rx_ena_pre_1), .rx_ena_pre_o(rx_ena_pre_2),  .rx_eop_i(rx_eop_1), .rx_eop_o(rx_eop_2), .rx_err(rx_err_1), .rx_vr_i(rx_vr_1), .rx_vr_o(rx_vr_2), .rx_nr_i(rx_nr_1), .rx_nr_o(rx_nr_2),
+			.rx_sop_i(rx_sop_1), .rx_sop_o(rx_sop_2), .rx_adr_i(rx_adr_1), .rx_adr_o(rx_adr_2), .clk(clk_1), .rx_dav(rx_dav_1), .resetb(resetb_1), .rx_cmd_reset_i(rx_cmd_reset_1), .rx_cmd_reset_o(rx_cmd_reset_2), .rx_cmd_test_i(rx_cmd_test_1), .rx_cmd_test_o(rx_cmd_test_2),
+			.phy_data(phy_data_1), .phy_dvalid(phy_dvalid_1), .phy_dstrobe(phy_dstrobe_1),  .crc_zero(crc_zero_1),.fifo_data_w(fifo_data_w_1),
+			.fifo_data_r(fifo_data_r_1), .fifo_addr_w(fifo_addr_w_1), .fifo_addr_r_i(fifo_addr_r_1), .fifo_addr_r_o(fifo_addr_r_2), .fifo_w(fifo_w_1), .cmd_busy(cmd_busy_1), .active(active_1),
+			.rx_cmd_ua_i(rx_cmd_ua_1), .rx_cmd_ua_o(rx_cmd_ua_2), .rx_cmd_srej_i(rx_cmd_srej_1), .rx_cmd_srej_o(rx_cmd_srej_2), .tx_cmd_srej_i(tx_cmd_srej_1), .tx_cmd_srej_o(tx_cmd_srej_2), .rx_ns_i(rx_ns_1), .rx_ns_o(rx_ns_2), .rx_cmd_sabm_i(rx_cmd_sabm_1), .rx_cmd_sabm_o(rx_cmd_sabm_2),
+			.disconnect(disconnect_1), .tx_cmd_ua_i(tx_cmd_ua_1), .tx_cmd_ua_o(tx_cmd_ua_2), .tx_cmd_reset(tx_cmd_reset_1), .fifo_addr_w_int_i(fifo_addr_w_int_1), .fifo_addr_w_int_o(fifo_addr_w_int_2), .phy_bytesel_i(phy_bytesel_1), .phy_bytesel_o(phy_bytesel_2), .phy_dvalid_old_i(phy_dvalid_old_1), .phy_dvalid_old_o(phy_dvalid_old_2), .fifo_addr_w_last_i(fifo_addr_w_last_1), .fifo_addr_w_last_o(fifo_addr_w_last_2), .phy_data_old_i(phy_data_old_1), .phy_data_old_o(phy_data_old_2), .phy_data_lowbyte_i(phy_data_lowbyte_1), .phy_data_lowbyte_o(phy_data_lowbyte_2), .phy_data_old2_i(phy_data_old2_1), .phy_data_old2_o(phy_data_old2_2), .overflow_i(overflow_1), .overflow_o(overflow_2), .packet_length_i(packet_length_1), .packet_length_o(packet_length_2), .header_i(header_1), .header_o(header_2));
+
+	MAC_rx_iostate #(.ADDR_WIDTH(ADDR_WIDTH), .HEADER_FIELD(HEADER_FIELD), .MAX_LENGTH(MAX_LENGTH) ) MAC_rx_iostate_2 (.rx_dat_i(rx_dat_2), .rx_dat_o(rx_dat_3),  .rx_ena_i(rx_ena_2), .rx_ena_o(rx_ena_3), .rx_ena_pre_i(rx_ena_pre_2), .rx_ena_pre_o(rx_ena_pre_3),  .rx_eop_i(rx_eop_2), .rx_eop_o(rx_eop_3), .rx_err(rx_err_2), .rx_vr_i(rx_vr_2), .rx_vr_o(rx_vr_3), .rx_nr_i(rx_nr_2), .rx_nr_o(rx_nr_3),
+			.rx_sop_i(rx_sop_2), .rx_sop_o(rx_sop_3), .rx_adr_i(rx_adr_2), .rx_adr_o(rx_adr_3), .clk(clk_2), .rx_dav(rx_dav_2), .resetb(resetb_2), .rx_cmd_reset_i(rx_cmd_reset_2), .rx_cmd_reset_o(rx_cmd_reset_3), .rx_cmd_test_i(rx_cmd_test_2), .rx_cmd_test_o(rx_cmd_test_3),
+			.phy_data(phy_data_2), .phy_dvalid(phy_dvalid_2), .phy_dstrobe(phy_dstrobe_2),  .crc_zero(crc_zero_2),.fifo_data_w(fifo_data_w_2),
+			.fifo_data_r(fifo_data_r_2), .fifo_addr_w(fifo_addr_w_2), .fifo_addr_r_i(fifo_addr_r_2), .fifo_addr_r_o(fifo_addr_r_3), .fifo_w(fifo_w_2), .cmd_busy(cmd_busy_2), .active(active_2),
+			.rx_cmd_ua_i(rx_cmd_ua_2), .rx_cmd_ua_o(rx_cmd_ua_3), .rx_cmd_srej_i(rx_cmd_srej_2), .rx_cmd_srej_o(rx_cmd_srej_3), .tx_cmd_srej_i(tx_cmd_srej_2), .tx_cmd_srej_o(tx_cmd_srej_3), .rx_ns_i(rx_ns_2), .rx_ns_o(rx_ns_3), .rx_cmd_sabm_i(rx_cmd_sabm_2), .rx_cmd_sabm_o(rx_cmd_sabm_3),
+			.disconnect(disconnect_2), .tx_cmd_ua_i(tx_cmd_ua_2), .tx_cmd_ua_o(tx_cmd_ua_3), .tx_cmd_reset(tx_cmd_reset_2), .fifo_addr_w_int_i(fifo_addr_w_int_2), .fifo_addr_w_int_o(fifo_addr_w_int_3), .phy_bytesel_i(phy_bytesel_2), .phy_bytesel_o(phy_bytesel_3), .phy_dvalid_old_i(phy_dvalid_old_2), .phy_dvalid_old_o(phy_dvalid_old_3), .fifo_addr_w_last_i(fifo_addr_w_last_2), .fifo_addr_w_last_o(fifo_addr_w_last_3), .phy_data_old_i(phy_data_old_2), .phy_data_old_o(phy_data_old_3), .phy_data_lowbyte_i(phy_data_lowbyte_2), .phy_data_lowbyte_o(phy_data_lowbyte_3), .phy_data_old2_i(phy_data_old2_2), .phy_data_old2_o(phy_data_old2_3), .overflow_i(overflow_2), .overflow_o(overflow_3), .packet_length_i(packet_length_2), .packet_length_o(packet_length_3), .header_i(header_2), .header_o(header_3));
+
+	MAC_rx_iostate #(.ADDR_WIDTH(ADDR_WIDTH), .HEADER_FIELD(HEADER_FIELD), .MAX_LENGTH(MAX_LENGTH) ) MAC_rx_iostate_3 (.rx_dat_i(rx_dat_3), .rx_dat_o(rx_dat),  .rx_ena_i(rx_ena_3), .rx_ena_o(rx_ena), .rx_ena_pre_i(rx_ena_pre_3), .rx_ena_pre_o(rx_ena_pre),  .rx_eop_i(rx_eop_3), .rx_eop_o(rx_eop), .rx_err(rx_err_3), .rx_vr_i(rx_vr_3), .rx_vr_o(rx_vr), .rx_nr_i(rx_nr_3), .rx_nr_o(rx_nr),
+			.rx_sop_i(rx_sop_3), .rx_sop_o(rx_sop), .rx_adr_i(rx_adr_3), .rx_adr_o(rx_adr), .clk(clk_3), .rx_dav(rx_dav_3), .resetb(resetb_3), .rx_cmd_reset_i(rx_cmd_reset_3), .rx_cmd_reset_o(rx_cmd_reset), .rx_cmd_test_i(rx_cmd_test_3), .rx_cmd_test_o(rx_cmd_test),
+			.phy_data(phy_data_3), .phy_dvalid(phy_dvalid_3), .phy_dstrobe(phy_dstrobe_3),  .crc_zero(crc_zero_3),.fifo_data_w(fifo_data_w_3),
+			.fifo_data_r(fifo_data_r_3), .fifo_addr_w(fifo_addr_w_3), .fifo_addr_r_i(fifo_addr_r_3), .fifo_addr_r_o(fifo_addr_r), .fifo_w(fifo_w_3), .cmd_busy(cmd_busy_3), .active(active_3),
+			.rx_cmd_ua_i(rx_cmd_ua_3), .rx_cmd_ua_o(rx_cmd_ua), .rx_cmd_srej_i(rx_cmd_srej_3), .rx_cmd_srej_o(rx_cmd_srej), .tx_cmd_srej_i(tx_cmd_srej_3), .tx_cmd_srej_o(tx_cmd_srej), .rx_ns_i(rx_ns_3), .rx_ns_o(rx_ns), .rx_cmd_sabm_i(rx_cmd_sabm_3), .rx_cmd_sabm_o(rx_cmd_sabm),
+			.disconnect(disconnect_3), .tx_cmd_ua_i(tx_cmd_ua_3), .tx_cmd_ua_o(tx_cmd_ua), .tx_cmd_reset(tx_cmd_reset_3), .fifo_addr_w_int_i(fifo_addr_w_int_3), .fifo_addr_w_int_o(fifo_addr_w_int), .phy_bytesel_i(phy_bytesel_3), .phy_bytesel_o(phy_bytesel), .phy_dvalid_old_i(phy_dvalid_old_3), .phy_dvalid_old_o(phy_dvalid_old), .fifo_addr_w_last_i(fifo_addr_w_last_3), .fifo_addr_w_last_o(fifo_addr_w_last), .phy_data_old_i(phy_data_old_3), .phy_data_old_o(phy_data_old), .phy_data_lowbyte_i(phy_data_lowbyte_3), .phy_data_lowbyte_o(phy_data_lowbyte), .phy_data_old2_i(phy_data_old2_3), .phy_data_old2_o(phy_data_old2), .overflow_i(overflow_3), .overflow_o(overflow), .packet_length_i(packet_length_3), .packet_length_o(packet_length), .header_i(header_3), .header_o(header));
+
+	majority_voter #(.WIDTH(126+ADDR_WIDTH-1+ADDR_WIDTH-1+ADDR_WIDTH-1)) mv (
+		.in1({fifo_addr_w_int_2, phy_bytesel_2, phy_dvalid_old_2, fifo_addr_w_last_2, phy_data_old_2, phy_data_lowbyte_2, phy_data_old2_2, rx_cmd_reset_2, rx_cmd_test_2, rx_vr_2, rx_cmd_sabm_2, tx_cmd_srej_2, tx_cmd_ua_2, overflow_2, rx_cmd_srej_2, rx_cmd_ua_2, packet_length_2, header_2, rx_nr_2, fifo_addr_r_2, rx_sop_2, rx_ena_2, rx_adr_2, rx_ena_pre_2, rx_eop_2, rx_dat_2, rx_ns_2}),
+		.in2({fifo_addr_w_int_3, phy_bytesel_3, phy_dvalid_old_3, fifo_addr_w_last_3, phy_data_old_3, phy_data_lowbyte_3, phy_data_old2_3, rx_cmd_reset_3, rx_cmd_test_3, rx_vr_3, rx_cmd_sabm_3, tx_cmd_srej_3, tx_cmd_ua_3, overflow_3, rx_cmd_srej_3, rx_cmd_ua_3, packet_length_3, header_3, rx_nr_3, fifo_addr_r_3, rx_sop_3, rx_ena_3, rx_adr_3, rx_ena_pre_3, rx_eop_3, rx_dat_3, rx_ns_3}),
+		.in3({fifo_addr_w_int, phy_bytesel, phy_dvalid_old, fifo_addr_w_last, phy_data_old, phy_data_lowbyte, phy_data_old2, rx_cmd_reset, rx_cmd_test, rx_vr, rx_cmd_sabm, tx_cmd_srej, tx_cmd_ua, overflow, rx_cmd_srej, rx_cmd_ua, packet_length, header, rx_nr, fifo_addr_r, rx_sop, rx_ena, rx_adr, rx_ena_pre, rx_eop, rx_dat, rx_ns}),
+		.out({fifo_addr_w_int_1, phy_bytesel_1, phy_dvalid_old_1, fifo_addr_w_last_1, phy_data_old_1, phy_data_lowbyte_1, phy_data_old2_1, rx_cmd_reset_1, rx_cmd_test_1, rx_vr_1, rx_cmd_sabm_1, tx_cmd_srej_1, tx_cmd_ua_1, overflow_1, rx_cmd_srej_1, rx_cmd_ua_1, packet_length_1, header_1, rx_nr_1, fifo_addr_r_1, rx_sop_1, rx_ena_1, rx_adr_1, rx_ena_pre_1, rx_eop_1, rx_dat_1, rx_ns_1}),
+		.err()
+	);
+endmodule
+
+// Triplicate with:
+// python tri.py < MAC_rx.v > MAC_rx_tri.v
+
+// missing: rx_dstrobe_o <=#1 rx_dstrobe_i;
+module PHY_HDLC_rx_iostate (rx_data_i, rx_data_o, rx_sdr, rx_dvalid_i, rx_dvalid_o, rx_dstrobe_i, rx_dstrobe_o, rx_clk, resetb, rx_reg_i, rx_reg_o, ones_count_i, ones_count_o, bit_count_i, bit_count_o, start_i, start_o);
+
+	output [7:0] rx_data_o;
+	output [8:0] rx_reg_o;
+	input [7:0] rx_data_i;
+	input [1:0] rx_sdr;
+	output start_o;
+	output rx_dvalid_o;
+	output  rx_dstrobe_o;
+	input  rx_dstrobe_i;
+	
+	input start_i;
+	
+	input resetb;
+	output [3:0] bit_count_o;
+	output [2:0] ones_count_o;
+	input rx_clk;
+	input rx_dvalid_i;
+
+	input [3:0] bit_count_i;
+	input [2:0] ones_count_i;
+	input [8:0] rx_reg_i;
+	reg [8:0] rx_reg_o;
+	reg [7:0] rx_data_o;
+
+	reg [2:0] ones_count_o;
+	reg [3:0] bit_count_o;
+	reg rx_dvalid_o;
+
+	reg  rx_dstrobe_o;
+	reg start_o;
+	always @(posedge rx_clk or negedge resetb) begin
+		if (~resetb) begin
+			//rx_reg_o <=#1 0;
+			//ones_count_o <=#1 0;
+			//bit_count_o <=#1 0;
+			//rx_dvalid_o <=#1 0;
+			//rx_dstrobe_o <=#1 0;
+			//start_o <=#1 0;
+			//rx_dvalid_o <=#1 0;
+			//rx_data_o <=#1 0;
+		end
+		else begin
+			rx_data_o <=#1 rx_data_i;
+			start_o <=#1 start_i;
+			rx_dvalid_o <=#1 rx_dvalid_i;
+			bit_count_o <=#1 bit_count_i;
+			ones_count_o <=#1 ones_count_i;
+			rx_reg_o <=#1 rx_reg_i;
+		
+			rx_dstrobe_o <=#1 0;
+			if (rx_dvalid_i) start_o <=#1 0;
+			rx_reg_o <=#1 {rx_sdr[0], rx_sdr[1], rx_reg_i[8:2]};
+			bit_count_o <=#1 bit_count_i + 2;
+			if ((bit_count_i==8) && rx_dvalid_i) begin
+				rx_data_o <=#1 rx_reg_i[8:1];
+				bit_count_o <=#1 2;
+				rx_dstrobe_o <=#1 1;
+			end
+			if ((bit_count_i==9) && rx_dvalid_i) begin
+				rx_data_o <=#1 rx_reg_i[7:0];
+				bit_count_o <=#1 3;
+				rx_dstrobe_o <=#1 1;
+			end
+
+
+			if ((ones_count_i==4) && (~rx_sdr[0]) && (rx_sdr[1])) begin
+				rx_reg_o <=#1 {rx_sdr[1], rx_reg_i[8:1]};
+				bit_count_o <=#1 bit_count_i + 1;
+				if (bit_count_i==8) begin
+					bit_count_o <=#1 1;
+					rx_data_o <=#1 rx_reg_i[8:1];
+					rx_dstrobe_o <=#1 1;
+				end
+				if (bit_count_i==9) begin
+					bit_count_o <=#1 2;
+					rx_data_o <=#1 rx_reg_i[7:0];
+					rx_dstrobe_o <=#1 1;
+				end
+			end
+
+			if ((ones_count_i==5) && (~rx_sdr[1])) begin
+				rx_reg_o <=#1 {rx_sdr[0], rx_reg_i[8:1]};
+				bit_count_o <=#1 bit_count_i + 1;
+				if (bit_count_i==8) begin
+					bit_count_o <=#1 1;
+					rx_data_o <=#1 rx_reg_i[8:1];
+					rx_dstrobe_o <=#1 1;
+				end
+				if (bit_count_i==9) begin
+					bit_count_o <=#1 2;
+					rx_data_o <=#1 rx_reg_i[7:0];
+					rx_dstrobe_o <=#1 1;
+				end
+			end
+			
+			if (rx_sdr[0] && rx_sdr[1]) begin
+				if (ones_count_i<6) ones_count_o <=#1 ones_count_i + 2;
+				if (ones_count_i==6) ones_count_o <=#1 7;
+			end
+			else begin
+				if (start_i) rx_dvalid_o <=#1 1;
+				if (~rx_sdr[0]) ones_count_o <=#1 0;
+				else ones_count_o <=#1 1;
+			end
+			
+			
+			if ((ones_count_i==5) && (~rx_sdr[0]) && (rx_sdr[1])) begin
+				rx_dvalid_o <=#1 0;
+				bit_count_o<=#1 0;
+				start_o <=#1 1;
+			end
+
+			if (ones_count_i==6) begin
+				rx_dvalid_o <=#1 0;
+				bit_count_o<=#1 1;
+				if (~rx_sdr[1]) start_o <=#1 1;
+				else start_o <=#1 0;
+			end
+
+			if (ones_count_i==7) begin
+				rx_dvalid_o <=#1 0;
+				bit_count_o<=#1 0;
+				start_o<=#1 0;
+			end
+
+		end
+	end
+	
+
+endmodule
+
+module PHY_HDLC_rx_tri (rx_data_1, rx_data_2, rx_data_3, rx_sdr_1, rx_sdr_2, rx_sdr_3, rx_dvalid_1, rx_dvalid_2, rx_dvalid_3, rx_dstrobe_1, rx_dstrobe_2, rx_dstrobe_3, rx_clk_1, rx_clk_2, rx_clk_3, resetb_1, resetb_2, resetb_3);
+
+	output [7:0] rx_data_1, rx_data_2, rx_data_3;
+	input rx_clk_1, rx_clk_2, rx_clk_3;
+	input [1:0] rx_sdr_1, rx_sdr_2, rx_sdr_3;
+	input resetb_1, resetb_2, resetb_3;
+	output rx_dvalid_1, rx_dvalid_2, rx_dvalid_3;
+
+	output  rx_dstrobe_1, rx_dstrobe_2, rx_dstrobe_3;
+
+	wire [8:0] rx_reg_1, rx_reg_2, rx_reg_3;
+	wire [2:0] ones_count_1, ones_count_2, ones_count_3;
+	wire [3:0] bit_count_1, bit_count_2, bit_count_3;
+	wire rx_dvalid_1, rx_dvalid_2, rx_dvalid_3;
+	wire rx_dstrobe_1, rx_dstrobe_2, rx_dstrobe_3;
+	wire start_1, start_2, start_3;
+	wire [7:0] rx_data_1, rx_data_2, rx_data_3;
+	wire [8:0] rx_reg;
+	wire [2:0] ones_count;
+	wire [3:0] bit_count;
+	wire rx_dvalid;
+	wire rx_dstrobe;
+	wire start;
+	wire [7:0] rx_data;
+	PHY_HDLC_rx_iostate PHY_HDLC_rx_iostate_1   (.rx_data_i(rx_data_1), .rx_data_o(rx_data_2), .rx_sdr(rx_sdr_1), .rx_dvalid_i(rx_dvalid_1), .rx_dvalid_o(rx_dvalid_2), .rx_dstrobe_i(rx_dstrobe_1), .rx_dstrobe_o(rx_dstrobe_2), .rx_clk(rx_clk_1), .resetb(resetb_1), .rx_reg_i(rx_reg_1), .rx_reg_o(rx_reg_2), .ones_count_i(ones_count_1), .ones_count_o(ones_count_2), .bit_count_i(bit_count_1), .bit_count_o(bit_count_2), .start_i(start_1), .start_o(start_2));
+	PHY_HDLC_rx_iostate PHY_HDLC_rx_iostate_2   (.rx_data_i(rx_data_2), .rx_data_o(rx_data_3), .rx_sdr(rx_sdr_2), .rx_dvalid_i(rx_dvalid_2), .rx_dvalid_o(rx_dvalid_3), .rx_dstrobe_i(rx_dstrobe_2), .rx_dstrobe_o(rx_dstrobe_3), .rx_clk(rx_clk_2), .resetb(resetb_2), .rx_reg_i(rx_reg_2), .rx_reg_o(rx_reg_3), .ones_count_i(ones_count_2), .ones_count_o(ones_count_3), .bit_count_i(bit_count_2), .bit_count_o(bit_count_3), .start_i(start_2), .start_o(start_3));
+	PHY_HDLC_rx_iostate PHY_HDLC_rx_iostate_3   (.rx_data_i(rx_data_3), .rx_data_o(rx_data), .rx_sdr(rx_sdr_3), .rx_dvalid_i(rx_dvalid_3), .rx_dvalid_o(rx_dvalid), .rx_dstrobe_i(rx_dstrobe_3), .rx_dstrobe_o(rx_dstrobe), .rx_clk(rx_clk_3), .resetb(resetb_3), .rx_reg_i(rx_reg_3), .rx_reg_o(rx_reg), .ones_count_i(ones_count_3), .ones_count_o(ones_count), .bit_count_i(bit_count_3), .bit_count_o(bit_count), .start_i(start_3), .start_o(start));
+
+	majority_voter #(.WIDTH(27)) mv (
+		.in1({rx_reg_2, ones_count_2, bit_count_2, rx_dvalid_2, rx_dstrobe_2, start_2, rx_data_2}),
+		.in2({rx_reg_3, ones_count_3, bit_count_3, rx_dvalid_3, rx_dstrobe_3, start_3, rx_data_3}),
+		.in3({rx_reg, ones_count, bit_count, rx_dvalid, rx_dstrobe, start, rx_data}),
+		.out({rx_reg_1, ones_count_1, bit_count_1, rx_dvalid_1, rx_dstrobe_1, start_1, rx_data_1}),
+		.err()
+	);
+endmodule
+
+// missing: tx_sdr_o <=#1 tx_sdr_i;
+// missing: tx_dstrobe_o <=#1 tx_dstrobe_i;
+module PHY_HDLC_tx_iostate (tx_data, tx_dvalid, tx_dstrobe_i, tx_dstrobe_o, tx_sdr_i, tx_sdr_o, rx_clk, resetb, tx_reg_i, tx_reg_o, ones_count_i, ones_count_o, bit_count_i, bit_count_o, state_i, state_o, tx_dvalid_internal_i, tx_dvalid_internal_o);
+
+	input [7:0] tx_data;
+	input tx_dstrobe_i;
+	input tx_dvalid_internal_i;
+	
+	input resetb;
+	
+	input [1:0] state_i;
+	input [3:0] bit_count_i;
+	input [2:0] ones_count_i;
+	input [8:0] tx_reg_i;
+	
+	input rx_clk;
+	input tx_dvalid;
+	output [1:0] tx_sdr_o;
+	output [8:0] tx_reg_o;
+	input [1:0] tx_sdr_i;
+	output tx_dvalid_internal_o;
+	output tx_dstrobe_o;
+	output [1:0] state_o;
+	output [3:0] bit_count_o;
+	output [2:0] ones_count_o;
+	reg [8:0] tx_reg_o;
+	reg [2:0] ones_count_o;
+	reg [3:0] bit_count_o;
+	reg [1:0] state_o;
+	reg [1:0] tx_sdr_o;
+	reg tx_dstrobe_o;
+	reg tx_dvalid_internal_o;
+	parameter [1:0] IDLE = 2'd0,
+					START= 2'd1,
+					TX   = 2'd2,
+					END  = 2'd3;
+	
+	always @(posedge rx_clk or negedge resetb) begin
+		if (~resetb) begin
+			tx_reg_o<=#1 9'h1ff;
+			tx_sdr_o[0] <=#1 1;
+			tx_sdr_o[1] <=#1 1;
+			ones_count_o <=#1 0;
+			bit_count_o <=#1 0;
+			state_o <=#1 0;
+			tx_dstrobe_o <=#1 0;
+		end
+		else begin
+			state_o <=#1 state_i;
+			bit_count_o <=#1 bit_count_i;
+			ones_count_o <=#1 ones_count_i;
+			tx_sdr_o[1] <=#1 tx_sdr_i[1];
+			tx_sdr_o[0] <=#1 tx_sdr_i[0];
+			tx_reg_o <=#1 tx_reg_i;
+			tx_dvalid_internal_o <=#1 tx_dvalid_internal_i;
+
+			tx_dstrobe_o <=#1 0;
+		
+			if (tx_reg_i[0] && tx_reg_i[1]) begin
+				if (ones_count_i<6) ones_count_o <=#1 ones_count_i + 2;
+				if (ones_count_i==6) ones_count_o <=#1 7;
+			end
+			else begin
+				if (~tx_reg_i[1]) ones_count_o <=#1 0;
+				else ones_count_o <=#1 1;
+			end
+			
+			if (~tx_dvalid) tx_dvalid_internal_o<=#1 0;
+
+			case (state_i) // synopsys parallel_case
+				//IDLE state is default
+				START: begin
+					bit_count_o <=#1 bit_count_i - 2;
+					tx_reg_o <=#1 tx_reg_i>>2;
+					tx_sdr_o[0] <=#1 tx_reg_i[1];
+					tx_sdr_o[1] <=#1 tx_reg_i[0];
+					if ((bit_count_i ==2) || (bit_count_i ==1)) begin
+						state_o <=#1 TX;
+						tx_reg_o[7:0] <=#1 tx_data;
+						tx_dstrobe_o <=#1 1;
+						bit_count_o<=#1 8;
+					end
+					
+					if (~tx_dvalid) state_o <=#1 IDLE;
+				end
+			
+				TX: begin				
+					tx_reg_o <=#1 tx_reg_i>>2;
+					tx_sdr_o[0] <=#1 tx_reg_i[1];
+					tx_sdr_o[1] <=#1 tx_reg_i[0];
+					bit_count_o <=#1 bit_count_i - 2;
+					
+					if ((ones_count_i!=5) && ((ones_count_i!=4) || (~tx_reg_i[0]))) begin
+						if (bit_count_i==3) begin
+							if (tx_dvalid_internal_i & tx_dvalid) begin
+								tx_dstrobe_o <=#1 1;
+								bit_count_o <=#1 9;
+								tx_reg_o[8:1] <=#1 tx_data;
+							end
+							else begin
+								bit_count_o <=#1 1;
+								tx_reg_o[8:1] <=#1 'h7e;
+							end
+						end
+						if (bit_count_i==2) begin
+							bit_count_o <=#1 8;
+							if (tx_dvalid_internal_i & tx_dvalid) begin
+								tx_dstrobe_o <=#1 1;
+								tx_reg_o[7:0] <=#1 tx_data;
+							end
+							else begin
+								tx_reg_o[8:0] <=#1 'b101111110;
+								state_o <=#1 END;
+							end
+						end
+					end
+
+					
+					if ((ones_count_i==4) && tx_reg_i[0]) begin
+						tx_sdr_o[0] <=#1 0;
+						tx_sdr_o[1] <=#1 1;
+						tx_reg_o <=#1 tx_reg_i>>1;
+						ones_count_o <=#1 0;
+						bit_count_o <=#1 bit_count_i - 1;
+						if (bit_count_i==2) begin
+							bit_count_o <=#1 9;
+							if (tx_dvalid_internal_i & tx_dvalid) begin
+								tx_reg_o[8:1] <=#1 tx_data;
+								tx_dstrobe_o <=#1 1;
+							end
+							else begin
+								tx_reg_o[8:1] <=#1 'h7e;
+								state_o <=#1 END;
+							end
+						end
+					end
+					
+					if (ones_count_i==5) begin
+						tx_sdr_o[0] <=#1 tx_reg_i[0];
+						tx_sdr_o[1] <=#1 0;
+						tx_reg_o <=#1 tx_reg_i>>1;
+						ones_count_o <=#1 tx_reg_i[0];
+						bit_count_o <=#1 bit_count_i - 1;
+						if (bit_count_i==2) begin
+							bit_count_o <=#1 9;
+							if (tx_dvalid_internal_i & tx_dvalid) begin
+								tx_dstrobe_o <=#1 1;
+								tx_reg_o[8:1] <=#1 tx_data;
+							end
+							else begin
+								tx_reg_o[8:1] <=#1 'h7e;
+								state_o <=#1 END;
+							end
+						end
+					end
+					
+					if (bit_count_i==1) begin
+						state_o <=#1 END;
+						bit_count_o <=#1 7;
+					end
+				end
+				
+				END: begin
+					tx_reg_o <=#1 tx_reg_i>>2;
+					tx_sdr_o[0] <=#1 tx_reg_i[1];
+					tx_sdr_o[1] <=#1 tx_reg_i[0];
+					bit_count_o <=#1 bit_count_i - 2;
+					if ((bit_count_i==0) || (bit_count_i==1)) state_o <=#1 IDLE;
+
+					if ((ones_count_i==5) && (tx_reg_i[0])) begin
+						tx_sdr_o[0]<=#1 0;
+						if (tx_dvalid) begin
+							tx_dvalid_internal_o<=#1 1;
+							state_o <=#1 TX;
+							tx_reg_o[7:0] <=#1 tx_data;
+							tx_dstrobe_o <=#1 1;
+							bit_count_o<=#1 8;
+						end
+						else begin
+							tx_reg_o<=#1 'h7f;
+							state_o <=#1 IDLE;
+						end
+					end
+
+					if (ones_count_i==6) begin
+						tx_sdr_o[1]<=#1 0;
+						if (tx_dvalid) begin
+							tx_dvalid_internal_o<=#1 1;
+							state_o <=#1 TX;
+							tx_reg_o[6:0] <=#1 tx_data[7:1];
+							tx_sdr_o[0] <=#1 tx_data[0];
+							tx_dstrobe_o <=#1 1;
+							bit_count_o<=#1 7;
+							ones_count_o <=#1 tx_data[0];
+						end
+						else begin
+							tx_reg_o <=#1 'h7f;
+							tx_sdr_o[0]<=#1 1;
+							state_o <=#1 IDLE;
+						end
+					end
+					
+				end
+				
+				default: begin
+					//tx_sdr_o[1]<=#1 1;
+					//tx_sdr_o[0]<=#1 1;
+					tx_reg_o <=#1 tx_reg_i>>2;
+					tx_sdr_o[0] <=#1 tx_reg_i[1];
+					tx_sdr_o[1] <=#1 tx_reg_i[0];
+					bit_count_o <=#1 8;
+					tx_dvalid_internal_o <=#1 0;
+					if ((~tx_reg_i[1]) || (~tx_reg_i[0]))begin
+						if (tx_dvalid) begin
+							tx_sdr_o <=#1 2'b11;
+							tx_reg_o[7:0] <=#1 'h7e;
+							bit_count_o <=#1 8;
+							state_o <=#1 START;
+							tx_dvalid_internal_o<=#1 1;
+						end
+						else tx_reg_o<=#1 'h7f;
+					end
+				end
+
+
+			endcase
+
+		end
+	end
+
+
+endmodule
+
+module PHY_HDLC_tx_tri (tx_data_1, tx_data_2, tx_data_3, tx_dvalid_1, tx_dvalid_2, tx_dvalid_3, tx_dstrobe_1, tx_dstrobe_2, tx_dstrobe_3, tx_sdr_1, tx_sdr_2, tx_sdr_3, rx_clk_1, rx_clk_2, rx_clk_3, resetb_1, resetb_2, resetb_3);
+
+	input [7:0] tx_data_1, tx_data_2, tx_data_3;
+	input rx_clk_1, rx_clk_2, rx_clk_3;
+	input tx_dvalid_1, tx_dvalid_2, tx_dvalid_3;
+	output [1:0] tx_sdr_1, tx_sdr_2, tx_sdr_3;
+	output tx_dstrobe_1, tx_dstrobe_2, tx_dstrobe_3;
+	input resetb_1, resetb_2, resetb_3;
+
+	wire [8:0] tx_reg_1, tx_reg_2, tx_reg_3;
+	wire [2:0] ones_count_1, ones_count_2, ones_count_3;
+	wire [3:0] bit_count_1, bit_count_2, bit_count_3;
+	wire [1:0] state_1, state_2, state_3;
+	wire tx_dstrobe_1, tx_dstrobe_2, tx_dstrobe_3;
+	wire tx_dvalid_internal_1, tx_dvalid_internal_2, tx_dvalid_internal_3;
+	wire [1:0] tx_sdr_1, tx_sdr_2, tx_sdr_3;
+	wire [8:0] tx_reg;
+	wire [2:0] ones_count;
+	wire [3:0] bit_count;
+	wire [1:0] state;
+	wire tx_dstrobe;
+	wire tx_dvalid_internal;
+	wire [1:0] tx_sdr;
+	PHY_HDLC_tx_iostate PHY_HDLC_tx_iostate_1   (.tx_data(tx_data_1), .tx_dvalid(tx_dvalid_1), .tx_dstrobe_i(tx_dstrobe_1), .tx_dstrobe_o(tx_dstrobe_2), .tx_sdr_i(tx_sdr_1), .tx_sdr_o(tx_sdr_2), .rx_clk(rx_clk_1), .resetb(resetb_1), .tx_reg_i(tx_reg_1), .tx_reg_o(tx_reg_2), .ones_count_i(ones_count_1), .ones_count_o(ones_count_2), .bit_count_i(bit_count_1), .bit_count_o(bit_count_2), .state_i(state_1), .state_o(state_2), .tx_dvalid_internal_i(tx_dvalid_internal_1), .tx_dvalid_internal_o(tx_dvalid_internal_2));
+	PHY_HDLC_tx_iostate PHY_HDLC_tx_iostate_2   (.tx_data(tx_data_2), .tx_dvalid(tx_dvalid_2), .tx_dstrobe_i(tx_dstrobe_2), .tx_dstrobe_o(tx_dstrobe_3), .tx_sdr_i(tx_sdr_2), .tx_sdr_o(tx_sdr_3), .rx_clk(rx_clk_2), .resetb(resetb_2), .tx_reg_i(tx_reg_2), .tx_reg_o(tx_reg_3), .ones_count_i(ones_count_2), .ones_count_o(ones_count_3), .bit_count_i(bit_count_2), .bit_count_o(bit_count_3), .state_i(state_2), .state_o(state_3), .tx_dvalid_internal_i(tx_dvalid_internal_2), .tx_dvalid_internal_o(tx_dvalid_internal_3));
+	PHY_HDLC_tx_iostate PHY_HDLC_tx_iostate_3   (.tx_data(tx_data_3), .tx_dvalid(tx_dvalid_3), .tx_dstrobe_i(tx_dstrobe_3), .tx_dstrobe_o(tx_dstrobe), .tx_sdr_i(tx_sdr_3), .tx_sdr_o(tx_sdr), .rx_clk(rx_clk_3), .resetb(resetb_3), .tx_reg_i(tx_reg_3), .tx_reg_o(tx_reg), .ones_count_i(ones_count_3), .ones_count_o(ones_count), .bit_count_i(bit_count_3), .bit_count_o(bit_count), .state_i(state_3), .state_o(state), .tx_dvalid_internal_i(tx_dvalid_internal_3), .tx_dvalid_internal_o(tx_dvalid_internal));
+
+	majority_voter #(.WIDTH(22)) mv (
+		.in1({tx_reg_2, ones_count_2, bit_count_2, state_2, tx_dstrobe_2, tx_dvalid_internal_2, tx_sdr_2}),
+		.in2({tx_reg_3, ones_count_3, bit_count_3, state_3, tx_dstrobe_3, tx_dvalid_internal_3, tx_sdr_3}),
+		.in3({tx_reg, ones_count, bit_count, state, tx_dstrobe, tx_dvalid_internal, tx_sdr}),
+		.out({tx_reg_1, ones_count_1, bit_count_1, state_1, tx_dstrobe_1, tx_dvalid_internal_1, tx_sdr_1}),
+		.err()
+	);
+endmodule
+
+//  Author: 	BONACINI Sandro, CERN EP/MIC
+//
+//  CRC Generator/Checker
+//  
+//  CRC is calculated right-shifting, the polynomial must therefore
+//  be reversed.
+//  The output crc is directly the crc register value. There is no
+//  inversion in between.
+//  Default parameters produce a CRC16-CCITT output.
+//  When checking, correct reception is signaled by a zero in the crc
+//  output.
+//
+//  Parameters:
+//
+//  CRC_WIDTH	    bit width of the crc output;
+//
+//  DATA_WIDTH	    bit width of the data input (must be at least 2);
+//  	    	    
+//  INIT_VAL	    initialization value of the crc register,
+//  	    	    suggested values are all-zeros and all-ones;
+//
+//  POLY    	    Polynomial (remeber to reverse it)
+//  	    	    i.e. CCITT 1021h has POLY = 'h8408.
+//
+/////////////////////////////////////////////////////////////////////
+
+
+`timescale 1ns/1ns
+module crc_iostate (d, init, reset_b, clk, d_valid, crc_o, crc_i);
+    // synopsys template
+
+    parameter CRC_WIDTH = 16;
+    parameter DATA_WIDTH= 16;
+    parameter INIT_VAL	= 'hffff;
+    parameter POLY  	= 'h8408;
+
+
+    // I/Os
+    
+    input   [(DATA_WIDTH-1): 0] d;
+    input   	    	    	init;
+    input   	    	    	d_valid;
+    input         	    	clk;
+    input         	    	reset_b;
+
+    output  [(CRC_WIDTH-1) : 0] crc_o;
+    input  [(CRC_WIDTH-1) : 0] crc_i;
+    
+    
+    // Output regs
+    
+    reg     [(CRC_WIDTH-1) : 0] crc_o;
+
+
+    // Internal wires & regs
+    
+    reg     [(CRC_WIDTH-1) : 0] next_crc;
+
+    
+    // Always statements
+    
+    always @(d or crc_i or init) begin
+    	next_crc = crc_calc(crc_i, d);
+		if (init) next_crc = crc_calc(INIT_VAL, d);
+    end
+    
+    
+    // synopsys async_set_reset "reset_b"
+    always @ (posedge clk or negedge reset_b) begin
+		if (~reset_b) begin
+			crc_o <=#1 INIT_VAL;
+		end
+		else begin
+			 crc_o <=#1 crc_i;
+			if (init && (~d_valid)) begin
+				crc_o <=#1 INIT_VAL;
+			end
+			
+			if (d_valid) crc_o <=#1 next_crc;
+		end
+	end
+
+
+    // Functions
+
+    function [(CRC_WIDTH-1) : 0] crc_calc;
+		input   [(CRC_WIDTH-1) : 0] crc_in;
+		input   [(DATA_WIDTH-1): 0] d;
+		integer     	    	    i;
+    	reg     [(CRC_WIDTH-1) : 0] p_crc[0 :(DATA_WIDTH-2)];
+		begin
+	    	p_crc[0] = crc_atom(crc_in, d[0]);
+
+	    	for (i=1; i< (DATA_WIDTH-1); i=i+1) begin
+	    		p_crc[i] = crc_atom(p_crc[i-1], d[i]);
+	    	end
+
+	    	crc_calc = crc_atom(p_crc[DATA_WIDTH-2], d[DATA_WIDTH-1]);
+		end
+    endfunction
+    
+
+    function [(CRC_WIDTH-1) : 0] crc_atom;
+		input   [(CRC_WIDTH-1) : 0] crc_in;
+		input   	    	    d;
+		begin
+    	    if (!(crc_in[0] ^ d)) crc_atom = (crc_in >> 1);
+			else crc_atom = (crc_in >> 1) ^ POLY[(CRC_WIDTH-1):0];
+		end
+    endfunction
+    
+endmodule
+
+module crc_tri (d_1, d_2, d_3, init_1, init_2, init_3, reset_b_1, reset_b_2,
+	reset_b_3, clk_1, clk_2, clk_3, d_valid_1, d_valid_2, d_valid_3, crc_1,
+	crc_2, crc_3);
+
+    // synopsys template
+
+    parameter CRC_WIDTH = 16;
+    parameter DATA_WIDTH= 16;
+    parameter INIT_VAL	= 'hffff;
+    parameter POLY  	= 'h8408;
+
+
+    // I/Os
+    
+    wire  [(CRC_WIDTH-1) : 0] crc;
+
+    input   [(DATA_WIDTH-1): 0] d_1;
+    input   	    	    	init_1;
+    input   	    	    	d_valid_1;
+    input         	    	clk_1;
+    input         	    	reset_b_1;
+    output  [(CRC_WIDTH-1) : 0] crc_1;
+
+    input   [(DATA_WIDTH-1): 0] d_2;
+    input   	    	    	init_2;
+    input   	    	    	d_valid_2;
+    input         	    	clk_2;
+    input         	    	reset_b_2;
+    output  [(CRC_WIDTH-1) : 0] crc_2;
+
+    input   [(DATA_WIDTH-1): 0] d_3;
+    input   	    	    	init_3;
+    input   	    	    	d_valid_3;
+    input         	    	clk_3;
+    input         	    	reset_b_3;
+    output  [(CRC_WIDTH-1) : 0] crc_3;
+
+
+	crc_iostate #(.CRC_WIDTH(CRC_WIDTH),.DATA_WIDTH(DATA_WIDTH),.INIT_VAL(INIT_VAL),.POLY(POLY))  crc1 (
+		.d(d_1),
+		.init(init_1),
+		.reset_b(reset_b_1),
+		.clk(clk_1),
+		.d_valid(d_valid_1),
+		.crc_o(crc_2),
+		.crc_i(crc_1)
+	);
+
+	crc_iostate #(.CRC_WIDTH(CRC_WIDTH),.DATA_WIDTH(DATA_WIDTH),.INIT_VAL(INIT_VAL),.POLY(POLY))  crc2 (
+		.d(d_2),
+		.init(init_2),
+		.reset_b(reset_b_2),
+		.clk(clk_2),
+		.d_valid(d_valid_2),
+		.crc_o(crc_3),
+		.crc_i(crc_2)
+	);
+
+	crc_iostate #(.CRC_WIDTH(CRC_WIDTH),.DATA_WIDTH(DATA_WIDTH),.INIT_VAL(INIT_VAL),.POLY(POLY))  crc3 (
+		.d(d_3),
+		.init(init_3),
+		.reset_b(reset_b_3),
+		.clk(clk_3),
+		.d_valid(d_valid_3),
+		.crc_o(crc),
+		.crc_i(crc_3)
+	);
+	
+	majority_voter #(.WIDTH(CRC_WIDTH)) mv (
+		.in1(crc_2),
+		.in2(crc_3),
+		.in3(crc),
+		.out(crc_1),
+		.err()
+	);
+	
+	
+endmodule
+
+`timescale 1ns/1ns
+/*
+// MADE WITH LATCHES: (but IBM's smallest latch is bigger than smallest FF!)
+// Artisan TLATX1TF is smaller... 4.4x3.6 um2
+//
+module SRAM (data_w, data_r, addr_w, addr_r, w_enable, clk_w);
+	parameter ADDR_WIDTH = 8;
+	parameter DATA_WIDTH = 16;
+	parameter SIZE = 1<<ADDR_WIDTH;
+ 	
+	input [ADDR_WIDTH-1:0] addr_w, addr_r;
+ 	output [DATA_WIDTH-1:0] data_r;
+	input [DATA_WIDTH-1:0] data_w;
+	input w_enable, clk_w;
+	
+	reg [SIZE-1:0] wl_w;
+	reg [DATA_WIDTH-1:0] mem [SIZE-1:0];
+	
+	integer i;
+	always @* for (i=0; i<SIZE; i=i+1)	begin
+		wl_w[i] = clk_w || (!((i==addr_w) && w_enable));
+		if (!wl_w[i]) mem[i] = data_w;
+	end
+
+	wire [DATA_WIDTH-1:0] data_r = mem[addr_r];
+
+endmodule
+*/
+
+
+// MADE WITH FFs
+
+module SRAM #(
+	parameter ADDR_WIDTH = 3,
+	parameter DATA_WIDTH = 4,
+	parameter SIZE = 1<<ADDR_WIDTH
+)( 	
+	input [ADDR_WIDTH-1:0] addr_w, addr_r,
+ 	output [DATA_WIDTH-1:0] data_r,
+	input [DATA_WIDTH-1:0] data_w,
+	input w_enable, clk_w
+);	
+	reg [SIZE-1:0] wl_w, wl_w_latched;
+	reg [DATA_WIDTH-1:0] mem [SIZE-1:0];
+
+
+	//integer i;
+	/*
+	always @* for (i=0; i<SIZE; i=i+1)	begin
+		if (!clk_w) begin
+			wl_w_latched[i] = w_enable && (i==addr_w) ;
+		end
+		wl_w[i] = wl_w_latched[i] && clk_w;
+	end
+*/
+	reg w_enable_latched;
+	always @* begin
+		if (!clk_w) w_enable_latched = w_enable;
+	end
+	
+	wire clk_w_gated = clk_w && w_enable_latched;
+	
+	generate
+		genvar j;
+		for (j=0; j<SIZE; j=j+1)	begin: mygen
+ 			always @(posedge wl_w[j]) mem[j] <=#1 data_w;
+
+			always @* begin
+				if (!clk_w_gated) wl_w_latched[j] = (j==addr_w) ;
+				wl_w[j] = wl_w_latched[j] && clk_w_gated;
+			end
+		end
+	endgenerate
+
+	assign data_r = mem[addr_r];
+
+endmodule
+
+/*
+module SRAM (data_w, data_r, addr_w, addr_r, w_enable, clk_w);
+	parameter ADDR_WIDTH = 8;
+	parameter DATA_WIDTH = 16;
+	parameter SIZE = 1<<ADDR_WIDTH;
+ 	
+	input [ADDR_WIDTH-1:0] addr_w, addr_r;
+ 	output [DATA_WIDTH-1:0] data_r;
+	input [DATA_WIDTH-1:0] data_w;
+	input w_enable, clk_w;
+	
+	reg [DATA_WIDTH-1:0] mem [SIZE-1:0];
+
+
+	always @(posedge clk_w) begin
+		if(w_enable) mem[addr_w] <=#1 data_w;
+	end
+	wire [DATA_WIDTH-1:0] data_r = mem[addr_r];
+
+endmodule
+*/
+`timescale 1ns/1ps
+module SRAM_tri #(
+	parameter DATA_WIDTH=25, ADDR_WIDTH=8
+) (
+	input [ADDR_WIDTH-1:0] addr_w_1, addr_r_1,
+	input [ADDR_WIDTH-1:0] addr_w_2, addr_r_2,
+	input [ADDR_WIDTH-1:0] addr_w_3, addr_r_3,
+ 	output [DATA_WIDTH-1:0] data_r_1,
+ 	output [DATA_WIDTH-1:0] data_r_2,
+ 	output [DATA_WIDTH-1:0] data_r_3,
+	input [DATA_WIDTH-1:0] data_w_1,
+	input [DATA_WIDTH-1:0] data_w_2,
+	input [DATA_WIDTH-1:0] data_w_3,
+	input w_enable_1, clk_w_1,
+	input w_enable_2, clk_w_2,
+	input w_enable_3, clk_w_3
+);
+
+	wire [ADDR_WIDTH-1:0] addr_w, addr_r;
+ 	wire [DATA_WIDTH-1:0] data_r;
+	wire [DATA_WIDTH-1:0] data_w;
+
+	SRAM #(.ADDR_WIDTH(ADDR_WIDTH),.DATA_WIDTH(DATA_WIDTH)) SRAM_ (
+		.data_w(data_w), .data_r(data_r), .addr_w(addr_w), .addr_r(addr_r),
+		.w_enable(w_enable), .clk_w(clk_w)
+	);
+
+	majority_voter #(.WIDTH(2*ADDR_WIDTH+DATA_WIDTH+2)) mv (
+		.in1({w_enable_1, clk_w_1, addr_w_1, addr_r_1, data_w_1}),
+		.in2({w_enable_2, clk_w_2, addr_w_2, addr_r_2, data_w_2}),
+		.in3({w_enable_3, clk_w_3, addr_w_3, addr_r_3, data_w_3}),
+		.out({w_enable, clk_w, addr_w, addr_r, data_w}),
+		.err()
+	);
+	
+	
+	assign data_r_1 = data_r;
+	assign data_r_2 = data_r;
+	assign data_r_3 = data_r;
+endmodule
+`timescale 1ns/1ns
+module HDLC_tri 
+#(
+
+	parameter MASTER = 0,
+	 HEADER_FIELD = 1,
+	 ADDR_WIDTH = 5,
+	 MAX_PACKET_LENGTH = 16, 
+	 THRESHOLD = 2**ADDR_WIDTH -MAX_PACKET_LENGTH-1
+)
+ (
+input [15:0]  tx_dat_1,
+input [15:0]  tx_dat_2,
+input [15:0]  tx_dat_3,
+output [15:0]  rx_dat_1,
+output [15:0]  rx_dat_2,
+output [15:0]  rx_dat_3,
+input   rx_dav_1,user_clk_pri_1, user_clk_aux_1, 
+input   rx_dav_2,user_clk_pri_2, user_clk_aux_2, 
+input   rx_dav_3,user_clk_pri_3, user_clk_aux_3, 
+output  rx_ena_1, rx_eop_1, tx_dav_1, rx_sop_1, rx_err_1,
+output  rx_ena_2, rx_eop_2, tx_dav_2, rx_sop_2, rx_err_2,
+output  rx_ena_3, rx_eop_3, tx_dav_3, rx_sop_3, rx_err_3,
+input  resetb_1, tx_ena_1, disable_aux_1,
+input  resetb_2, tx_ena_2, disable_aux_2,
+input  resetb_3, tx_ena_3, disable_aux_3,
+output  user_clk_1,
+output  user_clk_2,
+output  user_clk_3,
+input [7:0]  tx_adr_1,
+input [7:0]  tx_adr_2,
+input [7:0]  tx_adr_3,
+output [7:0]  rx_adr_1,
+output [7:0]  rx_adr_2,
+output [7:0]  rx_adr_3,
+input  tx_cmd_reset_1, tx_cmd_test_1, tx_cmd_sabm_1,
+input  tx_cmd_reset_2, tx_cmd_test_2, tx_cmd_sabm_2,
+input  tx_cmd_reset_3, tx_cmd_test_3, tx_cmd_sabm_3,
+output  rx_cmd_reset_1, rx_cmd_test_1, rx_cmd_ua_1,
+output  rx_cmd_reset_2, rx_cmd_test_2, rx_cmd_ua_2,
+output  rx_cmd_reset_3, rx_cmd_test_3, rx_cmd_ua_3,
+output [2:0]  tx_ns_1, rx_nr_1,rx_ns_1,
+output [2:0]  tx_ns_2, rx_nr_2,rx_ns_2,
+output [2:0]  tx_ns_3, rx_nr_3,rx_ns_3,
+output [6:0]  rx_cmd_srej_1,
+output [6:0]  rx_cmd_srej_2,
+output [6:0]  rx_cmd_srej_3,
+output  cmd_busy_1,
+output  cmd_busy_2,
+output  cmd_busy_3,
+output [1:0]  tx_sdr_1,
+output [1:0]  tx_sdr_2,
+output [1:0]  tx_sdr_3,
+input [1:0]  rx_sdr_1, rx_sdr_aux_1,
+input [1:0]  rx_sdr_2, rx_sdr_aux_2,
+input [1:0]  rx_sdr_3, rx_sdr_aux_3,
+output  active_aux_1,
+output  active_aux_2,
+output  active_aux_3
+);
+wire  rx_cmd_reset__1, rx_cmd_test__1;
+wire  rx_cmd_reset__2, rx_cmd_test__2;
+wire  rx_cmd_reset__3, rx_cmd_test__3;
+wire [2:0]  rx_vr_1;
+wire [2:0]  rx_vr_2;
+wire [2:0]  rx_vr_3;
+wire [6:0]  tx_cmd_srej_1, tx_cmd_srej__1;
+wire [6:0]  tx_cmd_srej_2, tx_cmd_srej__2;
+wire [6:0]  tx_cmd_srej_3, tx_cmd_srej__3;
+
+rx_tri #(.HEADER_FIELD(HEADER_FIELD), .ADDR_WIDTH(ADDR_WIDTH)) rx (
+		.rx_dat_1(rx_dat_1),
+		.rx_sdr_pri_1(rx_sdr_1),
+		.clk_pri_1(user_clk_pri_1),
+		.rx_sdr_aux_1(rx_sdr_aux_1),
+		.clk_aux_1(user_clk_aux_1),
+		.clk_active_1(user_clk_1),
+		.rx_ena_1(rx_ena_1),
+		.rx_dav_1(rx_dav_1),
+		.rx_eop_1(rx_eop_1),
+		.rx_sop_1(rx_sop_1),
+		.rx_adr_1(rx_adr_1),
+		.rx_err_1(rx_err_1),
+		.rx_vr_1(rx_vr_1),
+		.rx_nr_1(rx_nr_1),
+		.rx_ns_1(rx_ns_1),
+		.cmd_busy_1(cmd_busy_1),
+		.rx_cmd_ua_1(rx_cmd_ua_1),
+		.tx_cmd_ua_1(tx_cmd_ua_1),
+		.rx_cmd_srej_1(rx_cmd_srej_1),
+		.tx_cmd_srej_1(tx_cmd_srej_1),
+		.resetb_1(resetb_1),
+		.rx_cmd_reset_1(rx_cmd_reset__1),
+		.rx_cmd_test_1(rx_cmd_test__1),
+		.tx_cmd_reset_1(tx_cmd_reset__1),
+		.active_aux_1(active_aux_1),
+		.disable_aux_1(disable_aux_1),
+		.rx_dat_2(rx_dat_2),
+		.rx_sdr_pri_2(rx_sdr_2),
+		.clk_pri_2(user_clk_pri_2),
+		.rx_sdr_aux_2(rx_sdr_aux_2),
+		.clk_aux_2(user_clk_aux_2),
+		.clk_active_2(user_clk_2),
+		.rx_ena_2(rx_ena_2),
+		.rx_dav_2(rx_dav_2),
+		.rx_eop_2(rx_eop_2),
+		.rx_sop_2(rx_sop_2),
+		.rx_adr_2(rx_adr_2),
+		.rx_err_2(rx_err_2),
+		.rx_vr_2(rx_vr_2),
+		.rx_nr_2(rx_nr_2),
+		.rx_ns_2(rx_ns_2),
+		.cmd_busy_2(cmd_busy_2),
+		.rx_cmd_ua_2(rx_cmd_ua_2),
+		.tx_cmd_ua_2(tx_cmd_ua_2),
+		.rx_cmd_srej_2(rx_cmd_srej_2),
+		.tx_cmd_srej_2(tx_cmd_srej_2),
+		.resetb_2(resetb_2),
+		.rx_cmd_reset_2(rx_cmd_reset__2),
+		.rx_cmd_test_2(rx_cmd_test__2),
+		.tx_cmd_reset_2(tx_cmd_reset__2),
+		.active_aux_2(active_aux_2),
+		.disable_aux_2(disable_aux_2),
+		.rx_dat_3(rx_dat_3),
+		.rx_sdr_pri_3(rx_sdr_3),
+		.clk_pri_3(user_clk_pri_3),
+		.rx_sdr_aux_3(rx_sdr_aux_3),
+		.clk_aux_3(user_clk_aux_3),
+		.clk_active_3(user_clk_3),
+		.rx_ena_3(rx_ena_3),
+		.rx_dav_3(rx_dav_3),
+		.rx_eop_3(rx_eop_3),
+		.rx_sop_3(rx_sop_3),
+		.rx_adr_3(rx_adr_3),
+		.rx_err_3(rx_err_3),
+		.rx_vr_3(rx_vr_3),
+		.rx_nr_3(rx_nr_3),
+		.rx_ns_3(rx_ns_3),
+		.cmd_busy_3(cmd_busy_3),
+		.rx_cmd_ua_3(rx_cmd_ua_3),
+		.tx_cmd_ua_3(tx_cmd_ua_3),
+		.rx_cmd_srej_3(rx_cmd_srej_3),
+		.tx_cmd_srej_3(tx_cmd_srej_3),
+		.resetb_3(resetb_3),
+		.rx_cmd_reset_3(rx_cmd_reset__3),
+		.rx_cmd_test_3(rx_cmd_test__3),
+		.tx_cmd_reset_3(tx_cmd_reset__3),
+		.active_aux_3(active_aux_3),
+		.disable_aux_3(disable_aux_3)
+	);
+
+
+tx_tri #(.HEADER_FIELD(HEADER_FIELD), .ADDR_WIDTH(ADDR_WIDTH), .THRESHOLD(THRESHOLD)) tx (
+		.tx_dat_1(tx_dat_1),
+		.tx_sdr_1(tx_sdr_1),
+		.clk_1(user_clk_1),
+		.tx_ena_1(tx_ena_1),
+		.tx_dav_1(tx_dav_1),
+		.tx_adr_1(tx_adr_1),
+		.tx_ns_1(tx_ns_1),
+		.tx_nr_1(rx_vr_1),
+		.cmd_busy_1(cmd_busy_1),
+		.tx_cmd_sabm_1(tx_cmd_sabm__1),
+		.tx_cmd_ua_1(tx_cmd_ua__1),
+		.tx_cmd_srej_1(tx_cmd_srej__1),
+		.tx_cmd_reset_1(tx_cmd_reset__1),
+		.tx_cmd_test_1(tx_cmd_test__1),
+		.rx_cmd_reset_1(rx_cmd_reset_1),
+		.resetb_1(resetb_1),
+		.tx_dat_2(tx_dat_2),
+		.tx_sdr_2(tx_sdr_2),
+		.clk_2(user_clk_2),
+		.tx_ena_2(tx_ena_2),
+		.tx_dav_2(tx_dav_2),
+		.tx_adr_2(tx_adr_2),
+		.tx_ns_2(tx_ns_2),
+		.tx_nr_2(rx_vr_2),
+		.cmd_busy_2(cmd_busy_2),
+		.tx_cmd_sabm_2(tx_cmd_sabm__2),
+		.tx_cmd_ua_2(tx_cmd_ua__2),
+		.tx_cmd_srej_2(tx_cmd_srej__2),
+		.tx_cmd_reset_2(tx_cmd_reset__2),
+		.tx_cmd_test_2(tx_cmd_test__2),
+		.rx_cmd_reset_2(rx_cmd_reset_2),
+		.resetb_2(resetb_2),
+		.tx_dat_3(tx_dat_3),
+		.tx_sdr_3(tx_sdr_3),
+		.clk_3(user_clk_3),
+		.tx_ena_3(tx_ena_3),
+		.tx_dav_3(tx_dav_3),
+		.tx_adr_3(tx_adr_3),
+		.tx_ns_3(tx_ns_3),
+		.tx_nr_3(rx_vr_3),
+		.cmd_busy_3(cmd_busy_3),
+		.tx_cmd_sabm_3(tx_cmd_sabm__3),
+		.tx_cmd_ua_3(tx_cmd_ua__3),
+		.tx_cmd_srej_3(tx_cmd_srej__3),
+		.tx_cmd_reset_3(tx_cmd_reset__3),
+		.tx_cmd_test_3(tx_cmd_test__3),
+		.rx_cmd_reset_3(rx_cmd_reset_3),
+		.resetb_3(resetb_3)
+	);
+
+
+assign rx_cmd_reset_1 = MASTER ? 1'b0 : rx_cmd_reset__1 ;
+assign rx_cmd_reset_2 = MASTER ? 1'b0 : rx_cmd_reset__2 ;
+assign rx_cmd_reset_3 = MASTER ? 1'b0 : rx_cmd_reset__3 ;
+
+assign rx_cmd_test_1 = MASTER ? rx_cmd_test__1 : 1'b0 ;
+assign rx_cmd_test_2 = MASTER ? rx_cmd_test__2 : 1'b0 ;
+assign rx_cmd_test_3 = MASTER ? rx_cmd_test__3 : 1'b0 ;
+
+assign tx_cmd_reset__1 = MASTER ? tx_cmd_reset_1 : 1'b0 ;
+assign tx_cmd_reset__2 = MASTER ? tx_cmd_reset_2 : 1'b0 ;
+assign tx_cmd_reset__3 = MASTER ? tx_cmd_reset_3 : 1'b0 ;
+
+assign tx_cmd_test__1 = MASTER ? tx_cmd_test_1 : rx_cmd_test__1 ;
+assign tx_cmd_test__2 = MASTER ? tx_cmd_test_2 : rx_cmd_test__2 ;
+assign tx_cmd_test__3 = MASTER ? tx_cmd_test_3 : rx_cmd_test__3 ;
+
+assign	tx_cmd_sabm__1 = MASTER ? tx_cmd_sabm_1 : 1'b0;
+assign	tx_cmd_sabm__2 = MASTER ? tx_cmd_sabm_2 : 1'b0;
+assign	tx_cmd_sabm__3 = MASTER ? tx_cmd_sabm_3 : 1'b0;
+
+assign  tx_cmd_ua__1 = MASTER ? 1'b0 : tx_cmd_ua_1;
+assign  tx_cmd_ua__2 = MASTER ? 1'b0 : tx_cmd_ua_2;
+assign  tx_cmd_ua__3 = MASTER ? 1'b0 : tx_cmd_ua_3;
+
+assign	tx_cmd_srej__1 = MASTER ? 7'b0 : tx_cmd_srej_1;
+assign	tx_cmd_srej__2 = MASTER ? 7'b0 : tx_cmd_srej_2;
+assign	tx_cmd_srej__3 = MASTER ? 7'b0 : tx_cmd_srej_3;
+
+assign user_clk_1 = active_aux_1 ? user_clk_aux_1 : user_clk_pri_1;
+assign user_clk_2 = active_aux_2 ? user_clk_aux_2 : user_clk_pri_2;
+assign user_clk_3 = active_aux_3 ? user_clk_aux_3 : user_clk_pri_3;
+endmodule
+/////////////////////////////////////////////////////////////////////
+// 
+//	Split 16 bits into 2 blocks of 8 bits, do Hamming, and viceversa
+//	Created by Sandro Bonacini
+//	(long time ago)
+//
+
+module Hamming16_24 (enc_in, enc_out, dec_in, dec_out);
+	input [15:0] enc_in;
+	output [23:0] enc_out;
+	input [23:0] dec_in;
+	output [15:0] dec_out;
+	
+	wire [23:0] pre_int_enc_out;
+	reg [23:0] enc_out, post_int_dec_in;
+
+	wire [2:0] unconnected_dec_out0,unconnected_dec_out1,unconnected_enc_out0,unconnected_enc_out1;
+
+	Hamming #(.CHECK_WIDTH(4)) Hamming1 (
+		.enc_in({3'b0,enc_in[7:0]}),
+		.enc_out({unconnected_enc_out0,pre_int_enc_out[11:0]}),
+		.dec_in({3'b0,post_int_dec_in[11:0]}),
+		.dec_out({unconnected_dec_out0, dec_out[7:0]})
+	);
+
+	Hamming #(.CHECK_WIDTH(4)) Hamming2 (
+		.enc_in({3'b0,enc_in[15:8]}),
+		.enc_out({unconnected_enc_out1,pre_int_enc_out[23:12]}),
+		.dec_in({3'b0,post_int_dec_in[23:12]}),
+		.dec_out({unconnected_dec_out1,dec_out[15:8]})
+	);
+
+	
+	integer i;
+	always @* begin
+		for (i=0; i<12; i=i+1) begin
+			enc_out[i<<1] = pre_int_enc_out[i];
+			enc_out[(i<<1)+1] = pre_int_enc_out[i+12];
+			post_int_dec_in[i] = dec_in[i<<1];
+			post_int_dec_in[i+12] = dec_in[(i<<1)+1];
+		end
+	end
+
+endmodule
+////////////////////////
+// 
+//	Hamming encoder decoder
+//	Created by Sandro Bonacini
+//	(long time ago)
+//
+
+module Hamming (enc_in, enc_out, dec_in, dec_out);
+	parameter CHECK_WIDTH=3; // this is log2(CODE_WIDTH+1) = log2(n+1) = n-k.
+	
+	parameter CODE_WIDTH=(1<<CHECK_WIDTH)-1; // n
+	parameter DATA_WIDTH=CODE_WIDTH-CHECK_WIDTH; // k
+	
+	input [DATA_WIDTH:1] enc_in;
+	output [CODE_WIDTH:1] enc_out;
+	output [DATA_WIDTH:1] dec_out;
+	input [CODE_WIDTH:1] dec_in;
+	reg [DATA_WIDTH:1] dec_out;
+	reg [CODE_WIDTH:1] enc_out;
+	reg [CODE_WIDTH:1] syndrome;
+	reg [CHECK_WIDTH-1:0] err_pos;
+	reg [CODE_WIDTH:1] corrected;
+	
+	integer i,p,q;
+	always @(enc_in) begin
+		enc_out = 0;
+		for (i=0;i<CHECK_WIDTH;i=i+1) begin
+			for (q=1;q<(1<<i);q=q+1) begin
+				enc_out[(1<<i)+q] = enc_in[(1<<i)+q-i-1];
+				//$display("enc_out[%d] = enc_in[%d];",(1<<i)+q,(1<<i)+q-i-1);
+				//$display("enc_out=%b",enc_out);
+			end
+		end
+
+		for (i=0;i<CHECK_WIDTH;i=i+1) begin
+			enc_out[1<<i] = 0;
+
+			for (p=0; p<=((1<<(CHECK_WIDTH-i-1))-1); p=p+1) begin
+				for (q=0;q<(1<<i);q=q+1) begin
+					enc_out[1<<i] = enc_out[1<<i] ^ enc_out[(p<<(i+1)) + (1<<i) +q];
+					//$display("enc_out[%d] += enc_out[%d];",(1<<i),(p<<(i+1)) + (1<<i) +q);
+					//$display("enc_out=%b",enc_out);
+				end
+			end
+
+		end
+	end
+
+	always @(dec_in) begin
+		err_pos = 0;
+		syndrome = dec_in;
+		
+		for (i=0;i<CHECK_WIDTH;i=i+1) begin
+			syndrome[1<<i] = 0;
+
+			for (p=0; p<=((1<<(CHECK_WIDTH-i-1))-1); p=p+1) begin
+				for (q=0;q<(1<<i);q=q+1) begin
+					syndrome[1<<i] = syndrome[1<<i] ^ syndrome[(p<<(i+1)) + (1<<i) +q];
+				end
+			end
+
+			//if (syndrome[1<<i] != dec_in[1<<i]) err_pos = err_pos + (1<<i);
+			err_pos[i]= syndrome[1<<i] ^ dec_in[1<<i];
+		end
+
+		//$display("syndrome: %b, err_pos: %d", syndrome, err_pos);
+
+
+		corrected = dec_in;
+		if (err_pos) corrected[err_pos] = ~corrected[err_pos];
+		
+		for (i=1;i<CHECK_WIDTH;i=i+1) begin
+			for (q=1;q<(1<<i);q=q+1) begin
+				dec_out[(1<<i)+q-i-1] = corrected[(1<<i)+q];
+			end
+		end
+		
+	end
+
+
+endmodule
+
+// missing: rx_sd_neg_o <=#1 rx_sd_neg_i;
+// missing: tx_dat_reg_o <=#1 tx_dat_reg_i;
+// missing: rx_dat_o <=#1 rx_dat_i;
+// missing: skip_done_o <=#1 skip_done_i;
+// missing: clkdiv_o <=#1 clkdiv_i;
+// missing: tx_sd_negneg_o <=#1 tx_sd_negneg_i;
+// missing: tx_sd_neg_o <=#1 tx_sd_neg_i;
+// missing: tx_sd_pos_o <=#1 tx_sd_pos_i;
+
+`timescale 1ns/1ps
+module serdes_iostate (
+	 rx_sd, rx_clk, resetb, tx_sd, clk40, tx_dat, rx_dat_i, rx_dat_o, rx_off, tx_off, clkdiv_skip
+, tx_sd_pos_i, tx_sd_pos_o, tx_sd_neg_i, tx_sd_neg_o, tx_sd_negneg_i, tx_sd_negneg_o, clkdiv_i, clkdiv_o, skip_done_i, skip_done_o, tx_dat_reg_i, tx_dat_reg_o, rx_sd_neg_i, rx_sd_neg_o);
+	parameter DATARATE = 0;
+
+	input rx_sd;
+
+
+	input rx_sd_neg_i;
+	
+	input [7:0] tx_dat_reg_i;
+	input clkdiv_skip;
+	
+	input skip_done_i;
+	
+	input [1:0] clkdiv_i;
+	input   tx_sd_negneg_i;
+	input tx_sd_neg_i;
+
+	input  tx_sd_pos_i;
+
+
+	input  rx_clk;
+
+
+
+	input   resetb;
+	output  tx_sd;
+	output rx_sd_neg_o;
+	output [7:0] tx_dat_reg_o;
+	output [7:0] rx_dat_o;
+	output skip_done_o;
+	output [1:0] clkdiv_o;
+	output   tx_sd_negneg_o;
+	output tx_sd_neg_o;
+	output  tx_sd_pos_o;
+	output  clk40;
+	input [7:0] tx_dat;
+	input [7:0] rx_dat_i;
+	input rx_off;
+
+	input  tx_off;
+	reg tx_sd;
+
+	
+	reg  clk40;
+	reg [7:0] rx_dat_o;
+	
+	
+	reg [1:0] clkdiv_o;
+	reg [7:0] des;
+
+	reg [7:0] ser;
+
+
+	reg [7:0] tx_dat_reg_o;
+	reg tx_sd_neg_o;
+	reg  tx_sd_pos_o;
+	reg   tx_sd_negneg_o;
+	reg tx_trig;
+	reg ckg_des1;
+
+	reg  ckg_des2;
+
+
+	reg   ckg_des4;
+	reg ckg_ser1;
+
+	reg  ckg_ser2;
+
+
+	reg   ckg_ser4;
+	reg skip_done_o;
+	wire [2:0] __CLKDIV__ = 3'b001 << DATARATE;
+	
+	reg [1:0] des_;
+	
+	
+	
+	always @* begin
+		des[1:0] = des_[1:0];
+
+		if (~tx_off) //cadence map_to_mux
+			ckg_ser1  = rx_clk;
+		else ckg_ser1 = 0;
+
+		if ((DATARATE==1) || (DATARATE==2)) /* cadence map_to_mux */ begin
+			ckg_des2  = ckg_des1;
+			ckg_ser2  = ckg_ser1;
+		end
+		else begin
+			ckg_des2  = 0;
+			ckg_ser2  = 0;
+		end
+
+		if (DATARATE==2) /* cadence map_to_mux */ begin
+			ckg_des4  = ckg_des2;
+			ckg_ser4  = ckg_ser2;
+		end
+		else begin 
+			ckg_ser4  = 0;
+			ckg_des4  = 0;
+		end
+
+		// took off map_to_mux to enhance synthesis performance
+		case (DATARATE) 
+			2: begin
+				tx_trig = clkdiv_o[0] & (~clkdiv_o[1]);
+				clk40 = clkdiv_o[1];
+			end
+			1: begin
+				tx_trig = ~clkdiv_o[0];
+				clk40 = clkdiv_o[0];
+
+			end
+			default: begin
+				tx_trig = 1;
+				clk40 = ~rx_clk;
+			end
+		endcase 
+		
+		if (ckg_ser1) // cadence map_to_mux
+			tx_sd = tx_sd_negneg_i;
+		else tx_sd = tx_sd_pos_o; 
+		
+	end
+
+	
+	always @(posedge ckg_ser1) begin
+		// MSB out first << for serializer
+		tx_sd_pos_o <=#0.1 ser[__CLKDIV__*2-1];
+		ser[1:0] <=#0.1 tx_dat_reg_i[1:0];
+	end
+
+
+	always @(negedge ckg_ser1) begin
+		tx_sd_neg_o <=#0.1 ser[__CLKDIV__*2-2];
+		tx_sd_negneg_o <=#0.1 tx_sd_neg_i;
+	end
+
+
+	always @(posedge ckg_des2) begin
+		des[2]<=#0.1 des[0];
+		des[3]<=#0.1 des[1];
+	end
+
+	always @(posedge ckg_ser2) begin
+		if (tx_trig) ser[3:2] <=#0.1 tx_dat_reg_i[3:2];
+		else begin
+			ser[3] <=#0.1 ser[1];
+			ser[2] <=#0.1 ser[0];
+		end
+	end
+
+
+	always @(posedge ckg_des4) begin
+		des[4]<=#0.1 des[2];
+		des[5]<=#0.1 des[3];
+		des[6]<=#0.1 des[4];
+		des[7]<=#0.1 des[5];
+	end
+
+	always @(posedge ckg_ser4) begin
+		if (tx_trig) ser[7:4] <=#0.1 tx_dat_reg_i[7:4];
+		else begin
+			ser[7] <=#0.1 ser[5];
+			ser[6] <=#0.1 ser[4];
+			ser[5] <=#0.1 ser[3];
+			ser[4] <=#0.1 ser[2];
+		end
+	end
+
+	
+	
+	always @(negedge rx_clk or negedge resetb) begin
+		if (~resetb) begin
+			clkdiv_o <=#0.1 0;
+		end
+		else begin
+			clkdiv_o <=#0.1 clkdiv_i;
+			skip_done_o <=#0.1 skip_done_i;
+			if ((!clkdiv_skip) || (skip_done_i)) begin
+				clkdiv_o <=#0.1 clkdiv_i + 1;
+			end
+			
+			skip_done_o <=#0.1 clkdiv_skip;
+		end
+	end
+
+
+	always @(posedge clk40) begin
+		rx_dat_o <=#0.1 des;
+		tx_dat_reg_o <=#0.1 tx_dat;
+	end
+	
+// DDRDES
+	reg rx_sd_neg_o;
+	always @* begin
+		if (~rx_off) //cadence map_to_mux
+			ckg_des1  = rx_clk;
+		else  ckg_des1 = 0;
+	end
+
+	always @(negedge ckg_des1) begin
+ 		rx_sd_neg_o<=#0.1 rx_sd;
+	end
+
+	always @(posedge ckg_des1) begin
+		// LSB in first << for deserializer
+		des_[1] <=#0.1 rx_sd_neg_i;
+		des_[0] <=#0.1 rx_sd;
+	end
+
+
+endmodule
+
+
+`timescale 1ns/1ps
+module serdes_tri (
+	 rx_sd_1, rx_sd_2, rx_sd_3, rx_clk_1, rx_clk_2, rx_clk_3, resetb_1, resetb_2, resetb_3, tx_sd_1, tx_sd_2, tx_sd_3, clk40_1, clk40_2, clk40_3, tx_dat_1, tx_dat_2, tx_dat_3, rx_dat_1, rx_dat_2, rx_dat_3, rx_off_1, rx_off_2, rx_off_3, tx_off_1, tx_off_2, tx_off_3, clkdiv_skip_1, clkdiv_skip_2, clkdiv_skip_3
+);
+
+	parameter DATARATE = 0;
+
+	input rx_sd_1, rx_sd_2, rx_sd_3;
+
+	input  rx_clk_1, rx_clk_2, rx_clk_3;
+
+	input   resetb_1, resetb_2, resetb_3;
+	output  tx_sd_1, tx_sd_2, tx_sd_3;
+	output  clk40_1, clk40_2, clk40_3;
+	input [7:0] tx_dat_1, tx_dat_2, tx_dat_3;
+	output [7:0] rx_dat_1, rx_dat_2, rx_dat_3;
+	input rx_off_1, rx_off_2, rx_off_3;
+
+	input  tx_off_1, tx_off_2, tx_off_3;
+	input clkdiv_skip_1, clkdiv_skip_2, clkdiv_skip_3;
+
+	wire tx_sd_pos_1, tx_sd_pos_2, tx_sd_pos_3;
+	wire tx_sd_neg_1, tx_sd_neg_2, tx_sd_neg_3;
+	wire tx_sd_negneg_1, tx_sd_negneg_2, tx_sd_negneg_3;
+	wire [1:0] clkdiv_1, clkdiv_2, clkdiv_3;
+	wire skip_done_1, skip_done_2, skip_done_3;
+	wire [7:0] rx_dat_1, rx_dat_2, rx_dat_3;
+	wire [7:0] tx_dat_reg_1, tx_dat_reg_2, tx_dat_reg_3;
+	wire rx_sd_neg_1, rx_sd_neg_2, rx_sd_neg_3;
+	wire tx_sd_pos;
+	wire tx_sd_neg;
+	wire tx_sd_negneg;
+	wire [1:0] clkdiv;
+	wire skip_done;
+	wire [7:0] rx_dat;
+	wire [7:0] tx_dat_reg;
+	wire rx_sd_neg;
+
+	serdes_iostate #(.DATARATE(DATARATE) ) serdes_iostate_1 (
+	 .rx_sd(rx_sd_1), .rx_clk(rx_clk_1), .resetb(resetb_1), .tx_sd(tx_sd_1), .clk40(clk40_1), .tx_dat(tx_dat_1), .rx_dat_i(rx_dat), .rx_dat_o(rx_dat_1), .rx_off(rx_off_1), .tx_off(tx_off_1), .clkdiv_skip(clkdiv_skip_1), .tx_sd_pos_i(tx_sd_pos), .tx_sd_pos_o(tx_sd_pos_1), .tx_sd_neg_i(tx_sd_neg), .tx_sd_neg_o(tx_sd_neg_1), .tx_sd_negneg_i(tx_sd_negneg), .tx_sd_negneg_o(tx_sd_negneg_1), .clkdiv_i(clkdiv), .clkdiv_o(clkdiv_1), .skip_done_i(skip_done), .skip_done_o(skip_done_1), .tx_dat_reg_i(tx_dat_reg), .tx_dat_reg_o(tx_dat_reg_1), .rx_sd_neg_i(rx_sd_neg), .rx_sd_neg_o(rx_sd_neg_1));
+
+	serdes_iostate #(.DATARATE(DATARATE) ) serdes_iostate_2 (
+	 .rx_sd(rx_sd_2), .rx_clk(rx_clk_2), .resetb(resetb_2), .tx_sd(tx_sd_2), .clk40(clk40_2), .tx_dat(tx_dat_2), .rx_dat_i(rx_dat_1), .rx_dat_o(rx_dat_2), .rx_off(rx_off_2), .tx_off(tx_off_2), .clkdiv_skip(clkdiv_skip_2), .tx_sd_pos_i(tx_sd_pos_1), .tx_sd_pos_o(tx_sd_pos_2), .tx_sd_neg_i(tx_sd_neg_1), .tx_sd_neg_o(tx_sd_neg_2), .tx_sd_negneg_i(tx_sd_negneg_1), .tx_sd_negneg_o(tx_sd_negneg_2), .clkdiv_i(clkdiv_1), .clkdiv_o(clkdiv_2), .skip_done_i(skip_done_1), .skip_done_o(skip_done_2), .tx_dat_reg_i(tx_dat_reg_1), .tx_dat_reg_o(tx_dat_reg_2), .rx_sd_neg_i(rx_sd_neg_1), .rx_sd_neg_o(rx_sd_neg_2));
+
+	serdes_iostate #(.DATARATE(DATARATE) ) serdes_iostate_3 (
+	 .rx_sd(rx_sd_3), .rx_clk(rx_clk_3), .resetb(resetb_3), .tx_sd(tx_sd_3), .clk40(clk40_3), .tx_dat(tx_dat_3), .rx_dat_i(rx_dat_2), .rx_dat_o(rx_dat_3), .rx_off(rx_off_3), .tx_off(tx_off_3), .clkdiv_skip(clkdiv_skip_3), .tx_sd_pos_i(tx_sd_pos_2), .tx_sd_pos_o(tx_sd_pos_3), .tx_sd_neg_i(tx_sd_neg_2), .tx_sd_neg_o(tx_sd_neg_3), .tx_sd_negneg_i(tx_sd_negneg_2), .tx_sd_negneg_o(tx_sd_negneg_3), .clkdiv_i(clkdiv_2), .clkdiv_o(clkdiv_3), .skip_done_i(skip_done_2), .skip_done_o(skip_done_3), .tx_dat_reg_i(tx_dat_reg_2), .tx_dat_reg_o(tx_dat_reg_3), .rx_sd_neg_i(rx_sd_neg_2), .rx_sd_neg_o(rx_sd_neg_3));
+
+	majority_voter #(.WIDTH(23),.QUIET(1)) mv (
+		.in1({tx_sd_pos_1, tx_sd_neg_1, tx_sd_negneg_1, clkdiv_1, skip_done_1, rx_dat_1, tx_dat_reg_1, rx_sd_neg_1}),
+		.in2({tx_sd_pos_2, tx_sd_neg_2, tx_sd_negneg_2, clkdiv_2, skip_done_2, rx_dat_2, tx_dat_reg_2, rx_sd_neg_2}),
+		.in3({tx_sd_pos_3, tx_sd_neg_3, tx_sd_negneg_3, clkdiv_3, skip_done_3, rx_dat_3, tx_dat_reg_3, rx_sd_neg_3}),
+		.out({tx_sd_pos, tx_sd_neg, tx_sd_negneg, clkdiv, skip_done, rx_dat, tx_dat_reg, rx_sd_neg}),
+		.err()
+	);
+endmodule
+
+
+module pri_aux_control_iostate (
+	resetb_pri, resetb_aux, disconnect_pri, 
+		  disconnect_aux, activate_commands_pri, activate_commands_aux,
+		 clk_pri, clk_aux, 
+	active_aux_i, active_aux_o, active_pri_i, active_pri_o, disable_aux
+);
+
+
+	input resetb_pri;
+
+
+
+	input disconnect_pri;
+
+	input  disconnect_aux;
+	
+	input  resetb_aux;
+
+
+
+
+	input     disable_aux;
+	input	 clk_pri;
+
+	input	  clk_aux;
+	input activate_commands_pri;
+
+	input  activate_commands_aux;
+	output active_aux_o;
+	output  active_pri_o ;
+	input active_aux_i;
+
+	input  active_pri_i ;
+	reg active_aux_o;
+
+	
+	reg  active_pri_o;
+
+	wire disconnectb_resetb_pri = resetb_pri & (~disconnect_pri) | disable_aux;
+
+
+	always @(posedge clk_pri or negedge disconnectb_resetb_pri) begin
+		if (~disconnectb_resetb_pri) active_pri_o <=#1 0;
+		else begin
+			active_pri_o <=#1 active_pri_i;
+			if (activate_commands_pri) active_pri_o <=#1 1;
+		end			
+	end
+
+
+	wire disconnectb_resetb_aux = resetb_aux & (~disconnect_aux) & (~disable_aux);
+
+	always @(posedge clk_aux or negedge disconnectb_resetb_aux) begin
+		if (~disconnectb_resetb_aux) active_aux_o <=#1 0;
+		else begin
+			active_aux_o <=#1 active_aux_i;
+			if (activate_commands_aux) active_aux_o <=#1 1;
+		end			
+	end
+
+endmodule
+
+// Triplicate with:
+// python tri.py < pri_aux_control.v > pri_aux_control_tri.v
+
+
+module pri_aux_control_tri (
+	resetb_pri_1, resetb_pri_2, resetb_pri_3, resetb_aux_1, resetb_aux_2, resetb_aux_3, disconnect_pri_1, disconnect_pri_2, disconnect_pri_3, 
+		  disconnect_aux_1, disconnect_aux_2, disconnect_aux_3, activate_commands_pri_1, activate_commands_pri_2, activate_commands_pri_3, activate_commands_aux_1, activate_commands_aux_2, activate_commands_aux_3,
+		 clk_pri_1, clk_pri_2, clk_pri_3, clk_aux_1, clk_aux_2, clk_aux_3, 
+	active_aux_1, active_aux_2, active_aux_3, active_pri_1, active_pri_2, active_pri_3, disable_aux_1, disable_aux_2, disable_aux_3
+);
+
+	input resetb_pri_1, resetb_pri_2, resetb_pri_3;
+
+	input  resetb_aux_1, resetb_aux_2, resetb_aux_3;
+
+	input     disable_aux_1, disable_aux_2, disable_aux_3;
+	input	 clk_pri_1, clk_pri_2, clk_pri_3;
+
+	input	  clk_aux_1, clk_aux_2, clk_aux_3;
+	input activate_commands_pri_1, activate_commands_pri_2, activate_commands_pri_3;
+
+	input  activate_commands_aux_1, activate_commands_aux_2, activate_commands_aux_3;
+	output active_aux_1, active_aux_2, active_aux_3;
+
+	output  active_pri_1, active_pri_2, active_pri_3 ;
+	input disconnect_pri_1, disconnect_pri_2, disconnect_pri_3;
+
+	input  disconnect_aux_1, disconnect_aux_2, disconnect_aux_3;
+
+	wire active_pri_1, active_pri_2, active_pri_3;
+	wire active_aux_1, active_aux_2, active_aux_3;
+	wire active_pri;
+	wire active_aux;
+
+	pri_aux_control_iostate pri_aux_control_iostate_1   (
+	.resetb_pri(resetb_pri_1), .resetb_aux(resetb_aux_1), .disconnect_pri(disconnect_pri_1), 
+		  .disconnect_aux(disconnect_aux_1), .activate_commands_pri(activate_commands_pri_1), .activate_commands_aux(activate_commands_aux_1),
+		 .clk_pri(clk_pri_1), .clk_aux(clk_aux_1), 
+	.active_aux_i(active_aux_1), .active_aux_o(active_aux_2), .active_pri_i(active_pri_1), .active_pri_o(active_pri_2), .disable_aux(disable_aux_1));
+
+	pri_aux_control_iostate pri_aux_control_iostate_2   (
+	.resetb_pri(resetb_pri_2), .resetb_aux(resetb_aux_2), .disconnect_pri(disconnect_pri_2), 
+		  .disconnect_aux(disconnect_aux_2), .activate_commands_pri(activate_commands_pri_2), .activate_commands_aux(activate_commands_aux_2),
+		 .clk_pri(clk_pri_2), .clk_aux(clk_aux_2), 
+	.active_aux_i(active_aux_2), .active_aux_o(active_aux_3), .active_pri_i(active_pri_2), .active_pri_o(active_pri_3), .disable_aux(disable_aux_2));
+
+	pri_aux_control_iostate pri_aux_control_iostate_3   (
+	.resetb_pri(resetb_pri_3), .resetb_aux(resetb_aux_3), .disconnect_pri(disconnect_pri_3), 
+		  .disconnect_aux(disconnect_aux_3), .activate_commands_pri(activate_commands_pri_3), .activate_commands_aux(activate_commands_aux_3),
+		 .clk_pri(clk_pri_3), .clk_aux(clk_aux_3), 
+	.active_aux_i(active_aux_3), .active_aux_o(active_aux), .active_pri_i(active_pri_3), .active_pri_o(active_pri), .disable_aux(disable_aux_3));
+
+	majority_voter #(.WIDTH(2)) mv (
+		.in1({active_pri_2, active_aux_2}),
+		.in2({active_pri_3, active_aux_3}),
+		.in3({active_pri, active_aux}),
+		.out({active_pri_1, active_aux_1}),
+		.err()
+	);
+endmodule
+
+// Triplicate with:
+// python tri.py < pri_aux_control.v > pri_aux_control_tri.v
+
+
+module regbank #(
+	parameter WIDTH=8
+) (
+	input [WIDTH-1:0] D,
+	input RN,
+	output reg [WIDTH-1:0] Q,
+	input clk
+);
+
+	always @(posedge clk or negedge RN) begin
+		if (~RN) Q<=#1 0;
+		else Q<=#1 D;
+	end
+
+endmodule
+/*
+module regbank #(
+	parameter WIDTH=8
+) (
+	input [WIDTH-1:0] D,
+	output reg [WIDTH-1:0] Q,
+	input clk
+);
+
+	always @(posedge clk) Q<=#1 D;
+
+
+endmodule
+*/
+module majority_voter_placeholder_tri (in_1, in_2, in_3, out_1, out_2, out_3,
+									err_1, err_2, err_3);
+    
+    parameter WIDTH = 1;
+	parameter QUIET = 0;
+	parameter HALT = 0;
+    
+	input   [(WIDTH-1):0]   in_1, in_2, in_3;
+    
+    output  [(WIDTH-1):0]   out_1, out_2, out_3;
+    output  err_1, err_2, err_3;
+ 
+	majority_voter #(.WIDTH(WIDTH),.QUIET(QUIET),.HALT(HALT)) mv1 (
+		.in1(in_1),
+		.in2(in_2),
+		.in3(in_3),
+		.out(out_1),
+		.err(err_1)
+	);
+
+	majority_voter #(.WIDTH(WIDTH),.QUIET(QUIET),.HALT(HALT)) mv2 (
+		.in1(in_2),
+		.in2(in_3),
+		.in3(in_1),
+		.out(out_2),
+		.err(err_2)
+	);
+
+	majority_voter #(.WIDTH(WIDTH),.QUIET(QUIET),.HALT(HALT)) mv3 (
+		.in1(in_3),
+		.in2(in_1),
+		.in3(in_2),
+		.out(out_3),
+		.err(err_3)
+	);
+
+
+endmodule
+module monostable (	input A, output Z );
+
+
+	DELAY6_C delay_reset (.Z(reset_del1),.A(Z)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+	DELAY6_C delay_reset1 (.Z(reset_del2),.A(reset_del1)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+	DELAY6_C delay_reset2 (.Z(reset_del3),.A(reset_del2)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+	DELAY6_C delay_reset3 (.Z(reset_del4),.A(reset_del3)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+	DELAY6_C delay_reset4 (.Z(reset_del5),.A(reset_del4)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+	DELAY6_C delay_reset5 (.Z(reset_del),.A(reset_del5)
+		`ifdef RC
+		`else
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+	
+	assign reset_delb = ~reset_del;
+	
+	regbank #(1) regbank (.D(1'b1), .Q(Z), .clk(A), .RN(reset_delb));
+	
+endmodule
+
+
+
+
diff --git a/vldb/code/Testbench/SCA-model/global_defines.v b/vldb/code/Testbench/SCA-model/global_defines.v
new file mode 100644
index 0000000..01954c3
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/global_defines.v
@@ -0,0 +1,11 @@
+
+   `define WithSEUcounter    //to activate single event upset counter logic
+   `define ClkGate_channels  //use clock gating and reset for specific channel
+// `define WithScanPath      //with scan path
+
+   `define RC
+   
+   `ifdef WithSEUcounter
+   `define SEUcnt_nbit 16
+   `endif
+
diff --git a/vldb/code/Testbench/SCA-model/gpio_defines.v b/vldb/code/Testbench/SCA-model/gpio_defines.v
new file mode 100644
index 0000000..82b3bfd
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/gpio_defines.v
@@ -0,0 +1,227 @@
+
+`define GPIO_IOS 32  //  31  modif CHP
+
+//depending on number of GPIO_IOS, define this...
+// for example: if there is 26 GPIO_IOS, define GPIO_LINES26
+//
+
+`define GPIO_LINES31
+
+//
+// Undefine this one if you don't want to remove GPIO block from your design
+// but you also don't need it. When it is undefined, all GPIO ports still
+// remain valid and the core can be synthesized however internally there is
+// no GPIO funationality.
+//
+// Defined by default (duhh !).
+//
+`define GPIO_IMPLEMENTED
+
+//
+// Define to register all WISHBONE outputs.
+//
+// Register outputs if you are using GPIO core as a block and synthesizing
+// and place&routing it separately from the rest of the system.
+//
+// If you do not need registered outputs, you can save some area by not defining
+// this macro. By default it is defined.
+//
+`define GPIO_REGISTERED_WB_OUTPUTS
+
+//
+// Define to register all GPIO pad outputs.
+//
+// Register outputs if you are using GPIO core as a block and synthesizing
+// and place&routing it separately from the rest of the system.
+//
+// If you do not need registered outputs, you can save some area by not defining
+// this macro. By default it is defined.
+//
+`define GPIO_REGISTERED_IO_OUTPUTS
+
+//
+// Implement aux feature. If this define is not defined also aux_i port and 
+// RGPIO_AUX register will be removed
+//
+// Defined by default.
+//
+`define GPIO_AUX_IMPLEMENT
+
+//
+// If this is not defined clk_pad_i will be removed. Input lines will be lached on 
+// positive edge of system clock
+// if disabled defines GPIO_NO_NEGEDGE_FLOPS, GPIO_NO_CLKPAD_LOGIC will have no effect.
+//
+// Defined by default.
+//
+`define GPIO_CLKPAD
+
+//
+// Define to avoid using negative edge clock flip-flops for external clock
+// (caused by NEC register. Instead an inverted external clock with
+// positive edge clock flip-flops will be used.
+// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined
+//
+// By default it is not defined.
+//
+//`define GPIO_NO_NEGEDGE_FLOPS
+
+//
+// If GPIO_NO_NEGEDGE_FLOPS is defined, a mux needs to be placed on external clock
+// clk_pad_i to implement RGPIO_CTRL[NEC] functionality. If no mux is allowed on
+// clock signal, enable the following define.
+// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined
+//
+// By default it is not defined.
+//
+//`define GPIO_NO_CLKPAD_LOGIC
+
+
+//
+// synchronization defines
+//
+// Two synchronization flops to input lineis added.
+// system clock synchronization.
+//
+`define GPIO_SYNC_IN_WB
+
+//
+// Add synchronization flops to external clock input line. Gpio will have just one clock domain, 
+// everithing will be synchronized to wishbone clock. External clock muas be at least 2-3x slower 
+// as systam clock.
+//
+`define GPIO_SYNC_CLK_WB
+
+//
+// Add synchronization to input pads. synchronization to external clock.
+// Don't hawe any effect if GPIO_SYNC_CLK_WB is defined.
+//
+//`define GPIO_SYNC_IN_CLK
+
+//
+// Add synchronization flops between system clock and external clock.
+// Only possible if external clock is enabled and clock synchroization is disabled.
+//
+//`define GPIO_SYNC_IN_CLK_WB
+
+
+
+// 
+// Undefine if you don't need to read GPIO registers except for RGPIO_IN register.
+// When it is undefined all reads of GPIO registers return RGPIO_IN register. This
+// is usually useful if you want really small area (for example when implemented in
+// FPGA).
+//
+// To follow GPIO IP core specification document this one must be defined. Also to
+// successfully run the test bench it must be defined. By default it is defined.
+//
+`define GPIO_READREGS
+
+//
+// Full WISHBONE address decoding
+//
+// It is is undefined, partial WISHBONE address decoding is performed.
+// Undefine it if you need to save some area.
+//
+// By default it is defined.
+//
+`define GPIO_FULL_DECODE
+
+//
+// Strict 32-bit WISHBONE access
+//
+// If this one is defined, all WISHBONE accesses must be 32-bit. If it is
+// not defined, err_o is asserted whenever 8- or 16-bit access is made.
+// Undefine it if you need to save some area.
+//
+// By default it is defined.
+//
+//`define GPIO_STRICT_32BIT_ACCESS
+//
+`ifdef GPIO_STRICT_32BIT_ACCESS
+`else
+// added by gorand :
+// if GPIO_STRICT_32BIT_ACCESS is not defined,
+// depending on number of gpio I/O lines, the following are defined :
+// if the number of I/O lines is in range 1-8,   GPIO_WB_BYTES1 is defined,
+// if the number of I/O lines is in range 9-16,  GPIO_WB_BYTES2 is defined,
+// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined,
+// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined,
+
+`define GPIO_WB_BYTES4
+//`define GPIO_WB_BYTES3
+//`define GPIO_WB_BYTES2
+//`define GPIO_WB_BYTES1
+
+`endif
+
+//
+// WISHBONE address bits used for full decoding of GPIO registers.
+//
+`define GPIO_ADDRHH 7
+`define GPIO_ADDRHL 6
+`define GPIO_ADDRLH 1
+`define GPIO_ADDRLL 0
+
+//
+// Bits of WISHBONE address used for partial decoding of GPIO registers.
+//
+// Default 5:2.
+//
+`define GPIO_OFS_BITS	`GPIO_ADDRHL-1:`GPIO_ADDRLH+1
+
+//
+// Addresses of GPIO registers
+//
+// To comply with GPIO IP core specification document they must go from
+// address 0 to address 0x18 in the following order: RGPIO_IN, RGPIO_OUT,
+// RGPIO_OE, RGPIO_INTE, RGPIO_PTRIG, RGPIO_AUX and RGPIO_CTRL
+//
+// If particular register is not needed, it's address definition can be omitted
+// and the register will not be implemented. Instead a fixed default value will
+// be used.
+//
+`define GPIO_RGPIO_IN		  4'h0	// Address 0x00
+`define GPIO_RGPIO_OUT		4'h1	// Address 0x04
+`define GPIO_RGPIO_OE		  4'h2	// Address 0x08
+`define GPIO_RGPIO_INTE		4'h3	// Address 0x0c
+`define GPIO_RGPIO_PTRIG	4'h4	// Address 0x10
+
+`ifdef GPIO_AUX_IMPLEMENT
+`define GPIO_RGPIO_AUX		4'h5	// Address 0x14
+`endif // GPIO_AUX_IMPLEMENT
+
+`define GPIO_RGPIO_CTRL		4'h6	// Address 0x18
+`define GPIO_RGPIO_INTS		4'h7	// Address 0x1c
+
+`ifdef GPIO_CLKPAD
+`define GPIO_RGPIO_ECLK   4'h8  // Address 0x20
+`define GPIO_RGPIO_NEC    4'h9  // Address 0x24
+`endif //  GPIO_CLKPAD
+
+//
+// Default values for unimplemented GPIO registers
+//
+`define GPIO_DEF_RGPIO_IN	`GPIO_IOS'h0
+`define GPIO_DEF_RGPIO_OUT	`GPIO_IOS'h0
+`define GPIO_DEF_RGPIO_OE	`GPIO_IOS'h0
+`define GPIO_DEF_RGPIO_INTE	`GPIO_IOS'h0
+`define GPIO_DEF_RGPIO_PTRIG	`GPIO_IOS'h0
+`define GPIO_DEF_RGPIO_AUX	`GPIO_IOS'h0
+`define GPIO_DEF_RGPIO_CTRL	`GPIO_IOS'h0
+`define GPIO_DEF_RGPIO_ECLK `GPIO_IOS'h0
+`define GPIO_DEF_RGPIO_NEC `GPIO_IOS'h0
+
+
+//
+// RGPIO_CTRL bits
+//
+// To comply with the GPIO IP core specification document they must go from
+// bit 0 to bit 1 in the following order: INTE, INT
+//
+`define GPIO_RGPIO_CTRL_INTE		0
+`define GPIO_RGPIO_CTRL_INTS		1
+
+
+
+
diff --git a/vldb/code/Testbench/SCA-model/majority_voter.v b/vldb/code/Testbench/SCA-model/majority_voter.v
new file mode 100644
index 0000000..29ca486
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/majority_voter.v
@@ -0,0 +1,71 @@
+`ifndef MAJORITY_VOTER_V
+`define MAJORITY_VOTER_V
+
+
+`timescale 1ns/1ps
+module majority_voter (in1, in2, in3, out, err);
+    // synopsys template
+    
+    parameter WIDTH = 1;
+	parameter QUIET = 0;
+	parameter HALT = 0;
+    
+    input   [(WIDTH-1):0]   in1, in2, in3;
+    
+    output  [(WIDTH-1):0]   out;
+    output          	    err;
+    
+    reg     [(WIDTH-1):0]   out;
+    reg     	    	    err;
+    
+	reg errdel ;
+	
+    always @* begin
+    	err = 0;
+		out = vote (in1,in2,in3);
+		
+		
+    end
+	
+`ifdef DC
+`else
+	always @* begin
+		errdel <=#0.001 err;
+		
+		if (errdel && err) begin
+			if (!QUIET) begin
+				//$display("........................%d: SEU!!! %m", $time);
+				if (HALT) $stop;
+			end
+		end
+	end
+`endif
+	
+    
+    function vote_atom;
+    	input in1,in2,in3;
+    	begin
+		if (in1 != in2) begin
+    	    		vote_atom   = in3;
+			err     	= 1;
+		end
+		else begin
+		    	if (in2 != in3) err = 1;
+    	    		vote_atom = in1;
+		end
+    	end
+    endfunction
+    
+    function [(WIDTH-1):0] vote;
+        input   [(WIDTH-1):0]   in1, in2, in3;
+	integer i;
+    	begin
+	    for (i=0; i<WIDTH; i=i+1)
+	    	vote[i] = vote_atom( in1[i], in2[i], in3[i] );
+	end
+    endfunction
+    
+ 
+endmodule
+
+`endif //MAJORITY_VOTER_V
diff --git a/vldb/code/Testbench/SCA-model/reset_logic.v b/vldb/code/Testbench/SCA-model/reset_logic.v
new file mode 100644
index 0000000..84cd4ac
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/reset_logic.v
@@ -0,0 +1,354 @@
+/////////////////////////////////////////////////////////////////////////////
+// Design Name:....GBT_SCA                                                 //
+// Module Name:....ResetLogic.v (TRI Version)                              //
+// Company:........CERN (PH-ESE)                                           //
+// Made by:........Alessandro Caratelli                                    //
+//                                                                         //
+// Date:...........17/Aug/2013 - Created                                   //
+//                 13/Dec/2013 - Changed adding voters                     //
+//                 31/Jan/2014 - changed voter & resyntetised in 3 steps   //
+/////////////////////////////////////////////////////////////////////////////
+
+// -> Define "use_syn_netlist" and set the "cadence dc::set_dont_touch [..]"
+//    pragma on the instantiation of this module to avoid unwanted optimizations
+
+`define use_syn_netlist
+`timescale 1ns / 1ps
+
+
+`ifndef use_syn_netlist /////////////////////////////////////////////////////
+
+module ResetLogicVoted(
+	input  clk_1,          clk_2,          clk_3,
+	input  PromtReset_1,   PromtReset_2,	
+	input  ElinkReset_1,   ElinkReset_2,   ElinkReset_3,
+ 	input  PowerUpReset_1, PowerUpReset_2, PowerUpReset_3,	
+	output wire SystemReset_1,  SystemReset_2,  SystemReset_3
+	);
+	wire reset_1_unvoted, reset_2_unvoted, reset_3_unvoted;
+	
+	// cadence dc::set_dont_touch RST_Logic
+	
+	ResetLogic RST_Logic(
+		.ElinkReset_1(ElinkReset_1),
+		.ElinkReset_2(ElinkReset_2),
+		.ElinkReset_3(ElinkReset_3),
+ 		.PowerUpReset_1(PowerUpReset_1),
+		.PowerUpReset_2(PowerUpReset_2),
+		.PowerUpReset_3(PowerUpReset_3),
+		.PromtReset_1(PromtReset_1),
+		.PromtReset_2(PromtReset_2),	
+		.SystemReset_1(reset_1_unvoted),
+		.SystemReset_2(reset_2_unvoted),
+		.SystemReset_3(reset_3_unvoted),
+		.clk_1(~clk_1),
+		.clk_2(~clk_2),
+		.clk_3(~clk_3)
+	); 
+	res_voter mvres1 (.in1(reset_1_unvoted),.in2(reset_2_unvoted),.in3(reset_3_unvoted), .out(SystemReset_1));
+	res_voter mvres2 (.in1(reset_2_unvoted),.in2(reset_3_unvoted),.in3(reset_1_unvoted), .out(SystemReset_2));     
+	res_voter mvres3 (.in1(reset_3_unvoted),.in2(reset_1_unvoted),.in3(reset_2_unvoted), .out(SystemReset_3));
+	
+endmodule
+
+module res_voter(
+	input  in1, in2, in3,
+	output wire out
+	);
+	assign out = (in1 != in2) ? in3 : in1;
+endmodule 
+
+
+module ResetLogic (
+	input  clk_1,          clk_2,          clk_3,
+	input  PromtReset_1,   PromtReset_2,	//
+	input  ElinkReset_1,   ElinkReset_2,   ElinkReset_3,//
+ 	input  PowerUpReset_1, PowerUpReset_2, PowerUpReset_3,//	
+	output SystemReset_1,  SystemReset_2,  SystemReset_3//
+	);
+	
+	// cadence dc::set_dont_touch RstOr1
+	// cadence dc::set_dont_touch RstOr2
+	// cadence dc::set_dont_touch RstOr3
+	// cadence dc::set_dont_touch promtAnd1
+	// cadence dc::set_dont_touch promtAnd2
+	// cadence dc::set_dont_touch promtAnd3
+	
+	ResMonostable ResMonostable_1 (.in(ElinkReset_1), .out(ElinkResEvent_1), .clk(clk_1), .res(PowerUpReset_1));
+	ResMonostable ResMonostable_2 (.in(ElinkReset_2), .out(ElinkResEvent_2), .clk(clk_2), .res(PowerUpReset_2));
+	ResMonostable ResMonostable_3 (.in(ElinkReset_3), .out(ElinkResEvent_3), .clk(clk_3), .res(PowerUpReset_3));
+	
+	AND2_B promtAnd1(.A(PromtReset_1), .B(PromtReset_2), .Z (promtOut1));
+	AND2_B promtAnd2(.A(PromtReset_1), .B(PromtReset_2), .Z (promtOut2));
+	AND2_B promtAnd3(.A(PromtReset_1), .B(PromtReset_2), .Z (promtOut3));	
+	
+	OR3_B RstOr1 (.Z(SystemReset_1), .A(ElinkResEvent_1), .B(promtOut1), .C(PowerUpReset_1));
+	OR3_B RstOr2 (.Z(SystemReset_2), .A(ElinkResEvent_2), .B(promtOut2), .C(PowerUpReset_2));
+	OR3_B RstOr3 (.Z(SystemReset_3), .A(ElinkResEvent_3), .B(promtOut3), .C(PowerUpReset_3));
+
+endmodule
+
+`timescale 1ns / 1ps
+module ResMonostable (
+	input  clk,
+	input  res,
+	input  in,
+	output out
+);	
+	Dflipflop catch(.D(1'b1), .Q(ev),  .clk(in),  .RN(~reset_del));
+	Dflipflop store(.D(ev),   .Q(out), .clk(clk), .RN(~res));
+	
+	DELAY6_C delay_reset (.Z(reset_del1),.A(out)
+		`ifndef RC
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+	DELAY6_C delay_reset1 (.Z(reset_del2),.A(reset_del1)
+		`ifndef RC
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+	DELAY6_C delay_reset2 (.Z(reset_del3),.A(reset_del2)
+		`ifndef RC
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+	DELAY6_C delay_reset3 (.Z(reset_del4),.A(reset_del3)
+		`ifndef RC
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+	DELAY6_C delay_reset4 (.Z(reset_del5),.A(reset_del4)
+		`ifndef RC
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);
+	DELAY6_C delay_reset5 (.Z(reset_del),.A(reset_del5)
+		`ifndef RC
+			, .VDD(), .GND(), .NW(), .SX()
+		`endif
+	);		
+endmodule	
+	
+`timescale 1ns / 1ps	
+module Dflipflop(
+	input  clk, RN, D,
+	output reg Q
+);
+	always @(posedge clk or negedge RN) begin
+		if (~RN) Q <=#1 1'b0;
+		else Q <=#1 D;
+	end
+endmodule	
+
+
+
+`else ////////////////////////////////////////////////////////////////////
+
+// Generated by Cadence Encounter(R) RTL Compiler RC9.1.203 - v09.10-s242_1
+
+module Dflipflop_r2g_r2g(clk, RN, D, Q);
+  input clk, RN, D;
+  output Q;
+  wire clk, RN, D;
+  wire Q;
+  DFFR_E Q_reg(.RN (RN), .CLK (clk), .D (1'b1), .Q (Q), .QBAR ());
+endmodule
+
+module Dflipflop_r2g_5_r2g(clk, RN, D, Q);
+  input clk, RN, D;
+  output Q;
+  wire clk, RN, D;
+  wire Q;
+  DFFR_E Q_reg(.RN (RN), .CLK (clk), .D (D), .Q (Q), .QBAR ());
+endmodule
+
+module ResMonostable_r2g_r2g(clk, res, in, out);
+  input clk, res, in;
+  output out;
+  wire clk, res, in;
+  wire out;
+  wire ev, n_0, n_1, reset_del, reset_del1, reset_del2, reset_del3,
+       reset_del4;
+  wire reset_del5;
+  Dflipflop_r2g_r2g catch(.clk (in), .RN (n_1), .D (1'b1), .Q (ev));
+  Dflipflop_r2g_5_r2g store(.clk (clk), .RN (n_0), .D (ev), .Q (out));
+  DELAY6_C delay_reset(.A (out), .Z (reset_del1));
+  DELAY6_C delay_reset1(.A (reset_del1), .Z (reset_del2));
+  DELAY6_C delay_reset2(.A (reset_del2), .Z (reset_del3));
+  DELAY6_C delay_reset3(.A (reset_del3), .Z (reset_del4));
+  DELAY6_C delay_reset4(.A (reset_del4), .Z (reset_del5));
+  DELAY6_C delay_reset5(.A (reset_del5), .Z (reset_del));
+  INVERT_A p214748365A(.A (reset_del), .Z (n_1));
+  INVERT_A p214748365A3(.A (res), .Z (n_0));
+endmodule
+
+module Dflipflop_r2g_4_r2g(clk, RN, D, Q);
+  input clk, RN, D;
+  output Q;
+  wire clk, RN, D;
+  wire Q;
+  DFFR_E Q_reg(.RN (RN), .CLK (clk), .D (1'b1), .Q (Q), .QBAR ());
+endmodule
+
+module Dflipflop_r2g_3_r2g(clk, RN, D, Q);
+  input clk, RN, D;
+  output Q;
+  wire clk, RN, D;
+  wire Q;
+  DFFR_E Q_reg(.RN (RN), .CLK (clk), .D (D), .Q (Q), .QBAR ());
+endmodule
+
+module ResMonostable_r2g_12_r2g(clk, res, in, out);
+  input clk, res, in;
+  output out;
+  wire clk, res, in;
+  wire out;
+  wire ev, n_0, n_1, reset_del, reset_del1, reset_del2, reset_del3,
+       reset_del4;
+  wire reset_del5;
+  Dflipflop_r2g_4_r2g catch(.clk (in), .RN (n_1), .D (1'b1), .Q (ev));
+  Dflipflop_r2g_3_r2g store(.clk (clk), .RN (n_0), .D (ev), .Q (out));
+  DELAY6_C delay_reset(.A (out), .Z (reset_del1));
+  DELAY6_C delay_reset1(.A (reset_del1), .Z (reset_del2));
+  DELAY6_C delay_reset2(.A (reset_del2), .Z (reset_del3));
+  DELAY6_C delay_reset3(.A (reset_del3), .Z (reset_del4));
+  DELAY6_C delay_reset4(.A (reset_del4), .Z (reset_del5));
+  DELAY6_C delay_reset5(.A (reset_del5), .Z (reset_del));
+  INVERT_A p214748365A(.A (reset_del), .Z (n_1));
+  INVERT_A p214748365A3(.A (res), .Z (n_0));
+endmodule
+
+module Dflipflop_r2g_2_r2g(clk, RN, D, Q);
+  input clk, RN, D;
+  output Q;
+  wire clk, RN, D;
+  wire Q;
+  DFFR_E Q_reg(.RN (RN), .CLK (clk), .D (1'b1), .Q (Q), .QBAR ());
+endmodule
+
+module Dflipflop_r2g_1_r2g(clk, RN, D, Q);
+  input clk, RN, D;
+  output Q;
+  wire clk, RN, D;
+  wire Q;
+  DFFR_E Q_reg(.RN (RN), .CLK (clk), .D (D), .Q (Q), .QBAR ());
+endmodule
+
+module ResMonostable_r2g_11_r2g(clk, res, in, out);
+  input clk, res, in;
+  output out;
+  wire clk, res, in;
+  wire out;
+  wire ev, n_0, n_1, reset_del, reset_del1, reset_del2, reset_del3,
+       reset_del4;
+  wire reset_del5;
+  Dflipflop_r2g_2_r2g catch(.clk (in), .RN (n_1), .D (1'b1), .Q (ev));
+  Dflipflop_r2g_1_r2g store(.clk (clk), .RN (n_0), .D (ev), .Q (out));
+  DELAY6_C delay_reset(.A (out), .Z (reset_del1));
+  DELAY6_C delay_reset1(.A (reset_del1), .Z (reset_del2));
+  DELAY6_C delay_reset2(.A (reset_del2), .Z (reset_del3));
+  DELAY6_C delay_reset3(.A (reset_del3), .Z (reset_del4));
+  DELAY6_C delay_reset4(.A (reset_del4), .Z (reset_del5));
+  DELAY6_C delay_reset5(.A (reset_del5), .Z (reset_del));
+  INVERT_A p214748365A(.A (reset_del), .Z (n_1));
+  INVERT_A p214748365A3(.A (res), .Z (n_0));
+endmodule
+
+module ResetLogic_r2g(clk_1, clk_2, clk_3, PromtReset_1, PromtReset_2,
+     ElinkReset_1, ElinkReset_2, ElinkReset_3, PowerUpReset_1,
+     PowerUpReset_2, PowerUpReset_3, SystemReset_1, SystemReset_2,
+     SystemReset_3);
+  input clk_1, clk_2, clk_3, PromtReset_1, PromtReset_2, ElinkReset_1,
+       ElinkReset_2, ElinkReset_3, PowerUpReset_1, PowerUpReset_2,
+       PowerUpReset_3;
+  output SystemReset_1, SystemReset_2, SystemReset_3;
+  wire clk_1, clk_2, clk_3, PromtReset_1, PromtReset_2, ElinkReset_1,
+       ElinkReset_2, ElinkReset_3, PowerUpReset_1, PowerUpReset_2,
+       PowerUpReset_3;
+  wire SystemReset_1, SystemReset_2, SystemReset_3;
+  wire ElinkResEvent_1, ElinkResEvent_2, ElinkResEvent_3, n_3, n_4,
+       n_19, n_21, n_23;
+  wire promtOut1, promtOut2, promtOut3;
+  ResMonostable_r2g_r2g ResMonostable_1(.clk (clk_1), .res
+       (PowerUpReset_1), .in (ElinkReset_1), .out (ElinkResEvent_1));
+  ResMonostable_r2g_12_r2g ResMonostable_2(.clk (clk_2), .res
+       (PowerUpReset_2), .in (ElinkReset_2), .out (ElinkResEvent_2));
+  ResMonostable_r2g_11_r2g ResMonostable_3(.clk (clk_3), .res
+       (PowerUpReset_3), .in (ElinkReset_3), .out (ElinkResEvent_3));
+  OR3_B RstOr1(.A (ElinkResEvent_1), .B (promtOut1), .C
+       (PowerUpReset_1), .Z (n_21));
+  OR3_B RstOr2(.A (ElinkResEvent_2), .B (promtOut2), .C
+       (PowerUpReset_2), .Z (n_23));
+  OR3_B RstOr3(.A (ElinkResEvent_3), .B (promtOut3), .C
+       (PowerUpReset_3), .Z (n_19));
+  BUFFER_F drc(.A (n_19), .Z (SystemReset_3));
+  BUFFER_F drc8(.A (n_21), .Z (SystemReset_1));
+  BUFFER_F drc9(.A (n_23), .Z (SystemReset_2));
+  BUFFER_C p214748365A5(.A (PromtReset_1), .Z (n_3));
+  BUFFER_C p214748365A7(.A (PromtReset_2), .Z (n_4));
+  AND2_B promtAnd1(.A (n_3), .B (n_4), .Z (promtOut1));
+  AND2_B promtAnd2(.A (n_3), .B (n_4), .Z (promtOut2));
+  AND2_B promtAnd3(.A (n_3), .B (n_4), .Z (promtOut3));
+endmodule
+
+module res_voter_r2g(in1, in2, in3, out);
+  input in1, in2, in3;
+  output out;
+  wire in1, in2, in3;
+  wire out;
+  ADDF_F g2(.A (in3), .B (in1), .CIN (in2), .COUT (out), .SUM ());
+endmodule
+
+module res_voter_r2g_2(in1, in2, in3, out);
+  input in1, in2, in3;
+  output out;
+  wire in1, in2, in3;
+  wire out;
+  ADDF_F g2(.A (in3), .B (in1), .CIN (in2), .COUT (out), .SUM ());
+endmodule
+
+module res_voter_r2g_1(in1, in2, in3, out);
+  input in1, in2, in3;
+  output out;
+  wire in1, in2, in3;
+  wire out;
+  ADDF_F g2(.A (in3), .B (in1), .CIN (in2), .COUT (out), .SUM ());
+endmodule
+
+module ResetLogicVoted(clk_1, clk_2, clk_3, PromtReset_1,
+     PromtReset_2, ElinkReset_1, ElinkReset_2, ElinkReset_3,
+     PowerUpReset_1, PowerUpReset_2, PowerUpReset_3, SystemReset_1,
+     SystemReset_2, SystemReset_3);
+  input clk_1, clk_2, clk_3, PromtReset_1, PromtReset_2, ElinkReset_1,
+       ElinkReset_2, ElinkReset_3, PowerUpReset_1, PowerUpReset_2,
+       PowerUpReset_3;
+  output SystemReset_1, SystemReset_2, SystemReset_3;
+  wire clk_1, clk_2, clk_3, PromtReset_1, PromtReset_2, ElinkReset_1,
+       ElinkReset_2, ElinkReset_3, PowerUpReset_1, PowerUpReset_2,
+       PowerUpReset_3;
+  wire SystemReset_1, SystemReset_2, SystemReset_3;
+  wire n_0, n_1, n_2, n_4, n_5, n_6, reset_1_unvoted, reset_2_unvoted;
+  wire reset_3_unvoted;
+  ResetLogic_r2g RST_Logic(.clk_1 (n_4), .clk_2 (n_2), .clk_3 (n_1),
+       .PromtReset_1 (PromtReset_1), .PromtReset_2 (PromtReset_2),
+       .ElinkReset_1 (ElinkReset_1), .ElinkReset_2 (ElinkReset_2),
+       .ElinkReset_3 (ElinkReset_3), .PowerUpReset_1 (n_6),
+       .PowerUpReset_2 (n_0), .PowerUpReset_3 (n_5), .SystemReset_1
+       (reset_1_unvoted), .SystemReset_2 (reset_2_unvoted),
+       .SystemReset_3 (reset_3_unvoted));
+  res_voter_r2g mvres1(.in1 (reset_1_unvoted), .in2 (reset_2_unvoted),
+       .in3 (reset_3_unvoted), .out (SystemReset_1));
+  res_voter_r2g_2 mvres2(.in1 (reset_2_unvoted), .in2
+       (reset_3_unvoted), .in3 (reset_1_unvoted), .out (SystemReset_2));
+  res_voter_r2g_1 mvres3(.in1 (reset_3_unvoted), .in2
+       (reset_1_unvoted), .in3 (reset_2_unvoted), .out (SystemReset_3));
+  BUFFER_C p214748365A9(.A (PowerUpReset_1), .Z (n_6));
+  BUFFER_C p214748365A10(.A (PowerUpReset_3), .Z (n_5));
+  INVERT_A p214748365A11(.A (clk_1), .Z (n_4));
+  INVERT_A p214748365A13(.A (clk_2), .Z (n_2));
+  INVERT_A p214748365A14(.A (clk_3), .Z (n_1));
+  BUFFER_C p214748365A15(.A (PowerUpReset_2), .Z (n_0));
+endmodule
+
+`endif
diff --git a/vldb/code/Testbench/SCA-model/spi_defines.v b/vldb/code/Testbench/SCA-model/spi_defines.v
new file mode 100644
index 0000000..4908e79
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/spi_defines.v
@@ -0,0 +1,43 @@
+
+
+
+
+
+`ifndef SPI_DEFINES
+`define SPI_DEFINES             
+	`define SPI_DIVIDER_LEN        16   
+	`define SPI_MAX_CHAR          128  
+	`define SPI_CHAR_LEN_BITS       7
+	`define SPI_SS_NB               8    
+	`define SPI_OFS_BITS          4:2
+	`define SPI_CTRL_BIT_NB        14
+	
+	//REGISTER ASSIGNAMENT	
+	`define SPI_RX_0                0
+	`define SPI_RX_1                1
+	`define SPI_RX_2                2
+	`define SPI_RX_3                3
+	`define SPI_TX_0                0
+	`define SPI_TX_1                1
+	`define SPI_TX_2                2
+	`define SPI_TX_3                3
+	`define SPI_CTRL                4
+	`define SPI_DEVIDE              5
+	`define SPI_SS                  6
+	`define SPI_GO_REG              7
+
+
+	// Control register bit position
+	`define SPI_CTRL_ASS            13
+	`define SPI_CTRL_IE             12
+	`define SPI_CTRL_LSB            11
+	`define SPI_CTRL_TX_NEGEDGE     10
+	`define SPI_CTRL_RX_NEGEDGE     9
+	`define SPI_CTRL_GO             8
+	`define SPI_CTRL_INV_SCLK       7
+	`define SPI_CTRL_CHAR_LEN       6:0
+`endif
+
+
+
+
diff --git a/vldb/code/Testbench/SCA-model/timescale.v b/vldb/code/Testbench/SCA-model/timescale.v
new file mode 100644
index 0000000..6b2825c
--- /dev/null
+++ b/vldb/code/Testbench/SCA-model/timescale.v
@@ -0,0 +1 @@
+`timescale 1ns / 1ps
\ No newline at end of file
diff --git a/vldb/code/Testbench/testbench_tools.vhd b/vldb/code/Testbench/testbench_tools.vhd
new file mode 100644
index 0000000..b24ff31
--- /dev/null
+++ b/vldb/code/Testbench/testbench_tools.vhd
@@ -0,0 +1,85 @@
+library ieee;
+use Std.TextIO.all;
+use ieee.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+package tb_tools_package is
+
+	function to_bstring(sl : std_logic) return string;
+	function to_bstring(slv : std_logic_vector) return string;
+	function to_hstring(sv: Std_Logic_Vector) return string;
+	procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR; JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
+
+end tb_tools_package;
+
+package body tb_tools_package is
+
+	function to_bstring(sl : std_logic) return string is
+	  variable sl_str_v : string(1 to 3);  -- std_logic image with quotes around
+	begin
+	  sl_str_v := std_logic'image(sl);
+	  return "" & sl_str_v(2);  -- "" & character to get string
+	end function;
+
+	function to_bstring(slv : std_logic_vector) return string is
+	  alias    slv_norm : std_logic_vector(1 to slv'length) is slv;
+	  variable sl_str_v : string(1 to 1);  -- String of std_logic
+	  variable res_v    : string(1 to slv'length);
+	begin
+	  for idx in slv_norm'range loop
+		sl_str_v := to_bstring(slv_norm(idx));
+		res_v(idx) := sl_str_v(1);
+	  end loop;
+	  return res_v;
+	end function;
+	 
+	function to_hstring(sv: Std_Logic_Vector) return string is
+		  use Std.TextIO.all;
+		  
+		  variable bv: bit_vector(sv'range) := to_bitvector(sv);
+		  variable lp: line;
+		begin
+		  hwrite(lp, bv);
+		  return lp.all;
+	end;
+
+	procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
+		JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is      
+		  variable quad: bit_vector(0 to 3);
+		  constant ne:   integer := (value'length+3)/4;
+		  constant displaybits: integer := ne*4;
+		  constant inputbits: integer := value'length;
+		  constant emptybits: integer := displaybits - inputbits;
+		  variable bv:   bit_vector(0 to value'length+4) := (others => '0');
+		  variable s:    string(1 to ne);
+		begin
+
+		  bv(emptybits to (emptybits+value'length-1)) := value;
+		
+		  for i in 0 to ne-1 loop
+			quad := bv(4*i to 4*i+3);
+			case quad is
+			  when x"0" => s(i+1) := '0';
+			  when x"1" => s(i+1) := '1';
+			  when x"2" => s(i+1) := '2';
+			  when x"3" => s(i+1) := '3';
+			  when x"4" => s(i+1) := '4';
+			  when x"5" => s(i+1) := '5';
+			  when x"6" => s(i+1) := '6';
+			  when x"7" => s(i+1) := '7';
+			  when x"8" => s(i+1) := '8';
+			  when x"9" => s(i+1) := '9';
+			  when x"A" => s(i+1) := 'A';
+			  when x"B" => s(i+1) := 'B';
+			  when x"C" => s(i+1) := 'C';
+			  when x"D" => s(i+1) := 'D';
+			  when x"E" => s(i+1) := 'E';
+			  when x"F" => s(i+1) := 'F';
+			end case;
+		  end loop;
+		  write(L, s, JUSTIFIED, FIELD);
+	end HWRITE;
+	
+end tb_tools_package;
+
+
diff --git a/vldb/code/Testbench/testbench_top.vhd b/vldb/code/Testbench/testbench_top.vhd
new file mode 100644
index 0000000..c58cf1c
--- /dev/null
+++ b/vldb/code/Testbench/testbench_top.vhd
@@ -0,0 +1,439 @@
+-- IEEE VHDL standard library:
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.SCA_PKG.all;
+use work.tb_tools_package.all;
+
+USE std.textio.all;
+use std.env.all;
+
+--=================================================================================================--
+--#######################################   Entity   ##############################################--
+--=================================================================================================--
+
+entity testbench_top is
+	port(
+
+		GPIO		: inout std_logic_vector(31 downto 0);
+
+		SCL_1				: out STD_LOGIC_VECTOR(15 downto 0);
+		SCLEN_1				: out STD_LOGIC_VECTOR(15 downto 0);
+		SDA_in_1			: in  STD_LOGIC_VECTOR(15 downto 0);
+		SDA_out_1			: out STD_LOGIC_VECTOR(15 downto 0);
+
+        JTAG_TDO            : out STD_LOGIC;
+        JTAG_TCK            : out STD_LOGIC;
+        JTAG_TMS            : out STD_LOGIC
+	);
+end testbench_top;
+
+--=================================================================================================--
+--####################################   Architecture   ###########################################--
+--=================================================================================================--
+
+architecture behabioral of testbench_top is
+
+    -- Signal declaration (Testbench)
+	signal powerup_reset			: std_logic := '1';
+	signal prompt_reset				: std_logic := '1';
+
+	signal general_reset_n			: std_logic	:= '1';
+	signal general_reset			: std_logic	:= '0';
+
+	signal sca_enable				: std_logic_vector(0 downto 0)	:= "1";
+	signal start_transaction		: std_logic := '0';
+	signal start_reset				: std_logic := '0';
+	signal start_connect			: std_logic := '0';
+	signal start_transaction_s0		: std_logic := '0';
+	signal start_reset_s0			: std_logic := '0';
+	signal start_connect_s0			: std_logic := '0';
+	signal inject_crc_error         : std_logic := '0';
+
+	signal hdlc_from_gbtsc			: std_logic_vector(1 downto 0)	:= "11";
+	signal hdlc_to_gbtsc			: std_logic_vector(1 downto 0)	:= "11";
+
+	signal hdlc_to_sca				: std_logic := '1';
+	signal hdlc_from_sca			: std_logic := '1';
+	signal hdlc_clock				: std_logic	:= '0';
+
+    signal tx_addr					: std_logic_vector(7 downto 0)	:= x"00";
+    signal tx_trid					: std_logic_vector(7 downto 0)	:= x"01";
+    signal tx_ch					: std_logic_vector(7 downto 0)	:= x"00";
+    signal tx_cmd					: std_logic_vector(7 downto 0)	:= x"02";
+    signal tx_data					: std_logic_vector(31 downto 0)	:= x"0000FF00";
+
+	signal rx_received				: std_logic						:= '0';
+	signal rx_received_s0			: std_logic						:= '0';
+    signal rx_addr					: std_logic_vector(7 downto 0)	:= x"00";
+    signal rx_ctrl					: std_logic_vector(7 downto 0)	:= x"00";
+    signal rx_trid					: std_logic_vector(7 downto 0)	:= x"00";
+    signal rx_ch					: std_logic_vector(7 downto 0)	:= x"00";
+    signal rx_len					: std_logic_vector(7 downto 0)	:= x"00";
+    signal rx_err					: std_logic_vector(7 downto 0)	:= x"00";
+    signal rx_data					: std_logic_vector(31 downto 0)	:= x"00000000";
+
+	signal GPIO_i					: std_logic_vector(31 downto 0);
+	signal GPIO_o					: std_logic_vector(31 downto 0);
+	signal GPIO_oe					: std_logic_vector(31 downto 0);
+	signal SDA_out_inv_1			: std_logic_vector(15 downto 0);
+
+    -- Component declaration (SCA Model)
+	COMPONENT TOP_core_sca_tri
+        PORT (
+         -- Elink HDLC
+         link_clk_1			: in  STD_LOGIC;
+         link_clk_aux_1		: in  STD_LOGIC;
+         disable_aux_1		: in  STD_LOGIC;
+         tx_sd_1			: out STD_LOGIC;
+         tx_sd_aux_1		: out STD_LOGIC;
+         rx_sd_1			: in  STD_LOGIC;
+         rx_sd_aux_1		: in  STD_LOGIC;
+         tx_adr_1			: in  STD_LOGIC_VECTOR(7 downto 0);
+         CRE_1				: out STD_LOGIC_VECTOR(7 downto 0);
+         active_aux_1		: out STD_LOGIC;
+
+         -- JTAG
+         JTAG_TCK_pad_o_1	: out STD_LOGIC;
+         JTAG_TMS_pad_o_1	: out STD_LOGIC;
+         JTAG_TDO_pad_o_1	: out STD_LOGIC;
+         JTAG_TDI_pad_i_1	: in  STD_LOGIC;
+         JTAG_RST_pad_o_1	: out STD_LOGIC;
+
+         -- SPI
+         SPI_sclk_pad_o_1	: out STD_LOGIC;
+         SPI_ss_pad_o_1		: out STD_LOGIC_VECTOR(7 downto 0);
+         SPI_miso_pad_i_1	: in  STD_LOGIC;
+         SPI_mosi_pad_o_1	: out STD_LOGIC;
+
+         -- GPIO
+         GPIO_ext_pad_o_1	: out STD_LOGIC_VECTOR(31 downto 0);
+         GPIO_ext_padOE_o_1	: out STD_LOGIC_VECTOR(31 downto 0);
+         GPIO_clk_pad_i_1	: in  STD_LOGIC;
+         GPIO_ext_pad_i_1	: in  STD_LOGIC_VECTOR(31 downto 0);
+
+         -- I2C
+         SCL_1				: out STD_LOGIC_VECTOR(15 downto 0);
+		 SCLEN_1			: out STD_LOGIC_VECTOR(15 downto 0);
+         SDA_in_1			: in  STD_LOGIC_VECTOR(15 downto 0);
+         SDA_out_inv_1		: out STD_LOGIC_VECTOR(15 downto 0);
+
+         -- ADC
+         ADC_wb_RES_1		: out STD_LOGIC;
+         ADC_wb_CLK_1		: out STD_LOGIC;
+         ADC_wb_SEL_1		: out STD_LOGIC;
+         ADC_wb_WE_1		: out STD_LOGIC;
+         ADC_wb_STB_1		: out STD_LOGIC;
+         ADC_wb_CYC_1		: out STD_LOGIC;
+         ADC_wb_ADR_1		: out STD_LOGIC_VECTOR(3 downto 0);
+         ADC_wb_DATi_1		: out STD_LOGIC_VECTOR(31 downto 0);
+         ADC_wb_DATo_1		: in  STD_LOGIC_VECTOR(31 downto 0);
+         ADC_wb_ACK_1		: in STD_LOGIC;
+         ADC_wb_INT_1		: in STD_LOGIC;
+
+         -- DAC
+         anaDAC_A_1			: out STD_LOGIC_VECTOR(7 downto 0);
+         anaDAC_B_1			: out STD_LOGIC_VECTOR(7 downto 0);
+         anaDAC_C_1			: out STD_LOGIC_VECTOR(7 downto 0);
+         anaDAC_D_1			: out STD_LOGIC_VECTOR(7 downto 0);
+
+         -- Reset Logic
+         PowerUpReset_1 	: in  STD_LOGIC;
+         PromtReset_1		: in  STD_LOGIC;
+         Reset_BG_1			: out STD_LOGIC;
+
+         -- Auxiliary Port I2C
+         auxPort_TestEn_1	: in  STD_LOGIC;
+         auxPort_SCL_1		: in  STD_LOGIC;
+         auxPort_SDA_in_1	: in  STD_LOGIC;
+         auxPort_SDA_out_1	: out STD_LOGIC;
+         auxPort_SDA_oEn_1	: out STD_LOGIC
+        );
+      END COMPONENT;
+
+      signal tdo_s : stD_logic;
+
+
+begin                 --========####   Architecture Body   ####========--
+
+    JTAG_TDO <= tdo_s;
+
+    SCAModel: TOP_core_sca_tri
+      port map (
+         -- Elink HDLC
+         link_clk_1			=>	hdlc_clock		,					--: in  STD_LOGIC;
+         link_clk_aux_1		=>	'0'				,					--: in  STD_LOGIC;
+         disable_aux_1		=>	'1'				,					--: in  STD_LOGIC;
+         tx_sd_1			=>	hdlc_from_sca	,					--: out STD_LOGIC;
+         tx_sd_aux_1		=>	open			,					--: out STD_LOGIC;
+         rx_sd_1			=>	hdlc_to_sca		,					--: in  STD_LOGIC;
+         rx_sd_aux_1		=>	'0'				,					--: in  STD_LOGIC;
+         tx_adr_1			=>	x"00"			,					--: in  STD_LOGIC_VECTOR(7 downto 0);
+         CRE_1				=>	open			,					--: out STD_LOGIC_VECTOR(7 downto 0);
+         active_aux_1		=>	open			,					--: out STD_LOGIC;
+
+         -- JTAG
+         JTAG_TCK_pad_o_1	=>	JTAG_TCK		,					--: out STD_LOGIC;
+         JTAG_TMS_pad_o_1	=>	JTAG_TMS		,					--: out STD_LOGIC;
+         JTAG_TDO_pad_o_1	=>	tdo_s		,					--: out STD_LOGIC;
+         JTAG_TDI_pad_i_1	=>	tdo_s				,					--: in  STD_LOGIC;
+         JTAG_RST_pad_o_1	=>	open			,					--: out STD_LOGIC;
+
+         -- SPI
+         SPI_sclk_pad_o_1	=>	open			,					--: out STD_LOGIC;
+         SPI_ss_pad_o_1		=>	open			,					--: out STD_LOGIC_VECTOR(7 downto 0);
+         SPI_miso_pad_i_1	=>	'0'				,					--: in  STD_LOGIC;
+         SPI_mosi_pad_o_1	=>	open			,					--: out STD_LOGIC;
+
+         -- GPIO
+         GPIO_ext_pad_o_1	=>	GPIO_o			,					--: out STD_LOGIC_VECTOR(31 downto 0);
+         GPIO_ext_padOE_o_1	=>	GPIO_oe			,					--: out STD_LOGIC_VECTOR(31 downto 0);
+         GPIO_clk_pad_i_1	=>	'0'				,					--: in  STD_LOGIC;
+         GPIO_ext_pad_i_1	=>	GPIO_i			,					--: in  STD_LOGIC_VECTOR(31 downto 0);
+
+         -- I2C
+         SCL_1				=>	SCL_1			,					--: out STD_LOGIC_VECTOR(15 downto 0);
+		 SCLEN_1			=>	SCLEN_1			,					--: out STD_LOGIC_VECTOR(15 downto 0);
+         SDA_in_1			=>	SDA_in_1		,					--: in  STD_LOGIC_VECTOR(15 downto 0);
+         SDA_out_inv_1		=>	SDA_out_inv_1	,					--: out STD_LOGIC_VECTOR(15 downto 0);
+
+         -- ADC
+         ADC_wb_RES_1		=>	open			,					--: out STD_LOGIC;
+         ADC_wb_CLK_1		=>	open			,					--: out STD_LOGIC;
+         ADC_wb_SEL_1		=>	open			,					--: out STD_LOGIC;
+         ADC_wb_WE_1		=>	open			,					--: out STD_LOGIC;
+         ADC_wb_STB_1		=>	open			,					--: out STD_LOGIC;
+         ADC_wb_CYC_1		=>	open			,					--: out STD_LOGIC;
+         ADC_wb_ADR_1		=>	open			,					--: out STD_LOGIC_VECTOR(3 downto 0);
+         ADC_wb_DATi_1		=>	open			,					--: out STD_LOGIC_VECTOR(31 downto 0);
+         ADC_wb_DATo_1		=>	(others => '0')	,					--: in  STD_LOGIC_VECTOR(31 downto 0);
+         ADC_wb_ACK_1		=>	'0'				,					--: in STD_LOGIC;
+         ADC_wb_INT_1		=>	'0'				,					--: in STD_LOGIC;
+
+         -- DAC
+         anaDAC_A_1			=>	open			,					--: out STD_LOGIC_VECTOR(7 downto 0);
+         anaDAC_B_1			=>	open			,					--: out STD_LOGIC_VECTOR(7 downto 0);
+         anaDAC_C_1			=>	open			,					--: out STD_LOGIC_VECTOR(7 downto 0);
+         anaDAC_D_1			=>	open			,					--: out STD_LOGIC_VECTOR(7 downto 0);
+
+         -- Reset Logic
+         PowerUpReset_1 	=>	powerup_reset	,					--: in  STD_LOGIC;
+         PromtReset_1		=>	prompt_reset	,					--: in  STD_LOGIC;
+         Reset_BG_1			=>	open			,					--: out STD_LOGIC;
+
+         -- Auxiliary Port I2C
+         auxPort_TestEn_1	=>	'0'				,					--: in  STD_LOGIC;
+         auxPort_SCL_1		=>	'0'				,					--: in  STD_LOGIC;
+         auxPort_SDA_in_1	=>	'0'				,					--: in  STD_LOGIC;
+         auxPort_SDA_out_1	=>	open			,					--: out STD_LOGIC;
+         auxPort_SDA_oEn_1	=>	open								--: out STD_LOGIC
+      );
+
+	SDA_out_1 <= not(SDA_out_inv_1);
+
+	general_reset <= '1' after 100ns;
+	general_reset_n <= not(general_reset);
+
+    gbtsc_inst: entity work.gbtsc_top
+        generic map(
+            -- IC configuration
+            g_IC_FIFO_DEPTH     => 20,
+
+            -- EC configuration
+            g_SCA_COUNT         => 1
+        )
+        port map(
+            -- Clock & reset
+            tx_clk_i                => hdlc_clock,
+            rx_clk_i                => hdlc_clock,
+            rx_reset_i              => general_reset_n,
+            tx_reset_i              => general_reset_n,
+
+            -- IC configuration
+            tx_GBTx_address_i       => (others => '0'),
+            tx_register_addr_i      => (others => '0'),
+            tx_nb_to_be_read_i      => (others => '0'),
+
+            -- IC Status
+            tx_ready_o              => open,
+            rx_empty_o              => open,
+
+            -- IC FIFO control
+            wr_clk_i                => hdlc_clock,
+            tx_wr_i                 => '0',
+            tx_data_to_gbtx_i       => (others => '0'),
+
+            rd_clk_i                => hdlc_clock,
+            rx_rd_i                 => '0',
+            rx_data_from_gbtx_o     => open,
+
+            -- IC control
+            tx_start_write_i        => '0',
+            tx_start_read_i         => '0',
+
+            -- SCA control
+            sca_enable_i            => "1",
+            start_reset_cmd_i       => start_reset,
+            start_connect_cmd_i     => start_connect,
+            start_command_i         => start_transaction,
+            inject_crc_error        => inject_crc_error,
+
+            -- SCA command
+            tx_address_i            => tx_addr,
+            tx_transID_i            => tx_trid,
+            tx_channel_i            => tx_ch,
+            tx_command_i            => tx_cmd,
+            tx_data_i               => tx_data,
+
+            rx_received_o(0)        => rx_received,
+            rx_address_o(0)         => rx_addr,
+            rx_control_o(0)         => rx_ctrl,
+            rx_transID_o(0)         => rx_trid,
+            rx_channel_o(0)         => rx_ch,
+            rx_len_o(0)             => rx_len,
+            rx_error_o(0)           => rx_err,
+            rx_data_o(0)            => rx_data,
+
+            -- EC line
+            ec_data_o(0)            => hdlc_from_gbtsc,
+            ec_data_i(0)            => hdlc_to_gbtsc,
+
+            -- IC lines
+            ic_data_o               => open,
+            ic_data_i               => "00"
+
+        );
+
+    --GBTSC_inst: entity work.sca_top
+	--   port map(
+	--	   tx_clk_i             => hdlc_clock,
+	--	   rx_clk_i             => hdlc_clock,
+	--	   reset_i              => general_reset_n,
+	--
+	--	   enable_i             => sca_enable,
+	--	   start_reset_cmd_i    => start_reset,
+	--	   start_connect_cmd_i  => start_connect,
+	--	   start_command_i      => start_transaction,
+	--
+	--	   tx_address_i         => tx_addr,
+	--	   tx_transID_i         => tx_trid,
+	--	   tx_channel_i         => tx_ch,
+	--	   tx_len_i             => tx_len,
+	--	   tx_command_i         => tx_cmd,
+	--	   tx_data_i            => tx_data,
+	--
+	--	   rx_received_o(0)     => rx_received,
+	--	   rx_address_o(0)      => rx_addr,
+	--	   rx_control_o(0)      => rx_ctrl,
+	--	   rx_transID_o(0)      => rx_trid,
+	--	   rx_channel_o(0)      => rx_ch,
+	--	   rx_len_o(0)          => rx_len,
+	--	   rx_error_o(0)        => rx_err,
+	--	   rx_data_o(0)         => rx_data,
+    --
+	--	   tx_data_o(0)         => hdlc_from_gbtsc,
+	--	   rx_data_i(0)         => hdlc_to_gbtsc
+	--   );
+
+	   -- Clock generation
+	   hdlc_clock	<= not(hdlc_clock) after 12.5ns;
+
+
+	   -- HDLC serializer
+	   hdlcser_proc: process(hdlc_clock)
+	   begin
+
+			if rising_edge(hdlc_clock) then
+				hdlc_to_sca <= hdlc_from_gbtsc(0);
+
+			elsif falling_edge(hdlc_clock) then
+				hdlc_to_sca <= hdlc_from_gbtsc(1);
+
+			end if;
+
+	   end process;
+
+	   -- HDLC deserializer
+	   hdlcdes_proc: process(hdlc_clock)
+			variable cnter:		integer range 0 to 1 	:= 0;
+			variable hdlc_des:	std_logic_vector(1 downto 0);
+	   begin
+
+			if falling_edge(hdlc_clock) then
+				hdlc_des(0) := hdlc_from_sca;
+				hdlc_to_gbtsc <= hdlc_des;
+
+			elsif rising_edge(hdlc_clock) then
+				hdlc_des(1) := hdlc_from_sca;
+
+			end if;
+
+	   end process;
+
+	   prompt_reset		<= '0' after 200ns;
+	   powerup_reset	<= '0' after 200ns;
+
+	   -- Manage GPIO
+	   GPIO_gen: for i in 0 to 31 generate
+
+		GPIO(i)		<= GPIO_o(i)	when GPIO_oe(i) = '1';
+		GPIO_i(i)	<= GPIO(i) when GPIO_oe(i) = '0';
+
+	   end generate;
+
+		-- Print Message
+		print_mess: process(hdlc_clock)
+		begin
+
+			if rising_edge(hdlc_clock) then
+
+				start_connect_s0 	<= start_connect;
+				start_reset_s0   		<= start_reset;
+				start_transaction_s0 	<= start_transaction;
+				rx_received_s0			<= rx_received;
+
+				if start_transaction = '1' and start_transaction_s0 = '0' then
+					write(output, "** Send packet to (0x" & to_hstring(tx_addr) & "):" & LF );
+					write(output, "      Transaction ID: 0x" & to_hstring(tx_trid) & LF );
+					write(output, "      Channel: 0x" & to_hstring(tx_ch) & LF );
+					write(output, "      Command: 0x" & to_hstring(tx_cmd) & LF );
+					write(output, "      Data: 0x" & to_hstring(tx_data) & LF );
+					write(output, "" & LF );
+
+				elsif start_reset = '1' and start_reset_s0 = '0' then
+					write(output, "** Send reset packet to (0x" & to_hstring(tx_addr) & ")" & LF );
+					write(output, "" & LF );
+
+				elsif start_connect = '1' and start_connect_s0 = '0' then
+					write(output, "** Send connect packet to (0x" & to_hstring(tx_addr) & ")" & LF );
+					write(output, "" & LF );
+
+				elsif rx_received = '1' and rx_ctrl(0) /= '1' then
+					write(output, "** Received packet from (0x" & to_hstring(rx_addr) & "):" & LF );
+					write(output, "      Transaction ID: 0x" & to_hstring(rx_trid) & LF );
+					write(output, "      Channel: 0x" & to_hstring(rx_ch) & LF );
+					write(output, "      Len: 0x" & to_hstring(rx_len) & LF );
+					write(output, "      Error: 0x" & to_hstring(rx_err) & LF );
+					write(output, "      Data: 0x" & to_hstring(rx_data) & LF );
+					write(output, "      Control: 0x" & to_hstring(rx_ctrl) & LF );
+					write(output, "" & LF );
+
+				elsif rx_received = '1' then
+					write(output, "** Received packet from (0x" & to_hstring(rx_addr) & "):" & LF );
+					write(output, "      Control: 0x" & to_hstring(rx_ctrl) & LF );
+					write(output, "" & LF );
+				end if;
+
+				if rx_received_s0 = '0' and rx_received = '1' then
+					stop(0);
+				end if;
+			end if;
+
+		end process;
+
+end behabioral;
+--=================================================================================================--
+--#################################################################################################--
+--=================================================================================================--
\ No newline at end of file
diff --git a/vldb/code/gbt_core.vhd b/vldb/code/gbt_core.vhd
index a7d33b6..26782a1 100644
--- a/vldb/code/gbt_core.vhd
+++ b/vldb/code/gbt_core.vhd
@@ -9,7 +9,7 @@ use work.trb_net_std.all;
 entity gbt_core is
   port(
     CLK_SYS : in std_logic;
-    CLK  : in std_logic;
+    CLK     : in std_logic;
     RESET   : in std_logic;
 
     BUS_RX  : in  CTRLBUS_RX;
@@ -53,6 +53,7 @@ architecture arch of gbt_core is
   signal gbtsc_rx_len_o            : std_logic_vector(7 downto 0);           --! Reply: len field (According to the SCA manual)
   signal gbtsc_rx_error_o          : std_logic_vector(7 downto 0);           --! Reply: error field (According to the SCA manual)
   signal gbtsc_rx_data_o           : std_logic_vector(31 downto 0);          --! Reply: data field (According to the SCA manual)
+  signal sync_reg                  : std_logic_vector(79 downto 0);          -- register for syncing
 
   -- EC line
   signal hdlc_from_gbtsc           : std_logic_vector(1 downto 0) := "11";           --! (TX) Array of bits to be mapped to the TX GBT-Frame
@@ -133,20 +134,31 @@ begin
       ic_data_i           => "00"     --! (RX) Array of bits to be mapped to the RX GBT-Frame (bits 83/84)
       );
 
-  -- -- shift signals to the next high enable
-  -- PROC_SHIFT_TO_EN : process
-  --     variable reg_res : std_logic_vector(1 downto 0) := "00";
-  --     variable reg_con : std_logic_vector(1 downto 0) := "00";
-  --     variable reg_cmd : std_logic_vector(1 downto 0) := "00";
-  --   begin
-  --     wait until rising_edge(CLK);
-  --       reg_res := reg_res(0) & gbtsc_start_reset_cmd_raw;
-  --       reg_con := reg_con(0) & gbtsc_start_connect_cmd_raw;
-  --       reg_cmd := reg_cmd(0) & gbtsc_start_command_raw;
-  --       gbtsc_start_reset_cmd_i <= (reg_res(0) and not gbtsc_tx_clk_en ) or (reg_res(1) and not gbtsc_tx_clk_en);
-  --       gbtsc_start_connect_cmd_i <= (reg_con(0) and not gbtsc_tx_clk_en ) or (reg_con(1) and not gbtsc_tx_clk_en);
-  --       gbtsc_start_command_i <= (reg_cmd(0) and not gbtsc_tx_clk_en ) or (reg_cmd(1) and not gbtsc_tx_clk_en);
-  --   end process;
+
+  -- shift signals to the next high enable
+  PROC_SHIFT_TX_EN : process
+      variable reg_res : std_logic_vector(1 downto 0) := "00";
+      variable reg_con : std_logic_vector(1 downto 0) := "00";
+      variable reg_cmd : std_logic_vector(1 downto 0) := "00";
+    begin
+      wait until rising_edge(CLK);
+        reg_res := reg_res(0) & gbtsc_start_reset_cmd_raw;
+        reg_con := reg_con(0) & gbtsc_start_connect_cmd_raw;
+        reg_cmd := reg_cmd(0) & gbtsc_start_command_raw;
+        gbtsc_start_reset_cmd_i <= (reg_res(0) and not gbtsc_tx_clk_en ) or (reg_res(1) and not gbtsc_tx_clk_en);
+        gbtsc_start_connect_cmd_i <= (reg_con(0) and not gbtsc_tx_clk_en ) or (reg_con(1) and not gbtsc_tx_clk_en);
+        gbtsc_start_command_i <= (reg_cmd(0) and not gbtsc_tx_clk_en ) or (reg_cmd(1) and not gbtsc_tx_clk_en);
+    end process;
+
+
+  PROC_SYNC_REG : process
+  begin
+    wait until rising_edge(CLK);
+    if gbtsc_rx_received_o = '1' then
+      sync_reg <= gbtsc_rx_address_o & gbtsc_rx_transID_o & gbtsc_rx_channel_o & gbtsc_rx_len_o & gbtsc_rx_data_o & gbtsc_rx_control_o & gbtsc_rx_error_o;
+    end if;
+  end process;
+
 
   -- HDLC serializer
   hdlcser_proc: process(CLK)
@@ -207,20 +219,20 @@ begin
         BUS_TX.unknown <= '1';
       end if;
 
-    elsif BUS_RX.read = '1' and gbtsc_rx_received_o = '1' then
+    elsif BUS_RX.read = '1' then
       BUS_TX.ack <= '1';
 
       if BUS_RX.addr(3 downto 0) = x"0" then
-        BUS_TX.data(7 downto 0) <= gbtsc_rx_address_o;
+        BUS_TX.data(7 downto 0) <= sync_reg(79 downto 72);
       elsif BUS_RX.addr(3 downto 0) = x"1" then
-        BUS_TX.data( 7 downto 0 ) <= gbtsc_rx_transID_o;
-        BUS_TX.data(15 downto 8 ) <= gbtsc_rx_channel_o;
-        BUS_TX.data(23 downto 16) <= gbtsc_rx_len_o;
+        BUS_TX.data( 7 downto 0 ) <= sync_reg(71 downto 64);
+        BUS_TX.data(15 downto 8 ) <= sync_reg(63 downto 56);
+        BUS_TX.data(23 downto 16) <= sync_reg(55 downto 48);
       elsif BUS_RX.addr(3 downto 0) = x"2" then
-        BUS_TX.data(31 downto 0) <= gbtsc_rx_data_o;
+        BUS_TX.data(31 downto 0) <= sync_reg(47 downto 16);
       elsif BUS_RX.addr(3 downto 0) = x"3" then
-        BUS_TX.data(7 downto 0)  <= gbtsc_rx_control_o;
-        BUS_TX.data(15 downto 8) <= gbtsc_rx_error_o;
+        BUS_TX.data(7 downto 0)  <= sync_reg(15 downto 8);
+        BUS_TX.data(15 downto 8) <= sync_reg(7 downto 0);
       else
         BUS_TX.ack  <= '0';
         BUS_TX.unknown <= '1';
@@ -230,15 +242,14 @@ begin
   end process;
 
 
-
   THE_CMD_SYNC : entity work.pulse_sync
     port map(
       CLK_A_IN        => CLK_SYS,
       RESET_A_IN      => RESET,
       PULSE_A_IN      => gbtsc_go,
-      CLK_B_IN        => gbtsc_tx_clk_en,
+      CLK_B_IN        => CLK,
       RESET_B_IN      => RESET,
-      PULSE_B_OUT     => gbtsc_start_command_i
+      PULSE_B_OUT     => gbtsc_start_command_raw
       );
 
   THE_RESET_SYNC : entity work.pulse_sync
@@ -246,9 +257,9 @@ begin
       CLK_A_IN        => CLK_SYS,
       RESET_A_IN      => RESET,
       PULSE_A_IN      => gbtsc_reset_go,
-      CLK_B_IN        => gbtsc_tx_clk_en,
+      CLK_B_IN        => CLK,
       RESET_B_IN      => RESET,
-      PULSE_B_OUT     => gbtsc_start_reset_cmd_i
+      PULSE_B_OUT     => gbtsc_start_reset_cmd_raw
       );
 
   THE_CONNECT_SYNC : entity work.pulse_sync
@@ -256,9 +267,9 @@ begin
       CLK_A_IN        => CLK_SYS,
       RESET_A_IN      => RESET,
       PULSE_A_IN      => gbtsc_connect_go,
-      CLK_B_IN        => gbtsc_tx_clk_en,
+      CLK_B_IN        => CLK,
       RESET_B_IN      => RESET,
-      PULSE_B_OUT     => gbtsc_start_connect_cmd_i
+      PULSE_B_OUT     => gbtsc_start_connect_cmd_raw
       );
 
 
diff --git a/vldb/trb5sc_mimosis.prj b/vldb/trb5sc_mimosis.prj
index 6c049dd..c0de50d 100644
--- a/vldb/trb5sc_mimosis.prj
+++ b/vldb/trb5sc_mimosis.prj
@@ -236,6 +236,8 @@ add_file -vhdl -lib work "./code/GBT-SC/IC/ic_tx.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
diff --git a/vldb/trb5sc_mimosis.vhd b/vldb/trb5sc_mimosis.vhd
index 0166ef5..2e1123a 100644
--- a/vldb/trb5sc_mimosis.vhd
+++ b/vldb/trb5sc_mimosis.vhd
@@ -419,24 +419,6 @@ begin
   FLASH_WP   <= '1';
 
 
----------------------------------------------------------------------------
--- GBT-SCA
----------------------------------------------------------------------------
-  THE_GBT_CORE : entity work.gbt_core
-    port map(
-      CLK_sys => clk_sys,
-      CLK     => clk_40,
-
-      RESET   => reset_i,
-
-      BUS_RX  => busgbtcore_rx,
-      BUS_TX  => busgbtcore_tx,
-
-      ELINK_RX => 0,
-      ELINK_TX => open
-      );
-
-
 ---------------------------------------------------------------------------
 -- LED
 ---------------------------------------------------------------------------