From: hadeshyp Date: Wed, 7 Nov 2007 13:54:31 +0000 (+0000) Subject: moved unused files to subfolder, Jan X-Git-Tag: oldGBE~674 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1bf08e3993f2eda9efd8eaa4368a28ef124f8eb1;p=trbnet.git moved unused files to subfolder, Jan --- diff --git a/L12TrigBusInterface.vhd b/oldfiles/L12TrigBusInterface.vhd similarity index 100% rename from L12TrigBusInterface.vhd rename to oldfiles/L12TrigBusInterface.vhd diff --git a/trb_net_18_to_16_converter.vhd b/oldfiles/trb_net_18_to_16_converter.vhd similarity index 100% rename from trb_net_18_to_16_converter.vhd rename to oldfiles/trb_net_18_to_16_converter.vhd diff --git a/trb_net_55_to_18_converter.vhd b/oldfiles/trb_net_55_to_18_converter.vhd similarity index 100% rename from trb_net_55_to_18_converter.vhd rename to oldfiles/trb_net_55_to_18_converter.vhd diff --git a/trb_net_64_to_18_converter.vhd b/oldfiles/trb_net_64_to_18_converter.vhd similarity index 100% rename from trb_net_64_to_18_converter.vhd rename to oldfiles/trb_net_64_to_18_converter.vhd diff --git a/trb_net_active_api.vhd b/oldfiles/trb_net_active_api.vhd similarity index 100% rename from trb_net_active_api.vhd rename to oldfiles/trb_net_active_api.vhd diff --git a/trb_net_active_apimbuf.vhd b/oldfiles/trb_net_active_apimbuf.vhd similarity index 100% rename from trb_net_active_apimbuf.vhd rename to oldfiles/trb_net_active_apimbuf.vhd diff --git a/trb_net_apimbuf_fast_lvds.vhd b/oldfiles/trb_net_apimbuf_fast_lvds.vhd similarity index 100% rename from trb_net_apimbuf_fast_lvds.vhd rename to oldfiles/trb_net_apimbuf_fast_lvds.vhd diff --git a/trb_net_base_api.vhd b/oldfiles/trb_net_base_api.vhd similarity index 100% rename from trb_net_base_api.vhd rename to oldfiles/trb_net_base_api.vhd diff --git a/trb_net_endpoint_3ch.vhd b/oldfiles/trb_net_endpoint_3ch.vhd similarity index 100% rename from trb_net_endpoint_3ch.vhd rename to oldfiles/trb_net_endpoint_3ch.vhd diff --git a/trb_net_fanout_hub.vhd b/oldfiles/trb_net_fanout_hub.vhd similarity index 100% rename from trb_net_fanout_hub.vhd rename to oldfiles/trb_net_fanout_hub.vhd diff --git a/trb_net_ibuf.vhd b/oldfiles/trb_net_ibuf.vhd similarity index 100% rename from trb_net_ibuf.vhd rename to oldfiles/trb_net_ibuf.vhd diff --git a/trb_net_io_multiplexer.vhd b/oldfiles/trb_net_io_multiplexer.vhd similarity index 100% rename from trb_net_io_multiplexer.vhd rename to oldfiles/trb_net_io_multiplexer.vhd diff --git a/trb_net_iobuf.vhd b/oldfiles/trb_net_iobuf.vhd similarity index 100% rename from trb_net_iobuf.vhd rename to oldfiles/trb_net_iobuf.vhd diff --git a/trb_net_med_13bit_slow.vhd b/oldfiles/trb_net_med_13bit_slow.vhd similarity index 100% rename from trb_net_med_13bit_slow.vhd rename to oldfiles/trb_net_med_13bit_slow.vhd diff --git a/trb_net_med_32lvds.vhd b/oldfiles/trb_net_med_32lvds.vhd similarity index 100% rename from trb_net_med_32lvds.vhd rename to oldfiles/trb_net_med_32lvds.vhd diff --git a/trb_net_med_tlkx501.vhd b/oldfiles/trb_net_med_tlkx501.vhd similarity index 100% rename from trb_net_med_tlkx501.vhd rename to oldfiles/trb_net_med_tlkx501.vhd diff --git a/trb_net_obuf.vhd b/oldfiles/trb_net_obuf.vhd similarity index 100% rename from trb_net_obuf.vhd rename to oldfiles/trb_net_obuf.vhd diff --git a/trb_net_old_to_new.vhd b/oldfiles/trb_net_old_to_new.vhd similarity index 100% rename from trb_net_old_to_new.vhd rename to oldfiles/trb_net_old_to_new.vhd diff --git a/trb_net_passive_api.vhd b/oldfiles/trb_net_passive_api.vhd similarity index 100% rename from trb_net_passive_api.vhd rename to oldfiles/trb_net_passive_api.vhd diff --git a/trb_net_passive_apimbuf.vhd b/oldfiles/trb_net_passive_apimbuf.vhd similarity index 100% rename from trb_net_passive_apimbuf.vhd rename to oldfiles/trb_net_passive_apimbuf.vhd diff --git a/trb_net_term_ibuf.vhd b/oldfiles/trb_net_term_ibuf.vhd similarity index 100% rename from trb_net_term_ibuf.vhd rename to oldfiles/trb_net_term_ibuf.vhd diff --git a/trb_net_term_mbuf.vhd b/oldfiles/trb_net_term_mbuf.vhd similarity index 100% rename from trb_net_term_mbuf.vhd rename to oldfiles/trb_net_term_mbuf.vhd diff --git a/trb_net_trigger_reader.vhd b/oldfiles/trb_net_trigger_reader.vhd similarity index 100% rename from trb_net_trigger_reader.vhd rename to oldfiles/trb_net_trigger_reader.vhd diff --git a/trb_net_trigger_sender.vhd b/oldfiles/trb_net_trigger_sender.vhd similarity index 100% rename from trb_net_trigger_sender.vhd rename to oldfiles/trb_net_trigger_sender.vhd diff --git a/trbnetendpoint.vhd b/oldfiles/trbnetendpoint.vhd similarity index 100% rename from trbnetendpoint.vhd rename to oldfiles/trbnetendpoint.vhd diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index b83ebd0..27235f2 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -1,450 +1,461 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net16_hub_base is - generic{ - --media interfaces - MII_NUMBER : integer range 2 to 16 := 2; - MII_INIT_DEPTH : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000"; - MII_REPLY_DEPTH : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000"; - -- settings for apis - API_NUMBER : integer range 0 to 16 := 1; - API_CHANNELS : bit_vector(API_NUMBER*4-1 downto 0) := x"3"; - --channel, each api is connected to - API_TYPE : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; - API_INIT_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; - API_REPLY_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; - API_FIFO_TO_INT_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; - API_FIFO_TO_APL_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; - --trigger reading interfaces - TRG_NUMBER : integer range 0 to 16 := 2; - TRG_CHANNELS : bit_vector(API_NUMBER*4-1 downto 0) := x"10"; - --general settings - MUX_SECURE_MODE : integer range 0 to 1 := 0; - MUX_WIDTH : integer range 1 to 5 := 3; - MUX_CTRL_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1)-1 := 3; - DATA_WIDTH : integer range 16 to 16 := 16; - NUM_WIDTH : integer range 2 to 2 := 2 - } - port { - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - --Media interfacces - --each port is one bit bigger than actually necessary to avoid error messages - MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER downto 0); - MED_DATA_OUT : out std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0); - MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0); - MED_READ_IN : in std_logic_vector (MII_NUMBER downto 0); - MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER downto 0); - MED_DATA_IN : in std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0); - MED_READ_OUT : out std_logic_vector (MII_NUMBER downto 0); -- buffer reads a word from media - MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3 downto 0); - --API: interfaces - APL_DATA_IN : in std_logic_vector (APL_NUMBER*DATA_WIDTH downto 0); - APL_PACKET_NUM_IN : in std_logic_vector (APL_NUMBER*NUM_WIDTH downto 0); - APL_WRITE_IN : in std_logic_vector (APL_NUMBER downto 0); - APL_FIFO_FULL_OUT : out std_logic_vector (APL_NUMBER downto 0); - APL_SHORT_TRANSFER_IN : in std_logic_vector (APL_NUMBER downto 0); - APL_DTYPE_IN : in std_logic_vector (APL_NUMBER*4 downto 0); - APL_ERROR_PATTERN_IN : in std_logic_vector (APL_NUMBER*32 downto 0); - APL_SEND_IN : in std_logic_vector (APL_NUMBER downto 0); - APL_TARGET_ADDRESS_IN : in std_logic_vector (APL_NUMBER*16 downto 0); - APL_DATA_OUT : out std_logic_vector (APL_NUMBER*16 downto 0); - APL_PACKET_NUM_OUT: out std_logic_vector (APL_NUMBER*NUM_WIDTH downto 0); - APL_TYP_OUT : out std_logic_vector (APL_NUMBER*3 downto 0); - APL_DATAREADY_OUT : out std_logic_vector (APL_NUMBER downto 0); - APL_READ_IN : in std_logic_vector (APL_NUMBER downto 0); - APL_RUN_OUT : out std_logic_vector (APL_NUMBER downto 0); - APL_MY_ADDRESS_IN : in std_logic_vector (APL_NUMBRT*16 downto 0); - APL_SEQNR_OUT : out std_logic_vector (APL_NUMBER*8 downto 0); - --TRG interfaces - TRG_GOT_TRIGGER_OUT : out std_logic_vector (TRG_NUMBER downto 0); - TRG_ERROR_PATTERN_OUT : out std_logic_vector (TRG_NUMBER*32 downto 0); - TRG_DTYPE_OUT : out std_logic_vector (TRG_NUMBER*4 downto 0); - TRG_SEQNR_OUT : out std_logic_vector (TRG_NUMBER*8 downto 0); - TRG_ERROR_PATTERN_IN : in std_logic_vector (TRG_NUMBER*32 downto 0); - TRG_RELEASE_IN : in std_logic_vector (TRG_NUMBER downto 0); - --Status ports (for debugging) - HUB_CHANNEL_STAT : out std_logic_vector (2**(MUX_WIDTH-1)*16 downto 0); - HUB_GEN_STAT : out std_logic_vector (31 downto 0); - MPLEX_CTRL : out std_logic_vector (MII_NUMBER*32-1 downto 0); - - } -end entity; - -architecture trb_net16_hub_base_arch of trb_net16_hub_base is - - signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); - signal m_DATA_OUT : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0); - signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0); - signal m_READ_IN : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); - signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); - signal m_DATA_IN : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0); - signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0); - signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); - - signal hub_to_buf_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - signal hub_to_buf_INIT_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); - signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); - signal hub_to_buf_INIT_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - - signal buf_to_hub_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - signal buf_to_hub_INIT_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); - signal buf_to_hub_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); - signal buf_to_hub_INIT_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - - signal hub_to_buf_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - signal hub_to_buf_REPLY_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); - signal hub_to_buf_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); - signal hub_to_buf_REPLY_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - - signal buf_to_hub_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - signal buf_to_hub_REPLY_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); - signal buf_to_hub_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); - signal buf_to_hub_REPLY_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - - component trb_net16_base_hub_logic is - generic ( - --media interfaces - POINT_NUMBER : integer range 2 to 16 := 2; - INIT_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; - REPLY_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; - --general settings - DATA_WIDTH : integer range 16 to 16 := 16; - NUM_WIDTH : integer range 2 to 2 := 2 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER downto 0); - INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0); - INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0); - INIT_READ_OUT : out std_logic_vector (POINT_NUMBER downto 0); - INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER downto 0); - INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0); - INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0); - INIT_READ_IN : in std_logic_vector (POINT_NUMBER downto 0); - REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER downto 0); - REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER downto 0); - REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0); - REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0); - REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER downto 0); - REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER downto 0); - REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0); - REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0); - REPLY_READ_IN : in std_logic_vector (POINT_NUMBER downto 0); - STAT_CHANNEL : out std_logic_vector (15 downto 0); - STAT_GEN : out std_logic_vector (31 downto 0); - CTRL_CHANNEL : in std_logic_vector (31 downto 0); - CTRL_GEN : in std_logic_vector (31 downto 0) - ); -end component; - - - component trb_net16_io_multiplexer is - generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; - MUX_WIDTH : integer range 1 to 5 := 3; - MUX_SECURE_MODE : integer range 0 to 1 := 0 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; - -- Internal direction port - INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - -- Status and control port - CTRL: in std_logic_vector (31 downto 0); - STAT: out std_logic_vector (31 downto 0) - ); - end component; - - component trb_net16_iobuf is - generic ( - INIT_DEPTH : integer := 1; - REPLY_DEPTH : integer := 1 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_INIT_READ_IN: in std_logic; -- Media is reading - MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media - MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_REPLY_READ_IN: in std_logic; -- Media is reading - MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - -- Internal direction port - INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_INIT_READ_IN: in std_logic; - INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_INIT_READ_OUT: out std_logic; - INT_REPLY_HEADER_IN: in std_logic; - INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_REPLY_READ_IN: in std_logic; - INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_REPLY_READ_OUT: out std_logic; - -- Status and control port - STAT_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - CTRL_GEN: in std_logic_vector (31 downto 0); - CTRL_LOCKED: in std_logic_vector (31 downto 0); - STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) - ); - end component; - - - component trb_net16_base_api is - generic ( - API_TYPE : integer := API_TYPE; - FIFO_TO_INT_DEPTH : integer := 1; - FIFO_TO_APL_DEPTH : integer := 1; - FIFO_TERM_BUFFER_DEPTH : integer := 0); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - -- Internal direction port - INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_MASTER_READ_IN : in std_logic; - INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_MASTER_READ_OUT : out std_logic; - INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR - INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_SLAVE_READ_IN : in std_logic; - INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_SLAVE_READ_OUT : out std_logic; - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); - end component; - - - -begin - ---generate multiplexers - gen_muxes: for i in 0 to MII_NUMBER-1 generate - MPLEX: trb_net16_io_multiplexer - generic map ( - DATA_WIDTH => DATA_WIDTH, - NUM_WIDTH => NUM_WIDTH, - MUX_WIDTH => MUX_WIDTH, - MUX_SECURE_MODE => MUX_SECURE_MODE - ) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_DATAREADY_IN(i*2+1 downto i*2), - MED_DATA_IN => MED_DATA_IN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), - MED_PACKET_NUM_IN => MED_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), - MED_READ_OUT => MED_READ_OUT(i*2+1 downto i*2), - MED_DATAREADY_OUT => MED_DATAREADY_OUT(i*2+1 downto i*2), - MED_DATA_OUT => MED_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), - MED_READ_IN => MED_READ_IN(i*2+1 downto i*2), - INT_DATAREADY_OUT => m_DATAREADY_IN(i*2+1 downto i*2), - INT_DATA_OUT => m_DATA_IN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), - INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), - INT_READ_IN => m_READ_OUT(i*2+1 downto i*2), - INT_DATAREADY_IN => m_DATAREADY_OUT(i*2+1 downto i*2), - INT_DATA_IN => m_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), - INT_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), - INT_READ_OUT => m_READ_IN(i*2+1 downto i*2), - CTRL => MPLEX_CTRL((i+1)*32-1) downto i*32) - ); - end generate; - ---generate IOBufs for MII - gen_iobufs: for i in 0 to 2**(MUX_WIDTH-1)*MII_NUMBER-1 generate - IOBUF: trb_net16_iobuf - generic map ( - INIT_DEPTH => to_integer(MII_INIT_DEPTH((i+1)*4-1 downto i)), - REPLY_DEPTH => to_integer(MII_REPLY_DEPTH((i+1)*4-1 downto i)) - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => m_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), - MED_INIT_READ_IN => m_READ_IN(i*2), - - MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), - MED_INIT_DATA_IN => m_DATA_�N((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), - MED_INIT_READ_OUT => m_READ_OUT(i*2), - MED_INIT_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), - - MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => m_DATA_OUT((i+2)*DATA_WIDTH*2-1 downto (i+1)*DATA_WIDTH*2), - MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i+2)*NUM_WIDTH*2-1 downto (i+1)*NUM_WIDTH*2), - MED_REPLY_READ_IN => m_READ_IN(i*2+1), - - MED_REPLY_DATAREADY_IN => m_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_IN => m_DATA_OUT((i+2)*DATA_WIDTH*2-1 downto (i+1)*DATA_WIDTH*2), - MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+2)*NUM_WIDTH*2-1 downto (i+1)*NUM_WIDTH*2), - MED_REPLY_READ_OUT => m_READ_IN(i*2+1), - MED_REPLY_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), - - -- Internal direction port - - INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), - INT_INIT_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_INIT_PACKET_NUM_OUT=> buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INT_INIT_READ_IN => buf_to_hub_INIT_READ(i), - - INT_INIT_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i), - INT_INIT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INT_INIT_READ_OUT => hub_to_buf_INIT_READ(i), - - INT_REPLY_HEADER_IN => buf_to_hub_REPLY_SEND_HEADER(i), - INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i), - INT_REPLY_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INT_REPLY_READ_IN => buf_to_hub_REPLY_READ(i), - - INT_REPLY_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i), - INT_REPLY_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_REPLY_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INT_REPLY_READ_OUT => hub_to_buf_REPLY_READ(i), - - -- Status and control port - STAT_GEN => IOBUF_STAT_GEN((i+1)*32 downto i*32), - STAT_LOCKED => IOBUF_STAT_LOCKED((i+1)*32 downto i*32), - STAT_INIT_BUFFER => IOBUF_buf_STAT_INIT_BUFFER((i+1)*32 downto i*32), - STAT_REPLY_BUFFER => IOBUF_STAT_REPLY_BUFFER((i+1)*32 downto i*32), - CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32 downto i*32), - CTRL_LOCKED => IOBUF_CTRL_LOCKED((i+1)*32 downto i*32), - STAT_CTRL_INIT_BUFFER => IOBUF_STAT_CTRL_INIT_BUFFER((i+1)*32 downto i*32), - STAT_CTRL_REPLY_BUFFER => IOBUF_STAT_CTRL_REPLY_BUFFER((i+1)*32 downto i*32) - ); - end generate; - - gen_hub_logic: for i in 0 to 2**(MUX_WIDTH-1)-1 generate - HUBLOGIC : trb_net16_base_hub_logic - generic map{ - --media interfaces - POINT_NUMBER => MII_NUMBER, - INIT_DEPTH => MII_INIT_DEPTH((i+1)*4 downto i*4), - REPLY_DEPTH => MII_REPLY_DEPTH((i+1)*4 downto i*4), - --general settings - DATA_WIDTH => DATA_WIDTH, - NUM_WIDTH => NUM_WIDTH - ) - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - INIT_DATAREADY_IN => buf_to_hub_INIT_DATAREADY(i), - INIT_DATA_IN => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INIT_PACKET_NUM_IN => buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INIT_READ_OUT => buf_to_hub_INIT_READ(i), - INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), - INIT_DATA_OUT => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INIT_PACKET_NUM_OUT => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INIT_READ_IN => hub_to_buf_INIT_READ(i), - REPLY_HEADER_OUT => hub_to_buf_REPLY_HEADER_OUT(i), - REPLY_DATAREADY_IN => buf_to_hub_REPLY_DATAREADY(i), - REPLY_DATA_IN => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - REPLY_PACKET_NUM_IN => buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - REPLY_READ_OUT => buf_to_hub_REPLY_READ(i), - REPLY_DATAREADY_OUT => hub_to_buf_REPLY_DATAREADY(i), - REPLY_DATA_OUT => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - REPLY_PACKET_NUM_OUT => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - REPLY_READ_IN => hub_to_buf_REPLY_READ(i), - STAT_INTERFACE => HUB_STAT_CHANNEL((i+1)*32-1 downto i*32), - STAT_GEN => HUB_STAT_GEN((i+1)*32-1 downto i*32), - CTRL_INTERFACE => HUB_CTRL_CHANNEL((i+1)*32-1 downto i*32), - CTRL_GEN => HUB_CTRL_GEN((i+1)*32-1 downto i*32) - ) - end generate; - -end architecture; +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +USE IEEE.numeric_std.ALL; + +use work.trb_net_std.all; + + +entity trb_net16_hub_base is + generic ( + --general settings + MUX_SECURE_MODE : integer range 0 to 1 := 0; + MUX_WIDTH : integer range 1 to 5 := 3; + MUX_CTRL_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1)-1 := 3; + DATA_WIDTH : integer range 16 to 16 := 16; + NUM_WIDTH : integer range 2 to 2 := 2; + --media interfaces + MII_NUMBER : integer range 2 to 16 := 2; + MII_INIT_DEPTH : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000"; + MII_REPLY_DEPTH : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000"; + -- settings for apis + API_NUMBER : integer range 0 to 16 := 1; + API_CHANNELS : bit_vector(API_NUMBER*4-1 downto 0) := x"3"; + --channel, each api is connected to + API_TYPE : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; + API_INIT_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; + API_REPLY_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; + API_FIFO_TO_INT_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; + API_FIFO_TO_APL_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; + --trigger reading interfaces + TRG_NUMBER : integer range 0 to 16 := 2; + TRG_CHANNELS : bit_vector(API_NUMBER*4-1 downto 0) := x"10" + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + --Media interfacces + --each port is one bit bigger than actually necessary to avoid error messages + MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER downto 0); + MED_DATA_OUT : out std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0); + MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0); + MED_READ_IN : in std_logic_vector (MII_NUMBER downto 0); + MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER downto 0); + MED_DATA_IN : in std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0); + MED_READ_OUT : out std_logic_vector (MII_NUMBER downto 0); -- buffer reads a word from media + MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3 downto 0); + --API: interfaces + APL_DATA_IN : in std_logic_vector (API_NUMBER*DATA_WIDTH downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (API_NUMBER*NUM_WIDTH downto 0); + APL_WRITE_IN : in std_logic_vector (API_NUMBER downto 0); + APL_FIFO_FULL_OUT : out std_logic_vector (API_NUMBER downto 0); + APL_SHORT_TRANSFER_IN : in std_logic_vector (API_NUMBER downto 0); + APL_DTYPE_IN : in std_logic_vector (API_NUMBER*4 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (API_NUMBER*32 downto 0); + APL_SEND_IN : in std_logic_vector (API_NUMBER downto 0); + APL_TARGET_ADDRESS_IN : in std_logic_vector (API_NUMBER*16 downto 0); + APL_DATA_OUT : out std_logic_vector (API_NUMBER*16 downto 0); + APL_PACKET_NUM_OUT: out std_logic_vector (API_NUMBER*NUM_WIDTH downto 0); + APL_TYP_OUT : out std_logic_vector (API_NUMBER*3 downto 0); + APL_DATAREADY_OUT : out std_logic_vector (API_NUMBER downto 0); + APL_READ_IN : in std_logic_vector (API_NUMBER downto 0); + APL_RUN_OUT : out std_logic_vector (API_NUMBER downto 0); + APL_MY_ADDRESS_IN : in std_logic_vector (API_NUMBER*16 downto 0); + APL_SEQNR_OUT : out std_logic_vector (API_NUMBER*8 downto 0); + --TRG interfaces + TRG_GOT_TRIGGER_OUT : out std_logic_vector (TRG_NUMBER downto 0); + TRG_ERROR_PATTERN_OUT : out std_logic_vector (TRG_NUMBER*32 downto 0); + TRG_DTYPE_OUT : out std_logic_vector (TRG_NUMBER*4 downto 0); + TRG_SEQNR_OUT : out std_logic_vector (TRG_NUMBER*8 downto 0); + TRG_ERROR_PATTERN_IN : in std_logic_vector (TRG_NUMBER*32 downto 0); + TRG_RELEASE_IN : in std_logic_vector (TRG_NUMBER downto 0); + --Status ports (for debugging) + HUB_STAT_CHANNEL : out std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0); + HUB_STAT_GEN : out std_logic_vector (31 downto 0); + HUB_CTRL_CHANNEL : in std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0); + HUB_CTRL_GEN : in std_logic_vector (31 downto 0); + MPLEX_CTRL : in std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0); + MPLEX_STAT : out std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0); + IOBUF_STAT_GEN : out std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0); + IOBUF_STAT_LOCKED : out std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0); + IOBUF_STAT_INIT_BUFFER : out std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0); + IOBUF_STAT_REPLY_BUFFER : out std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0); + IOBUF_CTRL_GEN : in std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0); + IOBUF_CTRL_LOCKED : in std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0); + IOBUF_STAT_CTRL_INIT_BUFFER : in std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0); + IOBUF_STAT_CTRL_REPLY_BUFFER : in std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0) + ); +end entity; + +architecture trb_net16_hub_base_arch of trb_net16_hub_base is + + signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); + signal m_DATA_OUT : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0); + signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0); + signal m_READ_IN : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); + signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); + signal m_DATA_IN : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0); + signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0); + signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); + signal m_ERROR_IN : std_logic_vector (MII_NUMBER*3*2**MUX_WIDTH-1 downto 0); + + signal hub_to_buf_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + signal hub_to_buf_INIT_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); + signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); + signal hub_to_buf_INIT_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + + signal buf_to_hub_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + signal buf_to_hub_INIT_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); + signal buf_to_hub_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); + signal buf_to_hub_INIT_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + + signal hub_to_buf_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + signal hub_to_buf_REPLY_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); + signal hub_to_buf_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); + signal hub_to_buf_REPLY_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + signal hub_to_buf_REPLY_SEND_HEADER : std_logic_vector(2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + + signal buf_to_hub_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + signal buf_to_hub_REPLY_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); + signal buf_to_hub_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); + signal buf_to_hub_REPLY_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + signal buf_to_hub_REPLY_SEND_HEADER : std_logic_vector(2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); + + component trb_net16_hub_logic is + generic ( + --media interfaces + POINT_NUMBER : integer range 2 to 16 := 2; + INIT_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; + REPLY_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; + --general settings + DATA_WIDTH : integer range 16 to 16 := 16; + NUM_WIDTH : integer range 2 to 2 := 2 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + STAT : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (31 downto 0) + ); +end component; + + + component trb_net16_io_multiplexer is + generic ( + DATA_WIDTH : integer := 16; + NUM_WIDTH : integer := 2; + MUX_WIDTH : integer range 1 to 5 := 3; + MUX_SECURE_MODE : integer range 0 to 1 := 0 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_DATAREADY_OUT: out std_logic; + MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0); + MED_READ_IN: in std_logic; + -- Internal direction port + INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); + INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); + INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); + -- Status and control port + CTRL: in std_logic_vector (31 downto 0); + STAT: out std_logic_vector (31 downto 0) + ); + end component; + + component trb_net16_iobuf is + generic ( + INIT_DEPTH : integer := 1; + REPLY_DEPTH : integer := 1 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out + MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_INIT_READ_IN: in std_logic; -- Media is reading + MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media + MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out + MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_REPLY_READ_IN: in std_logic; -- Media is reading + MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media + MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + -- Internal direction port + INT_INIT_DATAREADY_OUT: out std_logic; + INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_INIT_READ_IN: in std_logic; + INT_INIT_DATAREADY_IN: in std_logic; + INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_INIT_READ_OUT: out std_logic; + INT_REPLY_HEADER_IN: in std_logic; + INT_REPLY_DATAREADY_OUT: out std_logic; + INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_REPLY_READ_IN: in std_logic; + INT_REPLY_DATAREADY_IN: in std_logic; + INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_REPLY_READ_OUT: out std_logic; + -- Status and control port + STAT_GEN: out std_logic_vector (31 downto 0); -- General Status + STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status + CTRL_GEN: in std_logic_vector (31 downto 0); + CTRL_LOCKED: in std_logic_vector (31 downto 0); + STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); + STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) + ); + end component; + + + component trb_net16_base_api is + generic ( + API_TYPE : integer := 1; + FIFO_TO_INT_DEPTH : integer := 1; + FIFO_TO_APL_DEPTH : integer := 1; + FIFO_TERM_BUFFER_DEPTH : integer := 0); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN : in std_logic; -- + APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN : in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of + -- Receiver port + APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out + APL_READ_IN : in std_logic; -- Read data word + -- APL Control port + APL_RUN_OUT : out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + -- Internal direction port + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_MASTER_READ_IN : in std_logic; + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); + end component; + + + +begin + +--generate multiplexers + gen_muxes: for i in 0 to MII_NUMBER-1 generate + MPLEX: trb_net16_io_multiplexer + generic map ( + DATA_WIDTH => DATA_WIDTH, + NUM_WIDTH => NUM_WIDTH, + MUX_WIDTH => MUX_WIDTH, + MUX_SECURE_MODE => MUX_SECURE_MODE + ) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_DATAREADY_IN(i), + MED_DATA_IN => MED_DATA_IN((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + MED_READ_OUT => MED_READ_OUT(i), + MED_DATAREADY_OUT => MED_DATAREADY_OUT(i), + MED_DATA_OUT => MED_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + MED_READ_IN => MED_READ_IN(i), + INT_DATAREADY_OUT => m_DATAREADY_IN((i+1)*2**MUX_WIDTH-1 downto i*2**MUX_WIDTH), + INT_DATA_OUT => m_DATA_IN((i+1)*DATA_WIDTH*2**MUX_WIDTH-1 downto i*DATA_WIDTH*2**MUX_WIDTH), + INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2**MUX_WIDTH-1 downto i*NUM_WIDTH*2**MUX_WIDTH), + INT_READ_IN => m_READ_OUT((i+1)*2**MUX_WIDTH-1 downto i*2**MUX_WIDTH), + INT_DATAREADY_IN => m_DATAREADY_OUT((i+1)*2**MUX_WIDTH-1 downto i*2**MUX_WIDTH), + INT_DATA_IN => m_DATA_OUT((i+1)*DATA_WIDTH*2**MUX_WIDTH-1 downto i*DATA_WIDTH*2**MUX_WIDTH), + INT_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2**MUX_WIDTH-1 downto i*NUM_WIDTH*2**MUX_WIDTH), + INT_READ_OUT => m_READ_IN((i+1)*2**MUX_WIDTH-1 downto i*2**MUX_WIDTH), + CTRL => MPLEX_CTRL((i+1)*32-1 downto i*32), + STAT => MPLEX_STAT((i+1)*32-1 downto i*32) + ); + end generate; + +--generate IOBufs for MII + gen_iobufs: for i in 0 to 2**(MUX_WIDTH-1)*MII_NUMBER-1 generate + IOBUF: trb_net16_iobuf + generic map ( + INIT_DEPTH => conv_integer(to_stdlogicvector(MII_INIT_DEPTH((i+1)*4-1 downto i*4))), + REPLY_DEPTH => conv_integer(to_stdlogicvector(MII_REPLY_DEPTH((i+1)*4-1 downto i*4))) + ) + port map ( + -- Misc + CLK => CLK , + RESET => RESET, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*2*DATA_WIDTH), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*NUM_WIDTH-1 downto i*2*NUM_WIDTH), + MED_INIT_READ_IN => m_READ_IN(i*2), + + MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), + MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*2*DATA_WIDTH), + MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+1)*NUM_WIDTH-1 downto i*2*NUM_WIDTH), + MED_INIT_READ_OUT => m_READ_OUT(i*2), + MED_INIT_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), + + MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*NUM_WIDTH-1 downto (i*2+1)*NUM_WIDTH), + MED_REPLY_READ_IN => m_READ_IN(i*2+1), + + MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), + MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), + MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+2)*NUM_WIDTH-1 downto (i*2+1)*NUM_WIDTH), + MED_REPLY_READ_OUT => m_READ_OUT(i*2+1), + MED_REPLY_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), + + -- Internal direction port + + INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), + INT_INIT_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + INT_INIT_PACKET_NUM_OUT=> buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_INIT_READ_IN => buf_to_hub_INIT_READ(i), + + INT_INIT_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i), + INT_INIT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_INIT_READ_OUT => hub_to_buf_INIT_READ(i), + + INT_REPLY_HEADER_IN => buf_to_hub_REPLY_SEND_HEADER(i), + INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i), + INT_REPLY_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_REPLY_READ_IN => buf_to_hub_REPLY_READ(i), + + INT_REPLY_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i), + INT_REPLY_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), + INT_REPLY_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_REPLY_READ_OUT => hub_to_buf_REPLY_READ(i), + + -- Status and control port + STAT_GEN => IOBUF_STAT_GEN((i+1)*32-1 downto i*32), + STAT_LOCKED => IOBUF_STAT_LOCKED((i+1)*32-1 downto i*32), + STAT_INIT_BUFFER => IOBUF_STAT_INIT_BUFFER((i+1)*32-1 downto i*32), + STAT_REPLY_BUFFER => IOBUF_STAT_REPLY_BUFFER((i+1)*32-1 downto i*32), + CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32-1 downto i*32), + CTRL_LOCKED => IOBUF_CTRL_LOCKED((i+1)*32-1 downto i*32), + STAT_CTRL_INIT_BUFFER => IOBUF_STAT_CTRL_INIT_BUFFER((i+1)*32-1 downto i*32), + STAT_CTRL_REPLY_BUFFER => IOBUF_STAT_CTRL_REPLY_BUFFER((i+1)*32-1 downto i*32) + ); + end generate; + + gen_hub_logic: for i in 0 to 2**(MUX_WIDTH-1)-1 generate + HUBLOGIC : trb_net16_hub_logic + generic map ( + --media interfaces + POINT_NUMBER => MII_NUMBER, + INIT_DEPTH => MII_INIT_DEPTH((i+1)*4 downto i*4), + REPLY_DEPTH => MII_REPLY_DEPTH((i+1)*4 downto i*4), + --general settings + DATA_WIDTH => DATA_WIDTH, + NUM_WIDTH => NUM_WIDTH + ) + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + INIT_DATAREADY_IN => buf_to_hub_INIT_DATAREADY((i+1)*MII_NUMBER-1 downto i*MII_NUMBER), + INIT_DATA_IN => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH*MII_NUMBER-1 downto i*DATA_WIDTH*MII_NUMBER), + INIT_PACKET_NUM_IN => buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH*MII_NUMBER-1 downto i*NUM_WIDTH*MII_NUMBER), + INIT_READ_OUT => buf_to_hub_INIT_READ((i+1)*MII_NUMBER-1 downto i*MII_NUMBER), + INIT_DATAREADY_OUT => hub_to_buf_INIT_DATAREADY((i+1)*MII_NUMBER-1 downto i*MII_NUMBER), + INIT_DATA_OUT => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH*MII_NUMBER-1 downto i*DATA_WIDTH*MII_NUMBER), + INIT_PACKET_NUM_OUT => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH*MII_NUMBER-1 downto i*NUM_WIDTH*MII_NUMBER), + INIT_READ_IN => hub_to_buf_INIT_READ((i+1)*MII_NUMBER-1 downto i*MII_NUMBER), + REPLY_HEADER_OUT => hub_to_buf_REPLY_SEND_HEADER((i+1)*MII_NUMBER-1 downto i*MII_NUMBER), + REPLY_DATAREADY_IN => buf_to_hub_REPLY_DATAREADY((i+1)*MII_NUMBER-1 downto i*MII_NUMBER), + REPLY_DATA_IN => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH*MII_NUMBER-1 downto i*DATA_WIDTH*MII_NUMBER), + REPLY_PACKET_NUM_IN => buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH*MII_NUMBER-1 downto i*NUM_WIDTH*MII_NUMBER), + REPLY_READ_OUT => buf_to_hub_REPLY_READ((i+1)*MII_NUMBER-1 downto i*MII_NUMBER), + REPLY_DATAREADY_OUT => hub_to_buf_REPLY_DATAREADY((i+1)*MII_NUMBER-1 downto i*MII_NUMBER), + REPLY_DATA_OUT => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH*MII_NUMBER-1 downto i*DATA_WIDTH*MII_NUMBER), + REPLY_PACKET_NUM_OUT => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH*MII_NUMBER-1 downto i*NUM_WIDTH*MII_NUMBER), + REPLY_READ_IN => hub_to_buf_REPLY_READ((i+1)*MII_NUMBER-1 downto i*MII_NUMBER*MII_NUMBER), + STAT => HUB_STAT_CHANNEL((i+1)*32-1 downto i*32), + CTRL => HUB_CTRL_CHANNEL((i+1)*32-1 downto i*32) + ); + end generate; + +end architecture; diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index 9211b70..42641c7 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -9,7 +9,7 @@ use work.trb_net_std.all; entity trb_net16_hub_logic is generic ( --media interfaces - POINT_NUMBER : integer range 2 to 16 := 2; + POINT_NUMBER : integer range 2 to 16 := 10; INIT_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; REPLY_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; --general settings @@ -18,90 +18,162 @@ entity trb_net16_hub_logic is ); port ( CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; --Internal interfaccs to IOBufs - INIT_DATAREADY_IN : in std_logic_vector (PONUMBER downto 0); - INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*PONUMBER downto 0); - INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*PONUMBER downto 0); - INIT_READ_OUT : out std_logic_vector (PONUMBER downto 0); - INIT_DATAREADY_OUT : out std_logic_vector (PONUMBER downto 0); - INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*PONUMBER downto 0); - INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*PONUMBER downto 0); - INIT_READ_IN : in std_logic_vector (PONUMBER downto 0); - REPLY_HEADER_OUT : out std_logic_vector (PONUMBER downto 0); - REPLY_DATAREADY_IN : in std_logic_vector (PONUMBER downto 0); - REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*PONUMBER downto 0); - REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*PONUMBER downto 0); - REPLY_READ_OUT : out std_logic_vector (PONUMBER downto 0); - REPLY_DATAREADY_OUT : out std_logic_vector (PONUMBER downto 0); - REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*PONUMBER downto 0); - REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*PONUMBER downto 0); - REPLY_READ_IN : in std_logic_vector (PONUMBER downto 0); + INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); --Status ports (for debugging) - STAT_CHANNEL : out std_logic_vector (15 downto 0); - STAT_GEN : out std_logic_vector (31 downto 0); - CTRL_CHANNEL : in std_logic_vector (31 downto 0); - CTRL_GEN : in std_logic_vector (31 downto 0) + STAT : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (31 downto 0) ); end entity; architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is + +--signals init_pool + signal INIT_POOL_DATAREADY : std_logic; + signal INIT_POOL_READ : std_logic; + signal INIT_POOL_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); + signal INIT_POOL_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); + signal init_has_read_from_pool : std_logic_vector(POINT_NUMBER-1 downto 0); + signal saved_INIT_TYPE, current_INIT_TYPE : std_logic_vector(2 downto 0); + + + signal REPLY_POOL_DATAREADY : std_logic; + signal REPLY_POOL_READ : std_logic; + signal REPLY_POOL_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); + signal REPLY_POOL_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); + signal saved_REPLY_TYPE , current_REPLY_TYPE : std_logic_vector(2 downto 0); + +--general signals + signal locked, next_locked : std_logic; + signal get_locked, release_locked : std_logic; + signal locking_point, next_locking_point : std_logic_vector(POINT_NUMBER-1 downto 0); + begin + +STAT <= (others => '0'); + + --Datapool for Init-Channel - INIT_POOL_DATAREADY <= or_all(INIT_DATAREADY_IN(POINT_NUMBER-1 downto 0); + INIT_POOL_DATAREADY <= or_all(INIT_DATAREADY_IN(POINT_NUMBER-1 downto 0)); INIT_POOL_READ <= - and_all(INIT_READ_IN(POINT_NUMBER-1 downto 0) or init_pool_has_read(POINT_NUMBER-1 downto 0)); + and_all(INIT_READ_IN(POINT_NUMBER-1 downto 0) or init_has_read_from_pool(POINT_NUMBER-1 downto 0)); gen_init_pool_data0: for i in 0 to DATA_WIDTH-1 generate process(INIT_DATA_IN) variable VAR_INIT_POOL_DATA : std_logic; - begin - VAR_INIT_POOL_DATA := 0; - gen_init_pool_data1: for j in 0 to POINT_NUMBER-1 loop - VAR_INIT_POOL_DATA := VAR_INIT_POOL_DATA or INIT_DATA_IN(j*DATA_WIDTH+i); - end loop; - INIT_POOL_DATA(i) <= VAR_INIT_POOL_DATA; - end process; + begin + VAR_INIT_POOL_DATA := '0'; + gen_init_pool_data1: for j in 0 to POINT_NUMBER-1 loop + VAR_INIT_POOL_DATA := VAR_INIT_POOL_DATA or INIT_DATA_IN(j*DATA_WIDTH+i); + end loop; + INIT_POOL_DATA(i) <= VAR_INIT_POOL_DATA; + end process; end generate; ---Data for obuf output - gen_init_dataready_out: for i in 0 to POINT_NUMBER-1 generate - INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_pool_has_read(i); + gen_init_pool_data2: for i in 0 to NUM_WIDTH-1 generate + process(INIT_PACKET_NUM_IN) + variable VAR_INIT_POOL_PACKET_NUM : std_logic; + begin + VAR_INIT_POOL_PACKET_NUM := '0'; + gen_init_pool_data3: for j in 0 to POINT_NUMBER-1 loop + VAR_INIT_POOL_PACKET_NUM := VAR_INIT_POOL_PACKET_NUM or INIT_PACKET_NUM_IN(j*NUM_WIDTH+i); + end loop; + INIT_POOL_PACKET_NUM(i) <= VAR_INIT_POOL_PACKET_NUM; + end process; end generate; - gen_init_data_out: for i in 0 to POINT_NUMBER-1 generate +--has-read signal + gen_hasread: for i in 0 to POINT_NUMBER-1 generate + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or INIT_POOL_READ = '1' then + init_has_read_from_pool(i) <= '0'; + else + if INIT_POOL_DATAREADY = '1' and INIT_READ_IN(i) = '1' then + init_has_read_from_pool(i) <= '1'; + end if; + end if; + end if; + end process; + end generate; + +--signals to ibufs + INIT_READ_OUT <= (others => INIT_POOL_READ); + +--signals to obufs + gen_init_data_out: for i in 0 to POINT_NUMBER-1 generate + INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_has_read_from_pool(i); INIT_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) <= INIT_POOL_DATA; + INIT_PACKET_NUM_OUT((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) <= INIT_POOL_PACKET_NUM; end generate; - - gen_init_read_in - - --DATAREADY for each OBUF is dataready from all ibufs and not already have been reading this word - -- gen_init_datapool_c: for CHANNEL in 0 to 2**(MUX_WIDTH-1)-1 generate - -- gen_init_datapool_m: for MEDIA in 0 to MII_NUMBER-1 generate - -- hub_to_buf_INIT_DATAREADY(CHANNEL*MII_NUMBER+MEDIA) <= - -- or_all(buf_to_hub_DATAREADY((CHANNEL+1)*MII_NUMBER-1 downto CHANNEL*MII_NUMBER) - -- and not buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA); - -- hub_to_buf_INIT_DATA((CHANNEL*MII_NUMBER+MEDIA)*(DATA_WIDTH+1)-1 downto CHANNEL*MII_NUMBER+MEDIA)*(DATA_WIDTH)) <= - -- or_all( - -- end generate; - -- end generate; - - -- gen_init_has_read_c: for CHANNEL in 0 to 2**(MUX_WIDTH-1)-1 generate - -- gen_init_has_read_m: for MEDIA in 0 to MII_NUMBER-1 generate - -- process(CLK) - -- begin - -- if rising_edge(CLK) then - -- if RESET = '1' or buf_to_hub_INIT_CHANNEL_READ(CHANNEL) = '1' then - -- buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA) <= '0'; - -- else - -- if hub_to_buf_INIT_DATAREADY(CHANNEL*MII_NUMBER+MEDIA) = '1' - -- and hub_to_buf_INIT_READ(CHANNEL*MII_NUMBER+MEDIA) = '1' then - -- buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA) <= '1'; - -- end if; - -- end if; - -- end if; - -- end process; - -- end generate; - -- end generate; + + + +--locked signals + release_locked <= '1' when (saved_REPLY_TYPE = TYPE_TRM) and REPLY_POOL_PACKET_NUM = "11" else '0'; + get_locked <= INIT_POOL_DATAREADY; + next_locked <= (get_locked or locked) and not release_locked; + next_locking_point <= INIT_DATAREADY_IN when locked = '0' else locking_point; + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + locked <= '0'; + locking_point <= (others => '0'); + else + locked <= next_locked; + locking_point <= next_locking_point; + end if; + end if; + end process; + +--saving packet types + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + saved_INIT_TYPE <= TYPE_ILLEGAL; + elsif INIT_POOL_DATAREADY = '1' and INIT_POOL_PACKET_NUM = "00" then + saved_INIT_TYPE <= INIT_POOL_DATA(2 downto 0); + end if; + end if; + end process; + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + saved_REPLY_TYPE <= TYPE_ILLEGAL; + elsif REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = "00" then + saved_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0); + end if; + end if; + end process; + current_INIT_TYPE <= INIT_POOL_DATA(2 downto 0) when INIT_POOL_DATAREADY = '1' and INIT_POOL_PACKET_NUM = "00" + else saved_INIT_TYPE; + current_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0) when REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = "00" + else saved_REPLY_TYPE; + + + + end architecture; \ No newline at end of file