From: Cahit Date: Thu, 18 Apr 2013 12:48:01 +0000 (+0200) Subject: tdc_v1.4 is released. For details see tdc_releases/ReleaseNotes.txt - cu X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1c651c767bf9fb110a21d08391e8e0fdd1bc0dee;p=trb3.git tdc_v1.4 is released. For details see tdc_releases/ReleaseNotes.txt - cu --- diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd index 6744c66..5b72cc5 100644 --- a/base/trb3_components.vhd +++ b/base/trb3_components.vhd @@ -44,7 +44,7 @@ end component; ); end component; - component TDC + component TDC is generic ( CHANNEL_NUMBER : integer range 2 to 65; CONTROL_REG_NR : integer range 0 to 6); @@ -56,18 +56,18 @@ end component; HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1); TRG_WIN_PRE : in std_logic_vector(10 downto 0); TRG_WIN_POST : in std_logic_vector(10 downto 0); - TRG_DATA_VALID_IN : in std_logic; - VALID_TIMING_TRG_IN : in std_logic; - VALID_NOTIMING_TRG_IN : in std_logic; - INVALID_TRG_IN : in std_logic; - TMGTRG_TIMEOUT_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - SPURIOUS_TRG_IN : in std_logic; - TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - TRG_CODE_IN : in std_logic_vector(7 downto 0); - TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - TRG_TYPE_IN : in std_logic_vector(3 downto 0); + TRG_DATA_VALID_IN : in std_logic := '0'; + VALID_TIMING_TRG_IN : in std_logic := '0'; + VALID_NOTIMING_TRG_IN : in std_logic := '0'; + INVALID_TRG_IN : in std_logic := '0'; + TMGTRG_TIMEOUT_IN : in std_logic := '0'; + SPIKE_DETECTED_IN : in std_logic := '0'; + MULTI_TMG_TRG_IN : in std_logic := '0'; + SPURIOUS_TRG_IN : in std_logic := '0'; + TRG_NUMBER_IN : in std_logic_vector(15 downto 0) := (others => '0'); + TRG_CODE_IN : in std_logic_vector(7 downto 0) := (others => '0'); + TRG_INFORMATION_IN : in std_logic_vector(23 downto 0) := (others => '0'); + TRG_TYPE_IN : in std_logic_vector(3 downto 0) := (others => '0'); TRG_RELEASE_OUT : out std_logic; TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); DATA_OUT : out std_logic_vector(31 downto 0); @@ -91,12 +91,12 @@ end component; ESB_DATA_OUT : out std_logic_vector(31 downto 0); ESB_DATAREADY_OUT : out std_logic; ESB_UNKNOWN_ADDR_OUT : out std_logic; - FWB_READ_EN_IN : in std_logic; - FWB_WRITE_EN_IN : in std_logic; - FWB_ADDR_IN : in std_logic_vector(6 downto 0); - FWB_DATA_OUT : out std_logic_vector(31 downto 0); - FWB_DATAREADY_OUT : out std_logic; - FWB_UNKNOWN_ADDR_OUT : out std_logic; + EFB_READ_EN_IN : in std_logic; + EFB_WRITE_EN_IN : in std_logic; + EFB_ADDR_IN : in std_logic_vector(6 downto 0); + EFB_DATA_OUT : out std_logic_vector(31 downto 0); + EFB_DATAREADY_OUT : out std_logic; + EFB_UNKNOWN_ADDR_OUT : out std_logic; LHB_READ_EN_IN : in std_logic; LHB_WRITE_EN_IN : in std_logic; LHB_ADDR_IN : in std_logic_vector(6 downto 0); @@ -105,7 +105,7 @@ end component; LHB_UNKNOWN_ADDR_OUT : out std_logic; LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0); CONTROL_REG_IN : in std_logic_vector(32*CONTROL_REG_NR-1 downto 0)); - end component; + end component TDC; component Reference_Channel generic ( @@ -160,7 +160,7 @@ end component; COARSE_COUNTER_IN : in std_logic_vector(10 downto 0)); end component; - component Channel + component Channel is generic ( CHANNEL_ID : integer range 0 to 64); port ( @@ -170,8 +170,6 @@ end component; CLK_200 : in std_logic; CLK_100 : in std_logic; HIT_IN : in std_logic; - TRIGGER_IN : in std_logic; - SCALER_IN : in std_logic; TRIGGER_WIN_END_IN : in std_logic; READ_EN_IN : in std_logic; FIFO_DATA_OUT : out std_logic_vector(35 downto 0); @@ -181,16 +179,14 @@ end component; FIFO_ALMOST_FULL_OUT : out std_logic; COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); - DATA_FINISHED_IN : in std_logic; LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0); - FIFO_WR_NUMBER : out std_logic_vector(23 downto 0); ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0); Channel_DEBUG : out std_logic_vector(31 downto 0)); - end component; - - component Channel_200 + end component Channel; + + component Channel_200 is generic ( CHANNEL_ID : integer range 0 to 64); port ( @@ -199,11 +195,8 @@ end component; CLK_100 : in std_logic; RESET_100 : in std_logic; HIT_IN : in std_logic; - TRIGGER_IN : in std_logic; - SCALER_IN : in std_logic; TRIGGER_WIN_END_IN : in std_logic; EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); - DATA_FINISHED_IN : in std_logic; COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); READ_EN_IN : in std_logic; FIFO_DATA_OUT : out std_logic_vector(35 downto 0); @@ -211,12 +204,11 @@ end component; FIFO_EMPTY_OUT : out std_logic; FIFO_FULL_OUT : out std_logic; FIFO_ALMOST_FULL_OUT : out std_logic; - FIFO_WR_OUT : out std_logic; ENCODER_START_OUT : out std_logic; ENCODER_FINISHED_OUT : out std_logic); - end component; - - component Readout + end component Channel_200; + + component Readout is generic ( CHANNEL_NUMBER : integer range 2 to 65); port ( @@ -248,18 +240,17 @@ end component; TRG_CODE_IN : in std_logic_vector(7 downto 0); TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); TRG_TYPE_IN : in std_logic_vector(3 downto 0); + DATA_LIMIT_IN : in unsigned(7 downto 0); TRG_RELEASE_OUT : out std_logic; TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); DATA_OUT : out std_logic_vector(31 downto 0); DATA_WRITE_OUT : out std_logic; DATA_FINISHED_OUT : out std_logic; READ_EN_OUT : out std_logic_vector(CHANNEL_NUMBER-1 downto 0); - HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1); - READOUT_BUSY_OUT : out std_logic; TRIGGER_WIN_END_OUT : out std_logic; STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to 18); READOUT_DEBUG : out std_logic_vector(31 downto 0)); - end component; + end component Readout; component LogicAnalyser generic ( diff --git a/tdc_releases/ReleaseNotes.txt b/tdc_releases/ReleaseNotes.txt index 394ab7a..64c6f19 100644 --- a/tdc_releases/ReleaseNotes.txt +++ b/tdc_releases/ReleaseNotes.txt @@ -4,7 +4,9 @@ tdc_v2.0 15.11.2012 Double edge detection for longer than 20 ns is implemented. (Not stable-will be fixed in future releases.) -tdc_v1.4 Limiting data transfer functionality is added +tdc_v1.4 18.04.2013 Limiting data transfer functionality is + added. Use 0xc804 register to define the # of + word per channel to be read-out. tdc_v1.3 05.03.2013 Encoder efficiency is increased to 100%. Extra bits are encoded in the data (low resolution diff --git a/tdc_releases/tdc_v1.4/trb3_periph.vhd b/tdc_releases/tdc_v1.4/trb3_periph.vhd index 3488cca..a23d08a 100644 --- a/tdc_releases/tdc_v1.4/trb3_periph.vhd +++ b/tdc_releases/tdc_v1.4/trb3_periph.vhd @@ -230,7 +230,7 @@ architecture trb3_periph_arch of trb3_periph is signal tdc_ctrl_read : std_logic; signal last_tdc_ctrl_read : std_logic; signal tdc_ctrl_write : std_logic; - signal tdc_ctrl_addr : std_logic_vector(1 downto 0); + signal tdc_ctrl_addr : std_logic_vector(2 downto 0); signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); signal tdc_ctrl_reg : std_logic_vector(5*32-1 downto 0); @@ -337,6 +337,7 @@ begin -- -- x"4" - Wasa AddOn --edge_type_i <= x"0"; -- x"0" - single edge -- -- x"1" - double edge + -- -- x"8" - double edge on consecutive channels --tdc_channel_no_i <= x"6"; -- 2^n channels THE_ENDPOINT : trb_net16_endpoint_hades_full_handler @@ -347,7 +348,7 @@ begin BROADCAST_BITMASK => x"FF", BROADCAST_SPECIAL_ADDR => x"48", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => x"91000060", -- regio_hardware_version_i, + REGIO_HARDWARE_VERSION => x"91000860", -- regio_hardware_version_i, REGIO_INIT_ADDRESS => x"f305", REGIO_USE_VAR_ENDPOINT_ID => c_YES, CLOCK_FREQUENCY => 125, @@ -463,7 +464,7 @@ begin generic map( PORT_NUMBER => 9, PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 2, others => 0) + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, others => 0) ) port map( CLK => clk_100_i, @@ -580,8 +581,8 @@ begin BUS_READ_ENABLE_OUT(8) => tdc_ctrl_read, BUS_WRITE_ENABLE_OUT(8) => tdc_ctrl_write, BUS_DATA_OUT(8*32+31 downto 8*32) => tdc_ctrl_data_in, - BUS_ADDR_OUT(8*16+1 downto 8*16) => tdc_ctrl_addr, - BUS_ADDR_OUT(8*16+15 downto 8*16+2) => open, + BUS_ADDR_OUT(8*16+2 downto 8*16) => tdc_ctrl_addr, + BUS_ADDR_OUT(8*16+15 downto 8*16+3) => open, BUS_TIMEOUT_OUT(8) => open, BUS_DATA_IN(8*32+31 downto 8*32) => tdc_ctrl_data_out, BUS_DATAREADY_IN(8) => last_tdc_ctrl_read, @@ -710,14 +711,14 @@ begin THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 5, -- Number of TDC channels - CONTROL_REG_NR => 5) -- Number of control regs + CHANNEL_NUMBER => 65, -- Number of TDC channels + CONTROL_REG_NR => 5) -- Number of control regs - higher than 8 check tdc_ctrl_addr port map ( RESET => reset_i, CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement CLK_READOUT => clk_100_i, -- Clock for the readout - REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(4 downto 1), -- Channel start signals + REFERENCE_TIME => timing_trg_received_i, -- Reference time input + HIT_IN => hit_in_i(64 downto 1), -- Channel start signals TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width -- diff --git a/tdc_test/compile_constraints.pl b/tdc_test/compile_constraints.pl old mode 100644 new mode 100755 index cc53986..a34a22a --- a/tdc_test/compile_constraints.pl +++ b/tdc_test/compile_constraints.pl @@ -4,8 +4,10 @@ use warnings; use strict; my $TOPNAME = "trb3_periph"; #Name of top-level entity -my $BasePath = "../base/"; #path to "base" directory + #create full lpf file -system("cp ../base/trb3_periph_mainz.lpf workdir/$TOPNAME.lpf"); -system("cat ../tdc_releases/tdc_v0.5/".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); +system("cp ../base/trb3_periph_mainz.lpf diamond/$TOPNAME.lpf"); +system("cat ../tdc_releases/tdc_v1.4/trbnet_constraints.lpf >> diamond/$TOPNAME.lpf"); +system("cat ../tdc_releases/tdc_v1.4/tdc_constraints.lpf >> diamond/$TOPNAME.lpf"); + diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd index e2b8b00..9de4ea2 100644 --- a/wasa/trb3_periph_padiwa.vhd +++ b/wasa/trb3_periph_padiwa.vhd @@ -387,6 +387,7 @@ begin -- -- x"4" - Wasa AddOn --edge_type_i <= x"0"; -- x"0" - single edge -- -- x"1" - double edge + -- -- x"8" - double edge on consecutive channels --tdc_channel_no_i <= x"6"; -- 2^n channels THE_ENDPOINT : trb_net16_endpoint_hades_full_handler @@ -397,7 +398,7 @@ begin BROADCAST_BITMASK => x"FF", BROADCAST_SPECIAL_ADDR => x"48", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => x"91004160", + REGIO_HARDWARE_VERSION => x"91004860", REGIO_INIT_ADDRESS => x"f306", REGIO_USE_VAR_ENDPOINT_ID => c_YES, CLOCK_FREQUENCY => 100,