From: hadeshyp Date: Thu, 31 Jan 2008 16:19:26 +0000 (+0000) Subject: reorderd fifo files for virtex 2 & 4, Jan X-Git-Tag: oldGBE~611 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1d68f2f8284df7525fbff95c996d11010734196c;p=trbnet.git reorderd fifo files for virtex 2 & 4, Jan --- diff --git a/xilinx/trb_net16_bram_fifo.vhd b/oldfiles/trb_net16_bram_fifo.vhd similarity index 100% rename from xilinx/trb_net16_bram_fifo.vhd rename to oldfiles/trb_net16_bram_fifo.vhd diff --git a/xilinx/trb_net_fifo_arch.vhd b/oldfiles/trb_net_fifo_arch.vhd similarity index 100% rename from xilinx/trb_net_fifo_arch.vhd rename to oldfiles/trb_net_fifo_arch.vhd diff --git a/xilinx/virtex2/trb_net16_fifo_arch.vhd b/xilinx/virtex2/trb_net16_fifo_arch.vhd new file mode 100644 index 0000000..3fa402c --- /dev/null +++ b/xilinx/virtex2/trb_net16_fifo_arch.vhd @@ -0,0 +1,191 @@ +library ieee; + +use ieee.std_logic_1164.all; +USE ieee.std_logic_signed.ALL; +USE IEEE.numeric_std.ALL; +use work.trb_net_std.all; + +-- entity trb_net16_fifo is +-- generic ( +-- USE_VENDOR_CORES : integer range 0 to 1 := c_NO; +-- DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets +-- ); +-- port ( +-- CLK : in std_logic; +-- RESET : in std_logic; +-- CLK_EN : in std_logic; +-- DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data +-- PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data +-- WRITE_ENABLE_IN : in std_logic; +-- DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data +-- PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data +-- READ_ENABLE_IN : in std_logic; +-- FULL_OUT : out std_logic; -- Full Flag +-- EMPTY_OUT : out std_logic; +-- DEPTH_OUT : out std_logic_vector(7 downto 0) +-- ); +-- end entity; + +architecture arch_trb_net16_fifo of trb_net16_fifo is + component xilinx_fifo_18x1k + port ( + clk: IN std_logic; + rst: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic + ); + end component; + + component xilinx_fifo_18x16 + port ( + clk: IN std_logic; + rst: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic + ); + end component; + + component xilinx_fifo_18x32 + port ( + clk: IN std_logic; + rst: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic + ); + end component; + + component xilinx_fifo_18x64 + port ( + clk: IN std_logic; + rst: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic + ); + end component; + + component xilinx_fifo_lut + generic ( + WIDTH : integer := 18; + DEPTH : integer := 3 + ); + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic + ); + end component; + + signal din, dout : std_logic_vector(c_DATA_WIDTH + c_NUM_WIDTH-1 downto 0); + signal depth16 : std_logic_vector(7 downto 0); + +begin + din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; + din(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; + DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT <= dout(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH); + DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8)); + + gen_FIFO6 : if DEPTH = 6 generate + fifo:xilinx_fifo_18x1k + port map ( + clk => CLK, + rd_en => READ_ENABLE_IN, + wr_en => WRITE_ENABLE_IN, + din => din, + rst => RESET, + dout => dout, + full => FULL_OUT, + empty => EMPTY_OUT + ); + end generate; + + gen_OWN_CORES : if USE_VENDOR_CORES = c_NO generate + gen_FIFO_LUT : if DEPTH < 6 generate + fifo:xilinx_fifo_lut + generic map ( + WIDTH => c_DATA_WIDTH + c_NUM_WIDTH, + DEPTH => ((DEPTH+3)) + ) + port map ( + clk => CLK, + rd_en => READ_ENABLE_IN, + wr_en => WRITE_ENABLE_IN, + din => din, + sinit => RESET, + dout => dout, + full => FULL_OUT, + empty => EMPTY_OUT + ); + end generate; + end generate; + + gen_XILINX_CORES : if USE_VENDOR_CORES = c_YES generate + gen_FIFO1 : if DEPTH = 1 generate + fifo:xilinx_fifo_18x16 + port map ( + clk => CLK, + rd_en => READ_ENABLE_IN, + wr_en => WRITE_ENABLE_IN, + din => din, + rst => RESET, + dout => dout, + full => FULL_OUT, + empty => EMPTY_OUT + ); + end generate; + + gen_FIFO2 : if DEPTH = 2 generate + fifo:xilinx_fifo_18x32 + port map ( + clk => CLK, + rd_en => READ_ENABLE_IN, + wr_en => WRITE_ENABLE_IN, + din => din, + rst => RESET, + dout => dout, + full => FULL_OUT, + empty => EMPTY_OUT + ); + end generate; + + + gen_FIFO3 : if DEPTH = 3 generate + fifo:xilinx_fifo_18x64 + port map ( + clk => CLK, + rd_en => READ_ENABLE_IN, + wr_en => WRITE_ENABLE_IN, + din => din, + rst => RESET, + dout => dout, + full => FULL_OUT, + empty => EMPTY_OUT + ); + end generate; + end generate; + + +end architecture; + + diff --git a/xilinx/virtex2/xilinx_fifo_18x16.xco b/xilinx/virtex2/xilinx_fifo_18x16.xco new file mode 100644 index 0000000..e7eafec --- /dev/null +++ b/xilinx/virtex2/xilinx_fifo_18x16.xco @@ -0,0 +1,64 @@ +# BEGIN Project Options +SET flowvendor = Foundation_iSE +SET vhdlsim = True +SET verilogsim = True +SET workingdirectory = . +SET speedgrade = -5 +SET simulationfiles = Behavioral +SET asysymbol = True +SET addpads = False +SET device = xc2v250 +SET implementationfiletype = Edif +SET busformat = BusFormatAngleBracketNotRipped +SET foundationsym = False +SET package = fg456 +SET createndf = False +SET designentry = VHDL +SET devicefamily = virtex2 +SET formalverification = False +SET removerpms = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 2.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET write_data_count=false +CSET full_threshold_negate_value=12 +CSET empty_threshold_negate_value=4 +CSET output_data_width=18 +CSET input_depth=16 +CSET valid_flag=false +CSET empty_threshold_negate_presets=3/4_Empty +CSET write_acknowledge_flag=false +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET full_threshold_negate_presets=3/4_Full +CSET fifo_implementation=Common_Clock_Shift_Register +CSET underflow_flag=false +CSET use_extra_logic=false +CSET register_outputs=false +CSET valid_sense=Active_High +CSET write_data_count_width=2 +CSET data_count_width=2 +CSET output_depth=16 +CSET dout_reset_value=0 +CSET underflow_sense=Active_High +CSET component_name=xilinx_fifo_18x16 +CSET overflow_sense=Active_High +CSET overflow_flag=false +CSET read_data_count=false +CSET data_count=false +CSET primitive_depth=512 +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_data_count_width=2 +CSET read_latency=1 +CSET empty_threshold_assert_presets=3/4_Empty +CSET full_threshold_assert_value=12 +CSET almost_full_flag=false +CSET full_threshold_assert_presets=3/4_Full +CSET write_acknowledge_sense=Active_High +CSET empty_threshold_assert_value=4 +CSET input_data_width=18 +# END Parameters +GENERATE + diff --git a/xilinx/virtex2/xilinx_fifo_18x1k.xco b/xilinx/virtex2/xilinx_fifo_18x1k.xco new file mode 100644 index 0000000..104ed7f --- /dev/null +++ b/xilinx/virtex2/xilinx_fifo_18x1k.xco @@ -0,0 +1,64 @@ +# BEGIN Project Options +SET flowvendor = Foundation_iSE +SET vhdlsim = True +SET verilogsim = True +SET workingdirectory = . +SET speedgrade = -5 +SET simulationfiles = Behavioral +SET asysymbol = True +SET addpads = False +SET device = xc2v250 +SET implementationfiletype = Edif +SET busformat = BusFormatAngleBracketNotRipped +SET foundationsym = False +SET package = fg456 +SET createndf = False +SET designentry = VHDL +SET devicefamily = virtex2 +SET formalverification = False +SET removerpms = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 2.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET write_data_count=false +CSET full_threshold_negate_value=768 +CSET empty_threshold_negate_value=256 +CSET output_data_width=18 +CSET input_depth=1024 +CSET valid_flag=false +CSET empty_threshold_negate_presets=3/4_Empty +CSET write_acknowledge_flag=false +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET full_threshold_negate_presets=3/4_Full +CSET fifo_implementation=Common_Clock_Block_RAM +CSET underflow_flag=false +CSET use_extra_logic=false +CSET register_outputs=false +CSET valid_sense=Active_High +CSET write_data_count_width=2 +CSET data_count_width=2 +CSET output_depth=1024 +CSET dout_reset_value=0 +CSET underflow_sense=Active_High +CSET component_name=xilinx_fifo_18x1k +CSET overflow_sense=Active_High +CSET overflow_flag=false +CSET read_data_count=false +CSET data_count=false +CSET primitive_depth=1024 +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_data_count_width=2 +CSET read_latency=1 +CSET empty_threshold_assert_presets=3/4_Empty +CSET full_threshold_assert_value=768 +CSET almost_full_flag=false +CSET full_threshold_assert_presets=3/4_Full +CSET write_acknowledge_sense=Active_High +CSET empty_threshold_assert_value=256 +CSET input_data_width=18 +# END Parameters +GENERATE + diff --git a/xilinx/virtex2/xilinx_fifo_18x32.xco b/xilinx/virtex2/xilinx_fifo_18x32.xco new file mode 100644 index 0000000..19d40fd --- /dev/null +++ b/xilinx/virtex2/xilinx_fifo_18x32.xco @@ -0,0 +1,64 @@ +# BEGIN Project Options +SET flowvendor = Foundation_iSE +SET vhdlsim = True +SET verilogsim = True +SET workingdirectory = . +SET speedgrade = -5 +SET simulationfiles = Behavioral +SET asysymbol = True +SET addpads = False +SET device = xc2v250 +SET implementationfiletype = Edif +SET busformat = BusFormatAngleBracketNotRipped +SET foundationsym = False +SET package = fg456 +SET createndf = False +SET designentry = VHDL +SET devicefamily = virtex2 +SET formalverification = False +SET removerpms = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 2.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET write_data_count=false +CSET full_threshold_negate_value=12 +CSET empty_threshold_negate_value=4 +CSET output_data_width=18 +CSET input_depth=32 +CSET valid_flag=false +CSET empty_threshold_negate_presets=3/4_Empty +CSET write_acknowledge_flag=false +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET full_threshold_negate_presets=3/4_Full +CSET fifo_implementation=Common_Clock_Shift_Register +CSET underflow_flag=false +CSET use_extra_logic=false +CSET register_outputs=false +CSET valid_sense=Active_High +CSET write_data_count_width=2 +CSET data_count_width=2 +CSET output_depth=16 +CSET dout_reset_value=0 +CSET underflow_sense=Active_High +CSET component_name=xilinx_fifo_18x32 +CSET overflow_sense=Active_High +CSET overflow_flag=false +CSET read_data_count=false +CSET data_count=false +CSET primitive_depth=512 +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_data_count_width=2 +CSET read_latency=1 +CSET empty_threshold_assert_presets=3/4_Empty +CSET full_threshold_assert_value=12 +CSET almost_full_flag=false +CSET full_threshold_assert_presets=3/4_Full +CSET write_acknowledge_sense=Active_High +CSET empty_threshold_assert_value=4 +CSET input_data_width=18 +# END Parameters +GENERATE + diff --git a/xilinx/virtex2/xilinx_fifo_18x64.xco b/xilinx/virtex2/xilinx_fifo_18x64.xco new file mode 100644 index 0000000..e669430 --- /dev/null +++ b/xilinx/virtex2/xilinx_fifo_18x64.xco @@ -0,0 +1,64 @@ +# BEGIN Project Options +SET flowvendor = Foundation_iSE +SET vhdlsim = True +SET verilogsim = True +SET workingdirectory = . +SET speedgrade = -5 +SET simulationfiles = Behavioral +SET asysymbol = True +SET addpads = False +SET device = xc2v250 +SET implementationfiletype = Edif +SET busformat = BusFormatAngleBracketNotRipped +SET foundationsym = False +SET package = fg456 +SET createndf = False +SET designentry = VHDL +SET devicefamily = virtex2 +SET formalverification = False +SET removerpms = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 2.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET write_data_count=false +CSET full_threshold_negate_value=12 +CSET empty_threshold_negate_value=4 +CSET output_data_width=18 +CSET input_depth=64 +CSET valid_flag=false +CSET empty_threshold_negate_presets=3/4_Empty +CSET write_acknowledge_flag=false +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET full_threshold_negate_presets=3/4_Full +CSET fifo_implementation=Common_Clock_Shift_Register +CSET underflow_flag=false +CSET use_extra_logic=false +CSET register_outputs=false +CSET valid_sense=Active_High +CSET write_data_count_width=2 +CSET data_count_width=2 +CSET output_depth=16 +CSET dout_reset_value=0 +CSET underflow_sense=Active_High +CSET component_name=xilinx_fifo_18x64 +CSET overflow_sense=Active_High +CSET overflow_flag=false +CSET read_data_count=false +CSET data_count=false +CSET primitive_depth=512 +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_data_count_width=2 +CSET read_latency=1 +CSET empty_threshold_assert_presets=3/4_Empty +CSET full_threshold_assert_value=12 +CSET almost_full_flag=false +CSET full_threshold_assert_presets=3/4_Full +CSET write_acknowledge_sense=Active_High +CSET empty_threshold_assert_value=4 +CSET input_data_width=18 +# END Parameters +GENERATE + diff --git a/xilinx/trb_net16_fifo_arch.vhd b/xilinx/virtex4/trb_net16_fifo_arch.vhd similarity index 97% rename from xilinx/trb_net16_fifo_arch.vhd rename to xilinx/virtex4/trb_net16_fifo_arch.vhd index 9b02688..c5a3ff0 100644 --- a/xilinx/trb_net16_fifo_arch.vhd +++ b/xilinx/virtex4/trb_net16_fifo_arch.vhd @@ -36,8 +36,7 @@ architecture arch_trb_net16_fifo of trb_net16_fifo is rd_en: IN std_logic; dout: OUT std_logic_VECTOR(17 downto 0); full: OUT std_logic; - empty: OUT std_logic; - data_count: OUT std_logic_VECTOR(3 downto 0) + empty: OUT std_logic ); end component; @@ -117,8 +116,7 @@ begin sinit => RESET, dout => dout, full => FULL_OUT, - empty => EMPTY_OUT, - data_count => open + empty => EMPTY_OUT ); end generate; diff --git a/xilinx/xilinx_fifo_18x16.xco b/xilinx/virtex4/xilinx_fifo_18x16.xco similarity index 100% rename from xilinx/xilinx_fifo_18x16.xco rename to xilinx/virtex4/xilinx_fifo_18x16.xco diff --git a/xilinx/xilinx_fifo_18x1k.xco b/xilinx/virtex4/xilinx_fifo_18x1k.xco similarity index 93% rename from xilinx/xilinx_fifo_18x1k.xco rename to xilinx/virtex4/xilinx_fifo_18x1k.xco index c913add..d956d6c 100644 --- a/xilinx/xilinx_fifo_18x1k.xco +++ b/xilinx/virtex4/xilinx_fifo_18x1k.xco @@ -2,7 +2,7 @@ SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True -SET workingdirectory = /d/jspc19/trb/ot_trb2/ise8 +SET workingdirectory = . SET speedgrade = -10 SET simulationfiles = Behavioral SET asysymbol = True @@ -30,7 +30,7 @@ CSET read_acknowledge_sense=Active_Low CSET data_count_width=4 CSET fifo_depth=1024 CSET component_name=xilinx_fifo_18x1k -CSET data_count=true +CSET data_count=false CSET read_acknowledge_flag=false CSET read_error_sense=Active_Low CSET read_error_flag=false diff --git a/xilinx/xilinx_fifo_18x32.xco b/xilinx/virtex4/xilinx_fifo_18x32.xco similarity index 95% rename from xilinx/xilinx_fifo_18x32.xco rename to xilinx/virtex4/xilinx_fifo_18x32.xco index bb3e5eb..c541337 100644 --- a/xilinx/xilinx_fifo_18x32.xco +++ b/xilinx/virtex4/xilinx_fifo_18x32.xco @@ -2,7 +2,7 @@ SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True -SET workingdirectory = /d/jspc19/trb/ot_trb2/ise8 +SET workingdirectory = . SET speedgrade = -10 SET simulationfiles = Behavioral SET asysymbol = True diff --git a/xilinx/xilinx_fifo_18x64.xco b/xilinx/virtex4/xilinx_fifo_18x64.xco similarity index 95% rename from xilinx/xilinx_fifo_18x64.xco rename to xilinx/virtex4/xilinx_fifo_18x64.xco index 9b17203..21ecab7 100644 --- a/xilinx/xilinx_fifo_18x64.xco +++ b/xilinx/virtex4/xilinx_fifo_18x64.xco @@ -2,7 +2,7 @@ SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True -SET workingdirectory = /d/jspc19/trb/ot_trb2/ise8 +SET workingdirectory = . SET speedgrade = -10 SET simulationfiles = Behavioral SET asysymbol = True diff --git a/xilinx/xilinx_fifo_18x16.vhd b/xilinx/xilinx_fifo_18x16.vhd deleted file mode 100644 index c873934..0000000 --- a/xilinx/xilinx_fifo_18x16.vhd +++ /dev/null @@ -1,105 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2005 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- You must compile the wrapper file xilinx_fifo_18x16.vhd when simulating --- the core, xilinx_fifo_18x16. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synopsys directives "translate_off/translate_on" specified --- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; --- synopsys translate_off -Library XilinxCoreLib; --- synopsys translate_on -ENTITY xilinx_fifo_18x16 IS - port ( - clk: IN std_logic; - sinit: IN std_logic; - din: IN std_logic_VECTOR(17 downto 0); - wr_en: IN std_logic; - rd_en: IN std_logic; - dout: OUT std_logic_VECTOR(17 downto 0); - full: OUT std_logic; - empty: OUT std_logic); -END xilinx_fifo_18x16; - -ARCHITECTURE xilinx_fifo_18x16_a OF xilinx_fifo_18x16 IS --- synopsys translate_off -component wrapped_xilinx_fifo_18x16 - port ( - clk: IN std_logic; - sinit: IN std_logic; - din: IN std_logic_VECTOR(17 downto 0); - wr_en: IN std_logic; - rd_en: IN std_logic; - dout: OUT std_logic_VECTOR(17 downto 0); - full: OUT std_logic; - empty: OUT std_logic); -end component; - --- Configuration specification - for all : wrapped_xilinx_fifo_18x16 use entity XilinxCoreLib.sync_fifo_v5_0(behavioral) - generic map( - c_read_data_width => 18, - c_has_wr_ack => 0, - c_dcount_width => 1, - c_has_wr_err => 0, - c_wr_err_low => 1, - c_wr_ack_low => 1, - c_enable_rlocs => 0, - c_has_dcount => 0, - c_rd_err_low => 1, - c_rd_ack_low => 1, - c_read_depth => 16, - c_has_rd_ack => 0, - c_write_depth => 16, - c_ports_differ => 0, - c_memory_type => 0, - c_write_data_width => 18, - c_has_rd_err => 0); --- synopsys translate_on -BEGIN --- synopsys translate_off -U0 : wrapped_xilinx_fifo_18x16 - port map ( - clk => clk, - sinit => sinit, - din => din, - wr_en => wr_en, - rd_en => rd_en, - dout => dout, - full => full, - empty => empty); --- synopsys translate_on - -END xilinx_fifo_18x16_a; - diff --git a/xilinx/xilinx_fifo_18x1k.vhd b/xilinx/xilinx_fifo_18x1k.vhd deleted file mode 100644 index f654692..0000000 --- a/xilinx/xilinx_fifo_18x1k.vhd +++ /dev/null @@ -1,108 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2005 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- You must compile the wrapper file xilinx_fifo_18x1k.vhd when simulating --- the core, xilinx_fifo_18x1k. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synopsys directives "translate_off/translate_on" specified --- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; --- synopsys translate_off -Library XilinxCoreLib; --- synopsys translate_on -ENTITY xilinx_fifo_18x1k IS - port ( - clk: IN std_logic; - sinit: IN std_logic; - din: IN std_logic_VECTOR(17 downto 0); - wr_en: IN std_logic; - rd_en: IN std_logic; - dout: OUT std_logic_VECTOR(17 downto 0); - full: OUT std_logic; - empty: OUT std_logic; - data_count: OUT std_logic_VECTOR(3 downto 0)); -END xilinx_fifo_18x1k; - -ARCHITECTURE xilinx_fifo_18x1k_a OF xilinx_fifo_18x1k IS --- synopsys translate_off -component wrapped_xilinx_fifo_18x1k - port ( - clk: IN std_logic; - sinit: IN std_logic; - din: IN std_logic_VECTOR(17 downto 0); - wr_en: IN std_logic; - rd_en: IN std_logic; - dout: OUT std_logic_VECTOR(17 downto 0); - full: OUT std_logic; - empty: OUT std_logic; - data_count: OUT std_logic_VECTOR(3 downto 0)); -end component; - --- Configuration specification - for all : wrapped_xilinx_fifo_18x1k use entity XilinxCoreLib.sync_fifo_v5_0(behavioral) - generic map( - c_read_data_width => 18, - c_has_wr_ack => 0, - c_dcount_width => 4, - c_has_wr_err => 0, - c_wr_err_low => 1, - c_wr_ack_low => 1, - c_enable_rlocs => 0, - c_has_dcount => 1, - c_rd_err_low => 1, - c_rd_ack_low => 1, - c_read_depth => 1024, - c_has_rd_ack => 0, - c_write_depth => 1024, - c_ports_differ => 0, - c_memory_type => 1, - c_write_data_width => 18, - c_has_rd_err => 0); --- synopsys translate_on -BEGIN --- synopsys translate_off -U0 : wrapped_xilinx_fifo_18x1k - port map ( - clk => clk, - sinit => sinit, - din => din, - wr_en => wr_en, - rd_en => rd_en, - dout => dout, - full => full, - empty => empty, - data_count => data_count); --- synopsys translate_on - -END xilinx_fifo_18x1k_a; - diff --git a/xilinx/xilinx_fifo_18x32.vhd b/xilinx/xilinx_fifo_18x32.vhd deleted file mode 100644 index 3117180..0000000 --- a/xilinx/xilinx_fifo_18x32.vhd +++ /dev/null @@ -1,105 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2005 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- You must compile the wrapper file xilinx_fifo_18x32.vhd when simulating --- the core, xilinx_fifo_18x32. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synopsys directives "translate_off/translate_on" specified --- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; --- synopsys translate_off -Library XilinxCoreLib; --- synopsys translate_on -ENTITY xilinx_fifo_18x32 IS - port ( - clk: IN std_logic; - sinit: IN std_logic; - din: IN std_logic_VECTOR(17 downto 0); - wr_en: IN std_logic; - rd_en: IN std_logic; - dout: OUT std_logic_VECTOR(17 downto 0); - full: OUT std_logic; - empty: OUT std_logic); -END xilinx_fifo_18x32; - -ARCHITECTURE xilinx_fifo_18x32_a OF xilinx_fifo_18x32 IS --- synopsys translate_off -component wrapped_xilinx_fifo_18x32 - port ( - clk: IN std_logic; - sinit: IN std_logic; - din: IN std_logic_VECTOR(17 downto 0); - wr_en: IN std_logic; - rd_en: IN std_logic; - dout: OUT std_logic_VECTOR(17 downto 0); - full: OUT std_logic; - empty: OUT std_logic); -end component; - --- Configuration specification - for all : wrapped_xilinx_fifo_18x32 use entity XilinxCoreLib.sync_fifo_v5_0(behavioral) - generic map( - c_read_data_width => 18, - c_has_wr_ack => 0, - c_dcount_width => 1, - c_has_wr_err => 0, - c_wr_err_low => 1, - c_wr_ack_low => 1, - c_enable_rlocs => 0, - c_has_dcount => 0, - c_rd_err_low => 1, - c_rd_ack_low => 1, - c_read_depth => 32, - c_has_rd_ack => 0, - c_write_depth => 32, - c_ports_differ => 0, - c_memory_type => 0, - c_write_data_width => 18, - c_has_rd_err => 0); --- synopsys translate_on -BEGIN --- synopsys translate_off -U0 : wrapped_xilinx_fifo_18x32 - port map ( - clk => clk, - sinit => sinit, - din => din, - wr_en => wr_en, - rd_en => rd_en, - dout => dout, - full => full, - empty => empty); --- synopsys translate_on - -END xilinx_fifo_18x32_a; - diff --git a/xilinx/xilinx_fifo_18x64.vhd b/xilinx/xilinx_fifo_18x64.vhd deleted file mode 100644 index 905c353..0000000 --- a/xilinx/xilinx_fifo_18x64.vhd +++ /dev/null @@ -1,105 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2005 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- You must compile the wrapper file xilinx_fifo_18x64.vhd when simulating --- the core, xilinx_fifo_18x64. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synopsys directives "translate_off/translate_on" specified --- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; --- synopsys translate_off -Library XilinxCoreLib; --- synopsys translate_on -ENTITY xilinx_fifo_18x64 IS - port ( - clk: IN std_logic; - sinit: IN std_logic; - din: IN std_logic_VECTOR(17 downto 0); - wr_en: IN std_logic; - rd_en: IN std_logic; - dout: OUT std_logic_VECTOR(17 downto 0); - full: OUT std_logic; - empty: OUT std_logic); -END xilinx_fifo_18x64; - -ARCHITECTURE xilinx_fifo_18x64_a OF xilinx_fifo_18x64 IS --- synopsys translate_off -component wrapped_xilinx_fifo_18x64 - port ( - clk: IN std_logic; - sinit: IN std_logic; - din: IN std_logic_VECTOR(17 downto 0); - wr_en: IN std_logic; - rd_en: IN std_logic; - dout: OUT std_logic_VECTOR(17 downto 0); - full: OUT std_logic; - empty: OUT std_logic); -end component; - --- Configuration specification - for all : wrapped_xilinx_fifo_18x64 use entity XilinxCoreLib.sync_fifo_v5_0(behavioral) - generic map( - c_read_data_width => 18, - c_has_wr_ack => 0, - c_dcount_width => 1, - c_has_wr_err => 0, - c_wr_err_low => 1, - c_wr_ack_low => 1, - c_enable_rlocs => 0, - c_has_dcount => 0, - c_rd_err_low => 1, - c_rd_ack_low => 1, - c_read_depth => 64, - c_has_rd_ack => 0, - c_write_depth => 64, - c_ports_differ => 0, - c_memory_type => 0, - c_write_data_width => 18, - c_has_rd_err => 0); --- synopsys translate_on -BEGIN --- synopsys translate_off -U0 : wrapped_xilinx_fifo_18x64 - port map ( - clk => clk, - sinit => sinit, - din => din, - wr_en => wr_en, - rd_en => rd_en, - dout => dout, - full => full, - empty => empty); --- synopsys translate_on - -END xilinx_fifo_18x64_a; -