From: Jan Michel Date: Mon, 17 Nov 2014 09:59:47 +0000 (+0100) Subject: gbe update X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1d7941b0bfe803f701e84dc27e6203280c67dde6;p=trbnet.git gbe update --- diff --git a/gbe2_ecp3/trb_net16_gbe_buf.vhd b/gbe2_ecp3/trb_net16_gbe_buf.vhd index 98ccb27..c6196dd 100755 --- a/gbe2_ecp3/trb_net16_gbe_buf.vhd +++ b/gbe2_ecp3/trb_net16_gbe_buf.vhd @@ -22,9 +22,12 @@ generic( USE_125MHZ_EXTCLK : integer range 0 to 1 := 1; FIXED_SIZE_MODE : integer range 0 to 1 := 1; + INCREMENTAL_MODE : integer range 0 to 1 := 0; FIXED_SIZE : integer range 0 to 65535 := 10; FIXED_DELAY_MODE : integer range 0 to 1 := 1; - FIXED_DELAY : integer range 0 to 65535 := 4096 + UP_DOWN_MODE : integer range 0 to 1 := 0; + UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; + FIXED_DELAY : integer range 0 to 16777215 := 16777215 ); port( CLK : in std_logic; @@ -761,7 +764,10 @@ main_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate generic map( DO_SIMULATION => DO_SIMULATION, FIXED_SIZE_MODE => FIXED_SIZE_MODE, + INCREMENTAL_MODE => INCREMENTAL_MODE, FIXED_SIZE => FIXED_SIZE, + UP_DOWN_MODE => UP_DOWN_MODE, + UP_DOWN_LIMIT => UP_DOWN_LIMIT, FIXED_DELAY_MODE => FIXED_DELAY_MODE, FIXED_DELAY => FIXED_DELAY ) diff --git a/gbe2_ecp3/trb_net16_gbe_event_constr.vhd b/gbe2_ecp3/trb_net16_gbe_event_constr.vhd index a93e6d9..2324dc0 100644 --- a/gbe2_ecp3/trb_net16_gbe_event_constr.vhd +++ b/gbe2_ecp3/trb_net16_gbe_event_constr.vhd @@ -83,6 +83,7 @@ signal load_eod_q : std_logic; signal loaded_queue_bytes : std_logic_vector(15 downto 0); signal shf_padding : std_logic; signal block_shf_after_divide, previous_tc_rd : std_logic; +signal block_term_after_divide : std_logic; begin @@ -512,7 +513,15 @@ begin header_ctr <= 3; elsif (TC_RD_EN_IN = '1') then if (load_current_state = LOAD_Q_HEADERS or load_current_state = LOAD_TERM or load_current_state = LOAD_PADDING) then - header_ctr <= header_ctr - 1; + if (load_current_state = LOAD_TERM) then + if (block_term_after_divide = '1') then + header_ctr <= 31; + else + header_ctr <= header_ctr - 1; + end if; + else + header_ctr <= header_ctr - 1; + end if; elsif (load_current_state = LOAD_SUB and block_shf_after_divide = '0') then header_ctr <= header_ctr - 1; else @@ -584,6 +593,7 @@ begin end if; end process; block_shf_after_divide <= '1' when previous_tc_rd = '0' and TC_RD_EN_IN = '1' and header_ctr = 15 else '0'; +block_term_after_divide <= '1' when previous_tc_rd = '0' and TC_RD_EN_IN = '1' and header_ctr = 31 else '0'; QUEUE_FIFO_RD_PROC : process(CLK) begin @@ -617,24 +627,32 @@ TERMINATION_PROC : process(CLK) begin if rising_edge(CLK) then if (load_current_state = IDLE) then - termination <= (others => '0'); + termination(255 downto 8) <= (others => '0'); elsif (TC_RD_EN_IN = '1' and term_ctr /= 33 and term_ctr /= 0) then - termination(255 downto 8) <= termination(247 downto 0); - - for I in 0 to 7 loop + termination(255 downto 8) <= termination(247 downto 0); + else + termination(255 downto 8) <= termination(255 downto 8); + end if; + end if; +end process TERMINATION_PROC; + +term_bits_gen : for I in 0 to 7 generate + process(CLK) + begin + if rising_edge(CLK) then + if (TC_RD_EN_IN = '1' and term_ctr /= 33 and term_ctr /= 0) then case (load_current_state) is when LOAD_Q_HEADERS => termination(I) <= qsf_q(I); when LOAD_SUB => termination(I) <= shf_q(I); when LOAD_DATA => termination(I) <= df_q(I); when others => termination(I) <= '0'; end case; - end loop; - - else - termination <= termination; + else + termination(I) <= termination(I); + end if; end if; - end if; -end process TERMINATION_PROC; + end process; +end generate term_bits_gen; TERM_CTR_PROC : process(CLK) begin diff --git a/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd b/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd index a1c5978..9120ba0 100755 --- a/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd +++ b/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd @@ -243,21 +243,17 @@ begin end process ipCsProc; -constructMachineProc: process( CLK ) +constructMachineProc: process(RESET, CLK ) begin if RESET = '1' then constructCurrentState <= IDLE; elsif( rising_edge(CLK) ) then --- if( RESET = '1' ) then --- constructCurrentState <= IDLE; --- else - constructCurrentState <= constructNextState; --- end if; + constructCurrentState <= constructNextState; end if; end process constructMachineProc; --find next state of construct machine -constructMachine: process( constructCurrentState, delay_ctr, FRAME_DELAY_IN, START_OF_DATA_IN, END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX, FRAME_TYPE_IN, DEST_IP_ADDRESS_IN, DEST_UDP_PORT_IN) +constructMachine: process( constructCurrentState, delay_ctr, FRAME_DELAY_IN, START_OF_DATA_IN, END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX, FRAME_TYPE_IN, DEST_UDP_PORT_IN) begin constructNextState <= constructCurrentState; if( headers_int_counter = cur_max ) then --can be checked everytime - if not in use, counter and cur_max are 0 @@ -403,7 +399,7 @@ begin end if; end process putUdpHeadersProc; -fpfWrEnProc : process(constructCurrentState, WR_EN_IN, RESET, LINK_OK_IN) +fpfWrEnProc : process(constructCurrentState, WR_EN_IN, LINK_OK_IN) begin if (LINK_OK_IN = '0') then -- gk 01.10.10 fpf_wr_en <= '0'; diff --git a/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd b/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd index a3df8c7..7a0c2d4 100644 --- a/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd +++ b/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd @@ -84,9 +84,9 @@ signal sizes_fifo_empty : std_logic; signal remove_ctr : std_logic_vector(7 downto 0); signal new_frame : std_logic; -signal new_frame_lock : std_logic; +signal new_frame_lock : std_logic := '0'; signal saved_frame_type : std_logic_vector(15 downto 0); -signal saved_vid : std_logic_vector(15 downto 0); +signal saved_vid : std_logic_vector(15 downto 0) := (others => '0'); signal saved_src_mac : std_logic_vector(47 downto 0); signal saved_dest_mac : std_logic_vector(47 downto 0); signal frame_type_valid : std_logic; @@ -139,7 +139,7 @@ begin end process NEW_FRAME_PROC; -FILTER_MACHINE_PROC : process(RX_MAC_CLK) +FILTER_MACHINE_PROC : process(RX_MAC_CLK, RESET) begin if RESET = '1' then filter_current_state <= IDLE; diff --git a/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd b/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd index 98815ab..3e77ecd 100644 --- a/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd +++ b/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd @@ -93,7 +93,7 @@ signal subevent_size : std_logic_vector(17 downto 0); signal trigger_type : std_logic_vector(3 downto 0); signal bank_select : std_logic_vector(3 downto 0); -signal readout_ctr : std_logic_vector(23 downto 0); +signal readout_ctr : std_logic_vector(23 downto 0) := x"000000"; signal pc_ready_q : std_logic; signal sf_afull_q : std_logic; signal sf_aempty : std_logic; diff --git a/gbe2_ecp3/trb_net16_gbe_main_control.vhd b/gbe2_ecp3/trb_net16_gbe_main_control.vhd index 714a973..07af024 100644 --- a/gbe2_ecp3/trb_net16_gbe_main_control.vhd +++ b/gbe2_ecp3/trb_net16_gbe_main_control.vhd @@ -593,20 +593,35 @@ end process; --*********************** -- LINK STATE CONTROL -LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK) -begin - if MC_RESET_LINK_IN = '1' then - link_current_state <= INACTIVE; - elsif rising_edge(CLK) then - if RX_PATH_ENABLE = 1 and DO_SIMULATION = 0 then - link_current_state <= link_next_state; - elsif DO_SIMULATION = 1 then - link_current_state <= ACTIVE; - else - link_current_state <= ACTIVE; +lsm_impl_gen : if DO_SIMULATION = 0 generate + LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK) + begin + if MC_RESET_LINK_IN = '1' then + link_current_state <= INACTIVE; + elsif rising_edge(CLK) then + if RX_PATH_ENABLE = 1 then + link_current_state <= link_next_state; + else + link_current_state <= INACTIVE; + end if; end if; - end if; -end process; + end process; +end generate lsm_impl_gen; + +lsm_sim_gen : if DO_SIMULATION = 1 generate + LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK) + begin + if MC_RESET_LINK_IN = '1' then + link_current_state <= GET_ADDRESS; + elsif rising_edge(CLK) then + if RX_PATH_ENABLE = 1 then + link_current_state <= link_next_state; + else + link_current_state <= ACTIVE; + end if; + end if; + end process; +end generate lsm_sim_gen; LINK_STATE_MACHINE : process(link_current_state, dhcp_done, wait_ctr, PCS_AN_COMPLETE_IN, tsm_ready, link_ok_timeout_ctr) begin @@ -647,7 +662,7 @@ begin if (PCS_AN_COMPLETE_IN = '0') then link_next_state <= INACTIVE; else - link_next_state <= WAIT_FOR_BOOT; --ACTIVE; + link_next_state <= ACTIVE; end if; when WAIT_FOR_BOOT => diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd index 170e37e..d4d301b 100644 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd +++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd @@ -193,7 +193,7 @@ begin when BOOTING => state2 <= x"1"; if (DHCP_START_IN = '1') then - main_next_state <= DELAY; --SENDING_DISCOVER; + main_next_state <= DELAY; else main_next_state <= BOOTING; end if; diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd index bae1424..deb3c07 100644 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd +++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd @@ -139,7 +139,7 @@ signal tc_rd_en : std_logic; signal tc_data : std_logic_vector(8 downto 0); signal tc_size : std_logic_vector(15 downto 0); signal tc_sod : std_logic; -signal pc_trig_type : std_logic_vector(3 downto 0); +signal pc_trig_type, pc_trig_type_shift : std_logic_vector(3 downto 0); type dissect_states is (IDLE, WAIT_FOR_LOAD, LOAD, CLEANUP); signal dissect_current_state, dissect_next_state : dissect_states; @@ -158,7 +158,105 @@ signal tc_sod_flag : std_logic; signal reset_all_hist : std_logic_vector(31 downto 0); signal ipu_monitor : std_logic_vector(223 downto 0); +-- JUST FOR DEBUGING PURPOSE +type sim_check_states is (IDLE, SAVE_HDR, GO_OVER_DATA, SAVE_TLR, GET_ONE_MORE, GET_SECOND_MORE, CLEANUP); +signal sim_check_current, sim_check_next : sim_check_states; + +signal hdr, tlr : std_logic_vector(255 downto 0); + + + begin + + +sim_check_gen : if DO_SIMULATION = 1 generate + + process(RESET, CLK) + begin + if RESET = '1' then + sim_check_current <= IDLE; + elsif rising_edge(CLK) then + sim_check_current <= sim_check_next; + end if; + end process; + + process(sim_check_current, tc_sod, loaded_bytes, tc_size, hdr, tlr, event_bytes) + begin + case (sim_check_current) is + + when IDLE => + if (tc_sod = '1') then + sim_check_next <= SAVE_HDR; + else + sim_check_next <= IDLE; + end if; + + when SAVE_HDR => + if (loaded_bytes = x"001f" + x"0002") then + sim_check_next <= GO_OVER_DATA; + else + sim_check_next <= SAVE_HDR; + end if; + + when GO_OVER_DATA => + if (loaded_bytes = tc_size + x"0001") then + sim_check_next <= SAVE_TLR; + else + sim_check_next <= GO_OVER_DATA; + end if; + + when SAVE_TLR => + if (loaded_bytes = event_bytes) then + sim_check_next <= GET_ONE_MORE; + else + sim_check_next <= SAVE_TLR; + end if; + + when GET_ONE_MORE => + sim_check_next <= GET_SECOND_MORE; + + when GET_SECOND_MORE => + sim_check_next <= CLEANUP; + + when CLEANUP => + + --assert (hdr = tlr) report "--------- >>>> Header Trailer mismatch" severity failure; + + sim_check_next <= IDLE; + + end case; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if (sim_check_current = SAVE_HDR and loaded_bytes > x"0001") then + hdr((to_integer(unsigned(loaded_bytes - x"0002") * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - x"0002")) * 8)) <= tc_data(7 downto 0); + else + hdr <= hdr; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if (sim_check_current = SAVE_TLR) then + tlr((to_integer(unsigned(loaded_bytes - tc_size - 2) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size - 2)) * 8)) <= tc_data(7 downto 0); + elsif (sim_check_current = GET_ONE_MORE) then + tlr((to_integer(unsigned(loaded_bytes - tc_size - 1) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size - 1)) * 8)) <= tc_data(7 downto 0); + elsif (sim_check_current = GET_ONE_MORE) then + tlr((to_integer(unsigned(loaded_bytes - tc_size) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size)) * 8)) <= tc_data(7 downto 0); + else + tlr <= tlr; + end if; + end if; + end process; + + +end generate sim_check_gen; + + THE_IP_CONFIGURATOR: ip_configurator @@ -273,7 +371,7 @@ port map( PC_DECODING_IN => CFG_SUBEVENT_DEC_IN, PC_EVENT_ID_IN => CFG_SUBEVENT_ID_IN, PC_TRIG_NR_IN => pc_trig_nr, - PC_TRIGGER_TYPE_IN => pc_trig_type, + PC_TRIGGER_TYPE_IN => pc_trig_type_shift, PC_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, PC_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, TC_RD_EN_IN => tc_rd_en, @@ -357,9 +455,13 @@ end process LOADED_BYTES_PROC; TC_FRAME_SIZE_OUT <= event_bytes; TC_FRAME_TYPE_OUT <= x"0008"; -TC_DEST_MAC_OUT <= ic_dest_mac_shift; --x"c4e870211b00"; --ic_dest_mac; -TC_DEST_IP_OUT <= ic_dest_ip_shift; --x"0300a8c0"; --ic_dest_ip; -TC_DEST_UDP_OUT <= ic_dest_udp_shift; --x"c35c"; --ic_dest_udp; +--TC_DEST_MAC_OUT <= ic_dest_mac_shift; --x"c4e870211b00"; --ic_dest_mac; +--TC_DEST_IP_OUT <= ic_dest_ip_shift; --x"0300a8c0"; --ic_dest_ip; +--TC_DEST_UDP_OUT <= ic_dest_udp_shift; --x"c35c"; --ic_dest_udp; + +TC_DEST_MAC_OUT <= x"87883c290c00"; --ic_dest_mac; +TC_DEST_IP_OUT <= x"0188a8c0"; --ic_dest_ip; +TC_DEST_UDP_OUT <= x"c35b"; --ic_dest_udp; process(CLK) begin @@ -368,25 +470,30 @@ begin ic_dest_mac_shift <= ic_dest_mac; ic_dest_ip_shift <= ic_dest_ip; ic_dest_udp_shift <= ic_dest_udp; + pc_trig_type_shift <= pc_trig_type; else ic_dest_mac_shift <= ic_dest_mac_shift; ic_dest_ip_shift <= ic_dest_ip_shift; ic_dest_udp_shift <= ic_dest_udp_shift; + pc_trig_type_shift <= pc_trig_type_shift; end if; end if; end process; -rx_enable_gen : if (RX_PATH_ENABLE = 1) generate - TC_SRC_MAC_OUT <= g_MY_MAC; - TC_SRC_IP_OUT <= g_MY_IP; -end generate rx_enable_gen; +--rx_enable_gen : if (RX_PATH_ENABLE = 1) generate +-- TC_SRC_MAC_OUT <= g_MY_MAC; +-- TC_SRC_IP_OUT <= g_MY_IP; +--end generate rx_enable_gen; +-- +--rx_disable_gen : if (RX_PATH_ENABLE = 0) generate +-- TC_SRC_MAC_OUT <= g_MY_MAC; +-- TC_SRC_IP_OUT <= ic_src_ip; +--end generate rx_disable_gen; -rx_disable_gen : if (RX_PATH_ENABLE = 0) generate - TC_SRC_MAC_OUT <= g_MY_MAC; - TC_SRC_IP_OUT <= ic_src_ip; -end generate rx_disable_gen; +TC_SRC_MAC_OUT <= x"99883c290c00"; +TC_SRC_IP_OUT <= x"0288a8c0"; TC_SRC_UDP_OUT <= ic_src_udp; TC_IP_PROTOCOL_OUT <= x"11"; @@ -486,7 +593,7 @@ MONITOR_SELECT_REC_OUT <= (others => '0'); DEBUG_OUT(31 downto 0) <= ipu_dbg(31 downto 0); DEBUG_OUT(63 downto 32) <= constr_dbg(31 downto 0); - + end trb_net16_gbe_response_constructor_TrbNetData; diff --git a/gbe2_ecp3/trb_net16_gbe_setup.vhd b/gbe2_ecp3/trb_net16_gbe_setup.vhd index ad6f4a6..c9bf2f3 100644 --- a/gbe2_ecp3/trb_net16_gbe_setup.vhd +++ b/gbe2_ecp3/trb_net16_gbe_setup.vhd @@ -143,7 +143,7 @@ begin insert_ttype <= '0'; additional_hdr <= '1'; GBE_SOFT_RESET_OUT <= '0'; - max_sub <= x"e998"; -- 59800 + max_sub <= x"e998"; -- 59800 max_queue <= x"ea60"; -- 60000 max_subs_in_queue <= x"00c8"; -- 200 max_single_sub <= x"7d00"; -- 32000 diff --git a/gbe2_ecp3/trb_net16_gbe_type_validator.vhd b/gbe2_ecp3/trb_net16_gbe_type_validator.vhd index 10fe5fe..23bab0d 100644 --- a/gbe2_ecp3/trb_net16_gbe_type_validator.vhd +++ b/gbe2_ecp3/trb_net16_gbe_type_validator.vhd @@ -52,10 +52,11 @@ signal partially_valid : std_logic; -- only protocols, vlan to be check signal zeros : std_logic_vector(c_MAX_FRAME_TYPES - 1 downto 0); begin + + zeros <= (others => '0'); -- DO NOT TOUCH IP_RESULTS_GEN : for i in 0 to c_MAX_IP_PROTOCOLS - 1 generate - process(CLK) begin if rising_edge(CLK) then @@ -66,11 +67,6 @@ begin end if; end if; end process; --- ip_result(i) <= '1' when ( --- IP_PROTOCOLS(i) = IP_PROTOCOLS_IN and --- ALLOWED_IP_PROTOCOLS_IN(i) = '1' --- ) else '0'; - end generate IP_RESULTS_GEN; UDP_RESULTS_GEN : for i in 0 to c_MAX_UDP_PROTOCOLS - 1 generate @@ -84,11 +80,6 @@ begin end if; end if; end process; --- udp_result(i) <= '1' when ( --- UDP_PROTOCOLS(i) = UDP_PROTOCOL_IN and --- ALLOWED_UDP_PROTOCOLS_IN(i) = '1' --- ) else '0'; - end generate UDP_RESULTS_GEN; @@ -103,11 +94,6 @@ begin end if; end if; end process; --- result(i) <= '1' when ( --- FRAME_TYPES(i) = FRAME_TYPE_IN and --- ALLOWED_TYPES_IN(i) = '1' --- ) else '0'; - end generate RESULT_GEN; PARTIALLY_VALID_PROC : process(CLK) @@ -124,18 +110,16 @@ begin partially_valid <= '0'; end if; elsif (result /= zeros) then-- other frame - partially_valid <= '1'; --or_all(result); + partially_valid <= '1'; else partially_valid <= '0'; end if; end if; end process PARTIALLY_VALID_PROC; -VALID_OUT_PROC : process(CLK) --partially_valid, SAVED_VLAN_ID_IN, VLAN_ID_IN) +VALID_OUT_PROC : process(CLK) begin if rising_edge(CLK) then - -- if (RESET = '1') then - -- VALID_OUT <= '0'; if (partially_valid = '1') then if (SAVED_VLAN_ID_IN = x"0000") then VALID_OUT <= '1'; @@ -152,53 +136,6 @@ begin end if; end process VALID_OUT_PROC; - --if rising_edge(CLK) then - -- if (SAVED_VLAN_ID_IN = x"0000") then -- frame without vlan tag - -- if (FRAME_TYPE_IN = x"0800") then -- in case of ip frame - -- if (IP_PROTOCOLS_IN = x"11") then -- in case of udp inside ip - -- VALID_OUT <= or_all(udp_result); - -- elsif (IP_PROTOCOLS_IN = x"01") then -- in case of ICMP - -- VALID_OUT <= '1'; - -- else -- do not accept other protocols than udp inside ip - -- VALID_OUT <= '0'; - -- end if; - -- else -- in case of other frame_type - -- VALID_OUT <= or_all(result); - -- end if; - -- - -- -- cases for tagged frames - -- elsif (VLAN_ID_IN = x"0000_0000") then -- no vlan id configured - -- VALID_OUT <= '0'; - -- elsif (SAVED_VLAN_ID_IN = VLAN_ID_IN(15 downto 0)) then -- match to first vlan id - -- if (FRAME_TYPE_IN = x"0800") then -- in case of ip frame - -- if (IP_PROTOCOLS_IN = x"11") then -- in case of udp inside ip - -- VALID_OUT <= or_all(udp_result); - -- elsif (IP_PROTOCOLS_IN = x"01") then -- in case of ICMP - -- VALID_OUT <= '1'; - -- else -- do not accept other protocols than udp inside ip - -- VALID_OUT <= '0'; - -- end if; - -- else -- in case of other frame_type - -- VALID_OUT <= or_all(result); - -- end if; - -- elsif (SAVED_VLAN_ID_IN = VLAN_ID_IN(31 downto 16)) then -- match to second vlan id - -- if (FRAME_TYPE_IN = x"0800") then -- in case of ip frame - -- if (IP_PROTOCOLS_IN = x"11") then -- in case of udp inside ip - -- VALID_OUT <= or_all(udp_result); - -- elsif (IP_PROTOCOLS_IN = x"01") then -- in case of ICMP - -- VALID_OUT <= '1'; - -- else -- do not accept other protocols than udp inside ip - -- VALID_OUT <= '0'; - -- end if; - -- else -- in case of other frame_type - -- VALID_OUT <= or_all(result); - -- end if; - -- else - -- VALID_OUT <= '0'; - -- end if; - --end if; ---end process VALID_OUT_PROC; - end trb_net16_gbe_type_validator; diff --git a/gbe2_ecp3/trb_net_gbe_components.vhd b/gbe2_ecp3/trb_net_gbe_components.vhd index fb98a11..42e2667 100644 --- a/gbe2_ecp3/trb_net_gbe_components.vhd +++ b/gbe2_ecp3/trb_net_gbe_components.vhd @@ -141,9 +141,12 @@ component gbe_ipu_dummy is generic ( DO_SIMULATION : integer range 0 to 1 := 0; FIXED_SIZE_MODE : integer range 0 to 1 := 1; + INCREMENTAL_MODE : integer range 0 to 1 := 0; FIXED_SIZE : integer range 0 to 65535 := 10; FIXED_DELAY_MODE : integer range 0 to 1 := 1; - FIXED_DELAY : integer range 0 to 65535 := 4096 + UP_DOWN_MODE : integer range 0 to 1 := 0; + UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; + FIXED_DELAY : integer range 0 to 16777215 := 16777215 ); port ( clk : in std_logic; @@ -210,9 +213,12 @@ generic( USE_125MHZ_EXTCLK : integer range 0 to 1 := 1; FIXED_SIZE_MODE : integer range 0 to 1 := 1; + INCREMENTAL_MODE : integer range 0 to 1 := 0; FIXED_SIZE : integer range 0 to 65535 := 10; + UP_DOWN_MODE : integer range 0 to 1 := 0; + UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; FIXED_DELAY_MODE : integer range 0 to 1 := 1; - FIXED_DELAY : integer range 0 to 65535 := 4096 + FIXED_DELAY : integer range 0 to 16777215 := 16777215 ); port( CLK : in std_logic;