From: Jan Michel Date: Fri, 10 Feb 2023 12:44:08 +0000 (+0100) Subject: update ecp5 media interfaces with 2-link interface on any dual X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1e2de2f8063fb88b69defc17241d3a389b5091f4;p=trbnet.git update ecp5 media interfaces with 2-link interface on any dual --- diff --git a/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd b/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd index c8b0baa..c68011e 100644 --- a/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd +++ b/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd @@ -159,7 +159,7 @@ begin pll_lol <= pll_lol_c; DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", - D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0", CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0", diff --git a/media_interfaces/ecp5/chan0_1/serdes_sync_1.vhd b/media_interfaces/ecp5/chan0_1/serdes_sync_1.vhd new file mode 100644 index 0000000..3375432 --- /dev/null +++ b/media_interfaces/ecp5/chan0_1/serdes_sync_1.vhd @@ -0,0 +1,436 @@ + +-- +-- Verific VHDL Description of module DCUA +-- + +-- DCUA is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module serdes_sync_0rsl_core +-- + +-- serdes_sync_0rsl_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module serdes_sync_0sll_core +-- + +-- serdes_sync_0sll_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module serdes_sync_0 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +library ecp5um ; +use ecp5um.components.all ; + +entity serdes_sync_1 is + port (hdoutp: out std_logic; + hdoutn: out std_logic; + hdinp: in std_logic; + hdinn: in std_logic; + rxrefclk: in std_logic; + rx_pclk: out std_logic; + tx_pclk: out std_logic; + txdata: in std_logic_vector(7 downto 0); + tx_k: in std_logic_vector(0 downto 0); + tx_force_disp: in std_logic_vector(0 downto 0); + tx_disp_sel: in std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_cv_err: out std_logic_vector(0 downto 0); + tx_idle_c: in std_logic; + signal_detect_c: in std_logic; + rx_los_low_s: out std_logic; + lsm_status_s: out std_logic; + rx_cdr_lol_s: out std_logic; + sli_rst: in std_logic; + tx_pwrup_c: in std_logic; + rx_pwrup_c: in std_logic; + sci_wrdata: in std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_en_dual: in std_logic; + sci_sel_dual: in std_logic; + sci_en: in std_logic; + sci_sel: in std_logic; + sci_rd: in std_logic; + sci_wrn: in std_logic; + sci_int: out std_logic; + cyawstn: in std_logic; + serdes_pdb: in std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + serdes_rst_dual_c: in std_logic; + rst_dual_c: in std_logic; + tx_serdes_rst_c: in std_logic; + tx_pcs_rst_c: in std_logic; + pll_lol: out std_logic; + rsl_tx_rdy: out std_logic; + rx_serdes_rst_c: in std_logic; + rx_pcs_rst_c: in std_logic; + rsl_rx_rdy: out std_logic + ); + +end entity serdes_sync_1; + +architecture v1 of serdes_sync_1 is + component serdes_sync_0rsl_core is + generic (pnum_channels: integer := 1; + pprotocol: string := "G8B10B"; + pserdes_mode: string := "RX AND TX"; + pport_tx_rdy: string := "ENABLED"; + pwait_tx_rdy: integer := 3000; + pport_rx_rdy: string := "ENABLED"; + pwait_rx_rdy: integer := 3000); + port (rui_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132) + rui_serdes_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133) + rui_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134) + rui_rsl_disable: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135) + rui_tx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137) + rui_tx_serdes_rst_c: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138) + rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139) + rdi_pll_lol: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140) + rui_rx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142) + rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143) + rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144) + rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145) + rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146) + rdo_serdes_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149) + rdo_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150) + ruo_tx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152) + rdo_tx_serdes_rst_c: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153) + rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154) + ruo_rx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156) + rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157) + rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158) + ); + + end component serdes_sync_0rsl_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88) + component serdes_sync_0sll_core is + generic (PPROTOCOL: string := "G8B10B"; + PLOL_SETTING: integer := 1; + PDYN_RATE_CTRL: string := "DISABLED"; + PPCIE_MAX_RATE: string := "2.5"; + PDIFF_VAL_LOCK: integer := 20; + PDIFF_VAL_UNLOCK: integer := 132; + PPCLK_TC: integer := 65536; + PDIFF_DIV11_VAL_LOCK: integer := 0; + PDIFF_DIV11_VAL_UNLOCK: integer := 0; + PPCLK_DIV11_TC: integer := 0); + port (sli_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(125) + sli_refclk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(126) + sli_pclk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(127) + sli_div2_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(128) + sli_div11_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(129) + sli_gear_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(130) + sli_cpri_mode: in std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(131) + sli_pcie_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(132) + slo_plol: out std_logic -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(135) + ); + + end component serdes_sync_0sll_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(107) + signal n48,n47,n1,n2,n3,n4,rx_pclk_c,tx_pclk_c,n5,n6,n7,n8,n9, + n10,n11,n12,rx_los_low_s_c,n13,n14,n15,n16,rx_cdr_lol_s_c,n17, + n18,rsl_tx_pcs_rst_c,rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c, + rsl_serdes_rst_dual_c,rsl_tx_serdes_rst_c,n19,n20,n21,n22,n23, + n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37, + n38,n39,n40,n41,n42,n43,n44,n45,n46,n49,n106,n105,n50,n51, + n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65, + n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79, + n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93, + n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n115,n114, + n113,pll_lol_c,n125,n124,n116,n117,n118,n119,n120,n121,n122, + n123,\_Z\,n127,n126,gnd,pwr : std_logic; + attribute LOC : string; + attribute LOC of DCU0_inst : label is "DCU0"; + attribute CHAN : string; + attribute CHAN of DCU0_inst : label is "CH1"; +begin + rx_pclk <= rx_pclk_c; + tx_pclk <= tx_pclk_c; + rx_los_low_s <= rx_los_low_s_c; + rx_cdr_lol_s <= rx_cdr_lol_s_c; + pll_lol <= pll_lol_c; + DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", + D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", + D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", + D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b1",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", + CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", + CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", + CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", + CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", + CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0", + CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b1", + CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b0", + CH1_MATCH_4_ENABLE=>"0b1",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x1BC", + CH1_CC_MATCH_2=>"0x11C",CH1_CC_MATCH_3=>"0x11C",CH1_CC_MATCH_4=>"0x11C", + CH1_UDF_COMMA_MASK=>"0x0ff",CH1_UDF_COMMA_A=>"0x083",CH1_UDF_COMMA_B=>"0x07C", + CH1_RX_DCO_CK_DIV=>"0b000",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1", + CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00", + CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b00",CH1_TDRV_SLICE1_SEL=>"0b00", + CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01", + CH1_TDRV_SLICE5_SEL=>"0b00",CH1_TDRV_SLICE0_CUR=>"0b000",CH1_TDRV_SLICE1_CUR=>"0b000", + CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b01", + CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0", + CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0", + CH1_SEL_SD_RX_CLK=>"0b1",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0", + CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0", + CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00", + CH1_REQ_EN=>"0b0",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1", + CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000", + CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b000",CH1_RX_LOS_CEQ=>"0b11", + CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0", + CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2",CH1_CDR_MAX_RATE=>"2", + CH1_TXAMPLITUDE=>"0d800",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED", + CH1_PROTOCOL=>"G8B10B",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b10",D_SETICONST_AUX=>"0b01", + D_SETIRPOLY_CH=>"0b10",D_SETICONST_CH=>"0b10",D_REQ_ISET=>"0b001", + D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00", + CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00", + CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b000",CH1_DCOCTLGI=>"0b011", + CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b00",CH1_DCOFTNRG=>"0b001", + CH1_DCOIOSTUNE=>"0b010",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b010", + CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b100",CH1_DCOSCALEI=>"0b01", + CH1_DCOSTARTVAL=>"0b010",CH1_DCOSTEP=>"0b11",CH1_BAND_THRESHOLD=>"0d0", + CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0", + CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0", + CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", + D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", + D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", + D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d10", + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b01", + D_RG_EN=>"0b0",D_RG_SET=>"0b00") + port map (CH0_HDINP=>n106,CH1_HDINP=>hdinp,CH0_HDINN=>n106,CH1_HDINN=>hdinn, + D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47, + CH0_RX_REFCLK=>n106,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n105,CH1_FF_RXI_CLK=>rx_pclk_c, + CH0_FF_TXI_CLK=>n105,CH1_FF_TXI_CLK=>tx_pclk_c,CH0_FF_EBRD_CLK=>n105, + CH1_FF_EBRD_CLK=>n48,CH0_FF_TX_D_0=>n106,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n106, + CH1_FF_TX_D_1=>txdata(1),CH0_FF_TX_D_2=>n106,CH1_FF_TX_D_2=>txdata(2), + CH0_FF_TX_D_3=>n106,CH1_FF_TX_D_3=>txdata(3),CH0_FF_TX_D_4=>n106,CH1_FF_TX_D_4=>txdata(4), + CH0_FF_TX_D_5=>n106,CH1_FF_TX_D_5=>txdata(5),CH0_FF_TX_D_6=>n106,CH1_FF_TX_D_6=>txdata(6), + CH0_FF_TX_D_7=>n106,CH1_FF_TX_D_7=>txdata(7),CH0_FF_TX_D_8=>n106,CH1_FF_TX_D_8=>tx_k(0), + CH0_FF_TX_D_9=>n106,CH1_FF_TX_D_9=>tx_force_disp(0),CH0_FF_TX_D_10=>n106, + CH1_FF_TX_D_10=>tx_disp_sel(0),CH0_FF_TX_D_11=>n106,CH1_FF_TX_D_11=>n47, + CH0_FF_TX_D_12=>n106,CH1_FF_TX_D_12=>n106,CH0_FF_TX_D_13=>n106,CH1_FF_TX_D_13=>n106, + CH0_FF_TX_D_14=>n106,CH1_FF_TX_D_14=>n106,CH0_FF_TX_D_15=>n106,CH1_FF_TX_D_15=>n106, + CH0_FF_TX_D_16=>n106,CH1_FF_TX_D_16=>n106,CH0_FF_TX_D_17=>n106,CH1_FF_TX_D_17=>n106, + CH0_FF_TX_D_18=>n106,CH1_FF_TX_D_18=>n106,CH0_FF_TX_D_19=>n106,CH1_FF_TX_D_19=>n106, + CH0_FF_TX_D_20=>n106,CH1_FF_TX_D_20=>n106,CH0_FF_TX_D_21=>n106,CH1_FF_TX_D_21=>n106, + CH0_FF_TX_D_22=>n106,CH1_FF_TX_D_22=>n106,CH0_FF_TX_D_23=>n106,CH1_FF_TX_D_23=>n47, + CH0_FFC_EI_EN=>n106,CH1_FFC_EI_EN=>tx_idle_c,CH0_FFC_PCIE_DET_EN=>n106, + CH1_FFC_PCIE_DET_EN=>n47,CH0_FFC_PCIE_CT=>n106,CH1_FFC_PCIE_CT=>n47,CH0_FFC_SB_INV_RX=>n106, + CH1_FFC_SB_INV_RX=>n106,CH0_FFC_ENABLE_CGALIGN=>n106,CH1_FFC_ENABLE_CGALIGN=>n106, + CH0_FFC_SIGNAL_DETECT=>n106,CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n106, + CH1_FFC_FB_LOOPBACK=>n47,CH0_FFC_SB_PFIFO_LP=>n106,CH1_FFC_SB_PFIFO_LP=>n47, + CH0_FFC_PFIFO_CLR=>n106,CH1_FFC_PFIFO_CLR=>n47,CH0_FFC_RATE_MODE_RX=>n106, + CH1_FFC_RATE_MODE_RX=>n106,CH0_FFC_RATE_MODE_TX=>n106,CH1_FFC_RATE_MODE_TX=>n106, + CH0_FFC_DIV11_MODE_RX=>n106,CH1_FFC_DIV11_MODE_RX=>n47,CH0_FFC_DIV11_MODE_TX=>n106, + CH1_FFC_DIV11_MODE_TX=>n47,CH0_FFC_RX_GEAR_MODE=>n106,CH1_FFC_RX_GEAR_MODE=>n47, + CH0_FFC_TX_GEAR_MODE=>n106,CH1_FFC_TX_GEAR_MODE=>n47,CH0_FFC_LDR_CORE2TX_EN=>n106, + CH1_FFC_LDR_CORE2TX_EN=>n106,CH0_FFC_LANE_TX_RST=>n106,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c, + CH0_FFC_LANE_RX_RST=>n106,CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n106, + CH1_FFC_RRST=>rsl_rx_serdes_rst_c,CH0_FFC_TXPWDNB=>n106,CH1_FFC_TXPWDNB=>tx_pwrup_c, + CH0_FFC_RXPWDNB=>n106,CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n106, + CH1_LDR_CORE2TX=>n106,D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1), + D_SCIWDATA2=>sci_wrdata(2),D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4), + D_SCIWDATA5=>sci_wrdata(5),D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7), + D_SCIADDR0=>sci_addr(0),D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2), + D_SCIADDR3=>sci_addr(3),D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5), + D_SCIENAUX=>sci_en_dual,D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n106,CH1_SCIEN=>sci_en, + CH0_SCISEL=>n106,CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn, + D_CYAWSTN=>cyawstn,D_FFC_SYNC_TOGGLE=>n106,D_FFC_DUAL_RST=>rsl_rst_dual_c, + D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c,D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c, + CH0_FFC_CDR_EN_BITSLIP=>n106,CH1_FFC_CDR_EN_BITSLIP=>n47,D_SCAN_ENABLE=>n47, + D_SCAN_IN_0=>n47,D_SCAN_IN_1=>n47,D_SCAN_IN_2=>n47,D_SCAN_IN_3=>n47, + D_SCAN_IN_4=>n47,D_SCAN_IN_5=>n47,D_SCAN_IN_6=>n47,D_SCAN_IN_7=>n47, + D_SCAN_MODE=>n47,D_SCAN_RESET=>n47,D_CIN0=>n47,D_CIN1=>n47,D_CIN2=>n47, + D_CIN3=>n47,D_CIN4=>n47,D_CIN5=>n47,D_CIN6=>n47,D_CIN7=>n47,D_CIN8=>n47, + D_CIN9=>n47,D_CIN10=>n47,D_CIN11=>n47,CH0_HDOUTP=>n50,CH1_HDOUTP=>hdoutp, + CH0_HDOUTN=>n51,CH1_HDOUTN=>hdoutn,D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2, + D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,CH0_FF_RX_F_CLK=>n52,CH1_FF_RX_F_CLK=>n5, + CH0_FF_RX_H_CLK=>n53,CH1_FF_RX_H_CLK=>n6,CH0_FF_TX_F_CLK=>n54,CH1_FF_TX_F_CLK=>n7, + CH0_FF_TX_H_CLK=>n55,CH1_FF_TX_H_CLK=>n8,CH0_FF_RX_PCLK=>n56,CH1_FF_RX_PCLK=>rx_pclk_c, + CH0_FF_TX_PCLK=>n57,CH1_FF_TX_PCLK=>tx_pclk_c,CH0_FF_RX_D_0=>n58,CH1_FF_RX_D_0=>rxdata(0), + CH0_FF_RX_D_1=>n59,CH1_FF_RX_D_1=>rxdata(1),CH0_FF_RX_D_2=>n60,CH1_FF_RX_D_2=>rxdata(2), + CH0_FF_RX_D_3=>n61,CH1_FF_RX_D_3=>rxdata(3),CH0_FF_RX_D_4=>n62,CH1_FF_RX_D_4=>rxdata(4), + CH0_FF_RX_D_5=>n63,CH1_FF_RX_D_5=>rxdata(5),CH0_FF_RX_D_6=>n64,CH1_FF_RX_D_6=>rxdata(6), + CH0_FF_RX_D_7=>n65,CH1_FF_RX_D_7=>rxdata(7),CH0_FF_RX_D_8=>n66,CH1_FF_RX_D_8=>rx_k(0), + CH0_FF_RX_D_9=>n67,CH1_FF_RX_D_9=>rx_disp_err(0),CH0_FF_RX_D_10=>n68, + CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n69,CH1_FF_RX_D_11=>n9,CH0_FF_RX_D_12=>n70, + CH1_FF_RX_D_12=>n71,CH0_FF_RX_D_13=>n72,CH1_FF_RX_D_13=>n73,CH0_FF_RX_D_14=>n74, + CH1_FF_RX_D_14=>n75,CH0_FF_RX_D_15=>n76,CH1_FF_RX_D_15=>n77,CH0_FF_RX_D_16=>n78, + CH1_FF_RX_D_16=>n79,CH0_FF_RX_D_17=>n80,CH1_FF_RX_D_17=>n81,CH0_FF_RX_D_18=>n82, + CH1_FF_RX_D_18=>n83,CH0_FF_RX_D_19=>n84,CH1_FF_RX_D_19=>n85,CH0_FF_RX_D_20=>n86, + CH1_FF_RX_D_20=>n87,CH0_FF_RX_D_21=>n88,CH1_FF_RX_D_21=>n89,CH0_FF_RX_D_22=>n90, + CH1_FF_RX_D_22=>n91,CH0_FF_RX_D_23=>n92,CH1_FF_RX_D_23=>n10,CH0_FFS_PCIE_DONE=>n93, + CH1_FFS_PCIE_DONE=>n11,CH0_FFS_PCIE_CON=>n94,CH1_FFS_PCIE_CON=>n12,CH0_FFS_RLOS=>n95, + CH1_FFS_RLOS=>rx_los_low_s_c,CH0_FFS_LS_SYNC_STATUS=>n96,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s, + CH0_FFS_CC_UNDERRUN=>n97,CH1_FFS_CC_UNDERRUN=>n13,CH0_FFS_CC_OVERRUN=>n98, + CH1_FFS_CC_OVERRUN=>n14,CH0_FFS_RXFBFIFO_ERROR=>n99,CH1_FFS_RXFBFIFO_ERROR=>n15, + CH0_FFS_TXFBFIFO_ERROR=>n100,CH1_FFS_TXFBFIFO_ERROR=>n16,CH0_FFS_RLOL=>n101, + CH1_FFS_RLOL=>rx_cdr_lol_s_c,CH0_FFS_SKP_ADDED=>n102,CH1_FFS_SKP_ADDED=>n17, + CH0_FFS_SKP_DELETED=>n103,CH1_FFS_SKP_DELETED=>n18,CH0_LDR_RX2CORE=>n104, + CH1_LDR_RX2CORE=>n115,D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1), + D_SCIRDATA2=>sci_rddata(2),D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4), + D_SCIRDATA5=>sci_rddata(5),D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7), + D_SCIINT=>sci_int,D_SCAN_OUT_0=>n19,D_SCAN_OUT_1=>n20,D_SCAN_OUT_2=>n21, + D_SCAN_OUT_3=>n22,D_SCAN_OUT_4=>n23,D_SCAN_OUT_5=>n24,D_SCAN_OUT_6=>n25, + D_SCAN_OUT_7=>n26,D_COUT0=>n27,D_COUT1=>n28,D_COUT2=>n29,D_COUT3=>n30, + D_COUT4=>n31,D_COUT5=>n32,D_COUT6=>n33,D_COUT7=>n34,D_COUT8=>n35,D_COUT9=>n36, + D_COUT10=>n37,D_COUT11=>n38,D_COUT12=>n39,D_COUT13=>n40,D_COUT14=>n41, + D_COUT15=>n42,D_COUT16=>n43,D_COUT17=>n44,D_COUT18=>n45,D_COUT19=>n46, + D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n49); + n48 <= '1' ; + n47 <= '0' ; + n1 <= 'Z' ; + n2 <= 'Z' ; + n3 <= 'Z' ; + n4 <= 'Z' ; + n5 <= 'Z' ; + n6 <= 'Z' ; + n7 <= 'Z' ; + n8 <= 'Z' ; + n9 <= 'Z' ; + n10 <= 'Z' ; + n11 <= 'Z' ; + n12 <= 'Z' ; + n13 <= 'Z' ; + n14 <= 'Z' ; + n15 <= 'Z' ; + n16 <= 'Z' ; + n17 <= 'Z' ; + n18 <= 'Z' ; + n19 <= 'Z' ; + n20 <= 'Z' ; + n21 <= 'Z' ; + n22 <= 'Z' ; + n23 <= 'Z' ; + n24 <= 'Z' ; + n25 <= 'Z' ; + n26 <= 'Z' ; + n27 <= 'Z' ; + n28 <= 'Z' ; + n29 <= 'Z' ; + n30 <= 'Z' ; + n31 <= 'Z' ; + n32 <= 'Z' ; + n33 <= 'Z' ; + n34 <= 'Z' ; + n35 <= 'Z' ; + n36 <= 'Z' ; + n37 <= 'Z' ; + n38 <= 'Z' ; + n39 <= 'Z' ; + n40 <= 'Z' ; + n41 <= 'Z' ; + n42 <= 'Z' ; + n43 <= 'Z' ; + n44 <= 'Z' ; + n45 <= 'Z' ; + n46 <= 'Z' ; + n49 <= 'Z' ; + n106 <= '0' ; + n105 <= '1' ; + n50 <= 'Z' ; + n51 <= 'Z' ; + n52 <= 'Z' ; + n53 <= 'Z' ; + n54 <= 'Z' ; + n55 <= 'Z' ; + n56 <= 'Z' ; + n57 <= 'Z' ; + n58 <= 'Z' ; + n59 <= 'Z' ; + n60 <= 'Z' ; + n61 <= 'Z' ; + n62 <= 'Z' ; + n63 <= 'Z' ; + n64 <= 'Z' ; + n65 <= 'Z' ; + n66 <= 'Z' ; + n67 <= 'Z' ; + n68 <= 'Z' ; + n69 <= 'Z' ; + n70 <= 'Z' ; + n71 <= 'Z' ; + n72 <= 'Z' ; + n73 <= 'Z' ; + n74 <= 'Z' ; + n75 <= 'Z' ; + n76 <= 'Z' ; + n77 <= 'Z' ; + n78 <= 'Z' ; + n79 <= 'Z' ; + n80 <= 'Z' ; + n81 <= 'Z' ; + n82 <= 'Z' ; + n83 <= 'Z' ; + n84 <= 'Z' ; + n85 <= 'Z' ; + n86 <= 'Z' ; + n87 <= 'Z' ; + n88 <= 'Z' ; + n89 <= 'Z' ; + n90 <= 'Z' ; + n91 <= 'Z' ; + n92 <= 'Z' ; + n93 <= 'Z' ; + n94 <= 'Z' ; + n95 <= 'Z' ; + n96 <= 'Z' ; + n97 <= 'Z' ; + n98 <= 'Z' ; + n99 <= 'Z' ; + n100 <= 'Z' ; + n101 <= 'Z' ; + n102 <= 'Z' ; + n103 <= 'Z' ; + n104 <= 'Z' ; + n115 <= 'Z' ; + rsl_inst: component serdes_sync_0rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c, + rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki, + rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n125, + rui_tx_pcs_rst_c(2)=>n125,rui_tx_pcs_rst_c(1)=>n125,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c, + rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n125, + rui_rx_serdes_rst_c(2)=>n125,rui_rx_serdes_rst_c(1)=>n125,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c, + rui_rx_pcs_rst_c(3)=>n125,rui_rx_pcs_rst_c(2)=>n125,rui_rx_pcs_rst_c(1)=>n125, + rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n125,rdi_rx_los_low_s(2)=>n125, + rdi_rx_los_low_s(1)=>n125,rdi_rx_los_low_s(0)=>rx_los_low_s_c, + rdi_rx_cdr_lol_s(3)=>n125,rdi_rx_cdr_lol_s(2)=>n125,rdi_rx_cdr_lol_s(1)=>n125, + rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c, + rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c, + rdo_tx_pcs_rst_c(3)=>n116,rdo_tx_pcs_rst_c(2)=>n117,rdo_tx_pcs_rst_c(1)=>n118, + rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n119, + rdo_rx_serdes_rst_c(2)=>n120,rdo_rx_serdes_rst_c(1)=>n121,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c, + rdo_rx_pcs_rst_c(3)=>n122,rdo_rx_pcs_rst_c(2)=>n123,rdo_rx_pcs_rst_c(1)=>\_Z\, + rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c); + n114 <= '1' ; + n113 <= '0' ; + n125 <= '0' ; + n124 <= '1' ; + n116 <= 'Z' ; + n117 <= 'Z' ; + n118 <= 'Z' ; + n119 <= 'Z' ; + n120 <= 'Z' ; + n121 <= 'Z' ; + n122 <= 'Z' ; + n123 <= 'Z' ; + \_Z\ <= 'Z' ; + sll_inst: component serdes_sync_0sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki, + sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd, + sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd, + sli_pcie_mode=>gnd,slo_plol=>pll_lol_c); + n127 <= '1' ; + n126 <= '0' ; + gnd <= '0' ; + pwr <= '1' ; + +end architecture v1; + diff --git a/media_interfaces/ecp5/chan1_0/serdes_sync_1.ipx b/media_interfaces/ecp5/chan1_0/serdes_sync_1.ipx new file mode 100644 index 0000000..5f446bc --- /dev/null +++ b/media_interfaces/ecp5/chan1_0/serdes_sync_1.ipx @@ -0,0 +1,6 @@ + + + + + + diff --git a/media_interfaces/ecp5/chan1_0/serdes_sync_1.lpc b/media_interfaces/ecp5/chan1_0/serdes_sync_1.lpc new file mode 100644 index 0000000..bbee5da --- /dev/null +++ b/media_interfaces/ecp5/chan1_0/serdes_sync_1.lpc @@ -0,0 +1,98 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG381C +SpeedGrade=8 +Package=CABGA381 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PCS +CoreRevision=8.2 +ModuleName=serdes_sync_1 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/09/2020 +Time=18:01:17 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +PROTOCOL=G8B10B +NUM_CHS=1 +CH_MODE=Rx and Tx +TX_MAX_RATE=2 +TXPLLMULT=10X +REFCLK_RATE=200.0000 +TXPLLLOLTHRESHOLD=1 +CDR_MAX_RATE=2 +CDR_MULT=10X +RX_RATE_DIV=Full Rate +CDR_REF_RATE=200.0000 +RX_LINE_RATE=2.0000 +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=200.0000 +RXLDR=Off +CDRLOLRANGE=3 +TX_LINE_RATE=2.0000 +TX_RATE_DIV=Full Rate +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=200.0000 +TXLDR=Off +IO_TYPE=G8B10B +TXAMPLITUDE=800 +TXDIFFTERM=50 ohms +TXDEPRE=Disabled +TXDEPOST=Disabled +RXDIFFTERM=50 ohms +RXCOUPLING=AC +LEQ=Disabled +RXLOSTHRESHOLD=0 +TXINVPOL=Non-invert +TX8B10B=Enabled +TXFIFO_ENABLE=Enabled +RXINVPOL=Non-invert +RX8B10B=Enabled +RXFIFO_ENABLE=Enabled +RXLSM=Enabled +RXWA=Barrel Shift +RXSC=K28P157 +RXCOMMAA=0010000011 +RXCOMMAB=0001111100 +RXCOMMAM=0011111111 +RXCTC=Disabled +RXCTCMATCHPATTERN=M4-S4 +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=0 00H +RXCTCBYTEN3=0 00H +;RXMCAENABLE=Disabled +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +LOOPBACK=Disabled +RCSRC=Disabled +LOSPORT=Enabled +CDRLOLACTION=Full Recalibration +RSTSEQSEL=Enabled +PPORT_TX_RDY=Enabled +PWAIT_TX_RDY=3000 +PPORT_RX_RDY=Enabled +PWAIT_RX_RDY=3000 +SCIPORT=Enabled +SOFTLOL=Enabled + +[FilesGenerated] +serdes_sync_1.pp=pp +serdes_sync_1.tft=tft +serdes_sync_1.txt=pcs_module +serdes_sync_1.sym=sym diff --git a/media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd b/media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd index d769bb8..0651ba5 100644 --- a/media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd +++ b/media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd @@ -159,7 +159,7 @@ begin pll_lol <= pll_lol_c; DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", - D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0", CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0", diff --git a/media_interfaces/ecp5/dual_serdes/serdes1/serdes1.vhd b/media_interfaces/ecp5/dual_serdes/serdes1/serdes1.vhd index 39c1ff9..f3193c3 100644 --- a/media_interfaces/ecp5/dual_serdes/serdes1/serdes1.vhd +++ b/media_interfaces/ecp5/dual_serdes/serdes1/serdes1.vhd @@ -127,7 +127,7 @@ begin rx_cdr_lol_s <= rx_cdr_lol_s_c; DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", - D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b1",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", diff --git a/media_interfaces/ecp5/dual_serdes_1/dual_serdes_1.vhd b/media_interfaces/ecp5/dual_serdes_1/dual_serdes_1.vhd new file mode 100644 index 0000000..9a4b74c --- /dev/null +++ b/media_interfaces/ecp5/dual_serdes_1/dual_serdes_1.vhd @@ -0,0 +1,285 @@ + + + +-- +-- Verific VHDL Description of module dual_serdes +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity dual_serdes_1 is + port (serdes0_rx_cv_err: out std_logic_vector(0 downto 0); + serdes0_rx_disp_err: out std_logic_vector(0 downto 0); + serdes0_rx_k: out std_logic_vector(0 downto 0); + serdes0_rxdata: out std_logic_vector(7 downto 0); + serdes0_tx_disp_sel: in std_logic_vector(0 downto 0); + serdes0_tx_force_disp: in std_logic_vector(0 downto 0); + serdes0_tx_k: in std_logic_vector(0 downto 0); + serdes0_txdata: in std_logic_vector(7 downto 0); + serdes1_rx_cv_err: out std_logic_vector(0 downto 0); + serdes1_rx_disp_err: out std_logic_vector(0 downto 0); + serdes1_rx_k: out std_logic_vector(0 downto 0); + serdes1_rxdata: out std_logic_vector(7 downto 0); + serdes1_sci_addr: in std_logic_vector(5 downto 0); + serdes1_sci_rddata: out std_logic_vector(7 downto 0); + serdes1_sci_wrdata: in std_logic_vector(7 downto 0); + serdes1_tx_disp_sel: in std_logic_vector(0 downto 0); + serdes1_tx_force_disp: in std_logic_vector(0 downto 0); + serdes1_tx_k: in std_logic_vector(0 downto 0); + serdes1_txdata: in std_logic_vector(7 downto 0); + serdes0_hdinn: in std_logic; + serdes0_hdinp: in std_logic; + serdes0_hdoutn: out std_logic; + serdes0_hdoutp: out std_logic; + serdes0_lsm_status_s: out std_logic; + serdes0_pll_lol: out std_logic; + serdes0_rsl_disable: in std_logic; + serdes0_rsl_rst: in std_logic; + serdes0_rsl_rx_rdy: out std_logic; + serdes0_rsl_tx_rdy: out std_logic; + serdes0_rst_dual_c: in std_logic; + serdes0_rx_cdr_lol_s: out std_logic; + serdes0_rx_los_low_s: out std_logic; + serdes0_rx_pclk: out std_logic; + serdes0_rx_pcs_rst_c: in std_logic; + serdes0_rx_pwrup_c: in std_logic; + serdes0_rx_serdes_rst_c: in std_logic; + serdes0_rxrefclk: in std_logic; + serdes0_sci_en: in std_logic; + serdes0_sci_sel: in std_logic; + serdes0_serdes_rst_dual_c: in std_logic; + serdes0_signal_detect_c: in std_logic; + serdes0_tx_idle_c: in std_logic; + serdes0_tx_pclk: out std_logic; + serdes0_tx_pcs_rst_c: in std_logic; + serdes0_tx_pwrup_c: in std_logic; + serdes0_tx_serdes_rst_c: in std_logic; + serdes1_cyawstn: in std_logic; + serdes1_hdinn: in std_logic; + serdes1_hdinp: in std_logic; + serdes1_hdoutn: out std_logic; + serdes1_hdoutp: out std_logic; + serdes1_lsm_status_s: out std_logic; + serdes1_pll_refclki: in std_logic; + serdes1_rsl_disable: in std_logic; + serdes1_rsl_rst: in std_logic; + serdes1_rsl_rx_rdy: out std_logic; + serdes1_rsl_tx_rdy: out std_logic; + serdes1_rst_dual_c: in std_logic; + serdes1_rx_cdr_lol_s: out std_logic; + serdes1_rx_los_low_s: out std_logic; + serdes1_rx_pclk: out std_logic; + serdes1_rx_pcs_rst_c: in std_logic; + serdes1_rx_pwrup_c: in std_logic; + serdes1_rx_serdes_rst_c: in std_logic; + serdes1_rxrefclk: in std_logic; + serdes1_sci_en: in std_logic; + serdes1_sci_en_dual: in std_logic; + serdes1_sci_rd: in std_logic; + serdes1_sci_sel: in std_logic; + serdes1_sci_sel_dual: in std_logic; + serdes1_sci_wrn: in std_logic; + serdes1_serdes_pdb: in std_logic; + serdes1_serdes_rst_dual_c: in std_logic; + serdes1_signal_detect_c: in std_logic; + serdes1_tx_idle_c: in std_logic; + serdes1_tx_pclk: out std_logic; + serdes1_tx_pcs_rst_c: in std_logic; + serdes1_tx_pwrup_c: in std_logic; + serdes1_tx_serdes_rst_c: in std_logic + ); + +end entity dual_serdes_1; +architecture dual_serdes_syn of dual_serdes_1 is + component serdes1_0 is + port (rx_cv_err: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_wrdata: in std_logic_vector(7 downto 0); + tx_disp_sel: in std_logic_vector(0 downto 0); + tx_force_disp: in std_logic_vector(0 downto 0); + tx_k: in std_logic_vector(0 downto 0); + txdata: in std_logic_vector(7 downto 0); + cyawstn: in std_logic; + hdinn: in std_logic; + hdinp: in std_logic; + hdoutn: out std_logic; + hdoutp: out std_logic; + lsm_status_s: out std_logic; + pll_lol: out std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + rsl_rx_rdy: out std_logic; + rsl_tx_rdy: out std_logic; + rst_dual_c: in std_logic; + rx_cdr_lol_s: out std_logic; + rx_los_low_s: out std_logic; + rx_pclk: out std_logic; + rx_pcs_rst_c: in std_logic; + rx_pwrup_c: in std_logic; + rx_serdes_rst_c: in std_logic; + rxrefclk: in std_logic; + sci_en: in std_logic; + sci_en_dual: in std_logic; + sci_int: out std_logic; + sci_rd: in std_logic; + sci_sel: in std_logic; + sci_sel_dual: in std_logic; + sci_wrn: in std_logic; + serdes_pdb: in std_logic; + serdes_rst_dual_c: in std_logic; + signal_detect_c: in std_logic; + sli_rst: in std_logic; + tx_idle_c: in std_logic; + tx_pclk: out std_logic; + tx_pcs_rst_c: in std_logic; + tx_pwrup_c: in std_logic; + tx_serdes_rst_c: in std_logic + ); + + end component serdes1_0; -- not_need_bbox=true + + + component serdes1_1 is + port (rx_cv_err: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_wrdata: in std_logic_vector(7 downto 0); + tx_disp_sel: in std_logic_vector(0 downto 0); + tx_force_disp: in std_logic_vector(0 downto 0); + tx_k: in std_logic_vector(0 downto 0); + txdata: in std_logic_vector(7 downto 0); + cyawstn: in std_logic; + hdinn: in std_logic; + hdinp: in std_logic; + hdoutn: out std_logic; + hdoutp: out std_logic; + lsm_status_s: out std_logic; + pll_lol: in std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + rsl_rx_rdy: out std_logic; + rsl_tx_rdy: out std_logic; + rst_dual_c: in std_logic; + rx_cdr_lol_s: out std_logic; + rx_los_low_s: out std_logic; + rx_pclk: out std_logic; + rx_pcs_rst_c: in std_logic; + rx_pwrup_c: in std_logic; + rx_serdes_rst_c: in std_logic; + rxrefclk: in std_logic; + sci_en: in std_logic; + sci_en_dual: in std_logic; + sci_int: out std_logic; + sci_rd: in std_logic; + sci_sel: in std_logic; + sci_sel_dual: in std_logic; + sci_wrn: in std_logic; + serdes_pdb: in std_logic; + serdes_rst_dual_c: in std_logic; + signal_detect_c: in std_logic; + tx_idle_c: in std_logic; + tx_pclk: out std_logic; + tx_pcs_rst_c: in std_logic; + tx_pwrup_c: in std_logic; + tx_serdes_rst_c: in std_logic + ); + + end component serdes1_1; -- not_need_bbox=true + + + signal i_serdes0_sci_rddata : std_logic_vector(7 downto 0); + signal o_serdes0_sci_rddata : std_logic_vector(7 downto 0); + signal i_serdes1_sci_rddata : std_logic_vector(7 downto 0); + signal i_serdes0_pll_lol,i_serdes1_pll_lol,o_serdes1_pll_lol,i_serdes0_sci_int, + o_serdes0_sci_int,i_serdes1_sci_int,o_serdes1_sci_int,sli_rst_wire0, + gnd : std_logic; +begin + serdes1_sci_rddata <= i_serdes1_sci_rddata; + serdes0_pll_lol <= i_serdes0_pll_lol; + sli_rst_wire0 <= serdes0_serdes_rst_dual_c OR serdes0_tx_serdes_rst_c OR (NOT serdes1_serdes_pdb) OR (NOT serdes0_tx_pwrup_c) OR (NOT serdes1_tx_pwrup_c); + serdes0_inst: component serdes1_0 port map (rx_cv_err(0)=>serdes0_rx_cv_err(0), + rx_disp_err(0)=>serdes0_rx_disp_err(0),rx_k(0)=>serdes0_rx_k(0), + rxdata(7)=>serdes0_rxdata(7),rxdata(6)=>serdes0_rxdata(6),rxdata(5)=>serdes0_rxdata(5), + rxdata(4)=>serdes0_rxdata(4),rxdata(3)=>serdes0_rxdata(3),rxdata(2)=>serdes0_rxdata(2), + rxdata(1)=>serdes0_rxdata(1),rxdata(0)=>serdes0_rxdata(0),sci_addr(5)=>serdes1_sci_addr(5), + sci_addr(4)=>serdes1_sci_addr(4),sci_addr(3)=>serdes1_sci_addr(3), + sci_addr(2)=>serdes1_sci_addr(2),sci_addr(1)=>serdes1_sci_addr(1), + sci_addr(0)=>serdes1_sci_addr(0),sci_rddata(7)=>i_serdes0_sci_rddata(7), + sci_rddata(6)=>i_serdes0_sci_rddata(6),sci_rddata(5)=>i_serdes0_sci_rddata(5), + sci_rddata(4)=>i_serdes0_sci_rddata(4),sci_rddata(3)=>i_serdes0_sci_rddata(3), + sci_rddata(2)=>i_serdes0_sci_rddata(2),sci_rddata(1)=>i_serdes0_sci_rddata(1), + sci_rddata(0)=>i_serdes0_sci_rddata(0),sci_wrdata(7)=>serdes1_sci_wrdata(7), + sci_wrdata(6)=>serdes1_sci_wrdata(6),sci_wrdata(5)=>serdes1_sci_wrdata(5), + sci_wrdata(4)=>serdes1_sci_wrdata(4),sci_wrdata(3)=>serdes1_sci_wrdata(3), + sci_wrdata(2)=>serdes1_sci_wrdata(2),sci_wrdata(1)=>serdes1_sci_wrdata(1), + sci_wrdata(0)=>serdes1_sci_wrdata(0),tx_disp_sel(0)=>serdes0_tx_disp_sel(0), + tx_force_disp(0)=>serdes0_tx_force_disp(0),tx_k(0)=>serdes0_tx_k(0), + txdata(7)=>serdes0_txdata(7),txdata(6)=>serdes0_txdata(6),txdata(5)=>serdes0_txdata(5), + txdata(4)=>serdes0_txdata(4),txdata(3)=>serdes0_txdata(3),txdata(2)=>serdes0_txdata(2), + txdata(1)=>serdes0_txdata(1),txdata(0)=>serdes0_txdata(0),cyawstn=>serdes1_cyawstn, + hdinn=>serdes0_hdinn,hdinp=>serdes0_hdinp,hdoutn=>serdes0_hdoutn, + hdoutp=>serdes0_hdoutp,lsm_status_s=>serdes0_lsm_status_s,pll_lol=>i_serdes0_pll_lol, + pll_refclki=>serdes1_pll_refclki,rsl_disable=>serdes0_rsl_disable, + rsl_rst=>serdes0_rsl_rst,rsl_rx_rdy=>serdes0_rsl_rx_rdy,rsl_tx_rdy=>serdes0_rsl_tx_rdy, + rst_dual_c=>serdes0_rst_dual_c,rx_cdr_lol_s=>serdes0_rx_cdr_lol_s, + rx_los_low_s=>serdes0_rx_los_low_s,rx_pclk=>serdes0_rx_pclk,rx_pcs_rst_c=>serdes0_rx_pcs_rst_c, + rx_pwrup_c=>serdes0_rx_pwrup_c,rx_serdes_rst_c=>serdes0_rx_serdes_rst_c, + rxrefclk=>serdes0_rxrefclk,sci_en=>serdes0_sci_en,sci_en_dual=>serdes1_sci_en_dual, + sci_int=>i_serdes0_sci_int,sci_rd=>serdes1_sci_rd,sci_sel=>serdes0_sci_sel, + sci_sel_dual=>serdes1_sci_sel_dual,sci_wrn=>serdes1_sci_wrn,serdes_pdb=>serdes1_serdes_pdb, + serdes_rst_dual_c=>serdes0_serdes_rst_dual_c,signal_detect_c=>serdes0_signal_detect_c, + sli_rst=>sli_rst_wire0,tx_idle_c=>serdes0_tx_idle_c,tx_pclk=>serdes0_tx_pclk, + tx_pcs_rst_c=>serdes0_tx_pcs_rst_c,tx_pwrup_c=>serdes0_tx_pwrup_c, + tx_serdes_rst_c=>serdes0_tx_serdes_rst_c); + serdes1_inst: component serdes1_1 port map (rx_cv_err(0)=>serdes1_rx_cv_err(0), + rx_disp_err(0)=>serdes1_rx_disp_err(0),rx_k(0)=>serdes1_rx_k(0), + rxdata(7)=>serdes1_rxdata(7),rxdata(6)=>serdes1_rxdata(6),rxdata(5)=>serdes1_rxdata(5), + rxdata(4)=>serdes1_rxdata(4),rxdata(3)=>serdes1_rxdata(3),rxdata(2)=>serdes1_rxdata(2), + rxdata(1)=>serdes1_rxdata(1),rxdata(0)=>serdes1_rxdata(0),sci_addr(5)=>serdes1_sci_addr(5), + sci_addr(4)=>serdes1_sci_addr(4),sci_addr(3)=>serdes1_sci_addr(3), + sci_addr(2)=>serdes1_sci_addr(2),sci_addr(1)=>serdes1_sci_addr(1), + sci_addr(0)=>serdes1_sci_addr(0),sci_rddata(7)=>i_serdes1_sci_rddata(7), + sci_rddata(6)=>i_serdes1_sci_rddata(6),sci_rddata(5)=>i_serdes1_sci_rddata(5), + sci_rddata(4)=>i_serdes1_sci_rddata(4),sci_rddata(3)=>i_serdes1_sci_rddata(3), + sci_rddata(2)=>i_serdes1_sci_rddata(2),sci_rddata(1)=>i_serdes1_sci_rddata(1), + sci_rddata(0)=>i_serdes1_sci_rddata(0),sci_wrdata(7)=>serdes1_sci_wrdata(7), + sci_wrdata(6)=>serdes1_sci_wrdata(6),sci_wrdata(5)=>serdes1_sci_wrdata(5), + sci_wrdata(4)=>serdes1_sci_wrdata(4),sci_wrdata(3)=>serdes1_sci_wrdata(3), + sci_wrdata(2)=>serdes1_sci_wrdata(2),sci_wrdata(1)=>serdes1_sci_wrdata(1), + sci_wrdata(0)=>serdes1_sci_wrdata(0),tx_disp_sel(0)=>serdes1_tx_disp_sel(0), + tx_force_disp(0)=>serdes1_tx_force_disp(0),tx_k(0)=>serdes1_tx_k(0), + txdata(7)=>serdes1_txdata(7),txdata(6)=>serdes1_txdata(6),txdata(5)=>serdes1_txdata(5), + txdata(4)=>serdes1_txdata(4),txdata(3)=>serdes1_txdata(3),txdata(2)=>serdes1_txdata(2), + txdata(1)=>serdes1_txdata(1),txdata(0)=>serdes1_txdata(0),cyawstn=>serdes1_cyawstn, + hdinn=>serdes1_hdinn,hdinp=>serdes1_hdinp,hdoutn=>serdes1_hdoutn, + hdoutp=>serdes1_hdoutp,lsm_status_s=>serdes1_lsm_status_s,pll_lol=>i_serdes1_pll_lol, + pll_refclki=>serdes1_pll_refclki,rsl_disable=>serdes1_rsl_disable, + rsl_rst=>serdes1_rsl_rst,rsl_rx_rdy=>serdes1_rsl_rx_rdy,rsl_tx_rdy=>serdes1_rsl_tx_rdy, + rst_dual_c=>serdes1_rst_dual_c,rx_cdr_lol_s=>serdes1_rx_cdr_lol_s, + rx_los_low_s=>serdes1_rx_los_low_s,rx_pclk=>serdes1_rx_pclk,rx_pcs_rst_c=>serdes1_rx_pcs_rst_c, + rx_pwrup_c=>serdes1_rx_pwrup_c,rx_serdes_rst_c=>serdes1_rx_serdes_rst_c, + rxrefclk=>serdes1_rxrefclk,sci_en=>serdes1_sci_en,sci_en_dual=>serdes1_sci_en_dual, + sci_int=>i_serdes1_sci_int,sci_rd=>serdes1_sci_rd,sci_sel=>serdes1_sci_sel, + sci_sel_dual=>serdes1_sci_sel_dual,sci_wrn=>serdes1_sci_wrn,serdes_pdb=>serdes1_serdes_pdb, + serdes_rst_dual_c=>serdes1_serdes_rst_dual_c,signal_detect_c=>serdes1_signal_detect_c, + tx_idle_c=>serdes1_tx_idle_c,tx_pclk=>serdes1_tx_pclk,tx_pcs_rst_c=>serdes1_tx_pcs_rst_c, + tx_pwrup_c=>serdes1_tx_pwrup_c,tx_serdes_rst_c=>serdes1_tx_serdes_rst_c); + gnd <= '0' ; + +end architecture dual_serdes_syn; -- sbp_module=true +--synthesis translate_off +configuration dual_serdes_config of dual_serdes_1 is +for dual_serdes_sim +end for; +end dual_serdes_config; +--synthesis translate_on diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.lpc b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.lpc new file mode 100644 index 0000000..490c1c6 --- /dev/null +++ b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.lpc @@ -0,0 +1,97 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA381 +PartName=LFE5UM-45F-8BG381C +PartType=LFE5UM-45F +SpeedGrade=8 +Status=P +[IP] +CoreName=PCS +CoreRevision=8.2 +CoreStatus=Demo +CoreType=LPM +Date=11/23/2020 +ModuleName=serdes1_0 +ParameterFileVersion=1.0 +SourceFormat=vhdl +Time=19:09:52 +VendorName=Lattice Semiconductor Corporation +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=3 +CDR_MAX_RATE=2 +CDR_MULT=10X +CDR_REF_RATE=200.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=G8B10B +LEQ=Disabled +LOOPBACK=Disabled +LOSPORT=Enabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Enabled +PPORT_TX_RDY=Enabled +PROTOCOL=G8B10B +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=200.0000 +RSTSEQSEL=Enabled +RX8B10B=Enabled +RXCOMMAA=0010000011 +RXCOMMAB=0001111100 +RXCOMMAM=0011111111 +RXCOUPLING=AC +RXCTC=Disabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=0 00H +RXCTCBYTEN3=0 00H +RXCTCMATCHPATTERN=M4-S4 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Non-invert +RXLDR=Off +RXLOSTHRESHOLD=0 +RXLSM=Enabled +RXSC=K28P157 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=200.0000 +RX_LINE_RATE=2.0000 +RX_RATE_DIV=Full Rate +SCIPORT=Enabled +SOFTLOL=Enabled +TX8B10B=Enabled +TXAMPLITUDE=600 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Non-invert +TXLDR=Off +TXPLLLOLTHRESHOLD=1 +TXPLLMULT=10X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=200.0000 +TX_LINE_RATE=2.0000 +TX_MAX_RATE=2 +TX_RATE_DIV=Full Rate +VHDL=1 +Verilog=0 +[FilesGenerated] +serdes0.pp=pp +serdes0.sym=sym +serdes0.tft=tft +serdes0.txt=pcs_module +[SYSTEMPNR] +LN0=DCU1_CH0 diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.ngd b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.ngd new file mode 100644 index 0000000..18c3d4b Binary files /dev/null and b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.ngd differ diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.ngo b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.ngo new file mode 100644 index 0000000..b205295 Binary files /dev/null and b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.ngo differ diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.vhd b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.vhd new file mode 100644 index 0000000..d62e2ee --- /dev/null +++ b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.vhd @@ -0,0 +1,435 @@ + +-- +-- Verific VHDL Description of module DCUA +-- + +-- DCUA is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module serdes0rsl_core +-- + +-- serdes0rsl_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module serdes0sll_core +-- + +-- serdes0sll_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module serdes0 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +library ecp5um ; +use ecp5um.components.all ; + +entity serdes1_0 is + port (hdoutp: out std_logic; + hdoutn: out std_logic; + hdinp: in std_logic; + hdinn: in std_logic; + rxrefclk: in std_logic; + rx_pclk: out std_logic; + tx_pclk: out std_logic; + txdata: in std_logic_vector(7 downto 0); + tx_k: in std_logic_vector(0 downto 0); + tx_force_disp: in std_logic_vector(0 downto 0); + tx_disp_sel: in std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_cv_err: out std_logic_vector(0 downto 0); + tx_idle_c: in std_logic; + signal_detect_c: in std_logic; + rx_los_low_s: out std_logic; + lsm_status_s: out std_logic; + rx_cdr_lol_s: out std_logic; + sli_rst: in std_logic; + tx_pwrup_c: in std_logic; + rx_pwrup_c: in std_logic; + sci_wrdata: in std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_en_dual: in std_logic; + sci_sel_dual: in std_logic; + sci_en: in std_logic; + sci_sel: in std_logic; + sci_rd: in std_logic; + sci_wrn: in std_logic; + sci_int: out std_logic; + cyawstn: in std_logic; + serdes_pdb: in std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + serdes_rst_dual_c: in std_logic; + rst_dual_c: in std_logic; + tx_serdes_rst_c: in std_logic; + tx_pcs_rst_c: in std_logic; + pll_lol: out std_logic; + rsl_tx_rdy: out std_logic; + rx_serdes_rst_c: in std_logic; + rx_pcs_rst_c: in std_logic; + rsl_rx_rdy: out std_logic + ); + +end entity serdes1_0; + +architecture v1 of serdes1_0 is + component serdes1_0rsl_core is + generic (pnum_channels: integer := 1; + pprotocol: string := "G8B10B"; + pserdes_mode: string := "RX AND TX"; + pport_tx_rdy: string := "ENABLED"; + pwait_tx_rdy: integer := 3000; + pport_rx_rdy: string := "ENABLED"; + pwait_rx_rdy: integer := 3000); + port (rui_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132) + rui_serdes_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133) + rui_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134) + rui_rsl_disable: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135) + rui_tx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137) + rui_tx_serdes_rst_c: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138) + rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139) + rdi_pll_lol: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140) + rui_rx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142) + rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143) + rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144) + rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145) + rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146) + rdo_serdes_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149) + rdo_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150) + ruo_tx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152) + rdo_tx_serdes_rst_c: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153) + rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154) + ruo_rx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156) + rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157) + rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158) + ); + + end component serdes1_0rsl_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88) + component serdes1_0sll_core is + generic (PPROTOCOL: string := "G8B10B"; + PLOL_SETTING: integer := 1; + PDYN_RATE_CTRL: string := "DISABLED"; + PPCIE_MAX_RATE: string := "2.5"; + PDIFF_VAL_LOCK: integer := 20; + PDIFF_VAL_UNLOCK: integer := 132; + PPCLK_TC: integer := 65536; + PDIFF_DIV11_VAL_LOCK: integer := 0; + PDIFF_DIV11_VAL_UNLOCK: integer := 0; + PPCLK_DIV11_TC: integer := 0); + port (sli_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(125) + sli_refclk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(126) + sli_pclk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(127) + sli_div2_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(128) + sli_div11_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(129) + sli_gear_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(130) + sli_cpri_mode: in std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(131) + sli_pcie_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(132) + slo_plol: out std_logic -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(135) + ); + + end component serdes1_0sll_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(107) + signal n48,n47,n1,n2,n3,n4,rx_pclk_c,tx_pclk_c,n5,n6,n7,n8,n9, + n10,n11,n12,rx_los_low_s_c,n13,n14,n15,n16,rx_cdr_lol_s_c,n17, + n18,rsl_tx_pcs_rst_c,rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c, + rsl_serdes_rst_dual_c,rsl_tx_serdes_rst_c,n19,n20,n21,n22,n23, + n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37, + n38,n39,n40,n41,n42,n43,n44,n45,n46,n49,n106,n105,n50,n51, + n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65, + n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79, + n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93, + n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n115,n114, + n113,pll_lol_c,n125,n124,n116,n117,n118,n119,n120,n121,n122, + n123,\_Z\,n127,n126,gnd,pwr : std_logic; + attribute LOC : string; + attribute LOC of DCU0_inst : label is "DCU1"; + attribute CHAN : string; + attribute CHAN of DCU0_inst : label is "CH0"; +begin + rx_pclk <= rx_pclk_c; + tx_pclk <= tx_pclk_c; + rx_los_low_s <= rx_los_low_s_c; + rx_cdr_lol_s <= rx_cdr_lol_s_c; + pll_lol <= pll_lol_c; + DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", + D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", + D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", + D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0", + CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0", + CH0_GE_AN_ENABLE=>"0b0",CH0_PRBS_LOCK=>"0b0",CH0_PRBS_ENABLE=>"0b0", + CH0_ENABLE_CG_ALIGN=>"0b1",CH0_TX_GEAR_MODE=>"0b0",CH0_RX_GEAR_MODE=>"0b0", + CH0_PCS_DET_TIME_SEL=>"0b00",CH0_PCIE_EI_EN=>"0b0",CH0_TX_GEAR_BYPASS=>"0b0", + CH0_ENC_BYPASS=>"0b0",CH0_SB_BYPASS=>"0b0",CH0_RX_SB_BYPASS=>"0b0", + CH0_WA_BYPASS=>"0b0",CH0_DEC_BYPASS=>"0b0",CH0_CTC_BYPASS=>"0b1", + CH0_RX_GEAR_BYPASS=>"0b0",CH0_LSM_DISABLE=>"0b0",CH0_MATCH_2_ENABLE=>"0b0", + CH0_MATCH_4_ENABLE=>"0b1",CH0_MIN_IPG_CNT=>"0b11",CH0_CC_MATCH_1=>"0x1BC", + CH0_CC_MATCH_2=>"0x11C",CH0_CC_MATCH_3=>"0x11C",CH0_CC_MATCH_4=>"0x11C", + CH0_UDF_COMMA_MASK=>"0x0ff",CH0_UDF_COMMA_A=>"0x083",CH0_UDF_COMMA_B=>"0x07C", + CH0_RX_DCO_CK_DIV=>"0b000",CH0_RCV_DCC_EN=>"0b0",CH0_TPWDNB=>"0b1", + CH0_RATE_MODE_TX=>"0b0",CH0_RTERM_TX=>"0d19",CH0_TX_CM_SEL=>"0b00", + CH0_TDRV_PRE_EN=>"0b0",CH0_TDRV_SLICE0_SEL=>"0b01",CH0_TDRV_SLICE1_SEL=>"0b00", + CH0_TDRV_SLICE2_SEL=>"0b01",CH0_TDRV_SLICE3_SEL=>"0b01",CH0_TDRV_SLICE4_SEL=>"0b00", + CH0_TDRV_SLICE5_SEL=>"0b00",CH0_TDRV_SLICE0_CUR=>"0b011",CH0_TDRV_SLICE1_CUR=>"0b000", + CH0_TDRV_SLICE2_CUR=>"0b11",CH0_TDRV_SLICE3_CUR=>"0b10",CH0_TDRV_SLICE4_CUR=>"0b00", + CH0_TDRV_SLICE5_CUR=>"0b00",CH0_TDRV_DAT_SEL=>"0b00",CH0_TX_DIV11_SEL=>"0b0", + CH0_RPWDNB=>"0b1",CH0_RATE_MODE_RX=>"0b0",CH0_RX_DIV11_SEL=>"0b0", + CH0_SEL_SD_RX_CLK=>"0b1",CH0_FF_RX_H_CLK_EN=>"0b0",CH0_FF_RX_F_CLK_DIS=>"0b0", + CH0_FF_TX_H_CLK_EN=>"0b0",CH0_FF_TX_F_CLK_DIS=>"0b0",CH0_TDRV_POST_EN=>"0b0", + CH0_TX_POST_SIGN=>"0b0",CH0_TX_PRE_SIGN=>"0b0",CH0_REQ_LVL_SET=>"0b00", + CH0_REQ_EN=>"0b0",CH0_RTERM_RX=>"0d22",CH0_RXTERM_CM=>"0b11",CH0_PDEN_SEL=>"0b1", + CH0_RXIN_CM=>"0b11",CH0_LEQ_OFFSET_SEL=>"0b0",CH0_LEQ_OFFSET_TRIM=>"0b000", + CH0_RLOS_SEL=>"0b1",CH0_RX_LOS_LVL=>"0b000",CH0_RX_LOS_CEQ=>"0b11", + CH0_RX_LOS_HYST_EN=>"0b0",CH0_RX_LOS_EN=>"0b1",CH0_LDR_RX2CORE_SEL=>"0b0", + CH0_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2",CH0_CDR_MAX_RATE=>"2", + CH0_TXAMPLITUDE=>"0d600",CH0_TXDEPRE=>"DISABLED",CH0_TXDEPOST=>"DISABLED", + CH0_PROTOCOL=>"G8B10B",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b10",D_SETICONST_AUX=>"0b01", + D_SETIRPOLY_CH=>"0b10",D_SETICONST_CH=>"0b10",D_REQ_ISET=>"0b001", + D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH0_CDR_CNT4SEL=>"0b00", + CH0_CDR_CNT8SEL=>"0b00",CH0_DCOATDCFG=>"0b00",CH0_DCOATDDLY=>"0b00", + CH0_DCOBYPSATD=>"0b1",CH0_DCOCALDIV=>"0b000",CH0_DCOCTLGI=>"0b011", + CH0_DCODISBDAVOID=>"0b0",CH0_DCOFLTDAC=>"0b00",CH0_DCOFTNRG=>"0b001", + CH0_DCOIOSTUNE=>"0b010",CH0_DCOITUNE=>"0b00",CH0_DCOITUNE4LSB=>"0b010", + CH0_DCOIUPDNX2=>"0b1",CH0_DCONUOFLSB=>"0b100",CH0_DCOSCALEI=>"0b01", + CH0_DCOSTARTVAL=>"0b010",CH0_DCOSTEP=>"0b11",CH0_BAND_THRESHOLD=>"0d0", + CH0_AUTO_FACQ_EN=>"0b1",CH0_AUTO_CALIB_EN=>"0b1",CH0_CALIB_CK_MODE=>"0b0", + CH0_REG_BAND_OFFSET=>"0d0",CH0_REG_BAND_SEL=>"0d0",CH0_REG_IDAC_SEL=>"0d0", + CH0_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", + D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", + D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", + D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH0_RX_RATE_SEL=>"0d10", + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b01", + D_RG_EN=>"0b0",D_RG_SET=>"0b00") + port map (CH0_HDINP=>hdinp,CH1_HDINP=>n106,CH0_HDINN=>hdinn,CH1_HDINN=>n106, + D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47, + CH0_RX_REFCLK=>rxrefclk,CH1_RX_REFCLK=>n106,CH0_FF_RXI_CLK=>rx_pclk_c, + CH1_FF_RXI_CLK=>n105,CH0_FF_TXI_CLK=>tx_pclk_c,CH1_FF_TXI_CLK=>n105,CH0_FF_EBRD_CLK=>n48, + CH1_FF_EBRD_CLK=>n105,CH0_FF_TX_D_0=>txdata(0),CH1_FF_TX_D_0=>n106,CH0_FF_TX_D_1=>txdata(1), + CH1_FF_TX_D_1=>n106,CH0_FF_TX_D_2=>txdata(2),CH1_FF_TX_D_2=>n106,CH0_FF_TX_D_3=>txdata(3), + CH1_FF_TX_D_3=>n106,CH0_FF_TX_D_4=>txdata(4),CH1_FF_TX_D_4=>n106,CH0_FF_TX_D_5=>txdata(5), + CH1_FF_TX_D_5=>n106,CH0_FF_TX_D_6=>txdata(6),CH1_FF_TX_D_6=>n106,CH0_FF_TX_D_7=>txdata(7), + CH1_FF_TX_D_7=>n106,CH0_FF_TX_D_8=>tx_k(0),CH1_FF_TX_D_8=>n106,CH0_FF_TX_D_9=>tx_force_disp(0), + CH1_FF_TX_D_9=>n106,CH0_FF_TX_D_10=>tx_disp_sel(0),CH1_FF_TX_D_10=>n106, + CH0_FF_TX_D_11=>n47,CH1_FF_TX_D_11=>n106,CH0_FF_TX_D_12=>n106,CH1_FF_TX_D_12=>n106, + CH0_FF_TX_D_13=>n106,CH1_FF_TX_D_13=>n106,CH0_FF_TX_D_14=>n106,CH1_FF_TX_D_14=>n106, + CH0_FF_TX_D_15=>n106,CH1_FF_TX_D_15=>n106,CH0_FF_TX_D_16=>n106,CH1_FF_TX_D_16=>n106, + CH0_FF_TX_D_17=>n106,CH1_FF_TX_D_17=>n106,CH0_FF_TX_D_18=>n106,CH1_FF_TX_D_18=>n106, + CH0_FF_TX_D_19=>n106,CH1_FF_TX_D_19=>n106,CH0_FF_TX_D_20=>n106,CH1_FF_TX_D_20=>n106, + CH0_FF_TX_D_21=>n106,CH1_FF_TX_D_21=>n106,CH0_FF_TX_D_22=>n106,CH1_FF_TX_D_22=>n106, + CH0_FF_TX_D_23=>n47,CH1_FF_TX_D_23=>n106,CH0_FFC_EI_EN=>tx_idle_c,CH1_FFC_EI_EN=>n106, + CH0_FFC_PCIE_DET_EN=>n47,CH1_FFC_PCIE_DET_EN=>n106,CH0_FFC_PCIE_CT=>n47, + CH1_FFC_PCIE_CT=>n106,CH0_FFC_SB_INV_RX=>n106,CH1_FFC_SB_INV_RX=>n106, + CH0_FFC_ENABLE_CGALIGN=>n106,CH1_FFC_ENABLE_CGALIGN=>n106,CH0_FFC_SIGNAL_DETECT=>signal_detect_c, + CH1_FFC_SIGNAL_DETECT=>n106,CH0_FFC_FB_LOOPBACK=>n47,CH1_FFC_FB_LOOPBACK=>n106, + CH0_FFC_SB_PFIFO_LP=>n47,CH1_FFC_SB_PFIFO_LP=>n106,CH0_FFC_PFIFO_CLR=>n47, + CH1_FFC_PFIFO_CLR=>n106,CH0_FFC_RATE_MODE_RX=>n106,CH1_FFC_RATE_MODE_RX=>n106, + CH0_FFC_RATE_MODE_TX=>n106,CH1_FFC_RATE_MODE_TX=>n106,CH0_FFC_DIV11_MODE_RX=>n47, + CH1_FFC_DIV11_MODE_RX=>n106,CH0_FFC_DIV11_MODE_TX=>n47,CH1_FFC_DIV11_MODE_TX=>n106, + CH0_FFC_RX_GEAR_MODE=>n47,CH1_FFC_RX_GEAR_MODE=>n106,CH0_FFC_TX_GEAR_MODE=>n47, + CH1_FFC_TX_GEAR_MODE=>n106,CH0_FFC_LDR_CORE2TX_EN=>n106,CH1_FFC_LDR_CORE2TX_EN=>n106, + CH0_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH1_FFC_LANE_TX_RST=>n106,CH0_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c, + CH1_FFC_LANE_RX_RST=>n106,CH0_FFC_RRST=>rsl_rx_serdes_rst_c,CH1_FFC_RRST=>n106, + CH0_FFC_TXPWDNB=>tx_pwrup_c,CH1_FFC_TXPWDNB=>n106,CH0_FFC_RXPWDNB=>rx_pwrup_c, + CH1_FFC_RXPWDNB=>n106,CH0_LDR_CORE2TX=>n106,CH1_LDR_CORE2TX=>n106,D_SCIWDATA0=>sci_wrdata(0), + D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2),D_SCIWDATA3=>sci_wrdata(3), + D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5),D_SCIWDATA6=>sci_wrdata(6), + D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0),D_SCIADDR1=>sci_addr(1), + D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3),D_SCIADDR4=>sci_addr(4), + D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual,D_SCISELAUX=>sci_sel_dual, + CH0_SCIEN=>sci_en,CH1_SCIEN=>n106,CH0_SCISEL=>sci_sel,CH1_SCISEL=>n106, + D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn,D_FFC_SYNC_TOGGLE=>n106, + D_FFC_DUAL_RST=>rsl_rst_dual_c,D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c, + D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n47, + CH1_FFC_CDR_EN_BITSLIP=>n106,D_SCAN_ENABLE=>n47,D_SCAN_IN_0=>n47,D_SCAN_IN_1=>n47, + D_SCAN_IN_2=>n47,D_SCAN_IN_3=>n47,D_SCAN_IN_4=>n47,D_SCAN_IN_5=>n47, + D_SCAN_IN_6=>n47,D_SCAN_IN_7=>n47,D_SCAN_MODE=>n47,D_SCAN_RESET=>n47, + D_CIN0=>n47,D_CIN1=>n47,D_CIN2=>n47,D_CIN3=>n47,D_CIN4=>n47,D_CIN5=>n47, + D_CIN6=>n47,D_CIN7=>n47,D_CIN8=>n47,D_CIN9=>n47,D_CIN10=>n47,D_CIN11=>n47, + CH0_HDOUTP=>hdoutp,CH1_HDOUTP=>n50,CH0_HDOUTN=>hdoutn,CH1_HDOUTN=>n51, + D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4, + CH0_FF_RX_F_CLK=>n5,CH1_FF_RX_F_CLK=>n52,CH0_FF_RX_H_CLK=>n6,CH1_FF_RX_H_CLK=>n53, + CH0_FF_TX_F_CLK=>n7,CH1_FF_TX_F_CLK=>n54,CH0_FF_TX_H_CLK=>n8,CH1_FF_TX_H_CLK=>n55, + CH0_FF_RX_PCLK=>rx_pclk_c,CH1_FF_RX_PCLK=>n56,CH0_FF_TX_PCLK=>tx_pclk_c, + CH1_FF_TX_PCLK=>n57,CH0_FF_RX_D_0=>rxdata(0),CH1_FF_RX_D_0=>n58,CH0_FF_RX_D_1=>rxdata(1), + CH1_FF_RX_D_1=>n59,CH0_FF_RX_D_2=>rxdata(2),CH1_FF_RX_D_2=>n60,CH0_FF_RX_D_3=>rxdata(3), + CH1_FF_RX_D_3=>n61,CH0_FF_RX_D_4=>rxdata(4),CH1_FF_RX_D_4=>n62,CH0_FF_RX_D_5=>rxdata(5), + CH1_FF_RX_D_5=>n63,CH0_FF_RX_D_6=>rxdata(6),CH1_FF_RX_D_6=>n64,CH0_FF_RX_D_7=>rxdata(7), + CH1_FF_RX_D_7=>n65,CH0_FF_RX_D_8=>rx_k(0),CH1_FF_RX_D_8=>n66,CH0_FF_RX_D_9=>rx_disp_err(0), + CH1_FF_RX_D_9=>n67,CH0_FF_RX_D_10=>rx_cv_err(0),CH1_FF_RX_D_10=>n68,CH0_FF_RX_D_11=>n9, + CH1_FF_RX_D_11=>n69,CH0_FF_RX_D_12=>n70,CH1_FF_RX_D_12=>n71,CH0_FF_RX_D_13=>n72, + CH1_FF_RX_D_13=>n73,CH0_FF_RX_D_14=>n74,CH1_FF_RX_D_14=>n75,CH0_FF_RX_D_15=>n76, + CH1_FF_RX_D_15=>n77,CH0_FF_RX_D_16=>n78,CH1_FF_RX_D_16=>n79,CH0_FF_RX_D_17=>n80, + CH1_FF_RX_D_17=>n81,CH0_FF_RX_D_18=>n82,CH1_FF_RX_D_18=>n83,CH0_FF_RX_D_19=>n84, + CH1_FF_RX_D_19=>n85,CH0_FF_RX_D_20=>n86,CH1_FF_RX_D_20=>n87,CH0_FF_RX_D_21=>n88, + CH1_FF_RX_D_21=>n89,CH0_FF_RX_D_22=>n90,CH1_FF_RX_D_22=>n91,CH0_FF_RX_D_23=>n10, + CH1_FF_RX_D_23=>n92,CH0_FFS_PCIE_DONE=>n11,CH1_FFS_PCIE_DONE=>n93,CH0_FFS_PCIE_CON=>n12, + CH1_FFS_PCIE_CON=>n94,CH0_FFS_RLOS=>rx_los_low_s_c,CH1_FFS_RLOS=>n95, + CH0_FFS_LS_SYNC_STATUS=>lsm_status_s,CH1_FFS_LS_SYNC_STATUS=>n96,CH0_FFS_CC_UNDERRUN=>n13, + CH1_FFS_CC_UNDERRUN=>n97,CH0_FFS_CC_OVERRUN=>n14,CH1_FFS_CC_OVERRUN=>n98, + CH0_FFS_RXFBFIFO_ERROR=>n15,CH1_FFS_RXFBFIFO_ERROR=>n99,CH0_FFS_TXFBFIFO_ERROR=>n16, + CH1_FFS_TXFBFIFO_ERROR=>n100,CH0_FFS_RLOL=>rx_cdr_lol_s_c,CH1_FFS_RLOL=>n101, + CH0_FFS_SKP_ADDED=>n17,CH1_FFS_SKP_ADDED=>n102,CH0_FFS_SKP_DELETED=>n18, + CH1_FFS_SKP_DELETED=>n103,CH0_LDR_RX2CORE=>n104,CH1_LDR_RX2CORE=>n115, + D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2), + D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5), + D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int, + D_SCAN_OUT_0=>n19,D_SCAN_OUT_1=>n20,D_SCAN_OUT_2=>n21,D_SCAN_OUT_3=>n22, + D_SCAN_OUT_4=>n23,D_SCAN_OUT_5=>n24,D_SCAN_OUT_6=>n25,D_SCAN_OUT_7=>n26, + D_COUT0=>n27,D_COUT1=>n28,D_COUT2=>n29,D_COUT3=>n30,D_COUT4=>n31,D_COUT5=>n32, + D_COUT6=>n33,D_COUT7=>n34,D_COUT8=>n35,D_COUT9=>n36,D_COUT10=>n37,D_COUT11=>n38, + D_COUT12=>n39,D_COUT13=>n40,D_COUT14=>n41,D_COUT15=>n42,D_COUT16=>n43, + D_COUT17=>n44,D_COUT18=>n45,D_COUT19=>n46,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n49); + n48 <= '1' ; + n47 <= '0' ; + n1 <= 'Z' ; + n2 <= 'Z' ; + n3 <= 'Z' ; + n4 <= 'Z' ; + n5 <= 'Z' ; + n6 <= 'Z' ; + n7 <= 'Z' ; + n8 <= 'Z' ; + n9 <= 'Z' ; + n10 <= 'Z' ; + n11 <= 'Z' ; + n12 <= 'Z' ; + n13 <= 'Z' ; + n14 <= 'Z' ; + n15 <= 'Z' ; + n16 <= 'Z' ; + n17 <= 'Z' ; + n18 <= 'Z' ; + n19 <= 'Z' ; + n20 <= 'Z' ; + n21 <= 'Z' ; + n22 <= 'Z' ; + n23 <= 'Z' ; + n24 <= 'Z' ; + n25 <= 'Z' ; + n26 <= 'Z' ; + n27 <= 'Z' ; + n28 <= 'Z' ; + n29 <= 'Z' ; + n30 <= 'Z' ; + n31 <= 'Z' ; + n32 <= 'Z' ; + n33 <= 'Z' ; + n34 <= 'Z' ; + n35 <= 'Z' ; + n36 <= 'Z' ; + n37 <= 'Z' ; + n38 <= 'Z' ; + n39 <= 'Z' ; + n40 <= 'Z' ; + n41 <= 'Z' ; + n42 <= 'Z' ; + n43 <= 'Z' ; + n44 <= 'Z' ; + n45 <= 'Z' ; + n46 <= 'Z' ; + n49 <= 'Z' ; + n106 <= '0' ; + n105 <= '1' ; + n50 <= 'Z' ; + n51 <= 'Z' ; + n52 <= 'Z' ; + n53 <= 'Z' ; + n54 <= 'Z' ; + n55 <= 'Z' ; + n56 <= 'Z' ; + n57 <= 'Z' ; + n58 <= 'Z' ; + n59 <= 'Z' ; + n60 <= 'Z' ; + n61 <= 'Z' ; + n62 <= 'Z' ; + n63 <= 'Z' ; + n64 <= 'Z' ; + n65 <= 'Z' ; + n66 <= 'Z' ; + n67 <= 'Z' ; + n68 <= 'Z' ; + n69 <= 'Z' ; + n70 <= 'Z' ; + n71 <= 'Z' ; + n72 <= 'Z' ; + n73 <= 'Z' ; + n74 <= 'Z' ; + n75 <= 'Z' ; + n76 <= 'Z' ; + n77 <= 'Z' ; + n78 <= 'Z' ; + n79 <= 'Z' ; + n80 <= 'Z' ; + n81 <= 'Z' ; + n82 <= 'Z' ; + n83 <= 'Z' ; + n84 <= 'Z' ; + n85 <= 'Z' ; + n86 <= 'Z' ; + n87 <= 'Z' ; + n88 <= 'Z' ; + n89 <= 'Z' ; + n90 <= 'Z' ; + n91 <= 'Z' ; + n92 <= 'Z' ; + n93 <= 'Z' ; + n94 <= 'Z' ; + n95 <= 'Z' ; + n96 <= 'Z' ; + n97 <= 'Z' ; + n98 <= 'Z' ; + n99 <= 'Z' ; + n100 <= 'Z' ; + n101 <= 'Z' ; + n102 <= 'Z' ; + n103 <= 'Z' ; + n104 <= 'Z' ; + n115 <= 'Z' ; + rsl_inst: component serdes1_0rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c, + rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki, + rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n125, + rui_tx_pcs_rst_c(2)=>n125,rui_tx_pcs_rst_c(1)=>n125,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c, + rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n125, + rui_rx_serdes_rst_c(2)=>n125,rui_rx_serdes_rst_c(1)=>n125,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c, + rui_rx_pcs_rst_c(3)=>n125,rui_rx_pcs_rst_c(2)=>n125,rui_rx_pcs_rst_c(1)=>n125, + rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n125,rdi_rx_los_low_s(2)=>n125, + rdi_rx_los_low_s(1)=>n125,rdi_rx_los_low_s(0)=>rx_los_low_s_c, + rdi_rx_cdr_lol_s(3)=>n125,rdi_rx_cdr_lol_s(2)=>n125,rdi_rx_cdr_lol_s(1)=>n125, + rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c, + rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c, + rdo_tx_pcs_rst_c(3)=>n116,rdo_tx_pcs_rst_c(2)=>n117,rdo_tx_pcs_rst_c(1)=>n118, + rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n119, + rdo_rx_serdes_rst_c(2)=>n120,rdo_rx_serdes_rst_c(1)=>n121,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c, + rdo_rx_pcs_rst_c(3)=>n122,rdo_rx_pcs_rst_c(2)=>n123,rdo_rx_pcs_rst_c(1)=>\_Z\, + rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c); + n114 <= '1' ; + n113 <= '0' ; + n125 <= '0' ; + n124 <= '1' ; + n116 <= 'Z' ; + n117 <= 'Z' ; + n118 <= 'Z' ; + n119 <= 'Z' ; + n120 <= 'Z' ; + n121 <= 'Z' ; + n122 <= 'Z' ; + n123 <= 'Z' ; + \_Z\ <= 'Z' ; + sll_inst: component serdes1_0sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki, + sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd, + sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd, + sli_pcie_mode=>gnd,slo_plol=>pll_lol_c); + n127 <= '1' ; + n126 <= '0' ; + gnd <= '0' ; + pwr <= '1' ; + +end architecture v1; + diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0_ngd.asd b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0_softlogic.v b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0_softlogic.v new file mode 100644 index 0000000..690b332 --- /dev/null +++ b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0_softlogic.v @@ -0,0 +1,2003 @@ + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2016 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : RSL- Reset Sequence Logic +// File : rsl_core.v +// Title : Top-level file for RSL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : BM +// Mod. Date : October 28, 2013 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : BM +// Mod. Date : November 06, 2013 +// Changes Made : Tx/Rx separation, ready port code exclusion +// ----------------------------------------------------------------------------- +// Version : 1.2 +// Author(s) : BM +// Mod. Date : June 13, 2014 +// Changes Made : Updated Rx PCS reset method +// ----------------------------------------------------------------------------- +// ----------------------------------------------------------------------------- +// Version : 1.3 +// Author(s) : UA +// Mod. Date : Dec 19, 2014 +// Changes Made : Added new parameter fro PCIE +// ----------------------------------------------------------------------------- +// Version : 1.31 +// Author(s) : BM/UM +// Mod. Date : Feb 23, 2016 +// Changes Made : Behavior of rx_rdy output modified. The output rx_rdy +// and the rx_rdy wait counter are reset to zero on +// LOL or LOS. Reverted back the counter value change for PCIE. +// ----------------------------------------------------------------------------- +// Version : 1.4 +// Author(s) : EB +// Mod. Date: : March 21, 2017 +// Changes Made : +// ----------------------------------------------------------------------------- +// Version : 1.5 +// Author(s) : ES +// Mod. Date: : May 8, 2017 +// Changes Made : Implemented common RSL behaviour as proposed by BM. +// ============================================================================= + +`timescale 1ns/10ps + +module serdes1_0rsl_core ( + // ------------ Inputs + // Common + rui_rst, // Active high reset for the RSL module + rui_serdes_rst_dual_c, // SERDES macro reset user command + rui_rst_dual_c, // PCS dual reset user command + rui_rsl_disable, // Active high signal that disables all reset outputs of RSL + // Tx + rui_tx_ref_clk, // Tx reference clock + rui_tx_serdes_rst_c, // Tx SERDES reset user command + rui_tx_pcs_rst_c, // Tx lane reset user command + rdi_pll_lol, // Tx PLL Loss of Lock status input from the SERDES + // Rx + rui_rx_ref_clk, // Rx reference clock + rui_rx_serdes_rst_c, // SERDES Receive channel reset user command + rui_rx_pcs_rst_c, // Rx lane reset user command + rdi_rx_los_low_s, // Receive loss of signal status input from SERDES + rdi_rx_cdr_lol_s, // Receive CDR loss of lock status input from SERDES + + // ------------ Outputs + // Common + rdo_serdes_rst_dual_c, // SERDES macro reset command output + rdo_rst_dual_c, // PCS dual reset command output + // Tx + ruo_tx_rdy, // Tx lane ready status output + rdo_tx_serdes_rst_c, // SERDES Tx reset command output + rdo_tx_pcs_rst_c, // PCS Tx lane reset command output + // Rx + ruo_rx_rdy, // Rx lane ready status output + rdo_rx_serdes_rst_c, // SERDES Rx channel reset command output + rdo_rx_pcs_rst_c // PCS Rx lane reset command output + ); + +// ------------ Module parameters +`ifdef NUM_CHANNELS + parameter pnum_channels = `NUM_CHANNELS; // 1,2,4 +`else + parameter pnum_channels = 1; +`endif + +`ifdef PCIE + parameter pprotocol = "PCIE"; +`else + parameter pprotocol = ""; +`endif + +`ifdef RX_ONLY + parameter pserdes_mode = "RX ONLY"; +`else + `ifdef TX_ONLY + parameter pserdes_mode = "TX ONLY"; + `else + parameter pserdes_mode = "RX AND TX"; + `endif +`endif + +`ifdef PORT_TX_RDY + parameter pport_tx_rdy = "ENABLED"; +`else + parameter pport_tx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_TX_RDY + parameter pwait_tx_rdy = `WAIT_TX_RDY; +`else + parameter pwait_tx_rdy = 3000; +`endif + +`ifdef PORT_RX_RDY + parameter pport_rx_rdy = "ENABLED"; +`else + parameter pport_rx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_RX_RDY + parameter pwait_rx_rdy = `WAIT_RX_RDY; +`else + parameter pwait_rx_rdy = 3000; +`endif + +// ------------ Local parameters + localparam wa_num_cycles = 1024; + localparam dac_num_cycles = 3; + localparam lreset_pwidth = 3; // reset pulse width-1, default=4-1=3 + localparam lwait_b4_trst = 781250; // 5ms wait with worst-case Fmax=156 MHz + localparam lwait_b4_trst_s = 781; // for simulation + localparam lplol_cnt_width = 20; // width for lwait_b4_trst + localparam lwait_after_plol0 = 4; + localparam lwait_b4_rrst = 180224; // total calibration time + localparam lrrst_wait_width = 20; + localparam lwait_after_rrst = 800000; // For CPRI- unused + localparam lwait_b4_rrst_s = 460; // wait cycles provided by design team + localparam lrlol_cnt_width = 19; // width for lwait_b4_rrst + localparam lwait_after_lols = (16384 * dac_num_cycles) + wa_num_cycles; // 16384 cycles * dac_num_cycles + 1024 cycles + localparam lwait_after_lols_s = 150; // wait cycles provided by design team + localparam llols_cnt_width = 18; // lols count width + localparam lrdb_max = 15; // maximum debounce count + localparam ltxr_wait_width = 12; // width of tx ready wait counter + localparam lrxr_wait_width = 12; // width of tx ready wait counter + +// ------------ input ports + input rui_rst; + input rui_serdes_rst_dual_c; + input rui_rst_dual_c; + input rui_rsl_disable; + + input rui_tx_ref_clk; + input rui_tx_serdes_rst_c; + input [3:0] rui_tx_pcs_rst_c; + input rdi_pll_lol; + + input rui_rx_ref_clk; + input [3:0] rui_rx_serdes_rst_c; + input [3:0] rui_rx_pcs_rst_c; + input [3:0] rdi_rx_los_low_s; + input [3:0] rdi_rx_cdr_lol_s; + +// ------------ output ports + output rdo_serdes_rst_dual_c; + output rdo_rst_dual_c; + + output ruo_tx_rdy; + output rdo_tx_serdes_rst_c; + output [3:0] rdo_tx_pcs_rst_c; + + output ruo_rx_rdy; + output [3:0] rdo_rx_serdes_rst_c; + output [3:0] rdo_rx_pcs_rst_c; + +// ------------ Internal registers and wires + // inputs + wire rui_rst; + wire rui_serdes_rst_dual_c; + wire rui_rst_dual_c; + wire rui_rsl_disable; + wire rui_tx_ref_clk; + wire rui_tx_serdes_rst_c; + wire [3:0] rui_tx_pcs_rst_c; + wire rdi_pll_lol; + wire rui_rx_ref_clk; + wire [3:0] rui_rx_serdes_rst_c; + wire [3:0] rui_rx_pcs_rst_c; + wire [3:0] rdi_rx_los_low_s; + wire [3:0] rdi_rx_cdr_lol_s; + + // outputs + wire rdo_serdes_rst_dual_c; + wire rdo_rst_dual_c; + wire ruo_tx_rdy; + wire rdo_tx_serdes_rst_c; + wire [3:0] rdo_tx_pcs_rst_c; + wire ruo_rx_rdy; + wire [3:0] rdo_rx_serdes_rst_c; + wire [3:0] rdo_rx_pcs_rst_c; + + // internal signals + // common + wire rsl_enable; + wire [lplol_cnt_width-1:0] wait_b4_trst; + wire [lrlol_cnt_width-1:0] wait_b4_rrst; + wire [llols_cnt_width-1:0] wait_after_lols; + reg pll_lol_p1; + reg pll_lol_p2; + reg pll_lol_p3; + // ------------ Tx + // rdo_tx_serdes_rst_c + reg [lplol_cnt_width-1:0] plol_cnt; + wire plol_cnt_tc; + + reg [2:0] txs_cnt; + reg txs_rst; + wire txs_cnt_tc; + // rdo_tx_pcs_rst_c + wire plol_fedge; + wire plol_redge; + reg waita_plol0; + reg [2:0] plol0_cnt; + wire plol0_cnt_tc; + reg [2:0] txp_cnt; + reg txp_rst; + wire txp_cnt_tc; + // ruo_tx_rdy + wire dual_or_serd_rst; + wire tx_any_pcs_rst; + wire tx_any_rst; + reg txsr_appd /* synthesis syn_keep=1 */; + reg txdpr_appd; + reg [pnum_channels-1:0] txpr_appd; + reg txr_wt_en; + reg [ltxr_wait_width-1:0] txr_wt_cnt; + wire txr_wt_tc; + reg ruo_tx_rdyr; + + // ------------ Rx + wire comb_rlos; + wire comb_rlol; + //wire rlols; + wire rx_all_well; + + //reg rlols_p1; + //reg rlols_p2; + //reg rlols_p3; + + reg rlol_p1; + reg rlol_p2; + reg rlol_p3; + reg rlos_p1; + reg rlos_p2; + reg rlos_p3; + + //reg [3:0] rdb_cnt; + //wire rdb_cnt_max; + //wire rdb_cnt_zero; + //reg rlols_db; + //reg rlols_db_p1; + + reg [3:0] rlol_db_cnt; + wire rlol_db_cnt_max; + wire rlol_db_cnt_zero; + reg rlol_db; + reg rlol_db_p1; + + reg [3:0] rlos_db_cnt; + wire rlos_db_cnt_max; + wire rlos_db_cnt_zero; + reg rlos_db; + reg rlos_db_p1; + + // rdo_rx_serdes_rst_c + reg [lrlol_cnt_width-1:0] rlol1_cnt; + wire rlol1_cnt_tc; + reg [2:0] rxs_cnt; + reg rxs_rst; + wire rxs_cnt_tc; + reg [lrrst_wait_width-1:0] rrst_cnt; + wire rrst_cnt_tc; + reg rrst_wait; + // rdo_rx_pcs_rst_c + //wire rlols_fedge; + //wire rlols_redge; + wire rlol_fedge; + wire rlol_redge; + wire rlos_fedge; + wire rlos_redge; + + reg wait_calib; + reg waita_rlols0; + reg [llols_cnt_width-1:0] rlols0_cnt; + wire rlols0_cnt_tc; + reg [2:0] rxp_cnt; + reg rxp_rst; + wire rxp_cnt_tc; + + wire rx_any_serd_rst; + reg [llols_cnt_width-1:0] rlolsz_cnt; + wire rlolsz_cnt_tc; + reg [2:0] rxp_cnt2; + reg rxp_rst2; + wire rxp_cnt2_tc; + reg [15:0] data_loop_b_cnt; + reg data_loop_b; + wire data_loop_b_tc; + + // ruo_rx_rdy + reg [pnum_channels-1:0] rxsr_appd; + reg [pnum_channels-1:0] rxpr_appd; + reg rxsdr_appd /* synthesis syn_keep=1 */; + reg rxdpr_appd; + wire rxsdr_or_sr_appd; + wire dual_or_rserd_rst; + wire rx_any_pcs_rst; + wire rx_any_rst; + reg rxr_wt_en; + reg [lrxr_wait_width-1:0] rxr_wt_cnt; + wire rxr_wt_tc; + reg ruo_rx_rdyr; + +// ================================================================== +// Start of code +// ================================================================== + assign rsl_enable = ~rui_rsl_disable; + +// ------------ rdo_serdes_rst_dual_c + assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c; + +// ------------ rdo_rst_dual_c + assign rdo_rst_dual_c = rui_rst_dual_c; + +// ------------ Setting counter values for RSL_SIM_MODE + `ifdef RSL_SIM_MODE + assign wait_b4_trst = lwait_b4_trst_s; + assign wait_b4_rrst = lwait_b4_rrst_s; + assign wait_after_lols = lwait_after_lols_s; + `else + assign wait_b4_trst = lwait_b4_trst; + assign wait_b4_rrst = lwait_b4_rrst; + assign wait_after_lols = lwait_after_lols; + `endif + +// ================================================================== +// Tx +// ================================================================== + generate + if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin + +// ------------ Synchronizing pll_lol to the tx clock + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + pll_lol_p1 <= 1'd0; + pll_lol_p2 <= 1'd0; + pll_lol_p3 <= 1'd0; + end + else begin + pll_lol_p1 <= rdi_pll_lol; + pll_lol_p2 <= pll_lol_p1; + pll_lol_p3 <= pll_lol_p2; + end + end + +// ------------ rdo_tx_serdes_rst_c + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol_cnt <= 'd0; + else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1)) + plol_cnt <= 'd0; + else + plol_cnt <= plol_cnt+1; + end + assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txs_cnt <= 'd0; // tx serdes reset pulse count + txs_rst <= 1'b0; // tx serdes reset + end + else if(plol_cnt_tc==1) + txs_rst <= 1'b1; + else if(txs_cnt_tc==1) begin + txs_cnt <= 'd0; + txs_rst <= 1'b0; + end + else if(txs_rst==1) + txs_cnt <= txs_cnt+1; + end + assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0; + + assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c; + +// ------------ rdo_tx_pcs_rst_c + assign plol_fedge = ~pll_lol_p2 & pll_lol_p3; + assign plol_redge = pll_lol_p2 & ~pll_lol_p3; + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + waita_plol0 <= 1'd0; + else if(plol_fedge==1'b1) + waita_plol0 <= 1'b1; + else if((plol0_cnt_tc==1)||(plol_redge==1)) + waita_plol0 <= 1'd0; + end + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol0_cnt <= 'd0; + else if((pll_lol_p2==1)||(plol0_cnt_tc==1)) + plol0_cnt <= 'd0; + else if(waita_plol0==1'b1) + plol0_cnt <= plol0_cnt+1; + end + assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txp_cnt <= 'd0; // tx serdes reset pulse count + txp_rst <= 1'b0; // tx serdes reset + end + else if(plol0_cnt_tc==1) + txp_rst <= 1'b1; + else if(txp_cnt_tc==1) begin + txp_cnt <= 'd0; + txp_rst <= 1'b0; + end + else if(txp_rst==1) + txp_cnt <= txp_cnt+1; + end + assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0; + + genvar i; + for(i=0;i>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : SLL - Soft Loss Of Lock(LOL) Logic +// File : sll_core.v +// Title : Top-level file for SLL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : March 2, 2015 +// Changes Made : Initial Creation +// ============================================================================= +// REVISION HISTORY +// Version : 1.1 +// Author(s) : AV +// Mod. Date : June 8, 2015 +// Changes Made : Following updates were made +// : 1. Changed all the PLOL status logic and FSM to run +// : on sli_refclk. +// : 2. Added the HB logic for presence of tx_pclk +// : 3. Changed the lparam assignment scheme for +// : simulation purposes. +// ============================================================================= +// REVISION HISTORY +// Version : 1.2 +// Author(s) : AV +// Mod. Date : June 24, 2015 +// Changes Made : Updated the gearing logic for SDI dynamic rate change +// ============================================================================= +// REVISION HISTORY +// Version : 1.3 +// Author(s) : AV +// Mod. Date : July 14, 2015 +// Changes Made : Added the logic for dynamic rate change in CPRI +// ============================================================================= +// REVISION HISTORY +// Version : 1.4 +// Author(s) : AV +// Mod. Date : August 21, 2015 +// Changes Made : Added the logic for dynamic rate change of 5G CPRI & +// PCIe. +// ============================================================================= +// REVISION HISTORY +// Version : 1.5 +// Author(s) : ES/EB +// Mod. Date : March 21, 2017 +// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff +// : to sli_refclk. +// : 2. Updated terminal count logic for PCIe 5G +// : 3. Modified checking of pcount_diff in SLL state +// : machine to cover actual count +// : (from 16-bits to 22-bits) +// ============================================================================= +// REVISION HISTORY +// Version : 1.6 +// Author(s) : ES +// Mod. Date : April 19, 2017 +// Changes Made : 1. Added registered lock and unlock signal from +// pdiff_sync to totally decouple pcount_diff from +// SLL state machine. +// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI +// is operating @ 4.9125Gbps data rate. +// ============================================================================= +`timescale 1ns/10ps + +module serdes1_0sll_core ( + //Reset and Clock inputs + sli_rst, //Active high asynchronous reset input + sli_refclk, //Refclk input to the Tx PLL + sli_pclk, //Tx pclk output from the PCS + + //Control inputs + sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate + sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11 + sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20 + sli_cpri_mode, //Mode of operation specific to CPRI protocol + sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G) + + //LOL Output + slo_plol //Tx PLL Loss of Lock output to the user logic + ); + +// Inputs +input sli_rst; +input sli_refclk; +input sli_pclk; +input sli_div2_rate; +input sli_div11_rate; +input sli_gear_mode; +input [2:0] sli_cpri_mode; +input sli_pcie_mode; + +// Outputs +output slo_plol; + + +// Parameters +parameter PPROTOCOL = "PCIE"; //Protocol selected by the User +parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3 +parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control +parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate +parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock +parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock +parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk +parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11 +parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11 +parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk + + +// Local Parameters +localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state +localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state +localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state +localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state +`ifdef RSL_SIM_MODE +localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk +`else +localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk +`endif +localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse +localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal + +// Local Parameters related to the CPRI dynamic modes +// Terminal count values for the four CPRI modes +localparam LPCLK_TC_0 = 32768; +localparam LPCLK_TC_1 = 65536; +localparam LPCLK_TC_2 = 131072; +localparam LPCLK_TC_3 = 163840; +localparam LPCLK_TC_4 = 65536; + +// Lock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19; +localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19; +localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98; +localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262; + +// Unlock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39; +localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131; +localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144; +localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393; + +// Input and Output reg and wire declarations +wire sli_rst; +wire sli_refclk; +wire sli_pclk; +wire sli_div2_rate; +wire sli_div11_rate; +wire sli_gear_mode; +wire [2:0] sli_cpri_mode; +wire sli_pcie_mode; +wire slo_plol; + +//-------------- Internal signals reg and wire declarations -------------------- + +//Signals running on sli_refclk +reg [15:0] rcount; //16-bit Counter +reg rtc_pul; //Terminal count pulse +reg rtc_pul_p1; //Terminal count pulse pipeline +reg rtc_ctrl; //Terminal count pulse control + +reg [7:0] rhb_wait_cnt; //Heartbeat wait counter + +//Heatbeat synchronization and pipeline registers +wire rhb_sync; +reg rhb_sync_p2; +reg rhb_sync_p1; + +//Pipeling registers for dynamic control mode +wire rgear; +wire rdiv2; +wire rdiv11; +reg rgear_p1; +reg rdiv2_p1; +reg rdiv11_p1; + +reg rstat_pclk; //Pclk presence/absence status + +reg [21:0] rcount_tc; //Tx_pclk terminal count register +reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock +reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock + +wire rpcie_mode; //PCIe mode signal synchronized to refclk +reg rpcie_mode_p1; //PCIe mode pipeline register + +wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk +reg rcpri_mod_ch_p1; //CPRI mode change pipeline register +reg rcpri_mod_ch_p2; //CPRI mode change pipeline register +reg rcpri_mod_ch_st; //CPRI mode change status + +reg [1:0] sll_state; //Current-state register for LOL FSM + +reg pll_lock; //PLL Lock signal + +//Signals running on sli_pclk +//Synchronization and pipeline registers +wire ppul_sync; +reg ppul_sync_p1; +reg ppul_sync_p2; +reg ppul_sync_p3; + +wire pdiff_sync; +reg pdiff_sync_p1; + +reg [21:0] pcount; //22-bit counter +reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value + +//Heartbeat counter and heartbeat signal running on pclk +reg [2:0] phb_cnt; +reg phb; + +//CPRI dynamic mode releated signals +reg [2:0] pcpri_mode; +reg pcpri_mod_ch; + +//Assignment scheme changed mainly for simulation purpose +wire [15:0] LRCLK_TC_w; +assign LRCLK_TC_w = LRCLK_TC; + +reg unlock; +reg lock; + +//Heartbeat synchronization +sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (phb), + .data_out(rhb_sync) + ); + + +//Terminal count pulse synchronization +sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( + .clk (sli_pclk), + .rst (sli_rst), + .data_in (rtc_pul), + .data_out(ppul_sync) + ); + +//Differential value logic update synchronization +sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (ppul_sync), + .data_out(pdiff_sync) + ); + +//Gear mode synchronization +sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_gear_mode), + .data_out(rgear) + ); + +//Div2 synchronization +sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div2_rate), + .data_out(rdiv2) + ); + +//Div11 synchronization +sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div11_rate), + .data_out(rdiv11) + ); + +//CPRI mode change synchronization +sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (pcpri_mod_ch), + .data_out(rcpri_mod_ch_sync) + ); + +//PCIe mode change synchronization +sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_pcie_mode), + .data_out(rpcie_mode) + ); + +// ============================================================================= +// Synchronized Lock/Unlock signals +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + unlock <= 1'b0; + lock <= 1'b0; + pdiff_sync_p1 <= 1'b0; + end + else begin + pdiff_sync_p1 <= pdiff_sync; + if (unlock) begin + unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock; + end + else begin + unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0; + end + if (lock) begin + lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock; + end + else begin + lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0; + end + end +end + +// ============================================================================= +// Refclk Counter, pulse generation logic and Heartbeat monitor logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount <= 16'd0; + rtc_pul <= 1'b0; + rtc_ctrl <= 1'b0; + rtc_pul_p1 <= 1'b0; + end + else begin + //Counter logic + if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + if (rtc_ctrl == 1'b1) begin + rcount <= LRCLK_TC_PUL_WIDTH; + end + end + else begin + if (rcount != LRCLK_TC_w) begin + rcount <= rcount + 1; + end + else begin + rcount <= 16'd0; + end + end + + //Pulse control logic + if (rcount == LRCLK_TC_w - 1) begin + rtc_ctrl <= 1'b1; + end + + //Pulse Generation logic + if (rtc_ctrl == 1'b1) begin + if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin + rtc_pul <= 1'b1; + end + else begin + rtc_pul <= 1'b0; + end + end + + rtc_pul_p1 <= rtc_pul; + end +end + + +// ============================================================================= +// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rhb_sync_p1 <= 1'b0; + rhb_sync_p2 <= 1'b0; + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + rgear_p1 <= 1'b0; + rdiv2_p1 <= 1'b0; + rdiv11_p1 <= 1'b0; + rcpri_mod_ch_p1 <= 1'b0; + rcpri_mod_ch_p2 <= 1'b0; + rcpri_mod_ch_st <= 1'b0; + rpcie_mode_p1 <= 1'b0; + + end + else begin + //Pipeline stages for the Heartbeat + rhb_sync_p1 <= rhb_sync; + rhb_sync_p2 <= rhb_sync_p1; + + //Pipeline stages of the Dynamic rate control signals + rgear_p1 <= rgear; + rdiv2_p1 <= rdiv2; + rdiv11_p1 <= rdiv11; + + //Pipeline stage for PCIe mode + rpcie_mode_p1 <= rpcie_mode; + + //Pipeline stage for CPRI mode change + rcpri_mod_ch_p1 <= rcpri_mod_ch_sync; + rcpri_mod_ch_p2 <= rcpri_mod_ch_p1; + + //CPRI mode change status logic + if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin + rcpri_mod_ch_st <= 1'b1; + end + + //Heartbeat wait counter and monitor logic + if (rtc_ctrl == 1'b1) begin + if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b1; + end + else if (rhb_wait_cnt == LHB_WAIT_CNT) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + end + else begin + rhb_wait_cnt <= rhb_wait_cnt + 1; + end + end + end +end + + +// ============================================================================= +// Pipleline registers for the TC pulse and CPRI mode change logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + ppul_sync_p1 <= 1'b0; + ppul_sync_p2 <= 1'b0; + ppul_sync_p3 <= 1'b0; + pcpri_mode <= 3'b0; + pcpri_mod_ch <= 1'b0; + end + else begin + ppul_sync_p1 <= ppul_sync; + ppul_sync_p2 <= ppul_sync_p1; + ppul_sync_p3 <= ppul_sync_p2; + + //CPRI mode change logic + pcpri_mode <= sli_cpri_mode; + + if (pcpri_mode != sli_cpri_mode) begin + pcpri_mod_ch <= ~pcpri_mod_ch; + end + end +end + + +// ============================================================================= +// Terminal count logic +// ============================================================================= + +//For SDI protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 11 is enabled + if (rdiv11 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_DIV11_TC; + rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0}; + rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0}; + rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0}; + end + end + //Div by 2 is enabled + else if (rdiv2 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end + //Both div by 11 and div by 2 are disabled + else begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_TC[20:0],1'b0}; + rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0}; + rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0}; + end + end + end +end +end +endgenerate + +//For G8B10B protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 2 is enabled + if (rdiv2 == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + + +//For CPRI protocol with Dynamic rate control is disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for CPRI protocol + //Only if there is a change in the rate mode from the default + if (rcpri_mod_ch_st == 1'b1) begin + if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin + case(sli_cpri_mode) + 3'd0 : begin //For 0.6Gbps + rcount_tc <= LPCLK_TC_0; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_01; + rdiff_comp_unlock <= LPDIFF_UNLOCK_01; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_02; + rdiff_comp_unlock <= LPDIFF_UNLOCK_02; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_03; + rdiff_comp_unlock <= LPDIFF_UNLOCK_03; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + + 3'd1 : begin //For 1.2Gbps + rcount_tc <= LPCLK_TC_1; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_11; + rdiff_comp_unlock <= LPDIFF_UNLOCK_11; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_12; + rdiff_comp_unlock <= LPDIFF_UNLOCK_12; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_13; + rdiff_comp_unlock <= LPDIFF_UNLOCK_13; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + endcase + end + + 3'd2 : begin //For 2.4Gbps + rcount_tc <= LPCLK_TC_2; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_21; + rdiff_comp_unlock <= LPDIFF_UNLOCK_21; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_22; + rdiff_comp_unlock <= LPDIFF_UNLOCK_22; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_23; + rdiff_comp_unlock <= LPDIFF_UNLOCK_23; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + endcase + end + + 3'd3 : begin //For 3.07Gbps + rcount_tc <= LPCLK_TC_3; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_30; + rdiff_comp_unlock <= LPDIFF_UNLOCK_30; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_31; + rdiff_comp_unlock <= LPDIFF_UNLOCK_31; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_32; + rdiff_comp_unlock <= LPDIFF_UNLOCK_32; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_33; + rdiff_comp_unlock <= LPDIFF_UNLOCK_33; + end + endcase + end + + 3'd4 : begin //For 4.9125bps + rcount_tc <= LPCLK_TC_4; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_41; + rdiff_comp_unlock <= LPDIFF_UNLOCK_41; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_42; + rdiff_comp_unlock <= LPDIFF_UNLOCK_42; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_43; + rdiff_comp_unlock <= LPDIFF_UNLOCK_43; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + endcase + end + + default : begin + rcount_tc <= LPCLK_TC_0; + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + end + else begin + //If there is no change in the CPRI rate mode from default + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + +//For PCIe protocol with Dynamic rate control disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + if (PPCIE_MAX_RATE == "2.5") begin + //2.5G mode is enabled + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //5G mode is enabled + if (rpcie_mode == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //2.5G mode is enabled + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + end + end +end +end +endgenerate + +//For all protocols other than CPRI & PCIe +generate +if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for all protocols other than CPRI & PCIe + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end +end +end +endgenerate + + +// ============================================================================= +// Tx_pclk counter, Heartbeat and Differential value logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pcount <= 22'd0; + pcount_diff <= 22'd65535; + phb_cnt <= 3'd0; + phb <= 1'b0; + end + else begin + //Counter logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount <= 22'd0; + end + else begin + pcount <= pcount + 1; + end + + //Heartbeat logic + phb_cnt <= phb_cnt + 1; + + if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin + phb <= 1'b1; + end + else begin + phb <= 1'b0; + end + + //Differential value logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount_diff <= rcount_tc + ~(pcount) + 1; + end + else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin + if (pcount_diff[21] == 1'b1) begin + pcount_diff <= ~(pcount_diff) + 1; + end + end + end +end + + +// ============================================================================= +// State transition logic for SLL FSM +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI + if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || + (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_LOSS_ST; + end + else if (lock) begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_PRELOCK_ST; + end + else begin + sll_state <= LPLL_LOCK_ST; + end + end + end + end + + LPLL_LOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + end + + LPLL_PRELOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + + LPLL_PRELOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_PRELOSS_ST; + end + else if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + end + end + + default: begin + sll_state <= LPLL_LOSS_ST; + end + endcase + end + end +end + + +// ============================================================================= +// Logic for Tx PLL Lock +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pll_lock <= 1'b0; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + pll_lock <= 1'b0; + end + + LPLL_LOCK_ST : begin + pll_lock <= 1'b1; + end + + LPLL_PRELOSS_ST : begin + pll_lock <= 1'b0; + end + + default: begin + pll_lock <= 1'b0; + end + endcase + end +end + +assign slo_plol = ~(pll_lock); + +endmodule + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : Synchronizer Logic +// File : sync.v +// Title : Synchronizer module +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : July 7, 2015 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : EB +// Mod. Date : March 21, 2017 +// Changes Made : +// ============================================================================= + +`ifndef PCS_SYNC_MODULE +`define PCS_SYNC_MODULE +module sync ( + clk, + rst, + data_in, + data_out + ); + +input clk; //Clock in which the async data needs to be synchronized to +input rst; //Active high reset +input data_in; //Asynchronous data +output data_out; //Synchronized data + +parameter PDATA_RST_VAL = 0; //Reset value for the registers + +reg data_p1; +reg data_p2; + +// ============================================================================= +// Synchronization logic +// ============================================================================= +always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + data_p1 <= PDATA_RST_VAL; + data_p2 <= PDATA_RST_VAL; + end + else begin + data_p1 <= data_in; + data_p2 <= data_p1; + end +end + +assign data_out = data_p2; + +endmodule +`endif + diff --git a/media_interfaces/ecp5/dual_serdes/serdes1/serdes1.ipx b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.ipx similarity index 100% rename from media_interfaces/ecp5/dual_serdes/serdes1/serdes1.ipx rename to media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.ipx diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.lpc b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.lpc new file mode 100644 index 0000000..91156e6 --- /dev/null +++ b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.lpc @@ -0,0 +1,97 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA381 +PartName=LFE5UM-45F-8BG381C +PartType=LFE5UM-45F +SpeedGrade=8 +Status=P +[IP] +CoreName=PCS +CoreRevision=8.2 +CoreStatus=Demo +CoreType=LPM +Date=11/23/2020 +ModuleName=serdes1_1 +ParameterFileVersion=1.0 +SourceFormat=vhdl +Time=19:09:02 +VendorName=Lattice Semiconductor Corporation +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=3 +CDR_MAX_RATE=2 +CDR_MULT=10X +CDR_REF_RATE=200.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=G8B10B +LEQ=Disabled +LOOPBACK=Disabled +LOSPORT=Enabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Enabled +PPORT_TX_RDY=Enabled +PROTOCOL=G8B10B +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=200.0000 +RSTSEQSEL=Enabled +RX8B10B=Enabled +RXCOMMAA=0010000011 +RXCOMMAB=0001111100 +RXCOMMAM=0011111111 +RXCOUPLING=AC +RXCTC=Disabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=0 00H +RXCTCBYTEN3=0 00H +RXCTCMATCHPATTERN=M4-S4 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Non-invert +RXLDR=Off +RXLOSTHRESHOLD=0 +RXLSM=Enabled +RXSC=K28P157 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=200.0000 +RX_LINE_RATE=2.0000 +RX_RATE_DIV=Full Rate +SCIPORT=Enabled +SOFTLOL=Disabled +TX8B10B=Enabled +TXAMPLITUDE=800 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Non-invert +TXLDR=Off +TXPLLLOLTHRESHOLD=1 +TXPLLMULT=10X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=200.0000 +TX_LINE_RATE=2.0000 +TX_MAX_RATE=2 +TX_RATE_DIV=Full Rate +VHDL=1 +Verilog=0 +[FilesGenerated] +serdes1.pp=pp +serdes1.sym=sym +serdes1.tft=tft +serdes1.txt=pcs_module +[SYSTEMPNR] +LN0=DCU1_CH1 diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.ngd b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.ngd new file mode 100644 index 0000000..a2ec94e Binary files /dev/null and b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.ngd differ diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.ngo b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.ngo new file mode 100644 index 0000000..56d290e Binary files /dev/null and b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.ngo differ diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.vhd b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.vhd new file mode 100644 index 0000000..30e182a --- /dev/null +++ b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.vhd @@ -0,0 +1,396 @@ + +-- +-- Verific VHDL Description of module DCUA +-- + +-- DCUA is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module serdes1rsl_core +-- + +-- serdes1rsl_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module serdes1 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +library ecp5um ; +use ecp5um.components.all ; + +entity serdes1_1 is + port (hdoutp: out std_logic; + hdoutn: out std_logic; + hdinp: in std_logic; + hdinn: in std_logic; + rxrefclk: in std_logic; + rx_pclk: out std_logic; + tx_pclk: out std_logic; + txdata: in std_logic_vector(7 downto 0); + tx_k: in std_logic_vector(0 downto 0); + tx_force_disp: in std_logic_vector(0 downto 0); + tx_disp_sel: in std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_cv_err: out std_logic_vector(0 downto 0); + tx_idle_c: in std_logic; + signal_detect_c: in std_logic; + rx_los_low_s: out std_logic; + lsm_status_s: out std_logic; + rx_cdr_lol_s: out std_logic; + tx_pwrup_c: in std_logic; + rx_pwrup_c: in std_logic; + sci_wrdata: in std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_en_dual: in std_logic; + sci_sel_dual: in std_logic; + sci_en: in std_logic; + sci_sel: in std_logic; + sci_rd: in std_logic; + sci_wrn: in std_logic; + sci_int: out std_logic; + cyawstn: in std_logic; + serdes_pdb: in std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + serdes_rst_dual_c: in std_logic; + rst_dual_c: in std_logic; + tx_serdes_rst_c: in std_logic; + tx_pcs_rst_c: in std_logic; + pll_lol: in std_logic; + rsl_tx_rdy: out std_logic; + rx_serdes_rst_c: in std_logic; + rx_pcs_rst_c: in std_logic; + rsl_rx_rdy: out std_logic + ); + +end entity serdes1_1; + +architecture v1 of serdes1_1 is + component serdes1_1rsl_core is + generic (pnum_channels: integer := 1; + pprotocol: string := "G8B10B"; + pserdes_mode: string := "RX AND TX"; + pport_tx_rdy: string := "ENABLED"; + pwait_tx_rdy: integer := 3000; + pport_rx_rdy: string := "ENABLED"; + pwait_rx_rdy: integer := 3000); + port (rui_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132) + rui_serdes_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133) + rui_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134) + rui_rsl_disable: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135) + rui_tx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137) + rui_tx_serdes_rst_c: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138) + rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139) + rdi_pll_lol: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140) + rui_rx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142) + rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143) + rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144) + rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145) + rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146) + rdo_serdes_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149) + rdo_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150) + ruo_tx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152) + rdo_tx_serdes_rst_c: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153) + rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154) + ruo_rx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156) + rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157) + rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158) + ); + + end component serdes1_1rsl_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88) + signal n48,n47,n1,n2,n3,n4,rx_pclk_c,tx_pclk_c,n5,n6,n7,n8,n9, + n10,n11,n12,rx_los_low_s_c,n13,n14,n15,n16,rx_cdr_lol_s_c,n17, + n18,rsl_tx_pcs_rst_c,rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c, + rsl_serdes_rst_dual_c,rsl_tx_serdes_rst_c,n19,n20,n21,n22,n23, + n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37, + n38,n39,n40,n41,n42,n43,n44,n45,n46,n49,n106,n105,n50,n51, + n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65, + n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79, + n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93, + n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n115,n114, + n113,gnd,pwr,n116,n117,n118,n119,n120,n121,n122,n123,\_Z\ : std_logic; + attribute LOC : string; + attribute LOC of DCU0_inst : label is "DCU1"; + attribute CHAN : string; + attribute CHAN of DCU0_inst : label is "CH1"; +begin + rx_pclk <= rx_pclk_c; + tx_pclk <= tx_pclk_c; + rx_los_low_s <= rx_los_low_s_c; + rx_cdr_lol_s <= rx_cdr_lol_s_c; + DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", + D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", + D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", + D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b1",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", + CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", + CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", + CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", + CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", + CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0", + CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b1", + CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b0", + CH1_MATCH_4_ENABLE=>"0b1",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x1BC", + CH1_CC_MATCH_2=>"0x11C",CH1_CC_MATCH_3=>"0x11C",CH1_CC_MATCH_4=>"0x11C", + CH1_UDF_COMMA_MASK=>"0x0ff",CH1_UDF_COMMA_A=>"0x083",CH1_UDF_COMMA_B=>"0x07C", + CH1_RX_DCO_CK_DIV=>"0b000",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1", + CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00", + CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b00",CH1_TDRV_SLICE1_SEL=>"0b00", + CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01", + CH1_TDRV_SLICE5_SEL=>"0b00",CH1_TDRV_SLICE0_CUR=>"0b000",CH1_TDRV_SLICE1_CUR=>"0b000", + CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b01", + CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0", + CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0", + CH1_SEL_SD_RX_CLK=>"0b1",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0", + CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0", + CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00", + CH1_REQ_EN=>"0b0",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1", + CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000", + CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b000",CH1_RX_LOS_CEQ=>"0b11", + CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0", + CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2",CH1_CDR_MAX_RATE=>"2", + CH1_TXAMPLITUDE=>"0d800",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED", + CH1_PROTOCOL=>"G8B10B",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b10",D_SETICONST_AUX=>"0b01", + D_SETIRPOLY_CH=>"0b10",D_SETICONST_CH=>"0b10",D_REQ_ISET=>"0b001", + D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00", + CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00", + CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b000",CH1_DCOCTLGI=>"0b011", + CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b00",CH1_DCOFTNRG=>"0b001", + CH1_DCOIOSTUNE=>"0b010",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b010", + CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b100",CH1_DCOSCALEI=>"0b01", + CH1_DCOSTARTVAL=>"0b010",CH1_DCOSTEP=>"0b11",CH1_BAND_THRESHOLD=>"0d0", + CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0", + CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0", + CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", + D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", + D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", + D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d10", + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b01", + D_RG_EN=>"0b0",D_RG_SET=>"0b00") + port map (CH0_HDINP=>n106,CH1_HDINP=>hdinp,CH0_HDINN=>n106,CH1_HDINN=>hdinn, + D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47, + CH0_RX_REFCLK=>n106,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n105,CH1_FF_RXI_CLK=>rx_pclk_c, + CH0_FF_TXI_CLK=>n105,CH1_FF_TXI_CLK=>tx_pclk_c,CH0_FF_EBRD_CLK=>n105, + CH1_FF_EBRD_CLK=>n48,CH0_FF_TX_D_0=>n106,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n106, + CH1_FF_TX_D_1=>txdata(1),CH0_FF_TX_D_2=>n106,CH1_FF_TX_D_2=>txdata(2), + CH0_FF_TX_D_3=>n106,CH1_FF_TX_D_3=>txdata(3),CH0_FF_TX_D_4=>n106,CH1_FF_TX_D_4=>txdata(4), + CH0_FF_TX_D_5=>n106,CH1_FF_TX_D_5=>txdata(5),CH0_FF_TX_D_6=>n106,CH1_FF_TX_D_6=>txdata(6), + CH0_FF_TX_D_7=>n106,CH1_FF_TX_D_7=>txdata(7),CH0_FF_TX_D_8=>n106,CH1_FF_TX_D_8=>tx_k(0), + CH0_FF_TX_D_9=>n106,CH1_FF_TX_D_9=>tx_force_disp(0),CH0_FF_TX_D_10=>n106, + CH1_FF_TX_D_10=>tx_disp_sel(0),CH0_FF_TX_D_11=>n106,CH1_FF_TX_D_11=>n47, + CH0_FF_TX_D_12=>n106,CH1_FF_TX_D_12=>n106,CH0_FF_TX_D_13=>n106,CH1_FF_TX_D_13=>n106, + CH0_FF_TX_D_14=>n106,CH1_FF_TX_D_14=>n106,CH0_FF_TX_D_15=>n106,CH1_FF_TX_D_15=>n106, + CH0_FF_TX_D_16=>n106,CH1_FF_TX_D_16=>n106,CH0_FF_TX_D_17=>n106,CH1_FF_TX_D_17=>n106, + CH0_FF_TX_D_18=>n106,CH1_FF_TX_D_18=>n106,CH0_FF_TX_D_19=>n106,CH1_FF_TX_D_19=>n106, + CH0_FF_TX_D_20=>n106,CH1_FF_TX_D_20=>n106,CH0_FF_TX_D_21=>n106,CH1_FF_TX_D_21=>n106, + CH0_FF_TX_D_22=>n106,CH1_FF_TX_D_22=>n106,CH0_FF_TX_D_23=>n106,CH1_FF_TX_D_23=>n47, + CH0_FFC_EI_EN=>n106,CH1_FFC_EI_EN=>tx_idle_c,CH0_FFC_PCIE_DET_EN=>n106, + CH1_FFC_PCIE_DET_EN=>n47,CH0_FFC_PCIE_CT=>n106,CH1_FFC_PCIE_CT=>n47,CH0_FFC_SB_INV_RX=>n106, + CH1_FFC_SB_INV_RX=>n106,CH0_FFC_ENABLE_CGALIGN=>n106,CH1_FFC_ENABLE_CGALIGN=>n106, + CH0_FFC_SIGNAL_DETECT=>n106,CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n106, + CH1_FFC_FB_LOOPBACK=>n47,CH0_FFC_SB_PFIFO_LP=>n106,CH1_FFC_SB_PFIFO_LP=>n47, + CH0_FFC_PFIFO_CLR=>n106,CH1_FFC_PFIFO_CLR=>n47,CH0_FFC_RATE_MODE_RX=>n106, + CH1_FFC_RATE_MODE_RX=>n106,CH0_FFC_RATE_MODE_TX=>n106,CH1_FFC_RATE_MODE_TX=>n106, + CH0_FFC_DIV11_MODE_RX=>n106,CH1_FFC_DIV11_MODE_RX=>n47,CH0_FFC_DIV11_MODE_TX=>n106, + CH1_FFC_DIV11_MODE_TX=>n47,CH0_FFC_RX_GEAR_MODE=>n106,CH1_FFC_RX_GEAR_MODE=>n47, + CH0_FFC_TX_GEAR_MODE=>n106,CH1_FFC_TX_GEAR_MODE=>n47,CH0_FFC_LDR_CORE2TX_EN=>n106, + CH1_FFC_LDR_CORE2TX_EN=>n106,CH0_FFC_LANE_TX_RST=>n106,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c, + CH0_FFC_LANE_RX_RST=>n106,CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n106, + CH1_FFC_RRST=>rsl_rx_serdes_rst_c,CH0_FFC_TXPWDNB=>n106,CH1_FFC_TXPWDNB=>tx_pwrup_c, + CH0_FFC_RXPWDNB=>n106,CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n106, + CH1_LDR_CORE2TX=>n106,D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1), + D_SCIWDATA2=>sci_wrdata(2),D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4), + D_SCIWDATA5=>sci_wrdata(5),D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7), + D_SCIADDR0=>sci_addr(0),D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2), + D_SCIADDR3=>sci_addr(3),D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5), + D_SCIENAUX=>sci_en_dual,D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n106,CH1_SCIEN=>sci_en, + CH0_SCISEL=>n106,CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn, + D_CYAWSTN=>cyawstn,D_FFC_SYNC_TOGGLE=>n106,D_FFC_DUAL_RST=>rsl_rst_dual_c, + D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c,D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c, + CH0_FFC_CDR_EN_BITSLIP=>n106,CH1_FFC_CDR_EN_BITSLIP=>n47,D_SCAN_ENABLE=>n47, + D_SCAN_IN_0=>n47,D_SCAN_IN_1=>n47,D_SCAN_IN_2=>n47,D_SCAN_IN_3=>n47, + D_SCAN_IN_4=>n47,D_SCAN_IN_5=>n47,D_SCAN_IN_6=>n47,D_SCAN_IN_7=>n47, + D_SCAN_MODE=>n47,D_SCAN_RESET=>n47,D_CIN0=>n47,D_CIN1=>n47,D_CIN2=>n47, + D_CIN3=>n47,D_CIN4=>n47,D_CIN5=>n47,D_CIN6=>n47,D_CIN7=>n47,D_CIN8=>n47, + D_CIN9=>n47,D_CIN10=>n47,D_CIN11=>n47,CH0_HDOUTP=>n50,CH1_HDOUTP=>hdoutp, + CH0_HDOUTN=>n51,CH1_HDOUTN=>hdoutn,D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2, + D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,CH0_FF_RX_F_CLK=>n52,CH1_FF_RX_F_CLK=>n5, + CH0_FF_RX_H_CLK=>n53,CH1_FF_RX_H_CLK=>n6,CH0_FF_TX_F_CLK=>n54,CH1_FF_TX_F_CLK=>n7, + CH0_FF_TX_H_CLK=>n55,CH1_FF_TX_H_CLK=>n8,CH0_FF_RX_PCLK=>n56,CH1_FF_RX_PCLK=>rx_pclk_c, + CH0_FF_TX_PCLK=>n57,CH1_FF_TX_PCLK=>tx_pclk_c,CH0_FF_RX_D_0=>n58,CH1_FF_RX_D_0=>rxdata(0), + CH0_FF_RX_D_1=>n59,CH1_FF_RX_D_1=>rxdata(1),CH0_FF_RX_D_2=>n60,CH1_FF_RX_D_2=>rxdata(2), + CH0_FF_RX_D_3=>n61,CH1_FF_RX_D_3=>rxdata(3),CH0_FF_RX_D_4=>n62,CH1_FF_RX_D_4=>rxdata(4), + CH0_FF_RX_D_5=>n63,CH1_FF_RX_D_5=>rxdata(5),CH0_FF_RX_D_6=>n64,CH1_FF_RX_D_6=>rxdata(6), + CH0_FF_RX_D_7=>n65,CH1_FF_RX_D_7=>rxdata(7),CH0_FF_RX_D_8=>n66,CH1_FF_RX_D_8=>rx_k(0), + CH0_FF_RX_D_9=>n67,CH1_FF_RX_D_9=>rx_disp_err(0),CH0_FF_RX_D_10=>n68, + CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n69,CH1_FF_RX_D_11=>n9,CH0_FF_RX_D_12=>n70, + CH1_FF_RX_D_12=>n71,CH0_FF_RX_D_13=>n72,CH1_FF_RX_D_13=>n73,CH0_FF_RX_D_14=>n74, + CH1_FF_RX_D_14=>n75,CH0_FF_RX_D_15=>n76,CH1_FF_RX_D_15=>n77,CH0_FF_RX_D_16=>n78, + CH1_FF_RX_D_16=>n79,CH0_FF_RX_D_17=>n80,CH1_FF_RX_D_17=>n81,CH0_FF_RX_D_18=>n82, + CH1_FF_RX_D_18=>n83,CH0_FF_RX_D_19=>n84,CH1_FF_RX_D_19=>n85,CH0_FF_RX_D_20=>n86, + CH1_FF_RX_D_20=>n87,CH0_FF_RX_D_21=>n88,CH1_FF_RX_D_21=>n89,CH0_FF_RX_D_22=>n90, + CH1_FF_RX_D_22=>n91,CH0_FF_RX_D_23=>n92,CH1_FF_RX_D_23=>n10,CH0_FFS_PCIE_DONE=>n93, + CH1_FFS_PCIE_DONE=>n11,CH0_FFS_PCIE_CON=>n94,CH1_FFS_PCIE_CON=>n12,CH0_FFS_RLOS=>n95, + CH1_FFS_RLOS=>rx_los_low_s_c,CH0_FFS_LS_SYNC_STATUS=>n96,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s, + CH0_FFS_CC_UNDERRUN=>n97,CH1_FFS_CC_UNDERRUN=>n13,CH0_FFS_CC_OVERRUN=>n98, + CH1_FFS_CC_OVERRUN=>n14,CH0_FFS_RXFBFIFO_ERROR=>n99,CH1_FFS_RXFBFIFO_ERROR=>n15, + CH0_FFS_TXFBFIFO_ERROR=>n100,CH1_FFS_TXFBFIFO_ERROR=>n16,CH0_FFS_RLOL=>n101, + CH1_FFS_RLOL=>rx_cdr_lol_s_c,CH0_FFS_SKP_ADDED=>n102,CH1_FFS_SKP_ADDED=>n17, + CH0_FFS_SKP_DELETED=>n103,CH1_FFS_SKP_DELETED=>n18,CH0_LDR_RX2CORE=>n104, + CH1_LDR_RX2CORE=>n115,D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1), + D_SCIRDATA2=>sci_rddata(2),D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4), + D_SCIRDATA5=>sci_rddata(5),D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7), + D_SCIINT=>sci_int,D_SCAN_OUT_0=>n19,D_SCAN_OUT_1=>n20,D_SCAN_OUT_2=>n21, + D_SCAN_OUT_3=>n22,D_SCAN_OUT_4=>n23,D_SCAN_OUT_5=>n24,D_SCAN_OUT_6=>n25, + D_SCAN_OUT_7=>n26,D_COUT0=>n27,D_COUT1=>n28,D_COUT2=>n29,D_COUT3=>n30, + D_COUT4=>n31,D_COUT5=>n32,D_COUT6=>n33,D_COUT7=>n34,D_COUT8=>n35,D_COUT9=>n36, + D_COUT10=>n37,D_COUT11=>n38,D_COUT12=>n39,D_COUT13=>n40,D_COUT14=>n41, + D_COUT15=>n42,D_COUT16=>n43,D_COUT17=>n44,D_COUT18=>n45,D_COUT19=>n46, + D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n49); + n48 <= '1' ; + n47 <= '0' ; + n1 <= 'Z' ; + n2 <= 'Z' ; + n3 <= 'Z' ; + n4 <= 'Z' ; + n5 <= 'Z' ; + n6 <= 'Z' ; + n7 <= 'Z' ; + n8 <= 'Z' ; + n9 <= 'Z' ; + n10 <= 'Z' ; + n11 <= 'Z' ; + n12 <= 'Z' ; + n13 <= 'Z' ; + n14 <= 'Z' ; + n15 <= 'Z' ; + n16 <= 'Z' ; + n17 <= 'Z' ; + n18 <= 'Z' ; + n19 <= 'Z' ; + n20 <= 'Z' ; + n21 <= 'Z' ; + n22 <= 'Z' ; + n23 <= 'Z' ; + n24 <= 'Z' ; + n25 <= 'Z' ; + n26 <= 'Z' ; + n27 <= 'Z' ; + n28 <= 'Z' ; + n29 <= 'Z' ; + n30 <= 'Z' ; + n31 <= 'Z' ; + n32 <= 'Z' ; + n33 <= 'Z' ; + n34 <= 'Z' ; + n35 <= 'Z' ; + n36 <= 'Z' ; + n37 <= 'Z' ; + n38 <= 'Z' ; + n39 <= 'Z' ; + n40 <= 'Z' ; + n41 <= 'Z' ; + n42 <= 'Z' ; + n43 <= 'Z' ; + n44 <= 'Z' ; + n45 <= 'Z' ; + n46 <= 'Z' ; + n49 <= 'Z' ; + n106 <= '0' ; + n105 <= '1' ; + n50 <= 'Z' ; + n51 <= 'Z' ; + n52 <= 'Z' ; + n53 <= 'Z' ; + n54 <= 'Z' ; + n55 <= 'Z' ; + n56 <= 'Z' ; + n57 <= 'Z' ; + n58 <= 'Z' ; + n59 <= 'Z' ; + n60 <= 'Z' ; + n61 <= 'Z' ; + n62 <= 'Z' ; + n63 <= 'Z' ; + n64 <= 'Z' ; + n65 <= 'Z' ; + n66 <= 'Z' ; + n67 <= 'Z' ; + n68 <= 'Z' ; + n69 <= 'Z' ; + n70 <= 'Z' ; + n71 <= 'Z' ; + n72 <= 'Z' ; + n73 <= 'Z' ; + n74 <= 'Z' ; + n75 <= 'Z' ; + n76 <= 'Z' ; + n77 <= 'Z' ; + n78 <= 'Z' ; + n79 <= 'Z' ; + n80 <= 'Z' ; + n81 <= 'Z' ; + n82 <= 'Z' ; + n83 <= 'Z' ; + n84 <= 'Z' ; + n85 <= 'Z' ; + n86 <= 'Z' ; + n87 <= 'Z' ; + n88 <= 'Z' ; + n89 <= 'Z' ; + n90 <= 'Z' ; + n91 <= 'Z' ; + n92 <= 'Z' ; + n93 <= 'Z' ; + n94 <= 'Z' ; + n95 <= 'Z' ; + n96 <= 'Z' ; + n97 <= 'Z' ; + n98 <= 'Z' ; + n99 <= 'Z' ; + n100 <= 'Z' ; + n101 <= 'Z' ; + n102 <= 'Z' ; + n103 <= 'Z' ; + n104 <= 'Z' ; + n115 <= 'Z' ; + rsl_inst: component serdes1_1rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c, + rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki, + rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>gnd, + rui_tx_pcs_rst_c(2)=>gnd,rui_tx_pcs_rst_c(1)=>gnd,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c, + rdi_pll_lol=>pll_lol,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>gnd, + rui_rx_serdes_rst_c(2)=>gnd,rui_rx_serdes_rst_c(1)=>gnd,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c, + rui_rx_pcs_rst_c(3)=>gnd,rui_rx_pcs_rst_c(2)=>gnd,rui_rx_pcs_rst_c(1)=>gnd, + rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>gnd,rdi_rx_los_low_s(2)=>gnd, + rdi_rx_los_low_s(1)=>gnd,rdi_rx_los_low_s(0)=>rx_los_low_s_c,rdi_rx_cdr_lol_s(3)=>gnd, + rdi_rx_cdr_lol_s(2)=>gnd,rdi_rx_cdr_lol_s(1)=>gnd,rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c, + rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c,rdo_rst_dual_c=>rsl_rst_dual_c, + ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c, + rdo_tx_pcs_rst_c(3)=>n116,rdo_tx_pcs_rst_c(2)=>n117,rdo_tx_pcs_rst_c(1)=>n118, + rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n119, + rdo_rx_serdes_rst_c(2)=>n120,rdo_rx_serdes_rst_c(1)=>n121,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c, + rdo_rx_pcs_rst_c(3)=>n122,rdo_rx_pcs_rst_c(2)=>n123,rdo_rx_pcs_rst_c(1)=>\_Z\, + rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c); + n114 <= '1' ; + n113 <= '0' ; + gnd <= '0' ; + pwr <= '1' ; + n116 <= 'Z' ; + n117 <= 'Z' ; + n118 <= 'Z' ; + n119 <= 'Z' ; + n120 <= 'Z' ; + n121 <= 'Z' ; + n122 <= 'Z' ; + n123 <= 'Z' ; + \_Z\ <= 'Z' ; + +end architecture v1; + diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1_ngd.asd b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1_softlogic.v b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1_softlogic.v new file mode 100644 index 0000000..9181f46 --- /dev/null +++ b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1_softlogic.v @@ -0,0 +1,943 @@ + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2016 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : RSL- Reset Sequence Logic +// File : rsl_core.v +// Title : Top-level file for RSL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : BM +// Mod. Date : October 28, 2013 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : BM +// Mod. Date : November 06, 2013 +// Changes Made : Tx/Rx separation, ready port code exclusion +// ----------------------------------------------------------------------------- +// Version : 1.2 +// Author(s) : BM +// Mod. Date : June 13, 2014 +// Changes Made : Updated Rx PCS reset method +// ----------------------------------------------------------------------------- +// ----------------------------------------------------------------------------- +// Version : 1.3 +// Author(s) : UA +// Mod. Date : Dec 19, 2014 +// Changes Made : Added new parameter fro PCIE +// ----------------------------------------------------------------------------- +// Version : 1.31 +// Author(s) : BM/UM +// Mod. Date : Feb 23, 2016 +// Changes Made : Behavior of rx_rdy output modified. The output rx_rdy +// and the rx_rdy wait counter are reset to zero on +// LOL or LOS. Reverted back the counter value change for PCIE. +// ----------------------------------------------------------------------------- +// Version : 1.4 +// Author(s) : EB +// Mod. Date: : March 21, 2017 +// Changes Made : +// ----------------------------------------------------------------------------- +// Version : 1.5 +// Author(s) : ES +// Mod. Date: : May 8, 2017 +// Changes Made : Implemented common RSL behaviour as proposed by BM. +// ============================================================================= + +`timescale 1ns/10ps + +module serdes1_1rsl_core ( + // ------------ Inputs + // Common + rui_rst, // Active high reset for the RSL module + rui_serdes_rst_dual_c, // SERDES macro reset user command + rui_rst_dual_c, // PCS dual reset user command + rui_rsl_disable, // Active high signal that disables all reset outputs of RSL + // Tx + rui_tx_ref_clk, // Tx reference clock + rui_tx_serdes_rst_c, // Tx SERDES reset user command + rui_tx_pcs_rst_c, // Tx lane reset user command + rdi_pll_lol, // Tx PLL Loss of Lock status input from the SERDES + // Rx + rui_rx_ref_clk, // Rx reference clock + rui_rx_serdes_rst_c, // SERDES Receive channel reset user command + rui_rx_pcs_rst_c, // Rx lane reset user command + rdi_rx_los_low_s, // Receive loss of signal status input from SERDES + rdi_rx_cdr_lol_s, // Receive CDR loss of lock status input from SERDES + + // ------------ Outputs + // Common + rdo_serdes_rst_dual_c, // SERDES macro reset command output + rdo_rst_dual_c, // PCS dual reset command output + // Tx + ruo_tx_rdy, // Tx lane ready status output + rdo_tx_serdes_rst_c, // SERDES Tx reset command output + rdo_tx_pcs_rst_c, // PCS Tx lane reset command output + // Rx + ruo_rx_rdy, // Rx lane ready status output + rdo_rx_serdes_rst_c, // SERDES Rx channel reset command output + rdo_rx_pcs_rst_c // PCS Rx lane reset command output + ); + +// ------------ Module parameters +`ifdef NUM_CHANNELS + parameter pnum_channels = `NUM_CHANNELS; // 1,2,4 +`else + parameter pnum_channels = 1; +`endif + +`ifdef PCIE + parameter pprotocol = "PCIE"; +`else + parameter pprotocol = ""; +`endif + +`ifdef RX_ONLY + parameter pserdes_mode = "RX ONLY"; +`else + `ifdef TX_ONLY + parameter pserdes_mode = "TX ONLY"; + `else + parameter pserdes_mode = "RX AND TX"; + `endif +`endif + +`ifdef PORT_TX_RDY + parameter pport_tx_rdy = "ENABLED"; +`else + parameter pport_tx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_TX_RDY + parameter pwait_tx_rdy = `WAIT_TX_RDY; +`else + parameter pwait_tx_rdy = 3000; +`endif + +`ifdef PORT_RX_RDY + parameter pport_rx_rdy = "ENABLED"; +`else + parameter pport_rx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_RX_RDY + parameter pwait_rx_rdy = `WAIT_RX_RDY; +`else + parameter pwait_rx_rdy = 3000; +`endif + +// ------------ Local parameters + localparam wa_num_cycles = 1024; + localparam dac_num_cycles = 3; + localparam lreset_pwidth = 3; // reset pulse width-1, default=4-1=3 + localparam lwait_b4_trst = 781250; // 5ms wait with worst-case Fmax=156 MHz + localparam lwait_b4_trst_s = 781; // for simulation + localparam lplol_cnt_width = 20; // width for lwait_b4_trst + localparam lwait_after_plol0 = 4; + localparam lwait_b4_rrst = 180224; // total calibration time + localparam lrrst_wait_width = 20; + localparam lwait_after_rrst = 800000; // For CPRI- unused + localparam lwait_b4_rrst_s = 460; // wait cycles provided by design team + localparam lrlol_cnt_width = 19; // width for lwait_b4_rrst + localparam lwait_after_lols = (16384 * dac_num_cycles) + wa_num_cycles; // 16384 cycles * dac_num_cycles + 1024 cycles + localparam lwait_after_lols_s = 150; // wait cycles provided by design team + localparam llols_cnt_width = 18; // lols count width + localparam lrdb_max = 15; // maximum debounce count + localparam ltxr_wait_width = 12; // width of tx ready wait counter + localparam lrxr_wait_width = 12; // width of tx ready wait counter + +// ------------ input ports + input rui_rst; + input rui_serdes_rst_dual_c; + input rui_rst_dual_c; + input rui_rsl_disable; + + input rui_tx_ref_clk; + input rui_tx_serdes_rst_c; + input [3:0] rui_tx_pcs_rst_c; + input rdi_pll_lol; + + input rui_rx_ref_clk; + input [3:0] rui_rx_serdes_rst_c; + input [3:0] rui_rx_pcs_rst_c; + input [3:0] rdi_rx_los_low_s; + input [3:0] rdi_rx_cdr_lol_s; + +// ------------ output ports + output rdo_serdes_rst_dual_c; + output rdo_rst_dual_c; + + output ruo_tx_rdy; + output rdo_tx_serdes_rst_c; + output [3:0] rdo_tx_pcs_rst_c; + + output ruo_rx_rdy; + output [3:0] rdo_rx_serdes_rst_c; + output [3:0] rdo_rx_pcs_rst_c; + +// ------------ Internal registers and wires + // inputs + wire rui_rst; + wire rui_serdes_rst_dual_c; + wire rui_rst_dual_c; + wire rui_rsl_disable; + wire rui_tx_ref_clk; + wire rui_tx_serdes_rst_c; + wire [3:0] rui_tx_pcs_rst_c; + wire rdi_pll_lol; + wire rui_rx_ref_clk; + wire [3:0] rui_rx_serdes_rst_c; + wire [3:0] rui_rx_pcs_rst_c; + wire [3:0] rdi_rx_los_low_s; + wire [3:0] rdi_rx_cdr_lol_s; + + // outputs + wire rdo_serdes_rst_dual_c; + wire rdo_rst_dual_c; + wire ruo_tx_rdy; + wire rdo_tx_serdes_rst_c; + wire [3:0] rdo_tx_pcs_rst_c; + wire ruo_rx_rdy; + wire [3:0] rdo_rx_serdes_rst_c; + wire [3:0] rdo_rx_pcs_rst_c; + + // internal signals + // common + wire rsl_enable; + wire [lplol_cnt_width-1:0] wait_b4_trst; + wire [lrlol_cnt_width-1:0] wait_b4_rrst; + wire [llols_cnt_width-1:0] wait_after_lols; + reg pll_lol_p1; + reg pll_lol_p2; + reg pll_lol_p3; + // ------------ Tx + // rdo_tx_serdes_rst_c + reg [lplol_cnt_width-1:0] plol_cnt; + wire plol_cnt_tc; + + reg [2:0] txs_cnt; + reg txs_rst; + wire txs_cnt_tc; + // rdo_tx_pcs_rst_c + wire plol_fedge; + wire plol_redge; + reg waita_plol0; + reg [2:0] plol0_cnt; + wire plol0_cnt_tc; + reg [2:0] txp_cnt; + reg txp_rst; + wire txp_cnt_tc; + // ruo_tx_rdy + wire dual_or_serd_rst; + wire tx_any_pcs_rst; + wire tx_any_rst; + reg txsr_appd /* synthesis syn_keep=1 */; + reg txdpr_appd; + reg [pnum_channels-1:0] txpr_appd; + reg txr_wt_en; + reg [ltxr_wait_width-1:0] txr_wt_cnt; + wire txr_wt_tc; + reg ruo_tx_rdyr; + + // ------------ Rx + wire comb_rlos; + wire comb_rlol; + //wire rlols; + wire rx_all_well; + + //reg rlols_p1; + //reg rlols_p2; + //reg rlols_p3; + + reg rlol_p1; + reg rlol_p2; + reg rlol_p3; + reg rlos_p1; + reg rlos_p2; + reg rlos_p3; + + //reg [3:0] rdb_cnt; + //wire rdb_cnt_max; + //wire rdb_cnt_zero; + //reg rlols_db; + //reg rlols_db_p1; + + reg [3:0] rlol_db_cnt; + wire rlol_db_cnt_max; + wire rlol_db_cnt_zero; + reg rlol_db; + reg rlol_db_p1; + + reg [3:0] rlos_db_cnt; + wire rlos_db_cnt_max; + wire rlos_db_cnt_zero; + reg rlos_db; + reg rlos_db_p1; + + // rdo_rx_serdes_rst_c + reg [lrlol_cnt_width-1:0] rlol1_cnt; + wire rlol1_cnt_tc; + reg [2:0] rxs_cnt; + reg rxs_rst; + wire rxs_cnt_tc; + reg [lrrst_wait_width-1:0] rrst_cnt; + wire rrst_cnt_tc; + reg rrst_wait; + // rdo_rx_pcs_rst_c + //wire rlols_fedge; + //wire rlols_redge; + wire rlol_fedge; + wire rlol_redge; + wire rlos_fedge; + wire rlos_redge; + + reg wait_calib; + reg waita_rlols0; + reg [llols_cnt_width-1:0] rlols0_cnt; + wire rlols0_cnt_tc; + reg [2:0] rxp_cnt; + reg rxp_rst; + wire rxp_cnt_tc; + + wire rx_any_serd_rst; + reg [llols_cnt_width-1:0] rlolsz_cnt; + wire rlolsz_cnt_tc; + reg [2:0] rxp_cnt2; + reg rxp_rst2; + wire rxp_cnt2_tc; + reg [15:0] data_loop_b_cnt; + reg data_loop_b; + wire data_loop_b_tc; + + // ruo_rx_rdy + reg [pnum_channels-1:0] rxsr_appd; + reg [pnum_channels-1:0] rxpr_appd; + reg rxsdr_appd /* synthesis syn_keep=1 */; + reg rxdpr_appd; + wire rxsdr_or_sr_appd; + wire dual_or_rserd_rst; + wire rx_any_pcs_rst; + wire rx_any_rst; + reg rxr_wt_en; + reg [lrxr_wait_width-1:0] rxr_wt_cnt; + wire rxr_wt_tc; + reg ruo_rx_rdyr; + +// ================================================================== +// Start of code +// ================================================================== + assign rsl_enable = ~rui_rsl_disable; + +// ------------ rdo_serdes_rst_dual_c + assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c; + +// ------------ rdo_rst_dual_c + assign rdo_rst_dual_c = rui_rst_dual_c; + +// ------------ Setting counter values for RSL_SIM_MODE + `ifdef RSL_SIM_MODE + assign wait_b4_trst = lwait_b4_trst_s; + assign wait_b4_rrst = lwait_b4_rrst_s; + assign wait_after_lols = lwait_after_lols_s; + `else + assign wait_b4_trst = lwait_b4_trst; + assign wait_b4_rrst = lwait_b4_rrst; + assign wait_after_lols = lwait_after_lols; + `endif + +// ================================================================== +// Tx +// ================================================================== + generate + if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin + +// ------------ Synchronizing pll_lol to the tx clock + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + pll_lol_p1 <= 1'd0; + pll_lol_p2 <= 1'd0; + pll_lol_p3 <= 1'd0; + end + else begin + pll_lol_p1 <= rdi_pll_lol; + pll_lol_p2 <= pll_lol_p1; + pll_lol_p3 <= pll_lol_p2; + end + end + +// ------------ rdo_tx_serdes_rst_c + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol_cnt <= 'd0; + else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1)) + plol_cnt <= 'd0; + else + plol_cnt <= plol_cnt+1; + end + assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txs_cnt <= 'd0; // tx serdes reset pulse count + txs_rst <= 1'b0; // tx serdes reset + end + else if(plol_cnt_tc==1) + txs_rst <= 1'b1; + else if(txs_cnt_tc==1) begin + txs_cnt <= 'd0; + txs_rst <= 1'b0; + end + else if(txs_rst==1) + txs_cnt <= txs_cnt+1; + end + assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0; + + assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c; + +// ------------ rdo_tx_pcs_rst_c + assign plol_fedge = ~pll_lol_p2 & pll_lol_p3; + assign plol_redge = pll_lol_p2 & ~pll_lol_p3; + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + waita_plol0 <= 1'd0; + else if(plol_fedge==1'b1) + waita_plol0 <= 1'b1; + else if((plol0_cnt_tc==1)||(plol_redge==1)) + waita_plol0 <= 1'd0; + end + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol0_cnt <= 'd0; + else if((pll_lol_p2==1)||(plol0_cnt_tc==1)) + plol0_cnt <= 'd0; + else if(waita_plol0==1'b1) + plol0_cnt <= plol0_cnt+1; + end + assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txp_cnt <= 'd0; // tx serdes reset pulse count + txp_rst <= 1'b0; // tx serdes reset + end + else if(plol0_cnt_tc==1) + txp_rst <= 1'b1; + else if(txp_cnt_tc==1) begin + txp_cnt <= 'd0; + txp_rst <= 1'b0; + end + else if(txp_rst==1) + txp_cnt <= txp_cnt+1; + end + assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0; + + genvar i; + for(i=0;i hdinn(0), serdes0_hdinp => hdinp(0), serdes0_hdoutn => hdoutn(0), @@ -218,7 +218,96 @@ THE_SERDES : entity work.dual_serdes serdes1_pll_refclki => CLK_REF_FULL, serdes1_serdes_pdb => '1' ); +end generate; + +gen_DCU1 : if DUAL = 1 generate +THE_SERDES : entity work.dual_serdes_1 + port map ( + serdes0_hdinn => hdinn(0), + serdes0_hdinp => hdinp(0), + serdes0_hdoutn => hdoutn(0), + serdes0_hdoutp => hdoutp(0), + serdes0_lsm_status_s => lsm_status(0), + serdes0_rsl_disable => '1', + serdes0_rsl_rst => '0', + serdes0_rsl_rx_rdy => rx_ready(0), + serdes0_rsl_tx_rdy => tx_ready(0), + serdes0_rst_dual_c => rst_qd(0), --ON EVERY CHANNEL? + serdes0_rx_cdr_lol_s => rx_cdr_lol(0), + serdes0_rx_cv_err(0) => rx_error(0), + serdes0_rxdata => rx_data(0), + serdes0_rx_disp_err => open, + serdes0_rx_k(0) => rx_k(0), + serdes0_rx_los_low_s => rx_los_low(0), + serdes0_rx_pclk => clk_rx_full(0), + serdes0_rx_pcs_rst_c => rx_pcs_rst(0), + serdes0_rx_pwrup_c => '1', + serdes0_rxrefclk => CLK_INTERNAL_FULL, + serdes0_rx_serdes_rst_c => rx_serdes_rst(0), + serdes0_serdes_rst_dual_c => '0', + serdes0_signal_detect_c => '0', + serdes0_txdata => tx_data(0), + serdes0_tx_disp_sel(0) => '0', + serdes0_tx_force_disp(0) => '0', + serdes0_tx_idle_c => '0', + serdes0_tx_k(0) => tx_k(0), + serdes0_tx_pclk => clk_tx_full(0), + serdes0_tx_pcs_rst_c => tx_pcs_rst(0), + serdes0_tx_pwrup_c => '1', + serdes0_tx_serdes_rst_c => '0', + serdes1_hdinn => hdinn(1), + serdes1_hdinp => hdinp(1), + serdes1_hdoutn => hdoutn(1), + serdes1_hdoutp => hdoutp(1), + serdes1_lsm_status_s => lsm_status(1), + serdes1_rsl_disable => '1', + serdes1_rsl_rst => '0', + serdes1_rsl_rx_rdy => rx_ready(1), + serdes1_rsl_tx_rdy => tx_ready(1), + serdes1_rst_dual_c => rst_qd(1), + serdes1_rx_cdr_lol_s => rx_cdr_lol(1), + serdes1_rx_cv_err(0) => rx_error(1), + serdes1_rxdata => rx_data(1), + serdes1_rx_disp_err => open, + serdes1_rx_k(0) => rx_k(1), + serdes1_rx_los_low_s => rx_los_low(1), + serdes1_rx_pclk => clk_rx_full(1), + serdes1_rx_pcs_rst_c => rx_pcs_rst(1), + serdes1_rx_pwrup_c => '1', + serdes1_rxrefclk => CLK_INTERNAL_FULL, + serdes1_rx_serdes_rst_c => rx_serdes_rst(1), + serdes1_serdes_rst_dual_c => '0', + serdes1_signal_detect_c => '0', + serdes1_txdata => tx_data(1), + serdes1_tx_disp_sel(0) => '0', + serdes1_tx_force_disp(0) => '0', + serdes1_tx_idle_c => '0', + serdes1_tx_k(0) => tx_k(1), + serdes1_tx_pclk => clk_tx_full(1), + serdes1_tx_pcs_rst_c => tx_pcs_rst(1), + serdes1_tx_pwrup_c => '1', + serdes1_tx_serdes_rst_c => '0', + + serdes0_sci_en => reset_n, + serdes0_sci_sel => sci_ch_i(0), + serdes1_sci_addr => sci_addr_i, + serdes1_sci_en_dual => reset_n, + serdes1_sci_en => reset_n, + serdes1_sci_rddata => sci_data_out_i(7 downto 0), + serdes1_sci_rd => sci_read_i, + serdes1_sci_sel_dual => sci_ch_i(4), + serdes1_sci_sel => sci_ch_i(1), + serdes1_sci_wrdata => sci_data_in_i, + serdes1_sci_wrn => sci_write_i, + + serdes0_pll_lol => tx_pll_lol, + + serdes1_cyawstn => '0', + serdes1_pll_refclki => CLK_REF_FULL, + serdes1_serdes_pdb => '1' + ); +end generate; gen_channels : for i in 0 to 1 generate THE_MED_CONTROL : entity work.med_sync_control