From: Michael Boehmer Date: Sat, 26 Mar 2022 21:16:17 +0000 (+0100) Subject: new simple link establishment X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1eba93d592e4d1e23ff2e113ad9cc50002cfb10b;p=trbnet.git new simple link establishment --- diff --git a/media_interfaces/sync/main_rx_reset_RS.vhd b/media_interfaces/sync/main_rx_reset_RS.vhd index ea5a254..5ce172d 100644 --- a/media_interfaces/sync/main_rx_reset_RS.vhd +++ b/media_interfaces/sync/main_rx_reset_RS.vhd @@ -66,6 +66,7 @@ begin RX_SERDES_RST_OUT <= '1'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; rx_sm <= powerup; STATE_OUT <= x"f"; @@ -83,6 +84,7 @@ begin RX_SERDES_RST_OUT <= '0'; -- needed for RX_LOS to be active RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; if( (los_s = '1') ) then -- seems to work cnt <= (others => '0'); else @@ -99,6 +101,7 @@ begin RX_SERDES_RST_OUT <= '1'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; if( cnt(Tshort_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= WAIT_CDR_LOCK; @@ -111,6 +114,7 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; if( cnt(Tcdr_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= TEST_CDR; @@ -123,6 +127,7 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; if ( los_s = '1' ) then rx_sm <= POWERUP; cnt <= (others => '0'); @@ -143,6 +148,7 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; if ( los_s = '1' ) then rx_sm <= POWERUP; cnt <= (others => '0'); @@ -158,6 +164,7 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; if ( los_s = '1' ) then rx_sm <= POWERUP; cnt <= (others => '0'); @@ -173,6 +180,7 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '1'; if ( los_s = '1' ) then rx_sm <= POWERUP; cnt <= (others => '0'); @@ -193,6 +201,7 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; cnt <= (others => '0'); if ( los_s = '1' ) then rx_sm <= POWERUP; @@ -213,6 +222,7 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '1'; + WAP_REQ_OUT <= '0'; cnt <= (others => '0'); if ( los_s = '1' ) then rx_sm <= POWERUP; @@ -227,6 +237,7 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; rx_sm <= POWERUP; cnt <= (others => '0'); @@ -234,7 +245,5 @@ begin end if; end process rx_reset_proc; - - WAP_REQ_OUT <= '1' when ((rx_sm = TEST_RXPCS)) else '0'; end architecture; diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index 21345e3..880c3a5 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -92,8 +92,6 @@ architecture med_sync_control_arch of med_sync_control_RS is signal debug_tx_control_i : std_logic_vector(31 downto 0); signal debug_rx_control_i : std_logic_vector(31 downto 0); - signal link_full_done_qsys : std_logic; - signal link_half_done_qsys : std_logic; signal link_rx_ready_qsys : std_logic; signal link_tx_ready_qsys : std_logic; signal link_status : std_logic_vector(3 downto 0); @@ -103,6 +101,14 @@ architecture med_sync_control_arch of med_sync_control_RS is signal link_rx_null_i : std_logic; signal link_rx_null_qref : std_logic; + ----- + signal link_ready_i : std_logic; + signal link_ready_q : std_logic_vector(1 downto 0); + signal link_alive_i : std_logic; + signal link_alive_q : std_logic; + signal link_dead_i : std_logic; + signal link_dead_q : std_logic; + begin ------------------------------------------------- @@ -111,16 +117,35 @@ begin -- TX_CONTROL and RX_CONTROL reset reset_i <= RESET; - + -- for syncing later - link_tx_ready_i <= LINK_TX_READY_IN; -- usually CLK_REF based + link_tx_ready_i <= LINK_TX_READY_IN; +---------------------------------------------------------------------------------------------- +-- "Link prepared" for action, used to reset certain part on +-- link going active / inactive. +-- Both signals are CLK_REF based. + link_ready_i <= link_rx_ready_i and link_tx_ready_i; + + THE_REF_SHIFT_PROC: process( CLK_REF ) + begin + if( rising_edge(CLK_REF) ) then + link_ready_q <= link_ready_q(0) & link_ready_i; + link_alive_q <= link_alive_i; + link_dead_q <= link_dead_i; + end if; + end process THE_REF_SHIFT_PROC; + + link_alive_i <= link_ready_q(0) and not link_ready_q(1); + link_dead_i <= not link_ready_q(0) and link_ready_q(1); +---------------------------------------------------------------------------------------------- + ------------------------------------------------- -- Reset RX FSM ------------------------------------------------- THE_MAIN_RX_RST: main_rx_reset_RS port map( - CLEAR => CLEAR, --'0', -- DO NOT USE + CLEAR => CLEAR, -- use GSR here CLK_REF => CLK_REF, CDR_LOL_IN => RX_CDR_LOL_IN, CV_IN => RX_CV_IN, @@ -159,7 +184,7 @@ begin port map( CLK_RXI => CLK_RXI, CLK_SYS => CLK_SYS, - RESET => CLEAR, --'0', -- DO NOT USE + RESET => CLEAR, -- use GSR here -- RX_DATA_OUT => media_med2int_i.data, RX_PACKET_NUMBER_OUT => media_med2int_i.packet_num, @@ -176,9 +201,9 @@ begin RX_RST_OUT => RX_RST_OUT, RX_RST_WORD_OUT => RX_RST_WORD_OUT, -- - LINK_RX_READY_IN => link_rx_ready_i, -- internally synced to CLK_RXI - LINK_HALF_DONE_OUT => link_half_done_i, -- CLK_RXI based - LINK_FULL_DONE_OUT => link_full_done_i, -- CLK_RXI based + LINK_TX_READY_IN => LINK_TX_READY_IN, + LINK_RX_READY_IN => link_rx_ready_i, + LINK_ACTIVE_OUT => link_active_i, -- CLK_RXI based LINK_RX_NULL_OUT => link_rx_null_i, -- CLK_RXI based -- DEBUG_OUT => debug_rx_control_i, @@ -201,7 +226,7 @@ begin port map( CLK_TXI => CLK_TXI, CLK_SYS => CLK_SYS, - CLEAR => CLEAR, --'0', -- DO NOT USE + CLEAR => CLEAR, -- use GSR here -- Media Interface TX_DATA_IN => MEDIA_INT2MED.data, TX_PACKET_NUMBER_IN => MEDIA_INT2MED.packet_num, @@ -218,10 +243,8 @@ begin SEND_RST_IN => TX_RST_IN, SEND_RST_WORD_IN => TX_RST_WORD_IN, -- link status signals, internally synced - LINK_TX_READY_IN => link_tx_ready_i, -- internally synced to CLK_TXI - LINK_RX_READY_IN => link_rx_ready_i, -- internally synced to CLK_TXI - LINK_HALF_DONE_IN => link_half_done_i, -- internally synced to CLK_TXI - LINK_FULL_DONE_IN => link_full_done_i, -- internally synced to CLK_TXI + LINK_TX_READY_IN => link_tx_ready_i, + LINK_ACTIVE_IN => link_active_i, LINK_TX_NULL_IN => LINK_TX_NULL_IN, -- debug DEBUG_OUT => debug_tx_control_i, @@ -241,7 +264,7 @@ begin ------------------------------------------------- -- Generate LED signals ------------------------------------------------- - led_ok <= link_full_done_i when rising_edge(CLK_SYS); + led_ok <= link_active_i when rising_edge(CLK_SYS); led_rx <= (media_med2int_i.dataready or led_rx) and not timer(20) when rising_edge(CLK_SYS); led_tx <= (MEDIA_INT2MED.dataready or led_tx or SFP_LOS_IN) and not timer(20) when rising_edge(CLK_SYS); @@ -273,32 +296,26 @@ begin media_med2int_i.stat_op(10) <= led_rx or last_led_rx; -- "LED RX" media_med2int_i.stat_op(9) <= led_ok; -- "LED status" media_med2int_i.stat_op(8 downto 6) <= (others => '0'); - media_med2int_i.stat_op(5) <= link_full_done_qsys; -- tx_allow - media_med2int_i.stat_op(4) <= link_full_done_qsys; -- rx_allow + media_med2int_i.stat_op(5) <= link_active_qsys; -- tx_allow + media_med2int_i.stat_op(4) <= link_active_qsys; -- rx_allow media_med2int_i.stat_op(3 downto 0) <= link_status_qsys; - link_active_i <= link_rx_ready_i and link_tx_ready_i and link_half_done_i and link_full_done_i; - link_status <= x"0" when (link_active_i = '1' ) else x"7"; SYNC_MEDIA_SIGS : entity work.signal_sync generic map( - WIDTH => 9, + WIDTH => 7, DEPTH => 3 ) port map( RESET => '0', CLK0 => CLK_SYS, CLK1 => CLK_SYS, - D_IN(8) => link_active_i, - D_IN(7) => link_full_done_i, - D_IN(6) => link_half_done_i, + D_IN(6) => link_active_i, D_IN(5) => link_tx_ready_i, D_IN(4) => link_rx_ready_i, D_IN(3 downto 0) => link_status, - D_OUT(8) => link_active_qsys, - D_OUT(7) => link_full_done_qsys, - D_OUT(6) => link_half_done_qsys, + D_OUT(6) => link_active_qsys, D_OUT(5) => link_tx_ready_qsys, D_OUT(4) => link_rx_ready_qsys, D_OUT(3 downto 0) => link_status_qsys @@ -323,17 +340,9 @@ begin DEBUG_OUT(31 downto 8) <= (others => '0'); -- these signals will be used outside! DEBUG_OUT(7 downto 4) <= (others => '0'); - DEBUG_OUT(3) <= link_full_done_qsys; - DEBUG_OUT(2) <= link_half_done_qsys; + DEBUG_OUT(3) <= '0'; + DEBUG_OUT(2) <= link_active_qsys; DEBUG_OUT(1) <= link_rx_ready_qsys; DEBUG_OUT(0) <= link_tx_ready_qsys; - --- Some remarks on the SerDes issue: --- - slave ports keep everything in global reset until SFP detects light on receiver (SFP_LOS = 0) --- - master ports take the slave port global reset, if available, otherwise GSR is used --- - the global reset connects to RST_QD_C to keep TX PLL in reset --- - slave ports establish the uplink first, with all checks for link integrity and WAP_ZERO_IN --- - - end architecture; diff --git a/media_interfaces/sync/med_sync_define_RS.vhd b/media_interfaces/sync/med_sync_define_RS.vhd index 8aefe48..16bae71 100644 --- a/media_interfaces/sync/med_sync_define_RS.vhd +++ b/media_interfaces/sync/med_sync_define_RS.vhd @@ -108,9 +108,9 @@ component rx_control_RS is RX_RST_OUT : out std_logic; RX_RST_WORD_OUT : out std_logic_vector(7 downto 0); -- link status signals + LINK_TX_READY_IN : in std_logic; LINK_RX_READY_IN : in std_logic; - LINK_HALF_DONE_OUT : out std_logic; - LINK_FULL_DONE_OUT : out std_logic; + LINK_ACTIVE_OUT : out std_logic; LINK_RX_NULL_OUT : out std_logic; -- debug DEBUG_OUT : out std_logic_vector(31 downto 0); @@ -127,25 +127,23 @@ component tx_control_RS is CLK_SYS : in std_logic; CLEAR : in std_logic; -- Media Interface - TX_DATA_IN : in std_logic_vector(15 downto 0); -- media interface - TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); -- media interface - TX_WRITE_IN : in std_logic; -- media interface - TX_READ_OUT : out std_logic; -- media interface + TX_DATA_IN : in std_logic_vector(15 downto 0); + TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); + TX_WRITE_IN : in std_logic; + TX_READ_OUT : out std_logic; -- SerDes data stream - TX_DATA_OUT : out std_logic_vector(7 downto 0); -- to TX SerDes - TX_K_OUT : out std_logic; -- to TX SerDes + TX_DATA_OUT : out std_logic_vector(7 downto 0); + TX_K_OUT : out std_logic; -- synchronous signals - WORD_SYNC_IN : in std_logic; -- byte/word sync + WORD_SYNC_IN : in std_logic; WORD_SYNC_OUT : out std_logic; SEND_DLM_IN : in std_logic; SEND_DLM_WORD_IN : in std_logic_vector(7 downto 0); SEND_RST_IN : in std_logic; SEND_RST_WORD_IN : in std_logic_vector(7 downto 0); -- link status signals, internally synced - LINK_TX_READY_IN : in std_logic; -- local ref clock - LINK_RX_READY_IN : in std_logic; -- local ref clock - LINK_HALF_DONE_IN : in std_logic; -- recovered RX clock - LINK_FULL_DONE_IN : in std_logic; -- recovered RX clock + LINK_TX_READY_IN : in std_logic; + LINK_ACTIVE_IN : in std_logic; LINK_TX_NULL_IN : in std_logic; -- debug DEBUG_OUT : out std_logic_vector(31 downto 0); diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd index 7c0dd8d..4852d46 100644 --- a/media_interfaces/sync/rx_control_RS.vhd +++ b/media_interfaces/sync/rx_control_RS.vhd @@ -26,9 +26,9 @@ entity rx_control_RS is RX_RST_OUT : out std_logic; RX_RST_WORD_OUT : out std_logic_vector(7 downto 0); -- link status signals - LINK_RX_READY_IN : in std_logic; -- used for synchronous reset - LINK_HALF_DONE_OUT : out std_logic; - LINK_FULL_DONE_OUT : out std_logic; + LINK_TX_READY_IN : in std_logic; + LINK_RX_READY_IN : in std_logic; + LINK_ACTIVE_OUT : out std_logic; LINK_RX_NULL_OUT : out std_logic; -- link received K_NULL -- debug DEBUG_OUT : out std_logic_vector(31 downto 0); @@ -71,18 +71,16 @@ architecture rx_control_arch of rx_control_RS is signal sync_k_i : std_logic; -- denotes a K_IDLE detected signal link_rx_ready_qrx : std_logic; - signal link_full_done_qrx : std_logic; - signal link_full_done_qsys : std_logic; + signal link_tx_ready_qrx : std_logic; signal ce_idle0_ctr : std_logic; signal rst_idle0_ctr : std_logic; - signal ctr_idle0 : unsigned(4 downto 0); - signal idle0_detected : std_logic; -- link_half_done - signal ce_idle1_ctr : std_logic; - signal rst_idle1_ctr : std_logic; - signal ctr_idle1 : unsigned(4 downto 0); - signal idle1_detected : std_logic; -- link_full_done - signal rst_link_state : std_logic; + signal ctr_idle0 : unsigned(8 downto 0); + signal idle0_detected : std_logic; + + signal link_active_i : std_logic; + signal link_active_qrx : std_logic; + signal link_active_qsys : std_logic; -- attribute syn_hier : string; -- attribute syn_hier of rx_control_arch : architecture is "hard"; @@ -91,10 +89,10 @@ architecture rx_control_arch of rx_control_RS is begin - -- Syncing things + -- Syncing things (CLK_RXI) SYNC_RXI: signal_sync generic map( - WIDTH => 1, + WIDTH => 3, DEPTH => 3 ) port map( @@ -102,10 +100,14 @@ begin CLK0 => CLK_RXI, CLK1 => CLK_RXI, D_IN(0) => LINK_RX_READY_IN, - D_OUT(0) => link_rx_ready_qrx + D_IN(1) => LINK_TX_READY_IN, + D_IN(2) => link_active_i, + D_OUT(0) => link_rx_ready_qrx, + D_OUT(1) => link_tx_ready_qrx, + D_OUT(2) => link_active_qrx ); - -- Syncing things + -- Syncing things (CLK_SYS) SYNC_SYS: signal_sync generic map( WIDTH => 1, @@ -115,8 +117,8 @@ begin RESET => '0', CLK0 => CLK_SYS, CLK1 => CLK_SYS, - D_IN(0) => idle1_detected, - D_OUT(0) => link_full_done_qsys + D_IN(0) => link_active_i, + D_OUT(0) => link_active_qsys ); ---------------------------------------------------------------------- @@ -133,7 +135,7 @@ begin process begin wait until rising_edge(CLK_SYS); - if ( link_full_done_qsys = '0' ) then + if ( link_active_qsys = '0' ) then rx_packet_num <= "100"; elsif( buf_rx_write_out = '1' ) then if rx_packet_num = "100" then @@ -164,7 +166,7 @@ begin ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty; - ct_fifo_reset <= not idle1_detected; + ct_fifo_reset <= not link_active_qrx; ---------------------------------------------------------------------- -- Read incoming data @@ -176,10 +178,7 @@ begin rx_rst_i <= '0'; sync_k_i <= '0'; ce_idle0_ctr <= '0'; - ce_idle1_ctr <= '0'; rst_idle0_ctr <= '0'; - rst_idle1_ctr <= '0'; - rst_link_state <= '0'; case rx_state is when SLEEP => @@ -187,9 +186,6 @@ begin rx_state_bits <= x"1"; rx_data(7 downto 0) <= reg_rx_data_in; rst_idle0_ctr <= '1'; - rst_idle1_ctr <= '1'; - rst_link_state <= '1'; --- if( (reg_rx_k_in = '1') and (reg_rx_data_in = K_IDLE) ) then if( (reg_rx_k_in = '1') and (reg_rx_data_in = K_IDLE) and (link_rx_ready_qrx = '1') ) then rx_state <= WAIT_1; sync_k_i <= '1'; @@ -230,17 +226,9 @@ begin next_sop <= '1'; case reg_rx_data_in is when D_IDLE0 => - -- first link establishment phase ce_idle0_ctr <= '1'; - rst_idle1_ctr <= '1'; - when D_IDLE1 => - -- second link establishment phase - ce_idle1_ctr <= '1'; - rst_idle0_ctr <= '1'; when others => - -- all other cases - rst_idle0_ctr <= '1'; - rst_idle1_ctr <= '1'; + rst_idle0_ctr <= '1'; -- DANGEROUS, inhibits usage of other idles end case; when GET_DATA => @@ -278,6 +266,7 @@ begin end case; -- BUG: master ports don't reset correctly + -- might need some MASTER/SLAVE stuff if( (RESET = '1') or (link_rx_ready_qrx = '0') ) then rx_state <= SLEEP; rx_dlm_word_i <= x"00"; @@ -295,46 +284,16 @@ begin if( rising_edge(CLK_RXI) ) then if ( rst_idle0_ctr = '1' ) then ctr_idle0 <= (others => '0'); - elsif( ce_idle0_ctr = '1' ) then + elsif( (ce_idle0_ctr = '1') and (idle0_detected = '0') ) then ctr_idle0 <= ctr_idle0 + 1 ; end if; end if; end process THE_CTR_IDLE0_PROC; - THE_CTR_IDLE1_PROC: process( CLK_RXI ) - begin - if( rising_edge(CLK_RXI) ) then - if ( rst_idle1_ctr = '1' ) then - ctr_idle1 <= (others => '0'); - elsif( ce_idle1_ctr = '1' ) then - ctr_idle1 <= ctr_idle1 + 1 ; - end if; - end if; - end process THE_CTR_IDLE1_PROC; + idle0_detected <= ctr_idle0(ctr_idle0'left); + + link_active_i <= link_rx_ready_qrx and link_tx_ready_qrx and idle0_detected; --- IDLE detection for link establishment - THE_IDLE0_DETECTED_PROC: process( CLK_RXI ) - begin - if( rising_edge(CLK_RXI) ) then - if ( rst_link_state = '1' ) then - idle0_detected <= '0'; - elsif ( (ctr_idle0(ctr_idle0'left) = '1') and (ce_idle0_ctr = '1') ) then - idle0_detected <= '1'; - end if; - end if; - end process THE_IDLE0_DETECTED_PROC; - - THE_IDLE1_DETECTED_PROC: process( CLK_RXI ) - begin - if( rising_edge(CLK_RXI) ) then - if ( rst_link_state = '1' ) then - idle1_detected <= '0'; - elsif ( (ctr_idle1(ctr_idle1'left) = '1') and (ce_idle1_ctr = '1') ) then - idle1_detected <= '1'; - end if; - end if; - end process THE_IDLE1_DETECTED_PROC; - ---------------------------------------------------------------------- -- Signals out ---------------------------------------------------------------------- @@ -344,10 +303,8 @@ begin RX_DLM_WORD_OUT <= rx_dlm_word_i when rising_edge(CLK_RXI); RX_RST_OUT <= rx_rst_i when rising_edge(CLK_RXI); RX_RST_WORD_OUT <= rx_rst_word_i when rising_edge(CLK_RXI); - - LINK_HALF_DONE_OUT <= idle0_detected; - LINK_FULL_DONE_OUT <= idle1_detected; - LINK_RX_NULL_OUT <= rst_link_state; + + LINK_ACTIVE_OUT <= link_active_qrx; ---------------------------------------------------------------------- -- Debug and Status diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index f553dfa..0b8d056 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -4,11 +4,8 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; ---use work.trb_net_components.all; use work.med_sync_define_RS.all; --- BUG: must be kept in reset while LINK_TX_READY_IN = '0' ! - entity tx_control_RS is generic( IS_MODE : integer := c_IS_UNUSED @@ -34,9 +31,7 @@ entity tx_control_RS is SEND_RST_WORD_IN : in std_logic_vector(7 downto 0); -- link status signals, internally synced LINK_TX_READY_IN : in std_logic; -- local ref clock - LINK_RX_READY_IN : in std_logic; -- local ref clock - LINK_HALF_DONE_IN : in std_logic; -- recovered RX clock - LINK_FULL_DONE_IN : in std_logic; -- recovered RX clock + LINK_ACTIVE_IN : in std_logic; -- recovered RX clock LINK_TX_NULL_IN : in std_logic; -- debug DEBUG_OUT : out std_logic_vector(31 downto 0); @@ -88,14 +83,9 @@ architecture arch of tx_control_RS is signal save_eop : std_logic; signal load_sop : std_logic; signal load_eop : std_logic; - signal send_steady_idle_int : std_logic; signal word_sync_i : std_logic; signal link_tx_ready_qtx : std_logic; - signal link_rx_ready_qtx : std_logic; - signal link_half_done_qtx : std_logic; - signal link_full_done_qtx : std_logic; - signal link_active_int : std_logic; signal link_active_qtx : std_logic; signal link_active_qsys : std_logic; signal link_tx_null_qtx : std_logic; @@ -108,7 +98,7 @@ begin -- Sync SYNC_STATUS_SIGS : entity work.signal_sync generic map( - WIDTH => 5, + WIDTH => 3, DEPTH => 3 ) port map( @@ -116,30 +106,13 @@ begin CLK0 => CLK_TXI, CLK1 => CLK_TXI, D_IN(0) => LINK_TX_READY_IN, - D_IN(1) => LINK_RX_READY_IN, - D_IN(2) => LINK_HALF_DONE_IN, - D_IN(3) => LINK_FULL_DONE_IN, - D_IN(4) => LINK_TX_NULL_IN, + D_IN(1) => LINK_ACTIVE_IN, + D_IN(2) => LINK_TX_NULL_IN, D_OUT(0) => link_tx_ready_qtx, - D_OUT(1) => link_rx_ready_qtx, - D_OUT(2) => link_half_done_qtx, - D_OUT(3) => link_full_done_qtx, - D_OUT(4) => link_tx_null_qtx + D_OUT(1) => link_active_qtx, + D_OUT(2) => link_tx_null_qtx ); - -- Payload is only allowed on fully active links - link_active_int <= link_tx_ready_qtx and link_rx_ready_qtx and - link_half_done_qtx and link_full_done_qtx; - - link_active_qtx <= link_active_int when rising_edge(CLK_TXI); - - -- if set send IDLE1, else IDLE0 - send_steady_idle_int <= link_tx_ready_qtx and link_rx_ready_qtx and - link_half_done_qtx when (IS_MODE = c_IS_MASTER) else - link_tx_ready_qtx and link_rx_ready_qtx and - link_half_done_qtx and link_full_done_qtx when (IS_MODE = c_IS_SLAVE) else - '0'; - SYNC_SYSCLK : entity work.signal_sync generic map( WIDTH => 1, @@ -149,7 +122,7 @@ begin RESET => '0', CLK0 => CLK_SYS, CLK1 => CLK_SYS, - D_IN(0) => link_active_int, + D_IN(0) => LINK_ACTIVE_IN, D_OUT(0) => link_active_qsys ); @@ -180,7 +153,7 @@ begin end if; end process; - ct_fifo_reset <= not link_active_qtx; + ct_fifo_reset <= not link_active_qtx; -- correct clock domain? TX_READ_OUT <= buf_tx_read_out; ct_fifo_write <= buf_tx_read_out and TX_WRITE_IN; @@ -295,11 +268,7 @@ begin when SEND_IDLE_H => word_sync_i <= '1'; - if( send_steady_idle_int = '1' ) then - tx_data_i <= D_IDLE1; - else - tx_data_i <= D_IDLE0; - end if; + tx_data_i <= D_IDLE0; when SEND_DATA_L => tx_data_i <= ram_dout(7 downto 0); @@ -402,9 +371,7 @@ begin DEBUG_OUT(31) <= debug_sending_dlm when rising_edge(CLK_TXI); DEBUG_OUT(30) <= send_dlm_i; DEBUG_OUT(29) <= debug_sending_rst when rising_edge(CLK_TXI); - DEBUG_OUT(28 downto 6) <= (others => '0'); - DEBUG_OUT(5) <= send_steady_idle_int when rising_edge(CLK_TXI); - DEBUG_OUT(4) <= '0'; --toggle_idle when rising_edge(CLK_TXI); + DEBUG_OUT(28 downto 4) <= (others => '0'); DEBUG_OUT(3 downto 0) <= state_bits when rising_edge(CLK_TXI); THE_STAT_PROC: process( CLK_SYS )