From: Ingo Froehlich <ingo@nomail.fake>
Date: Wed, 30 Aug 2017 14:49:26 +0000 (+0200)
Subject: burst option for flash, IF
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1f3a847f343a862ca8e9a02acb258b601604b5ca;p=vhdlbasics.git

burst option for flash, IF
---

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index f59260f..7585f6d 100644
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -18,7 +18,8 @@
 --         Bit 1 : Master start (starts unpacking = booting)
 --  0x5D : Bits 0/1: Flash memory read buswidth:
 --         00 : 8 Bit, 01 : 16 Bit, 11 : 32 Bit (if available)
---         Bit 8: 0: Little Endian; 1: Big Endian
+--         Bit 4: 0: Little Endian; 1: Big Endian
+--         Bit 11-8 : Burst counter
 --  0x5E-5F : Debug registers
 
 
@@ -112,7 +113,7 @@ architecture arch of generic_flash_ctrl is
   signal enable_cfg_flash : std_logic;
   signal testreg : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
   signal memreg  : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
-  
+  signal burst_counter : std_logic_vector(3 downto 0);
 
   signal out_delay : std_logic_vector(2 downto 0);
   
@@ -192,7 +193,9 @@ PROC_SELECTOR : process begin
   
   ram_write_i <= '0';
   ram_data_i <= x"00";
-  spi_ram_addr_i <= x"0";
+  if (burst_counter = "0000") then
+    spi_ram_addr_i <= x"0";
+  end if;
   spi_flash_go <= '0';
 
   if (clean_master_start_reg = '1') then
@@ -242,7 +245,9 @@ PROC_SELECTOR : process begin
       -- at least 16 bit burst
       spi_ram_addr_i <= std_logic_vector(unsigned(spi_ram_addr_i)+1); -- prepare nibble2
     end if;
-    out_delay <= "010";
+    if (SPI_BUSY_IN = '0') then
+      out_delay <= "010";
+    end if;
   elsif (out_delay = "010") then
     reg_LOC_READ_OUT  <= '0';    
     if (memreg(0) = '0') then
@@ -255,7 +260,7 @@ PROC_SELECTOR : process begin
         -- at least 24 bit burst
         spi_ram_addr_i <= std_logic_vector(unsigned(spi_ram_addr_i)+1); --prepare nibble3
       end if;
-      if (memreg(8) = '1') then
+      if (memreg(4) = '1') then
         reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-8) <= ram_data_o;
       else
         reg_SPI_DATA_OUT(15 downto 0) <= x"00" & ram_data_o; -- write nibble1
@@ -264,7 +269,7 @@ PROC_SELECTOR : process begin
     end if;
   elsif (out_delay = "011") then
     reg_LOC_READ_OUT  <= '0';
-    if (memreg(8) = '1') then
+    if (memreg(4) = '1') then
       reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-16) <= reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-8) & ram_data_o;
     else
       reg_SPI_DATA_OUT(15 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(7 downto 0);
@@ -282,7 +287,7 @@ PROC_SELECTOR : process begin
   elsif (out_delay = "100" and DATA_BUS_WIDTH > 16) then
     reg_LOC_READ_OUT  <= '0';
     reg_SPI_READY_OUT <= '0';
-    if (memreg(8) = '1') then
+    if (memreg(4) = '1') then
       reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-24) <= reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-16) & ram_data_o;
     else
       reg_SPI_DATA_OUT(23 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(15 downto 0);
@@ -291,7 +296,7 @@ PROC_SELECTOR : process begin
   elsif (out_delay = "101" and DATA_BUS_WIDTH > 24) then
     reg_LOC_READ_OUT  <= '0';
     reg_SPI_READY_OUT <= '1';
-    if (memreg(8) = '1') then
+    if (memreg(4) = '1') then
       reg_SPI_DATA_OUT(31 downto 0) <= reg_SPI_DATA_OUT(31 downto 8) & ram_data_o;
     else
       reg_SPI_DATA_OUT(31 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(23 downto 0);
@@ -300,13 +305,22 @@ PROC_SELECTOR : process begin
   else
     out_delay <= "000";
   end if;
+
+  if (out_delay = "000" and burst_counter /= "0000" and SPI_BUSY_IN = '0' and reg_SPI_READY_OUT = '0') then
+    out_delay <= "001";
+    reg_LOC_READ_OUT  <= '0';
+    reg_SPI_READY_OUT <= '0';
+    spi_ram_addr_i <= std_logic_vector(unsigned(spi_ram_addr_i)+1);
+    burst_counter <= std_logic_vector(unsigned(burst_counter)-1);
+  end if;
   
   if (SPI_READ_IN = '1') then    
-    if (SPI_ADDR_IN(7 downto 4) = x"4") then
+    if (SPI_ADDR_IN(7 downto 4) = x"4" and burst_counter = "0000") then
       out_delay <= "001";
       reg_LOC_READ_OUT  <= '0';
       reg_SPI_READY_OUT <= '0';
       spi_ram_addr_i <= SPI_ADDR_IN(3 downto 0); -- prepare nibble1
+      burst_counter <= memreg(11 downto 8);
     elsif (SPI_ADDR_IN(7 downto 0) = x"5C") then
       reg_LOC_READ_OUT  <= '0';
       reg_SPI_READY_OUT <= '1';
@@ -315,6 +329,7 @@ PROC_SELECTOR : process begin
       reg_LOC_READ_OUT  <= '0';
       reg_SPI_READY_OUT <= '1';
       reg_SPI_DATA_OUT  <= memreg;
+      reg_SPI_DATA_OUT(11 downto 8) <= burst_counter;
       -- reg_SPI_DATA_OUT(15 downto 0) <= auto_dbg & "00" & master_flash_page;
     elsif (SPI_ADDR_IN(7 downto 0) = x"5e") then
       reg_LOC_READ_OUT  <= '0';