From: Jan Michel Date: Fri, 24 Jun 2016 09:31:23 +0000 (+0200) Subject: ADC AddOn: changes to clock tree, baseline reset value writeable X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=20720ebe65be3906d9f22daa7451bad7ba6034d3;p=trb3.git ADC AddOn: changes to clock tree, baseline reset value writeable --- diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd index 3a1d16b..9835c0a 100644 --- a/ADC/source/adc_ad9219.vhd +++ b/ADC/source/adc_ad9219.vhd @@ -63,12 +63,12 @@ signal lock : std_logic_vector(1 downto 0); begin - THE_ADC_REF : entity work.pll_in200_out40 - port map( - CLK => CLK_ADCRAW, - CLKOP => ADCCLK_OUT, - LOCK => lock(0) - ); +-- THE_ADC_REF : entity work.pll_in240_out40 +-- port map( +-- CLK => CLK_ADCRAW, +-- CLKOP => ADCCLK_OUT, +-- LOCK => lock(0) +-- ); THE_ADC_PLL_0 : entity work.pll_adc10bit port map( diff --git a/ADC/source/adc_handler.vhd b/ADC/source/adc_handler.vhd index f2dace2..2016c07 100644 --- a/ADC/source/adc_handler.vhd +++ b/ADC/source/adc_handler.vhd @@ -11,7 +11,8 @@ entity adc_handler is port( CLK : in std_logic; CLK_ADCRAW : in std_logic; - + CLK_RAW_LEFT : in std_logic; + CLK_RAW_RIGHT : in std_logic; --ADC ADCCLK_OUT : out std_logic; ADC_DATA : in std_logic_vector((DEVICES_1+DEVICES_2)*(CHANNELS+1)-1 downto 0); @@ -115,7 +116,7 @@ THE_ADC_LEFT : entity work.adc_ad9219 ) port map( CLK => CLK, - CLK_ADCRAW => CLK_ADCRAW, + CLK_ADCRAW => CLK_RAW_LEFT, RESTART_IN => adc_restart, ADCCLK_OUT => ADCCLK_OUT, --FCO is another channel for each ADC @@ -154,7 +155,7 @@ THE_ADC_RIGHT : entity work.adc_ad9219 ) port map( CLK => CLK, - CLK_ADCRAW => CLK_ADCRAW, + CLK_ADCRAW => CLK_RAW_RIGHT, RESTART_IN => adc_restart, ADCCLK_OUT => open, --FCO is another channel for each ADC @@ -266,7 +267,9 @@ PROC_BUS : process begin BUS_TX.data(31) <= config.check_word_enable; when x"1a" => BUS_TX.data(31 downto 0) <= config.channel_disable(31 downto 0); when x"1b" => BUS_TX.data(15 downto 0) <= config.channel_disable(47 downto 32); - when x"1c" => BUS_TX.data(1 downto 0) <= std_logic_vector(to_unsigned(config.processing_mode,2)); + when x"1c" => BUS_TX.data(1 downto 0) <= std_logic_vector(to_unsigned(config.processing_mode,2)); + when x"1d" => BUS_TX.data <= (others => '0'); + when x"1e" => BUS_TX.data <= std_logic_vector(config.baseline_fix_value); when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; elsif BUS_RX.addr >= x"0020" and BUS_RX.addr <= x"002f" then @@ -306,7 +309,7 @@ PROC_BUS : process begin when x"10" => config.buffer_depth <= unsigned(BUS_RX.data(10 downto 0)); when x"11" => config.samples_after <= unsigned(BUS_RX.data(10 downto 0)); when x"12" => config.block_count <= unsigned(BUS_RX.data( 1 downto 0)); - when x"13" => config.trigger_threshold <= unsigned(BUS_RX.data(17 downto 0)); + when x"13" => config.trigger_threshold <= signed(BUS_RX.data(17 downto 0)); when x"14" => config.readout_threshold <= unsigned(BUS_RX.data(17 downto 0)); when x"15" => config.presum <= unsigned(BUS_RX.data( 7 downto 0)); when x"16" => config.averaging <= unsigned(BUS_RX.data( 3 downto 0)); @@ -318,6 +321,7 @@ PROC_BUS : process begin when x"1a" => config.channel_disable(31 downto 0) <= BUS_RX.data(31 downto 0); when x"1b" => config.channel_disable(47 downto 32) <= BUS_RX.data(15 downto 0); when x"1c" => config.processing_mode <= to_integer(unsigned(BUS_RX.data(1 downto 0))); + when x"1e" => config.baseline_fix_value <= unsigned(BUS_RX.data); when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; elsif BUS_RX.addr >= x"0020" and BUS_RX.addr <= x"002f" then @@ -358,8 +362,13 @@ proc_baseline_reset_value : process begin baseline_reset_value(2) <= baseline_reset_value(3); baseline_reset_value(1) <= baseline_reset_value(2)(23 downto 0) * resize(config.presum+1,8); baseline_reset_value(0) <= baseline_reset_value(1); + + if config.baseline_fix_value(30) = '0' then + config.baseline_reset_value <= baseline_reset_value(0); + else + config.baseline_reset_value <= config.baseline_fix_value(31) & '0' & config.baseline_fix_value(29 downto 0); + end if; end process; - config.baseline_reset_value <= baseline_reset_value(0); end architecture; diff --git a/ADC/source/adc_package.vhd b/ADC/source/adc_package.vhd index 16047e4..e8b3f03 100644 --- a/ADC/source/adc_package.vhd +++ b/ADC/source/adc_package.vhd @@ -29,14 +29,15 @@ type cfg_t is record buffer_depth : unsigned(10 downto 0); samples_after : unsigned(10 downto 0); block_count : unsigned( 1 downto 0); - trigger_threshold : unsigned(17 downto 0); - readout_threshold : unsigned(17 downto 0); + trigger_threshold : signed (17 downto 0); + readout_threshold : signed (17 downto 0); presum : unsigned( 7 downto 0); averaging : unsigned( 3 downto 0); trigger_enable : std_logic_vector(47 downto 0); channel_disable : std_logic_vector(47 downto 0); baseline_always_on: std_logic; baseline_reset_value : unsigned(31 downto 0); + baseline_fix_value : unsigned(31 downto 0); block_avg : unsigned_array_8(0 to 3); block_sums : unsigned_array_8(0 to 3); block_scale : unsigned_array_8(0 to 3); diff --git a/ADC/source/adc_processor.vhd b/ADC/source/adc_processor.vhd index 00f1665..5f408e5 100644 --- a/ADC/source/adc_processor.vhd +++ b/ADC/source/adc_processor.vhd @@ -358,8 +358,8 @@ end generate; gen_baselines : for i in 0 to CHANNELS-1 generate proc_baseline_calc : process begin wait until rising_edge(CLK); - if baseline_reset = '1' then - baseline_averages(i) <= CONF.baseline_reset_value; + if baseline_reset = '1' or CONF.baseline_reset_value(31) = '1' then + baseline_averages(i) <= "00" & CONF.baseline_reset_value(29 downto 0); elsif reg2_ram_remove = '1' and (reg_ram_data_out(i)(17) = '0' or CONF.baseline_always_on = '1') then baseline_averages(i) <= baseline_averages(i) + resize(reg_ram_data_out(i)(15 downto 0),32) @@ -380,8 +380,8 @@ gen_triggers : for i in 0 to CHANNELS-1 generate proc_trigger : process begin wait until rising_edge(CLK); if ram_write = '1' then - if (ram_data_in(i)(15 downto 0) > baseline(i) + CONF.trigger_threshold(15 downto 0) and CONF.trigger_threshold(16) = '0') - or (ram_data_in(i)(15 downto 0) < baseline(i) + CONF.trigger_threshold(15 downto 0) and CONF.trigger_threshold(16) = '1') then + if (ram_data_in(i)(15 downto 0) > unsigned(signed(baseline(i)) + CONF.trigger_threshold(15 downto 0)) and CONF.trigger_threshold(16) = '0') + or (ram_data_in(i)(15 downto 0) < unsigned(signed(baseline(i)) + CONF.trigger_threshold(15 downto 0)) and CONF.trigger_threshold(16) = '1') then trigger_gen(i) <= '1'; else trigger_gen(i) <= '0'; @@ -411,8 +411,8 @@ gen_rdo_thresh : for i in 0 to CHANNELS-1 generate readout_flag(i) <= '0'; end if; - if (ram_data_in(i)(15 downto 0) > baseline(i) + CONF.readout_threshold(15 downto 0) and CONF.readout_threshold(16) = '0') - or (ram_data_in(i)(15 downto 0) < baseline(i) + CONF.readout_threshold(15 downto 0) and CONF.readout_threshold(16) = '1') then + if (ram_data_in(i)(15 downto 0) > unsigned(signed(baseline(i)) + CONF.readout_threshold(15 downto 0)) and CONF.readout_threshold(16) = '0') + or (ram_data_in(i)(15 downto 0) < unsigned(signed(baseline(i)) + CONF.readout_threshold(15 downto 0)) and CONF.readout_threshold(16) = '1') then reset_threshold_counter(i) <= '1'; else reset_threshold_counter(i) <= '0'; diff --git a/base/cores/pll_adc10bit.ipx b/base/cores/pll_adc10bit.ipx index 8edb7d3..b7f1eb3 100644 --- a/base/cores/pll_adc10bit.ipx +++ b/base/cores/pll_adc10bit.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/base/cores/pll_adc10bit.lpc b/base/cores/pll_adc10bit.lpc index 50d3ca6..0da0993 100644 --- a/base/cores/pll_adc10bit.lpc +++ b/base/cores/pll_adc10bit.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=PLL -CoreRevision=5.3 +CoreRevision=5.8 ModuleName=pll_adc10bit SourceFormat=VHDL ParameterFileVersion=1.0 -Date=02/27/2014 -Time=18:02:53 +Date=06/10/2016 +Time=12:37:47 [Parameters] Verilog=0 @@ -29,8 +29,8 @@ Order=None IO=0 Type=ehxpllb mode=normal -IFrq=200 -Div=1 +IFrq=240 +Div=6 ClkOPBp=0 Post=4 U_OFrq=200 @@ -39,7 +39,7 @@ OFrq=200.000000 DutyTrimP=Rising DelayMultP=0 fb_mode=Internal -Mult=1 +Mult=5 Phase=0.0 Duty=8 DelayMultS=0 @@ -57,10 +57,13 @@ ClkRst=0 PCDR=0 FINDELA=0 VcoRate= -Bandwidth=2.970786 +Bandwidth=1.753251 ;DelayControl=No EnCLKOS=0 ClkOSBp=0 EnCLKOK=0 ClkOKBp=0 enClkOK2=0 + +[Command] +cmd_line= -w -n pll_adc10bit -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -noclkok -norst -noclkok2 -bw diff --git a/base/cores/pll_adc10bit.vhd b/base/cores/pll_adc10bit.vhd index ccd12a0..c8c71b8 100644 --- a/base/cores/pll_adc10bit.vhd +++ b/base/cores/pll_adc10bit.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) --- Module Version: 5.3 ---/d/jspc29/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n pll_adc10bit -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -noclkok -norst -noclkok2 -bw -e +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502 +-- Module Version: 5.7 +--/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_adc10bit -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -noclkok -norst -noclkok2 -bw --- Thu Feb 27 18:02:53 2014 +-- Fri Jun 10 12:37:47 2016 library IEEE; use IEEE.std_logic_1164.all; @@ -16,8 +16,6 @@ entity pll_adc10bit is CLK: in std_logic; CLKOP: out std_logic; LOCK: out std_logic); - attribute dont_touch : boolean; - attribute dont_touch of pll_adc10bit : entity is true; end pll_adc10bit; architecture Structure of pll_adc10bit is @@ -55,10 +53,8 @@ architecture Structure of pll_adc10bit is attribute FREQUENCY_PIN_CLKOP : string; attribute FREQUENCY_PIN_CLKI : string; attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "200.000000"; - attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "240.000000"; attribute syn_keep : boolean; - attribute syn_noprune : boolean; - attribute syn_noprune of Structure : architecture is true; attribute NGD_DRC_MASK : integer; attribute NGD_DRC_MASK of Structure : architecture is 1; @@ -74,8 +70,8 @@ begin CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", - CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 1, CLKI_DIV=> 1, - FIN=> "200.000000") + CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 5, CLKI_DIV=> 6, + FIN=> "240.000000") port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>scuba_vlo, RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,