From: Ludwig Maier Date: Fri, 31 Jan 2014 19:03:17 +0000 (+0100) Subject: new readout modes X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2093de16ffbcf8840807ed86a632177201c15a1e;p=trb3.git new readout modes --- diff --git a/nxyter/source/nx_event_buffer.vhd b/nxyter/source/nx_event_buffer.vhd index c26e101..b61f679 100644 --- a/nxyter/source/nx_event_buffer.vhd +++ b/nxyter/source/nx_event_buffer.vhd @@ -8,7 +8,7 @@ use work.trb3_components.all; entity nx_event_buffer is generic ( - BOARD_ID : std_logic_vector(15 downto 0) := x"ffff" + BOARD_ID : std_logic_vector(1 downto 0) := "11" ); port ( CLK_IN : in std_logic; diff --git a/nxyter/source/nx_i2c_master.vhd b/nxyter/source/nx_i2c_master.vhd index 777a700..0fd659c 100644 --- a/nxyter/source/nx_i2c_master.vhd +++ b/nxyter/source/nx_i2c_master.vhd @@ -21,6 +21,7 @@ entity nx_i2c_master is INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0); COMMAND_BUSY_OUT : out std_logic; I2C_DATA_OUT : out std_logic_vector(31 downto 0); + I2C_DATA_BYTES_OUT : out std_logic_vector(31 downto 0); I2C_LOCK_IN : in std_logic; -- Slave bus @@ -111,23 +112,24 @@ architecture Behavioral of nx_i2c_master is signal STATE, NEXT_STATE : STATES; -- TRBNet Slave Bus - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - - signal i2c_chipid : std_logic_vector(6 downto 0); - signal i2c_rw_bit : std_logic; - signal i2c_num_bytes : unsigned(2 downto 0); - signal i2c_registerid : std_logic_vector(7 downto 0); - signal i2c_register_data : std_logic_vector(7 downto 0); - signal i2c_register_value_read : std_logic_vector(7 downto 0); - - signal disable_slave_bus : std_logic; - signal internal_command : std_logic; - signal internal_command_d : std_logic; - signal i2c_data_internal_o : std_logic_vector(31 downto 0); - signal i2c_data_slave : std_logic_vector(31 downto 0); + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + + signal i2c_chipid : std_logic_vector(6 downto 0); + signal i2c_rw_bit : std_logic; + signal i2c_num_bytes : unsigned(2 downto 0); + signal i2c_registerid : std_logic_vector(7 downto 0); + signal i2c_register_data : std_logic_vector(7 downto 0); + signal i2c_register_value_read : std_logic_vector(7 downto 0); + + signal disable_slave_bus : std_logic; + signal internal_command : std_logic; + signal internal_command_d : std_logic; + signal i2c_data_internal_o : std_logic_vector(31 downto 0); + signal i2c_data_internal_bytes_o : std_logic_vector(31 downto 0); + signal i2c_data_slave : std_logic_vector(31 downto 0); begin @@ -422,17 +424,19 @@ begin begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - i2c_data_internal_o <= (others => '0'); - i2c_data_slave <= (others => '0'); - command_busy_o <= '0'; + i2c_data_internal_o <= (others => '0'); + i2c_data_internal_bytes_o <= (others => '0'); + i2c_data_slave <= (others => '0'); + command_busy_o <= '0'; else if (internal_command = '0' and internal_command_d = '0') then - i2c_data_slave <= i2c_data; + i2c_data_slave <= i2c_data; else - i2c_data_internal_o <= i2c_data; + i2c_data_internal_o <= i2c_data; + i2c_data_internal_bytes_o <= i2c_bytes; end if; end if; - command_busy_o <= i2c_busy; + command_busy_o <= i2c_busy; end if; end process PROC_I2C_DATA_MULTIPLEXER; @@ -592,6 +596,7 @@ begin COMMAND_BUSY_OUT <= command_busy_o; I2C_DATA_OUT <= i2c_data_internal_o; + I2C_DATA_BYTES_OUT <= i2c_data_internal_bytes_o; -- Slave Bus SLV_DATA_OUT <= slv_data_out_o; diff --git a/nxyter/source/nx_setup.vhd b/nxyter/source/nx_setup.vhd index c4f3978..422159d 100644 --- a/nxyter/source/nx_setup.vhd +++ b/nxyter/source/nx_setup.vhd @@ -15,6 +15,7 @@ entity nx_setup is I2C_COMMAND_OUT : out std_logic_vector(31 downto 0); I2C_COMMAND_BUSY_IN : in std_logic; I2C_DATA_IN : in std_logic_vector(31 downto 0); + I2C_DATA_BYTES_IN : in std_logic_vector(31 downto 0); I2C_LOCK_OUT : out std_logic; I2C_ONLINE_OUT : out std_logic; I2C_REG_RESET_IN : in std_logic; @@ -62,6 +63,7 @@ architecture Behavioral of nx_setup is signal i2c_command_done : std_logic; signal i2c_error : std_logic; signal i2c_data : std_logic_vector(31 downto 0); + signal i2c_data_bytes : std_logic_vector(31 downto 0); -- I2C Register Ram type i2c_ram_t is array(0 to 45) of std_logic_vector(7 downto 0); @@ -394,6 +396,7 @@ begin i2c_command_done <= '0'; i2c_error <= '0'; i2c_data <= (others => '0'); + i2c_data_bytes <= (others => '0'); I2C_STATE <= I2C_IDLE; else i2c_command_o <= (others => '0'); @@ -430,6 +433,7 @@ begin i2c_error <= '1'; end if; i2c_data <= I2C_DATA_IN; + i2c_data_bytes <= I2C_DATA_BYTES_IN; i2c_command_done <= '1'; I2C_STATE <= I2C_IDLE; end if; @@ -837,7 +841,7 @@ begin end if; when ADC_READ_I2C_STORE_MEM => - adc_ram(index) <= i2c_data(15 downto 0); + adc_ram(index) <= i2c_data_bytes(15 downto 0); i2c_lock_4_clear <= '1'; ADC_STATE <= ADC_NEXT_TOKEN; diff --git a/nxyter/source/nx_trigger_validate.vhd b/nxyter/source/nx_trigger_validate.vhd index da864ba..073c588 100644 --- a/nxyter/source/nx_trigger_validate.vhd +++ b/nxyter/source/nx_trigger_validate.vhd @@ -7,7 +7,7 @@ use work.nxyter_components.all; entity nx_trigger_validate is generic ( - BOARD_ID : std_logic_vector(15 downto 0) := x"ffff" + BOARD_ID : std_logic_vector(1 downto 0) := "11" ); port ( CLK_IN : in std_logic; @@ -59,7 +59,12 @@ entity nx_trigger_validate is end entity; architecture Behavioral of nx_trigger_validate is + constant VERSION_NUMBER : std_logic_vector(3 downto 0) := x"1"; + constant S_PARITY : integer := 2; + constant S_PILEUP : integer := 1; + constant S_OVFL : integer := 0; + -- Process Channel_Status signal channel_index : std_logic_vector(6 downto 0); signal channel_wait : std_logic_vector(127 downto 0); @@ -297,7 +302,7 @@ begin fifo_delay_time <= (others => '0'); end if; - -- Final ower Threshold value relative to TS Reference TS + -- Final lower Threshold value relative to TS Reference TS window_lower_thr := timestamp_fpga - window_lower_thr; window_upper_thr := @@ -354,54 +359,41 @@ begin if (store_data = '1') then case readout_mode(1 downto 0) is - when "00" => - -- RefValue + TS window filter + parity valid - if (TIMESTAMP_STATUS_IN(2) = '0') then + + when "00" | "11" => + -- Default Mode + -- RefValue + Parity Valid + Error Bits + if (TIMESTAMP_STATUS_IN(S_PARITY) = '0') then d_data_o(10 downto 0) <= deltaTStore(10 downto 0); - d_data_o(22 downto 11) <= ADC_DATA_IN; - d_data_o(29 downto 23) <= CHANNEL_IN; - d_data_o(31 downto 30) <= - TIMESTAMP_STATUS_IN(1 downto 0); + d_data_o(11) <= TIMESTAMP_STATUS_IN(S_PILEUP); + d_data_o(12) <= TIMESTAMP_STATUS_IN(S_OVFL); + d_data_o(24 downto 13) <= ADC_DATA_IN; + d_data_o(31 downto 25) <= CHANNEL_IN; d_data_clk_o <= '1'; end if; when "01" => - -- RefValue + TS window filter + pileup and Overflow valid - -- parity valid - if (TIMESTAMP_STATUS_IN(2) = '0' and - TIMESTAMP_STATUS_IN(0) = '0') then - d_data_o(10 downto 0) <= deltaTStore(10 downto 0); - d_data_o(22 downto 11) <= ADC_DATA_IN; - d_data_o(29 downto 23) <= CHANNEL_IN; - d_data_o(31 downto 30) <= - TIMESTAMP_STATUS_IN(1 downto 0); + -- Extended Timestamp Mode + -- RefValue + Parity Valid, Error Bits = extended Timestamp + if (TIMESTAMP_STATUS_IN(S_PARITY) = '0') then + d_data_o(12 downto 0) <= deltaTStore(12 downto 0); + d_data_o(24 downto 13) <= ADC_DATA_IN; + d_data_o(31 downto 25) <= CHANNEL_IN; d_data_clk_o <= '1'; end if; when "10" => - -- RefValue + TS window filter + pileup, Overflow and pileup - -- valid - -- parity valid - if (TIMESTAMP_STATUS_IN(2) = '0' and - TIMESTAMP_STATUS_IN(1) = '0' and - TIMESTAMP_STATUS_IN(0) = '0') then - d_data_o(10 downto 0) <= deltaTStore(10 downto 0); - d_data_o(22 downto 11) <= ADC_DATA_IN; - d_data_o(29 downto 23) <= CHANNEL_IN; - d_data_o(31 downto 30) <= - TIMESTAMP_STATUS_IN(1 downto 0); + -- Super Extended Timestamp Mode + -- ..... + if (TIMESTAMP_STATUS_IN(S_PARITY) = '0') then + d_data_o(13 downto 0) <= deltaTStore; + d_data_o(14) <= TIMESTAMP_STATUS_IN(S_PILEUP); + d_data_o(15) <= TIMESTAMP_STATUS_IN(S_OVFL); + d_data_o(24 downto 16) <= (others => '0'); + d_data_o(31 downto 25) <= CHANNEL_IN; d_data_clk_o <= '1'; end if; - - when others => - d_data_o(10 downto 0) <= deltaTStore(10 downto 0); - d_data_o(22 downto 11) <= ADC_DATA_IN; - d_data_o(29 downto 23) <= CHANNEL_IN; - d_data_o(31 downto 30) <= - TIMESTAMP_STATUS_IN(1 downto 0); - d_data_clk_o <= '1'; - -- RefValue + ignore status - + end case; end if; @@ -414,8 +406,8 @@ begin histogram_fill_o <= '1'; histogram_bin_o <= CHANNEL_IN; histogram_adc_o <= ADC_DATA_IN; - histogram_pileup_o <= TIMESTAMP_STATUS_IN(1); - histogram_ovfl_o <= TIMESTAMP_STATUS_IN(0); + histogram_pileup_o <= TIMESTAMP_STATUS_IN(S_PILEUP); + histogram_ovfl_o <= TIMESTAMP_STATUS_IN(S_OVFL); end if; end if; @@ -654,19 +646,20 @@ begin t_data_o(11 downto 0) <= timestamp_ref; t_data_o(21 downto 12) <= event_counter; - -- Readout Mode Mapping (so far) - -- 00: Standard - -- 01: Special - -- 10: DEBUG - -- 11: UNDEF - case readout_mode(2 downto 0) is - when "000" => t_data_o(23 downto 22) <= "00"; - when "001" => t_data_o(23 downto 22) <= "01"; - when "100" => t_data_o(23 downto 22) <= "10"; - when "101" => t_data_o(23 downto 22) <= "11"; - when others => t_data_o(23 downto 22) <= "11"; - end case; - t_data_o(31 downto 24) <= BOARD_ID(7 downto 0); + -- Readout Mode Mapping + -- Bit #3: self Triger mode + -- Bit #2: 0: activate TS Selection Window + -- 1: disable TS Selection Window, i.e. + -- data will be written to disk as long as + -- Readout Time Max (Reg.: 0x8184) is valid + -- + -- Bit #1..0: 00: Standard + -- 01: UNDEF + -- 10: UNDEF + -- 11: UNDEF + t_data_o(25 downto 22) <= readout_mode; + t_data_o(29 downto 26) <= VERSION_NUMBER; + t_data_o(31 downto 30) <= BOARD_ID; t_data_clk_o <= '1'; event_counter <= event_counter + 1; @@ -694,9 +687,9 @@ begin if (wait_timer_done = '1') then wait_timer_reset_all <= '1'; STATE <= S_WRITE_TRAILER; - elsif (readout_mode(2) = '0' and - min_val_time_expired = '1' and - (channel_all_done = '1' or + elsif (readout_mode(2) = '0' and + min_val_time_expired = '1' and + (channel_all_done = '1' or NX_NOMORE_DATA_IN = '1') ) then wait_timer_reset_all <= '1'; @@ -864,7 +857,7 @@ begin case SLV_ADDR_IN is when x"0000" => slv_data_out_o( 3 downto 0) <= readout_mode_r; - slv_data_out_o(31 downto 4) <= (others => '0'); + slv_data_out_o(31 downto 5) <= (others => '0'); slv_ack_o <= '1'; when x"0001" => diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 67dcfe8..5326de9 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -10,7 +10,7 @@ package nxyter_components is component nXyter_FEE_board generic ( - BOARD_ID : std_logic_vector(15 downto 0)); + BOARD_ID : std_logic_vector(1 downto 0)); port ( CLK_IN : in std_logic; RESET_IN : in std_logic; @@ -86,6 +86,7 @@ component nx_i2c_master INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0); COMMAND_BUSY_OUT : out std_logic; I2C_DATA_OUT : out std_logic_vector(31 downto 0); + I2C_DATA_BYTES_OUT : out std_logic_vector(31 downto 0); I2C_LOCK_IN : in std_logic; SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -313,6 +314,7 @@ component nx_setup I2C_COMMAND_OUT : out std_logic_vector(31 downto 0); I2C_COMMAND_BUSY_IN : in std_logic; I2C_DATA_IN : in std_logic_vector(31 downto 0); + I2C_DATA_BYTES_IN : in std_logic_vector(31 downto 0); I2C_LOCK_OUT : out std_logic; I2C_ONLINE_OUT : out std_logic; I2C_REG_RESET_IN : in std_logic; @@ -526,7 +528,7 @@ end component; component nx_trigger_validate generic ( - BOARD_ID : std_logic_vector(15 downto 0) + BOARD_ID : std_logic_vector(1 downto 0) ); port ( CLK_IN : in std_logic; @@ -568,7 +570,7 @@ end component; component nx_event_buffer generic ( - BOARD_ID : std_logic_vector(15 downto 0) + BOARD_ID : std_logic_vector(1 downto 0) ); port ( CLK_IN : in std_logic; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index 9ab2e58..56c6ef9 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -15,7 +15,7 @@ use work.nxyter_components.all; entity nXyter_FEE_board is generic ( - BOARD_ID : std_logic_vector(15 downto 0) := x"ffff" + BOARD_ID : std_logic_vector(1 downto 0) := "11" ); port ( CLK_IN : in std_logic; @@ -125,6 +125,7 @@ architecture Behavioral of nXyter_FEE_board is signal i2c_command : std_logic_vector(31 downto 0); signal i2c_command_busy : std_logic; signal i2c_data : std_logic_vector(31 downto 0); + signal i2c_data_bytes : std_logic_vector(31 downto 0); signal spi_lock : std_logic; signal spi_command : std_logic_vector(31 downto 0); signal spi_command_busy : std_logic; @@ -337,6 +338,7 @@ begin I2C_COMMAND_OUT => i2c_command, I2C_COMMAND_BUSY_IN => i2c_command_busy, I2C_DATA_IN => i2c_data, + I2C_DATA_BYTES_IN => i2c_data_bytes, I2C_LOCK_OUT => i2c_lock, I2C_ONLINE_OUT => nxyter_online_i2c, I2C_REG_RESET_IN => i2c_reg_reset_o, @@ -372,6 +374,7 @@ begin INTERNAL_COMMAND_IN => i2c_command, COMMAND_BUSY_OUT => i2c_command_busy, I2C_DATA_OUT => i2c_data, + I2C_DATA_BYTES_OUT => i2c_data_bytes, I2C_LOCK_IN => i2c_lock, SLV_READ_IN => slv_read(1), SLV_WRITE_IN => slv_write(1), diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd index 91bba43..da96296 100644 --- a/nxyter/trb3_periph.vhd +++ b/nxyter/trb3_periph.vhd @@ -699,7 +699,7 @@ begin nXyter_FEE_board_0: nXyter_FEE_board generic map ( - BOARD_ID => x"0001" + BOARD_ID => "01" ) port map ( CLK_IN => clk_100_i, @@ -781,7 +781,7 @@ begin nXyter_FEE_board_1: nXyter_FEE_board generic map ( - BOARD_ID => x"0002" + BOARD_ID => "10" ) port map ( CLK_IN => clk_100_i,