From: Thomas Gessler Date: Fri, 11 Sep 2020 14:01:54 +0000 (+0200) Subject: Overhaul clocking for XCKU MGTs X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=216fd00042cd50e776c689bce8ff241c305a31b3;p=trbnet.git Overhaul clocking for XCKU MGTs The clock inputs and outputs are now exposed to the instantiating layer. This allows more flexible clocking schemes, including a completely synchrounous system with multiple quads. The reference-clock frequency is now set 100 MHz, so that it matches the user-clock frequency. The single-GT version is removed to simplify maintenance. Where needed, it can be replaced by the quad version. --- diff --git a/media_interfaces/med_xcku_sfp_sync.vhd b/media_interfaces/med_xcku_sfp_sync.vhd deleted file mode 100644 index ec1aecc..0000000 --- a/media_interfaces/med_xcku_sfp_sync.vhd +++ /dev/null @@ -1,165 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.med_sync_define.all; - -entity med_xcku_sfp_sync is - generic ( - IS_SYNC_SLAVE : integer := c_NO - ); - port ( - SYSCLK : in std_logic; - CLK_200 : in std_logic; - GTREFCLK : in std_logic; - - RESET : in std_logic; - CLEAR : in std_logic; - - RXN : in std_logic; - RXP : in std_logic; - TXN : out std_logic; - TXP : out std_logic; - - MEDIA_MED2INT : out MED2INT; - MEDIA_INT2MED : in INT2MED; - - RX_DLM : out std_logic := '0'; - RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; - TX_DLM : in std_logic := '0'; - TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; - - SD_LOS_IN : in std_logic; - SD_TXDIS_OUT : out std_logic; - - BUS_RX : in CTRLBUS_RX; - BUS_TX : out CTRLBUS_TX; - - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') - ); -end entity; - - -architecture med_xcku_sfp_sync_arch of med_xcku_sfp_sync is - signal usrclk_full : std_logic; - signal usrclk_half : std_logic; - - signal txdata : std_logic_vector(7 downto 0); - signal txcharisk : std_logic; - signal txchardispmode : std_logic; - signal rxdata : std_logic_vector(7 downto 0); - signal rxcharisk : std_logic; - signal rxnotintable : std_logic; - - signal rxpmareset : std_logic; - signal txpcsreset : std_logic; - signal rxpcsreset : std_logic; - signal quad_rst : std_logic; - signal reset_all : std_logic; - - signal rx_los : std_logic; - signal rx_cdr_lol : std_logic; - signal tx_lol : std_logic; - - signal reset_tx_done : std_logic; - signal rxpmaresetdone : std_logic; - signal txpmaresetdone : std_logic; - - signal debug_rx_control_i : std_logic_vector(31 downto 0); - signal debug_tx_control_i : std_logic_vector(31 downto 0); -begin - SD_TXDIS_OUT <= '0'; - - reset_all <= quad_rst; - - THE_SERDES : entity work.gth_xcku_x0y8_top - port map ( - CLK_100 => SYSCLK, - GTREFCLK => GTREFCLK, - USRCLK_FULL => usrclk_full, - USRCLK_HALF => usrclk_half, - RESET_ALL => reset_all, - RXPMARESET => rxpmareset, - RXPCSRESET => rxpcsreset, - TXPMARESET => '0', - TXPCSRESET => txpcsreset, - USRCLK_LOCKED => open, - INIT_DONE => open, - RXRESETDONE => open, - TXRESETDONE => open, - RXPMARESETDONE => rxpmaresetdone, - TXPMARESETDONE => txpmaresetdone, - RXBYTEISALIGNED => open, - RXN => RXN, - RXP => RXP, - TXN => TXN, - TXP => TXP, - TXDATA => txdata, - TXCHARISK => txcharisk, - TXCHARDISPMODE => txchardispmode, - TXCHARDISPVAL => '0', - RXDATA => rxdata, - RXCHARISK => rxcharisk, - RXCHARISCOMMA => open, - RXNOTINTABLE => rxnotintable, - RXDISPERR => open - ); - - tx_lol <= not txpmaresetdone; - rx_cdr_lol <= not rxpmaresetdone; - - - THE_MED_CONTROL : entity work.med_sync_control - generic map( - IS_SYNC_SLAVE => IS_SYNC_SLAVE, - IS_TX_RESET => 1 - ) - port map( - CLK_SYS => SYSCLK, - CLK_RXI => usrclk_full, - CLK_RXHALF => usrclk_half, - CLK_TXI => usrclk_full, - CLK_REF => CLK_200, - RESET => RESET, - CLEAR => CLEAR, - SFP_LOS => SD_LOS_IN, - TX_LOL => tx_lol, - RX_CDR_LOL => rx_cdr_lol, - RX_LOS => SD_LOS_IN, - WA_POSITION => (others => '0'), - RX_SERDES_RST => rxpmareset, - RX_PCS_RST => rxpcsreset, - QUAD_RST => quad_rst, - TX_PCS_RST => txpcsreset, - MEDIA_MED2INT => MEDIA_MED2INT, - MEDIA_INT2MED => MEDIA_INT2MED, - TX_DATA => txdata, - TX_K => txcharisk, - TX_CD => txchardispmode, - RX_DATA => rxdata, - RX_K => rxcharisk, - TX_DLM_WORD => TX_DLM_WORD, - TX_DLM => TX_DLM, - RX_DLM_WORD => RX_DLM_WORD, - RX_DLM => RX_DLM, - STAT_TX_CONTROL => open, - STAT_RX_CONTROL => open, - DEBUG_TX_CONTROL => debug_tx_control_i, - DEBUG_RX_CONTROL => debug_rx_control_i, - STAT_RESET => open - ); - - THE_BUS: - process is - begin - wait until rising_edge(SYSCLK); - BUS_TX.unknown <= BUS_RX.read or BUS_RX.write; - BUS_TX.ack <= '0'; - end process; - - STAT_DEBUG(13 downto 0) <= debug_tx_control_i(13 downto 0); - STAT_DEBUG(15 downto 14) <= debug_tx_control_i(17 downto 16); -end architecture; diff --git a/media_interfaces/med_xcku_sfp_sync_4.vhd b/media_interfaces/med_xcku_sfp_sync_4.vhd index cdffa9f..7587987 100644 --- a/media_interfaces/med_xcku_sfp_sync_4.vhd +++ b/media_interfaces/med_xcku_sfp_sync_4.vhd @@ -12,42 +12,50 @@ entity med_xcku_sfp_sync_4 is IS_USED : int_array_t(0 to 3) := (c_YES, c_YES, c_YES, c_YES) ); port ( - SYSCLK : in std_logic; - CLK_200 : in std_logic; - GTREFCLK : in std_logic; - - RESET : in std_logic; - CLEAR : in std_logic; - - RXN : in std_logic_vector(3 downto 0); - RXP : in std_logic_vector(3 downto 0); - TXN : out std_logic_vector(3 downto 0); - TXP : out std_logic_vector(3 downto 0); - - MEDIA_MED2INT : out med2int_array_t(0 to 3); - MEDIA_INT2MED : in int2med_array_t(0 to 3); - - RX_DLM : out std_logic_vector(3 downto 0) := x"0"; - RX_DLM_WORD : out std_logic_vector(31 downto 0) := (others => '0'); - TX_DLM : in std_logic_vector(3 downto 0) := x"0"; - TX_DLM_WORD : in std_logic_vector(31 downto 0) := (others => '0'); - - SD_LOS_IN : in std_logic_vector(3 downto 0); - SD_TXDIS_OUT : out std_logic_vector(3 downto 0); - - BUS_RX : in CTRLBUS_RX; - BUS_TX : out CTRLBUS_TX; - - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + SYSCLK : in std_logic; + CLK_200 : in std_logic; + GTREFCLK : in std_logic; + RXOUTCLK : out std_logic_vector(3 downto 0); + TXOUTCLK : out std_logic_vector(3 downto 0); + RXUSRCLK : in std_logic_vector(3 downto 0); + RXUSRCLK_DOUBLE : in std_logic_vector(3 downto 0); + TXUSRCLK : in std_logic_vector(3 downto 0); + TXUSRCLK_DOUBLE : in std_logic_vector(3 downto 0); + + RXUSRCLK_ACTIVE : in std_logic; + TXUSRCLK_ACTIVE : in std_logic; + RXPMARESETDONE : out std_logic_vector(3 downto 0); + TXPMARESETDONE : out std_logic_vector(3 downto 0); + + RESET : in std_logic; + CLEAR : in std_logic; + + RXN : in std_logic_vector(3 downto 0); + RXP : in std_logic_vector(3 downto 0); + TXN : out std_logic_vector(3 downto 0); + TXP : out std_logic_vector(3 downto 0); + + MEDIA_MED2INT : out med2int_array_t(0 to 3); + MEDIA_INT2MED : in int2med_array_t(0 to 3); + + RX_DLM : out std_logic_vector(3 downto 0) := x"0"; + RX_DLM_WORD : out std_logic_vector(31 downto 0) := (others => '0'); + TX_DLM : in std_logic_vector(3 downto 0) := x"0"; + TX_DLM_WORD : in std_logic_vector(31 downto 0) := (others => '0'); + + SD_LOS_IN : in std_logic_vector(3 downto 0); + SD_TXDIS_OUT : out std_logic_vector(3 downto 0); + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; + + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') ); end entity; architecture med_xcku_sfp_sync_4_arch of med_xcku_sfp_sync_4 is - signal usrclk_full : std_logic; - signal usrclk_half : std_logic; - signal txdata : std_logic_vector(31 downto 0); signal txcharisk : std_logic_vector(3 downto 0); signal txchardispmode : std_logic_vector(3 downto 0); @@ -66,8 +74,8 @@ architecture med_xcku_sfp_sync_4_arch of med_xcku_sfp_sync_4 is signal tx_lol : std_logic; signal reset_tx_done : std_logic; - signal rxpmaresetdone : std_logic_vector(3 downto 0); - signal txpmaresetdone : std_logic_vector(3 downto 0); + signal rxpmaresetdone_i : std_logic_vector(3 downto 0); + signal txpmaresetdone_i : std_logic_vector(3 downto 0); signal debug_rx_control_i : std_logic_vector(127 downto 0); signal debug_tx_control_i : std_logic_vector(127 downto 0); @@ -80,19 +88,24 @@ begin port map ( CLK_100 => SYSCLK, GTREFCLK => GTREFCLK, - USRCLK_FULL => usrclk_full, - USRCLK_HALF => usrclk_half, + RXOUTCLK => RXOUTCLK, + TXOUTCLK => TXOUTCLK, + RXUSRCLK => RXUSRCLK, + RXUSRCLK_DOUBLE => RXUSRCLK_DOUBLE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK_DOUBLE => TXUSRCLK_DOUBLE, + RXUSRCLK_ACTIVE => RXUSRCLK_ACTIVE, + TXUSRCLK_ACTIVE => TXUSRCLK_ACTIVE, RESET_ALL => reset_all, RXPMARESET => rxpmareset, RXPCSRESET => rxpcsreset, TXPMARESET => "0000", TXPCSRESET => txpcsreset, - USRCLK_LOCKED => open, INIT_DONE => open, RXRESETDONE => open, TXRESETDONE => open, - RXPMARESETDONE => rxpmaresetdone, - TXPMARESETDONE => txpmaresetdone, + RXPMARESETDONE => rxpmaresetdone_i, + TXPMARESETDONE => txpmaresetdone_i, RXBYTEISALIGNED => open, RXN => RXN, RXP => RXP, @@ -109,9 +122,11 @@ begin RXDISPERR => open ); - tx_lol <= not txpmaresetdone(0); - rx_cdr_lol <= not rxpmaresetdone; + tx_lol <= not txpmaresetdone_i(0); + rx_cdr_lol <= not rxpmaresetdone_i; + RXPMARESETDONE <= rxpmaresetdone_i; + TXPMARESETDONE <= txpmaresetdone_i; gen_control : for i in 0 to 3 generate gen_used_control : if IS_USED(i) = c_YES generate @@ -122,9 +137,9 @@ begin ) port map( CLK_SYS => SYSCLK, - CLK_RXI => usrclk_full, - CLK_RXHALF => usrclk_half, - CLK_TXI => usrclk_full, + CLK_RXI => RXUSRCLK_DOUBLE(i), + CLK_RXHALF => RXUSRCLK(i), + CLK_TXI => TXUSRCLK_DOUBLE(i), CLK_REF => CLK_200, RESET => RESET, CLEAR => CLEAR, diff --git a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xci b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xci index ff9596a..eb0b642 100644 --- a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xci +++ b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xci @@ -60,7 +60,7 @@ 1 0 0x000000000000000000000000000000000000000000000000 - 125 + 100 0 0 0 @@ -91,7 +91,7 @@ 100.0000000 1 0 - 125 + 100 0 0 1 @@ -651,7 +651,7 @@ -1 -1 -1 - 15 + 16 0 None 8 @@ -788,7 +788,7 @@ 0 0 - 125 + 100 OFF 0 @@ -815,7 +815,7 @@ TXOUTCLKPMA QPLL0 0 - 125 + 100 16 false diff --git a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xml b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xml index a459dec..84a1b6a 100644 --- a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xml +++ b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xml @@ -14,7 +14,7 @@ outputProductCRC - 9:e9c230b8 + 9:95340453 @@ -14306,7 +14306,7 @@ C_RX_REFCLK_FREQUENCY - 125 + 100 C_RX_SLIDE_MODE @@ -14426,7 +14426,7 @@ C_TX_REFCLK_FREQUENCY - 125 + 100 C_TX_USER_CLOCKING_CONTENTS @@ -14469,6 +14469,13 @@ 32 64 + + choice_list_04c1b6c3 + RXOUTCLKPMA + RXOUTCLKPCS + RXPLLREFCLK_DIV1 + RXPROGDIVCLK + choice_list_0fbde0c1 20 @@ -14478,29 +14485,24 @@ -20 -40 - - choice_list_1fad77c0 - RXOUTCLKPMA - RXOUTCLKPCS - RXPROGDIVCLK - choice_list_24871ac1 AC DC - - choice_list_305f448a - TXOUTCLKPMA - TXOUTCLKPCS - TXPROGDIVCLK - choice_list_3179277f QPLL0 QPLL1 CPLL + + choice_list_39947cc7 + TXOUTCLKPMA + TXOUTCLKPCS + TXPLLREFCLK_DIV1 + TXPROGDIVCLK + choice_list_556e59ba 0 @@ -15352,7 +15354,7 @@ TX_REFCLK_FREQUENCY Actual Reference clock (MHz) Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type - 125 + 100 TX_DATA_ENCODING @@ -15395,7 +15397,7 @@ TX_OUTCLK_SOURCE TXOUTCLK source Select the source of TXOUTCLK - TXOUTCLKPMA + TXOUTCLKPMA TX_DIFF_SWING_EMPH_MODE @@ -15419,7 +15421,7 @@ RX_REFCLK_FREQUENCY Actual Reference clock (MHz) Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type - 125 + 100 RX_DATA_DECODING @@ -15480,7 +15482,7 @@ RX_OUTCLK_SOURCE RXOUTCLK source Select the source of RXOUTCLK - RXOUTCLKPMA + RXOUTCLKPMA SIM_CPLL_CAL_BYPASS @@ -16624,7 +16626,7 @@ INTERNAL_PORT_ENABLEMENT_UPDATED - 15 + 16 diff --git a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd index b73aac4..e3b5e91 100644 --- a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd +++ b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd @@ -8,16 +8,21 @@ entity gth_xcku_quad_x0y2_top is port ( CLK_100 : in std_logic; GTREFCLK : in std_logic; - USRCLK_FULL : out std_logic; - USRCLK_HALF : out std_logic; - + RXOUTCLK : out std_logic_vector(3 downto 0); + TXOUTCLK : out std_logic_vector(3 downto 0); + RXUSRCLK : in std_logic_vector(3 downto 0); + RXUSRCLK_DOUBLE : in std_logic_vector(3 downto 0); + TXUSRCLK : in std_logic_vector(3 downto 0); + TXUSRCLK_DOUBLE : in std_logic_vector(3 downto 0); + + RXUSRCLK_ACTIVE : in std_logic; + TXUSRCLK_ACTIVE : in std_logic; RESET_ALL : in std_logic; RXPMARESET : in std_logic_vector(3 downto 0); RXPCSRESET : in std_logic_vector(3 downto 0); TXPMARESET : in std_logic_vector(3 downto 0); TXPCSRESET : in std_logic_vector(3 downto 0); - USRCLK_LOCKED : out std_logic; INIT_DONE : out std_logic; RXRESETDONE : out std_logic_vector(3 downto 0); TXRESETDONE : out std_logic_vector(3 downto 0); @@ -124,76 +129,19 @@ architecture behavioral of gth_xcku_quad_x0y2_top is signal reset_tx_done_i : std_logic; signal reset_rx_done_i : std_logic; - signal userclk_tx_reset_i : std_logic := '0'; - signal txpmaresetdone_i : std_logic_vector(3 downto 0); - - signal usrclk : std_logic; - signal usrclk_double : std_logic; - - signal txdata_reg : std_logic_vector(31 downto 0); - signal txcharisk_reg : std_logic_vector(3 downto 0); - signal txchardispmode_reg : std_logic_vector(3 downto 0); - signal txchardispval_reg : std_logic_vector(3 downto 0); - - signal tx16data : std_logic_vector(63 downto 0); - signal tx16charisk : std_logic_vector(7 downto 0); - signal tx16chardispmode : std_logic_vector(7 downto 0); - signal tx16chardispval : std_logic_vector(7 downto 0); + signal reset_all_i : std_logic; + signal gtwiz_userdata_rx : std_logic_vector(63 downto 0); signal rxctrl0 : std_logic_vector(63 downto 0); signal rxctrl1 : std_logic_vector(63 downto 0); signal rxctrl2 : std_logic_vector(31 downto 0); signal rxctrl3 : std_logic_vector(31 downto 0); + signal gtwiz_userdata_tx : std_logic_vector(63 downto 0); signal txctrl0 : std_logic_vector(63 downto 0) := (others => '0'); signal txctrl1 : std_logic_vector(63 downto 0) := (others => '0'); signal txctrl2 : std_logic_vector(31 downto 0) := (others => '0'); - - signal rx16data : std_logic_vector(63 downto 0); - signal rx16charisk : std_logic_vector(7 downto 0); - signal rx16chariscomma : std_logic_vector(7 downto 0); - signal rx16notintable : std_logic_vector(7 downto 0); - signal rx16disperr : std_logic_vector(7 downto 0); - - signal rx16data_reg : std_logic_vector(63 downto 0); - signal rx16charisk_reg : std_logic_vector(7 downto 0); - signal rx16chariscomma_reg : std_logic_vector(7 downto 0); - signal rx16notintable_reg : std_logic_vector(7 downto 0); - signal rx16disperr_reg : std_logic_vector(7 downto 0); - - signal rxdata_i : std_logic_vector(31 downto 0); - signal rxcharisk_i : std_logic_vector(3 downto 0); - signal rxchariscomma_i : std_logic_vector(3 downto 0); - signal rxnotintable_i : std_logic_vector(3 downto 0); - signal rxdisperr_i : std_logic_vector(3 downto 0); - - signal usrclk_toggle : std_logic := '0'; - signal usrclk_toggle_reg : std_logic := '0'; - signal usrclk_phase : std_logic := '0'; - - signal reset_all_i : std_logic; - - signal txoutclk_int : std_logic_vector(3 downto 0); - signal usrclk_int : std_logic; - - signal usrclk_mmcm_fb : std_logic; - - signal usrclk_active_meta : std_logic := '0'; - signal usrclk_active : std_logic := '0'; - signal not_usrclk_active : std_logic; - - attribute ASYNC_REG : string; - attribute ASYNC_REG of usrclk_active_meta : signal is "true"; - attribute ASYNC_REG of usrclk_active : signal is "true"; begin - USRCLK_FULL <= usrclk_double; - USRCLK_HALF <= usrclk; - - userclk_tx_reset_i <= not (txpmaresetdone_i(0) and txpmaresetdone_i(1) - and txpmaresetdone_i(2) and txpmaresetdone_i(3)); - - TXPMARESETDONE <= txpmaresetdone_i; - THE_INIT : gth_xcku_init port map ( clk_freerun_in => CLK_100, @@ -208,66 +156,106 @@ begin ); - process (usrclk) is - begin - if rising_edge(usrclk) then - usrclk_toggle <= not usrclk_toggle; - - rx16data_reg <= rx16data; - rx16charisk_reg <= rx16charisk; - rx16chariscomma_reg <= rx16chariscomma; - rx16notintable_reg <= rx16notintable; - rx16disperr_reg <= rx16disperr; - - for i in 0 to 3 loop - tx16data(16 * i + 15 downto 16 * i) <= TXDATA(8 * i + 7 downto 8 * i) & txdata_reg(8 * i + 7 downto 8 * i); - tx16charisk(2 * i + 1 downto 2 * i) <= TXCHARISK(i) & txcharisk_reg(i); - tx16chardispmode(2 * i + 1 downto 2 * i) <= TXCHARDISPMODE(i) & txchardispmode_reg(i); - tx16chardispval(2 * i + 1 downto 2 * i) <= TXCHARDISPVAL(i) & txchardispval_reg(i); - end loop; - end if; - end process; - - process (usrclk_double) is + generate_lanes: + for i in 0 to 3 generate + signal rx16data : std_logic_vector(15 downto 0); + signal rx16charisk : std_logic_vector(1 downto 0); + signal rx16chariscomma : std_logic_vector(1 downto 0); + signal rx16notintable : std_logic_vector(1 downto 0); + signal rx16disperr : std_logic_vector(1 downto 0); + + signal rx16data_reg : std_logic_vector(15 downto 0) := x"0000"; + signal rx16charisk_reg : std_logic_vector(1 downto 0) := "00"; + signal rx16chariscomma_reg : std_logic_vector(1 downto 0) := "00"; + signal rx16notintable_reg : std_logic_vector(1 downto 0) := "00"; + signal rx16disperr_reg : std_logic_vector(1 downto 0) := "00"; + + signal rxusrclk_toggle : std_logic := '0'; + signal rxusrclk_toggle_reg : std_logic := '0'; + signal rxusrclk_phase : std_logic := '0'; + + signal txdata_reg : std_logic_vector(7 downto 0) := x"00"; + signal txcharisk_reg : std_logic := '0'; + signal txchardispmode_reg : std_logic := '0'; + signal txchardispval_reg : std_logic := '0'; + + signal tx16data : std_logic_vector(15 downto 0); + signal tx16charisk : std_logic_vector(1 downto 0); + signal tx16chardispmode : std_logic_vector(1 downto 0); + signal tx16chardispval : std_logic_vector(1 downto 0); begin - if rising_edge(usrclk_double) then - usrclk_toggle_reg <= usrclk_toggle; - usrclk_phase <= usrclk_toggle xor usrclk_toggle_reg; - - for i in 0 to 3 loop - if usrclk_phase = '0' then - rxdata_i(8 * i + 7 downto 8 * i) <= rx16data_reg(16 * i + 7 downto 16 * i); - rxcharisk_i(i) <= rx16charisk_reg(2 * i); - rxchariscomma_i(i) <= rx16chariscomma_reg(2 * i); - rxnotintable_i(i) <= rx16notintable_reg(2 * i); - rxdisperr_i(i) <= rx16disperr_reg(2 * i); + rx16data <= gtwiz_userdata_rx(16 * i + 15 downto 16 * i); + rx16charisk <= rxctrl0(16 * i + 1 downto 16 * i); + rx16disperr <= rxctrl1(16 * i + 1 downto 16 * i); + rx16chariscomma <= rxctrl2(8 * i + 1 downto 8 * i); + rx16notintable <= rxctrl3(8 * i + 1 downto 8 * i); + + process (RXUSRCLK) is + begin + if rising_edge(RXUSRCLK(i)) then + rx16data_reg <= rx16data; + rx16charisk_reg <= rx16charisk; + rx16chariscomma_reg <= rx16chariscomma; + rx16notintable_reg <= rx16notintable; + rx16disperr_reg <= rx16disperr; + + rxusrclk_toggle <= not rxusrclk_toggle; + end if; + end process; + + process (RXUSRCLK_DOUBLE) is + begin + if rising_edge(RXUSRCLK_DOUBLE(i)) then + rxusrclk_toggle_reg <= rxusrclk_toggle; + rxusrclk_phase <= rxusrclk_toggle xor rxusrclk_toggle_reg; + + if rxusrclk_phase = '0' then + RXDATA(8 * i + 7 downto 8 * i) <= rx16data_reg(7 downto 0); + RXCHARISK(i) <= rx16charisk_reg(0); + RXCHARISCOMMA(i) <= rx16chariscomma_reg(0); + RXNOTINTABLE(i) <= rx16notintable_reg(0); + RXDISPERR(i) <= rx16disperr_reg(0); else - rxdata_i(8 * i + 7 downto 8 * i) <= rx16data_reg(16 * i + 15 downto 16 * i + 8); - rxcharisk_i(i) <= rx16charisk_reg(2 * i + 1); - rxchariscomma_i(i) <= rx16chariscomma_reg(2 * i + 1); - rxnotintable_i(i) <= rx16notintable_reg(2 * i + 1); - rxdisperr_i(i) <= rx16disperr_reg(2 * i + 1); + RXDATA(8 * i + 7 downto 8 * i) <= rx16data_reg(15 downto 8); + RXCHARISK(i) <= rx16charisk_reg(1); + RXCHARISCOMMA(i) <= rx16chariscomma_reg(1); + RXNOTINTABLE(i) <= rx16notintable_reg(1); + RXDISPERR(i) <= rx16disperr_reg(1); end if; - end loop; - - txdata_reg <= TXDATA; - txcharisk_reg <= TXCHARISK; - txchardispmode_reg <= TXCHARDISPMODE; - txchardispval_reg <= TXCHARDISPVAL; - end if; - end process; - - RXDATA <= rxdata_i; - RXCHARISK <= rxcharisk_i; - RXCHARISCOMMA <= rxchariscomma_i; - RXNOTINTABLE <= rxnotintable_i; - RXDISPERR <= rxdisperr_i; + end if; + end process; + + process (TXUSRCLK_DOUBLE) is + begin + if rising_edge(TXUSRCLK_DOUBLE(i)) then + txdata_reg <= TXDATA(8 * i + 7 downto 8 * i); + txcharisk_reg <= TXCHARISK(i); + txchardispmode_reg <= TXCHARDISPMODE(i); + txchardispval_reg <= TXCHARDISPVAL(i); + end if; + end process; + + process (TXUSRCLK) is + begin + if rising_edge(TXUSRCLK(i)) then + tx16data <= TXDATA(8 * i + 7 downto 8 * i) & txdata_reg; + tx16charisk <= TXCHARISK(i) & txcharisk_reg; + tx16chardispmode <= TXCHARDISPMODE(i) & txchardispmode_reg; + tx16chardispval <= TXCHARDISPVAL(i) & txchardispval_reg; + end if; + end process; + + gtwiz_userdata_tx(16 * i + 15 downto 16 * i) <= tx16data; + txctrl0(16 * i + 1 downto 16 * i) <= tx16chardispval; + txctrl1(16 * i + 1 downto 16 * i) <= tx16chardispmode; + txctrl2(8 * i + 1 downto 8 * i) <= tx16charisk; + end generate generate_lanes; THE_GTH : gth_xcku_quad_x0y2 port map ( - gtwiz_userclk_tx_active_in(0) => usrclk_active, - gtwiz_userclk_rx_active_in(0) => usrclk_active, + gtwiz_userclk_tx_active_in(0) => TXUSRCLK_ACTIVE, + gtwiz_userclk_rx_active_in(0) => RXUSRCLK_ACTIVE, gtwiz_reset_clk_freerun_in(0) => CLK_100, gtwiz_reset_all_in(0) => reset_all_i, gtwiz_reset_tx_pll_and_datapath_in(0) => '0', @@ -277,8 +265,8 @@ begin gtwiz_reset_rx_cdr_stable_out => open, gtwiz_reset_tx_done_out(0) => reset_tx_done_i, gtwiz_reset_rx_done_out(0) => reset_rx_done_i, - gtwiz_userdata_tx_in => tx16data, - gtwiz_userdata_rx_out => rx16data, + gtwiz_userdata_tx_in => gtwiz_userdata_tx, + gtwiz_userdata_rx_out => gtwiz_userdata_rx, gtrefclk00_in(0) => GTREFCLK, qpll0outclk_out => open, qpll0outrefclk_out => open, @@ -292,28 +280,28 @@ begin rxpcommaalignen_in => "1111", rxpcsreset_in => RXPCSRESET, rxpmareset_in => RXPMARESET, - rxusrclk_in(0) => usrclk_int, - rxusrclk_in(1) => usrclk_int, - rxusrclk_in(2) => usrclk_int, - rxusrclk_in(3) => usrclk_int, - rxusrclk2_in(0) => usrclk_int, - rxusrclk2_in(1) => usrclk_int, - rxusrclk2_in(2) => usrclk_int, - rxusrclk2_in(3) => usrclk_int, + rxusrclk_in(0) => RXUSRCLK(0), + rxusrclk_in(1) => RXUSRCLK(1), + rxusrclk_in(2) => RXUSRCLK(2), + rxusrclk_in(3) => RXUSRCLK(3), + rxusrclk2_in(0) => RXUSRCLK(0), + rxusrclk2_in(1) => RXUSRCLK(1), + rxusrclk2_in(2) => RXUSRCLK(2), + rxusrclk2_in(3) => RXUSRCLK(3), tx8b10ben_in => "1111", txctrl0_in => txctrl0, txctrl1_in => txctrl1, txctrl2_in => txctrl2, txpcsreset_in => TXPCSRESET, txpmareset_in => TXPMARESET, - txusrclk_in(0) => usrclk_int, - txusrclk_in(1) => usrclk_int, - txusrclk_in(2) => usrclk_int, - txusrclk_in(3) => usrclk_int, - txusrclk2_in(0) => usrclk_int, - txusrclk2_in(1) => usrclk_int, - txusrclk2_in(2) => usrclk_int, - txusrclk2_in(3) => usrclk_int, + txusrclk_in(0) => TXUSRCLK(0), + txusrclk_in(1) => TXUSRCLK(1), + txusrclk_in(2) => TXUSRCLK(2), + txusrclk_in(3) => TXUSRCLK(3), + txusrclk2_in(0) => TXUSRCLK(0), + txusrclk2_in(1) => TXUSRCLK(1), + txusrclk2_in(2) => TXUSRCLK(2), + txusrclk2_in(3) => TXUSRCLK(3), gthtxn_out => TXN, gthtxp_out => TXP, gtpowergood_out => open, @@ -326,132 +314,11 @@ begin rxctrl1_out => rxctrl1, rxctrl2_out => rxctrl2, rxctrl3_out => rxctrl3, - rxoutclk_out => open, + rxoutclk_out => RXOUTCLK, rxpmaresetdone_out => RXPMARESETDONE, rxresetdone_out => RXRESETDONE, - txoutclk_out => txoutclk_int, - txpmaresetdone_out => txpmaresetdone_i, + txoutclk_out => TXOUTCLK, + txpmaresetdone_out => TXPMARESETDONE, txresetdone_out => TXRESETDONE ); - - rx16charisk(1 downto 0) <= rxctrl0(1 downto 0); - rx16charisk(3 downto 2) <= rxctrl0(17 downto 16); - rx16charisk(5 downto 4) <= rxctrl0(33 downto 32); - rx16charisk(7 downto 6) <= rxctrl0(49 downto 48); - - rx16notintable(1 downto 0) <= rxctrl1(1 downto 0); - rx16notintable(3 downto 2) <= rxctrl1(17 downto 16); - rx16notintable(5 downto 4) <= rxctrl1(33 downto 32); - rx16notintable(7 downto 6) <= rxctrl1(49 downto 48); - - rx16chariscomma(1 downto 0) <= rxctrl2(1 downto 0); - rx16chariscomma(3 downto 2) <= rxctrl2(9 downto 8); - rx16chariscomma(5 downto 4) <= rxctrl2(17 downto 16); - rx16chariscomma(7 downto 6) <= rxctrl2(25 downto 24); - - rx16disperr(1 downto 0) <= rxctrl3(1 downto 0); - rx16disperr(3 downto 2) <= rxctrl3(9 downto 8); - rx16disperr(5 downto 4) <= rxctrl3(17 downto 16); - rx16disperr(7 downto 6) <= rxctrl3(25 downto 24); - - txctrl0(1 downto 0) <= tx16chardispval(1 downto 0); - txctrl0(17 downto 16) <= tx16chardispval(3 downto 2); - txctrl0(33 downto 32) <= tx16chardispval(5 downto 4); - txctrl0(49 downto 48) <= tx16chardispval(7 downto 6); - - txctrl1(1 downto 0) <= tx16chardispmode(1 downto 0); - txctrl1(17 downto 16) <= tx16chardispmode(3 downto 2); - txctrl1(33 downto 32) <= tx16chardispmode(5 downto 4); - txctrl1(49 downto 48) <= tx16chardispmode(7 downto 6); - - txctrl2(1 downto 0) <= tx16charisk(1 downto 0); - txctrl2(9 downto 8) <= tx16charisk(3 downto 2); - txctrl2(17 downto 16) <= tx16charisk(5 downto 4); - txctrl2(25 downto 24) <= tx16charisk(7 downto 6); - - bufg_gt_usrclk_inst : BUFG_GT - port map ( - O => usrclk_int, - CE => '1', - CEMASK => '0', - CLR => userclk_tx_reset_i, - CLRMASK => '0', - DIV => "000", - I => txoutclk_int(0) - ); - - - -- Indicate active helper block functionality when the BUFG_GT divider is - -- not held in reset - process (userclk_tx_reset_i, usrclk_int) is - begin - if userclk_tx_reset_i = '1' then - usrclk_active_meta <= '0'; - usrclk_active <= '0'; - elsif rising_edge(usrclk_int) then - usrclk_active_meta <= '1'; - usrclk_active <= usrclk_active_meta; - end if; - end process; - - not_usrclk_active <= not usrclk_active; - - - mmcme3_adv_usrclk : MMCME3_ADV - generic map ( - BANDWIDTH => "OPTIMIZED", - CLKOUT4_CASCADE => "FALSE", - COMPENSATION => "AUTO", - STARTUP_WAIT => "FALSE", - DIVCLK_DIVIDE => 1, - CLKFBOUT_MULT_F => 10.000, - CLKFBOUT_PHASE => 0.000, - CLKFBOUT_USE_FINE_PS => "FALSE", - CLKOUT0_DIVIDE_F => 10.000, - CLKOUT0_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT0_USE_FINE_PS => "FALSE", - CLKOUT1_DIVIDE => 5, - CLKOUT1_PHASE => 0.000, - CLKOUT1_DUTY_CYCLE => 0.500, - CLKOUT1_USE_FINE_PS => "FALSE", - CLKIN1_PERIOD => 10.000 - ) - port map ( - CLKFBOUT => usrclk_mmcm_fb, - CLKFBOUTB => open, - CLKOUT0 => usrclk, - CLKOUT0B => open, - CLKOUT1 => usrclk_double, - CLKOUT1B => open, - CLKOUT2 => open, - CLKOUT2B => open, - CLKOUT3 => open, - CLKOUT3B => open, - CLKOUT4 => open, - CLKOUT5 => open, - CLKOUT6 => open, - CLKFBIN => usrclk_mmcm_fb, - CLKIN1 => usrclk_int, - CLKIN2 => '0', - CLKINSEL => '1', - DADDR => "0000000", - DCLK => '0', - DEN => '0', - DI => x"0000", - DO => open, - DRDY => open, - DWE => '0', - CDDCDONE => open, - CDDCREQ => '0', - PSCLK => '0', - PSEN => '0', - PSINCDEC => '0', - PSDONE => open, - LOCKED => USRCLK_LOCKED, - CLKINSTOPPED => open, - CLKFBSTOPPED => open, - PWRDWN => '0', - RST => not_usrclk_active - ); end architecture behavioral; diff --git a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xci b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xci deleted file mode 100644 index 983f2e5..0000000 --- a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xci +++ /dev/null @@ -1,1417 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - gth_xcku_x0y8 - - - "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000" - 1 - 2578.125 - 0 - 0 - 100 - 17 - 0 - 2 - 0 - 2 - 0 - 0 - 1 - 0 - 1 - 0 - 250 - 0 - 0 - 0 - 0 - 0 - 1 - "00000000" - "00000000" - 1 - 1 - 0 - "00000000000000000000000000000000000000000000000000000000000000000000000000000000" - "00000000" - 1 - "00100010" - 2 - 2 - 5000 - "00000000000000000000001011110000110001010000000000000000000000101111000001010000" - 1 - "1010000011" - 1 - "0101111100" - 1 - 1 - 20 - 2 - 8 - 1 - 100.0000000 - 1 - 0 - 0x000000000000000000000000000000000000000000000000 - 125 - 0 - 0 - 0 - 1 - 1 - 0 - 16 - 100.0000000 - 100.0000000 - 0 - 257.8125 - 1 - 1 - 1 - 0 - 0 - 0 - 100 - 0 - 0 - 1 - 1 - 1 - 20 - 2 - 8 - 1 - 100.0000000 - 1 - 0 - 125 - 0 - 0 - 1 - 1 - 0 - 16 - 100.0000000 - 100.0000000 - 0 - X0Y8 - gth_xcku_x0y8 - 0 - 0 - rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpmareset_in rxresetdone_out txresetdone_out - 100 - BOTH - 0 - GTH - 2 - 20 - 96 - 3 - gthe3 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - -1 - -1 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - -1 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - 1 - 1 - -1 - -1 - -1 - -1 - 1 - 1 - -1 - 1 - 1 - 1 - -1 - 1 - 1 - 1 - -1 - -1 - -1 - -1 - -1 - 1 - -1 - -1 - -1 - -1 - -1 - 1 - 1 - -1 - -1 - -1 - -1 - -1 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - -1 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - -1 - 0 - -1 - -1 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - -1 - -1 - 0 - 0 - -1 - 0 - -1 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - -1 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - -1 - -1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - -1 - 0 - 0 - 0 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - 0 - 0 - -1 - -1 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - -1 - 1 - 1 - 0 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - 0 - -1 - -1 - -1 - -1 - -1 - -1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 0 - -1 - -1 - -1 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - 0 - -1 - -1 - -1 - 0 - 0 - -1 - -1 - -1 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 1 - 1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - 14 - 0 - None - 8 - 100.0000000 - 1 - 1 - 100.0000000 - false - CORE - NONE - CORE - CORE - EXAMPLE_DESIGN - CORE - EXAMPLE_DESIGN - CORE - false - NAME - false - 250 - false - false - 250 - None - 0 - MULTI - 1 - ENABLE - DISABLE - ENABLE - 00000000 - false - false - false - false - false - false - false - false - 00000000 - false - false - false - false - false - false - false - false - 1 - 00000000 - false - false - false - false - false - false - false - false - 1 - 1 - 0 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000 - 00000000 - 00000000 - 00000000 - 00000000 - 00000000 - 00000000 - 00000000 - 00000000 - false - false - false - false - false - false - false - false - 00100010 - ENABLE - false - true - false - false - false - true - false - false - 2 - 00000000 - false - false - false - false - false - false - false - false - 2 - 5000 - ENABLE - 0 - 00000000000000000000001011110000110001010000000000000000000000101111000001010000 - 01010000 - 10111100 - 00000000 - 00000000 - 11000101 - 10111100 - 00000000 - 00000000 - 2 - false - 1111111111 - true - 1010000011 - K28.5 - true - 0101111100 - true - 0 - AC - 8B10B - true - AUTO - 20 - 1.19976 - -20 - 2 - X0Y8 - RXOUTCLKPMA - QPLL0 - 0 - 0 - - 125 - - OFF - 0 - PROGRAMMABLE - 800 - 16 - 15 - false - 0 - 10.3125 - 257.8125 - 1 - false - QPLL0 - 100 - 1 - ENABLE - 8B10B - CUSTOM - true - 20 - 2 - X0Y8 - TXOUTCLKPMA - QPLL0 - 0 - 125 - - 16 - false - 1 - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - true - true - true - false - false - false - false - false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - true - false - false - false - false - true - true - false - true - true - true - false - true - true - true - false - false - false - false - false - true - false - false - false - false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - false - true - true - true - true - false - false - false - false - false - true - false - false - false - false - false - false - false - false - false - false - false - false - false - true - false - true - true - false - false - true - true - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - false - false - false - true - true - false - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - false - false - false - false - false - false - true - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - false - false - false - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - false - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 8 - TRUE - . - - . - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xml b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xml deleted file mode 100644 index 6cc1bb2..0000000 --- a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xml +++ /dev/null @@ -1,22756 +0,0 @@ - - - xilinx.com - customized_ip - gth_xcku_x0y8 - 1.0 - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - gtwizard_ultrascale_v1_7_8_gtwizard_ultrascale - - - outputProductCRC - 9:3fc37fd2 - - - - - - - gtwiz_userclk_tx_reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_tx_active_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_userclk_tx_srcclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_tx_usrclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_tx_usrclk2_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_tx_active_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_rx_reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_rx_active_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_userclk_rx_srcclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_rx_usrclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_rx_usrclk2_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_rx_active_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_tx_reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_tx_start_user_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_tx_done_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_tx_error_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_rx_reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_rx_start_user_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_rx_done_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_rx_error_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_reset_clk_freerun_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_all_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_tx_pll_and_datapath_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_tx_datapath_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_rx_pll_and_datapath_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_rx_datapath_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_tx_done_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_reset_rx_done_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_reset_qpll0lock_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_reset_qpll1lock_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_reset_rx_cdr_stable_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_tx_done_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_rx_done_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_qpll0reset_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_reset_qpll1reset_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gthe3_cpll_cal_txoutclk_period_in - - in - - 17 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gthe3_cpll_cal_cnt_tol_in - - in - - 17 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gthe3_cpll_cal_bufg_ce_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gthe4_cpll_cal_txoutclk_period_in - - in - - 17 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gthe4_cpll_cal_cnt_tol_in - - in - - 17 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gthe4_cpll_cal_bufg_ce_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gtye4_cpll_cal_txoutclk_period_in - - in - - 17 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gtye4_cpll_cal_cnt_tol_in - - in - - 17 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gtye4_cpll_cal_bufg_ce_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userdata_tx_in - - in - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_userdata_rx_out - - out - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - bgbypassb_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - bgmonitorenb_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - bgpdb_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - bgrcalovrd_in - - in - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1F - - - - - - false - - - - - - bgrcalovrdenb_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - drpaddr_common_in - - in - - 8 - 0 - - - - wire - xilinx_elaborateports - - - - 0x000 - - - - - - false - - - - - - drpclk_common_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - drpdi_common_in - - in - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0000 - - - - - - false - - - - - - drpen_common_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - drpwe_common_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtgrefclk0_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtgrefclk1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtnorthrefclk00_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtnorthrefclk01_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtnorthrefclk10_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtnorthrefclk11_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtrefclk00_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtrefclk01_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtrefclk10_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtrefclk11_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtsouthrefclk00_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtsouthrefclk01_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtsouthrefclk10_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtsouthrefclk11_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - pcierateqpll0_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - pcierateqpll1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - pmarsvd0_in - - in - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - pmarsvd1_in - - in - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - qpll0clkrsvd0_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - qpll0clkrsvd1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - qpll0fbdiv_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - qpll0lockdetclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - qpll0locken_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - qpll0pd_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - qpll0refclksel_in - - in - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - qpll0reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - qpll1clkrsvd0_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - qpll1clkrsvd1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - qpll1fbdiv_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - qpll1lockdetclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - qpll1locken_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - qpll1pd_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - qpll1refclksel_in - - in - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - qpll1reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - qpllrsvd1_in - - in - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - qpllrsvd2_in - - in - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - qpllrsvd3_in - - in - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - qpllrsvd4_in - - in - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - rcalenb_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - sdm0data_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm0reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm0toggle_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm0width_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm1data_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm1reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm1toggle_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm1width_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - tcongpi_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - tconpowerup_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - tconreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - tconrsvdin1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubcfgstreamen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubdo_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubdrdy_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubenable_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubgpi_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubintr_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubiolmbrst_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubmbrst_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubmdmcapture_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubmdmdbgrst_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubmdmdbgupdate_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubmdmregen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubmdmshift_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubmdmsysrst_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubmdmtck_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubmdmtdi_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - drpdo_common_out - - out - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - drprdy_common_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pmarsvdout0_out - - out - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pmarsvdout1_out - - out - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - qpll0fbclklost_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - qpll0lock_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - qpll0outclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - qpll0outrefclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - qpll0refclklost_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - qpll1fbclklost_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - qpll1lock_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - qpll1outclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - qpll1outrefclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - qpll1refclklost_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - qplldmonitor0_out - - out - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - qplldmonitor1_out - - out - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - refclkoutmonitor0_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - refclkoutmonitor1_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxrecclk0_sel_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxrecclk1_sel_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxrecclk0sel_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxrecclk1sel_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm0finalout_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm0testdata_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm1finalout_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm1testdata_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - tcongpo_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - tconrsvdout0_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubdaddr_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubden_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubdi_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubdwe_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubmdmtdo_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubrsvdout_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - ubtxuart_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - cdrstepdir_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - cdrstepsq_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - cdrstepsx_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - cfgreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - clkrsvd0_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - clkrsvd1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - cpllfreqlock_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - cplllockdetclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - cplllocken_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - cpllpd_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - cpllrefclksel_in - - in - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - cpllreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - dmonfiforeset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - dmonitorclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - drpaddr_in - - in - - 8 - 0 - - - - wire - xilinx_elaborateports - - - - 0x000 - - - - - - false - - - - - - drpclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - drpdi_in - - in - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0000 - - - - - - false - - - - - - drpen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - drprst_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - drpwe_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - elpcaldvorwren_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - elpcalpaorwren_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - evoddphicaldone_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - evoddphicalstart_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - evoddphidrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - evoddphidwren_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - evoddphixrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - evoddphixwren_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - eyescanmode_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - eyescanreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - eyescantrigger_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - freqos_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtgrefclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gthrxn_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gthrxp_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtnorthrefclk0_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtnorthrefclk1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtrefclk0_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtrefclk1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtresetsel_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtrsvd_in - - in - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0000 - - - - - - false - - - - - - gtrxreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtrxresetsel_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtsouthrefclk0_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gtsouthrefclk1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - gttxreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gttxresetsel_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - incpctrl_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtyrxn_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtyrxp_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - loopback_in - - in - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - looprsvd_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - lpbkrxtxseren_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - lpbktxrxseren_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - pcieeqrxeqadaptdone_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - pcierstidle_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - pciersttxsyncstart_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - pcieuserratedone_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - pcsrsvdin_in - - in - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0000 - - - - - - false - - - - - - pcsrsvdin2_in - - in - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - pmarsvdin_in - - in - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - qpll0clk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - qpll0freqlock_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - qpll0refclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - qpll1clk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - qpll1freqlock_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - qpll1refclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - resetovrd_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rstclkentx_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rx8b10ben_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxafecfoken_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxbufreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxcdrfreqreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxcdrhold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxcdrovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxcdrreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - rxcdrresetrsv_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxchbonden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxchbondi_in - - in - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - rxchbondlevel_in - - in - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxchbondmaster_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxchbondslave_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxckcalreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxckcalstart_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxcommadeten_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxdfeagcctrl_in - - in - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - rxdccforcestart_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxdfeagchold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfeagcovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfecfokfcnum_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxdfecfokfen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxdfecfokfpulse_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxdfecfokhold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxdfecfokovren_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxdfekhhold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxdfekhovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxdfelfhold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfelfovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfelpmreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap10hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap10ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap11hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap11ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap12hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap12ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap13hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap13ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap14hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap14ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap15hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap15ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap2hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap2ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap3hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap3ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap4hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap4ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap5hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap5ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap6hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap6ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap7hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap7ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap8hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap8ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap9hold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfetap9ovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfeuthold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfeutovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfevphold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfevpovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfevsen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdfexyden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - rxdlybypass_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - rxdlyen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdlyovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxdlysreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxelecidlemode_in - - in - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0x3 - - - - - - false - - - - - - rxeqtraining_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxgearboxslip_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxlatclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxlpmen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxlpmgchold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxlpmgcovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxlpmhfhold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxlpmhfovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxlpmlfhold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxlpmlfklovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxlpmoshold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxlpmosovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxmcommaalignen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxmonitorsel_in - - in - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxoobreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxoscalreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxoshold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxosintcfg_in - - in - - 3 - 0 - - - - wire - xilinx_elaborateports - - - - 0xD - - - - - - false - - - - - - rxosinten_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - rxosinthold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxosintovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxosintstrobe_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxosinttestovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxosovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxoutclksel_in - - in - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0x2 - - - - - - false - - - - - - rxpcommaalignen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxpcsreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - rxpd_in - - in - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxphalign_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxphalignen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxphdlypd_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - rxphdlyreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxphovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxpllclksel_in - - in - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0x3 - - - - - - false - - - - - - rxpmareset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - rxpolarity_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxprbscntreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxprbssel_in - - in - - 3 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxprogdivreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - rxqpien_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxrate_in - - in - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxratemode_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxslide_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxslipoutclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxslippma_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxsyncallin_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxsyncin_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxsyncmode_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - rxsysclksel_in - - in - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0x2 - - - - - - false - - - - - - rxtermination_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxuserrdy_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - illegal - false - - - - - - rxusrclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxusrclk2_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - sigvalidclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - tstin_in - - in - - 19 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00000 - - - - - - false - - - - - - tx8b10bbypass_in - - in - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - tx8b10ben_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - txbufdiffctrl_in - - in - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txcominit_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txcomsas_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txcomwake_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txctrl0_in - - in - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - txctrl1_in - - in - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - txctrl2_in - - in - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - txdata_in - - in - - 127 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - txdataextendrsvd_in - - in - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - txdccforcestart_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - txdccreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - txdeemph_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txdetectrx_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txdiffctrl_in - - in - - 3 - 0 - - - - wire - xilinx_elaborateports - - - - 0xC - - - - - - false - - - - - - txdiffpd_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txdlybypass_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - txdlyen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txdlyhold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txdlyovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txdlysreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txdlyupdown_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txelecidle_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txelforcestart_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - txheader_in - - in - - 5 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - txinhibit_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txlatclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txlfpstreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - txlfpsu2lpexit_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - txlfpsu3wake_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - txmaincursor_in - - in - - 6 - 0 - - - - wire - xilinx_elaborateports - - - - 0x40 - - - - - - false - - - - - - txmargin_in - - in - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txmuxdcdexhold_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - txmuxdcdorwren_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - txoneszeros_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - txoutclksel_in - - in - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0x2 - - - - - - false - - - - - - txpcsreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - txpd_in - - in - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txpdelecidlemode_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txphalign_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txphalignen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txphdlypd_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - false - - - - - - txphdlyreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txphdlytstclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txphinit_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txphovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txpippmen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txpippmovrden_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txpippmpd_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txpippmsel_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txpippmstepsize_in - - in - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - txpisopd_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txpllclksel_in - - in - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0x3 - - - - - - false - - - - - - txpmareset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - txpolarity_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txpostcursor_in - - in - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - txpostcursorinv_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txprbsforceerr_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txprbssel_in - - in - - 3 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txprecursor_in - - in - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - txprecursorinv_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txprogdivreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - txqpibiasen_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txqpistrongpdown_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txqpiweakpup_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txrate_in - - in - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txratemode_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txsequence_in - - in - - 6 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - false - - - - - - txswing_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txsyncallin_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txsyncin_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txsyncmode_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - false - - - - - - txsysclksel_in - - in - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0x2 - - - - - - false - - - - - - txuserrdy_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - illegal - false - - - - - - txusrclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - txusrclk2_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - bufgtce_out - - out - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - bufgtcemask_out - - out - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - bufgtdiv_out - - out - - 8 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - bufgtreset_out - - out - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - bufgtrstmask_out - - out - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - cpllfbclklost_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - cplllock_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - cpllrefclklost_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - dmonitorout_out - - out - - 16 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - dmonitoroutclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - drpdo_out - - out - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - drprdy_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - eyescandataerror_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - gthtxn_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gthtxp_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtpowergood_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtrefclkmonitor_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - gtytxn_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtytxp_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - pcierategen3_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcierateidle_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcierateqpllpd_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcierateqpllreset_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pciesynctxsyncdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcieusergen3rdy_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcieuserphystatusrst_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcieuserratestart_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcsrsvdout_out - - out - - 11 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - phystatus_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pinrsrvdas_out - - out - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - powerpresent_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - resetexception_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxbufstatus_out - - out - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxbyteisaligned_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxbyterealign_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxcdrlock_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxcdrphdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxchanbondseq_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxchanisaligned_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxchanrealign_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxchbondo_out - - out - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxckcaldone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxclkcorcnt_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxcominitdet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxcommadet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxcomsasdet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxcomwakedet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxctrl0_out - - out - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxctrl1_out - - out - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxctrl2_out - - out - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxctrl3_out - - out - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxdata_out - - out - - 127 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxdataextendrsvd_out - - out - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxdatavalid_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxdlysresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxelecidle_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxheader_out - - out - - 5 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxheadervalid_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxlfpstresetdet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxlfpsu2lpexitdet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxlfpsu3wakedet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxmonitorout_out - - out - - 6 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxosintdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxosintstarted_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxosintstrobedone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxosintstrobestarted_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxoutclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxoutclkfabric_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxoutclkpcs_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxphaligndone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxphalignerr_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxpmaresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxprbserr_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxprbslocked_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxprgdivresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxqpisenn_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxqpisenp_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxratedone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxrecclkout_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - rxsliderdy_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxslipdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxslipoutclkrdy_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxslippmardy_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxstartofseq_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxstatus_out - - out - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxsyncdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxsyncout_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxvalid_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txbufstatus_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txcomfinish_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txdccdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - txdlysresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txoutclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - txoutclkfabric_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txoutclkpcs_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txphaligndone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txphinitdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txpmaresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - txprgdivresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txqpisenn_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txqpisenp_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txratedone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - txsyncdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txsyncout_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - - - C_CHANNEL_ENABLE - "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000" - - - C_PCIE_ENABLE - 0 - - - C_PCIE_CORECLK_FREQ - 250 - - - C_COMMON_SCALING_FACTOR - 1 - - - C_CPLL_VCO_FREQUENCY - 2578.125 - - - C_FORCE_COMMONS - 0 - - - C_FREERUN_FREQUENCY - 100 - - - C_GT_TYPE - 0 - - - C_GT_REV - 17 - - - C_INCLUDE_CPLL_CAL - 2 - - - C_ENABLE_COMMON_USRCLK - 0 - - - C_USER_GTPOWERGOOD_DELAY_EN - 0 - - - C_SIM_CPLL_CAL_BYPASS - 1 - - - C_LOCATE_COMMON - 0 - - - C_LOCATE_RESET_CONTROLLER - 0 - - - C_LOCATE_USER_DATA_WIDTH_SIZING - 0 - - - C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER - 0 - - - C_LOCATE_IN_SYSTEM_IBERT_CORE - 2 - - - C_LOCATE_RX_USER_CLOCKING - 1 - - - C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER - 0 - - - C_LOCATE_TX_USER_CLOCKING - 1 - - - C_RESET_CONTROLLER_INSTANCE_CTRL - 0 - - - C_RX_BUFFBYPASS_MODE - 0 - - - C_RX_BUFFER_BYPASS_INSTANCE_CTRL - 0 - - - C_RX_BUFFER_MODE - 1 - - - C_RX_CB_DISP - "00000000" - - - C_RX_CB_K - "00000000" - - - C_RX_CB_MAX_LEVEL - 1 - - - C_RX_CB_LEN_SEQ - 1 - - - C_RX_CB_NUM_SEQ - 0 - - - C_RX_CB_VAL - "00000000000000000000000000000000000000000000000000000000000000000000000000000000" - - - C_RX_CC_DISP - "00000000" - - - C_RX_CC_ENABLE - 1 - - - C_RESET_SEQUENCE_INTERVAL - 0 - - - C_RX_CC_K - "00100010" - - - C_RX_CC_LEN_SEQ - 2 - - - C_RX_CC_NUM_SEQ - 2 - - - C_RX_CC_PERIODICITY - 5000 - - - C_RX_CC_VAL - "00000000000000000000001011110000110001010000000000000000000000101111000001010000" - - - C_RX_COMMA_M_ENABLE - 1 - - - C_RX_COMMA_M_VAL - "1010000011" - - - C_RX_COMMA_P_ENABLE - 1 - - - C_RX_COMMA_P_VAL - "0101111100" - - - C_RX_DATA_DECODING - 1 - - - C_RX_ENABLE - 1 - - - C_RX_INT_DATA_WIDTH - 20 - - - C_RX_LINE_RATE - 2 - - - C_RX_MASTER_CHANNEL_IDX - 8 - - - C_RX_OUTCLK_BUFG_GT_DIV - 1 - - - C_RX_OUTCLK_FREQUENCY - 100.0000000 - - - C_RX_OUTCLK_SOURCE - 1 - - - C_RX_PLL_TYPE - 0 - - - C_RX_RECCLK_OUTPUT - 0x000000000000000000000000000000000000000000000000 - - - C_RX_REFCLK_FREQUENCY - 125 - - - C_RX_SLIDE_MODE - 0 - - - C_RX_USER_CLOCKING_CONTENTS - 0 - - - C_RX_USER_CLOCKING_INSTANCE_CTRL - 0 - - - C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK - 1 - - - C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 - 1 - - - C_RX_USER_CLOCKING_SOURCE - 0 - - - C_RX_USER_DATA_WIDTH - 16 - - - C_RX_USRCLK_FREQUENCY - 100.0000000 - - - C_RX_USRCLK2_FREQUENCY - 100.0000000 - - - C_SECONDARY_QPLL_ENABLE - 0 - - - C_SECONDARY_QPLL_REFCLK_FREQUENCY - 257.8125 - - - C_TOTAL_NUM_CHANNELS - 1 - - - C_TOTAL_NUM_COMMONS - 1 - - - C_TOTAL_NUM_COMMONS_EXAMPLE - 0 - - - C_TXPROGDIV_FREQ_ENABLE - 0 - - - C_TXPROGDIV_FREQ_SOURCE - 0 - - - C_TXPROGDIV_FREQ_VAL - 100 - - - C_TX_BUFFBYPASS_MODE - 0 - - - C_TX_BUFFER_BYPASS_INSTANCE_CTRL - 0 - - - C_TX_BUFFER_MODE - 1 - - - C_TX_DATA_ENCODING - 1 - - - C_TX_ENABLE - 1 - - - C_TX_INT_DATA_WIDTH - 20 - - - C_TX_LINE_RATE - 2 - - - C_TX_MASTER_CHANNEL_IDX - 8 - - - C_TX_OUTCLK_BUFG_GT_DIV - 1 - - - C_TX_OUTCLK_FREQUENCY - 100.0000000 - - - C_TX_OUTCLK_SOURCE - 1 - - - C_TX_PLL_TYPE - 0 - - - C_TX_REFCLK_FREQUENCY - 125 - - - C_TX_USER_CLOCKING_CONTENTS - 0 - - - C_TX_USER_CLOCKING_INSTANCE_CTRL - 0 - - - C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK - 1 - - - C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 - 1 - - - C_TX_USER_CLOCKING_SOURCE - 0 - - - C_TX_USER_DATA_WIDTH - 16 - - - C_TX_USRCLK_FREQUENCY - 100.0000000 - - - C_TX_USRCLK2_FREQUENCY - 100.0000000 - - - - - - choice_list_00d9575a - 16 - 32 - 64 - - - choice_list_0fbde0c1 - 20 - - - choice_list_13717074 - -20 - -40 - - - choice_list_1fad77c0 - RXOUTCLKPMA - RXOUTCLKPCS - RXPROGDIVCLK - - - choice_list_24871ac1 - AC - DC - - - choice_list_305f448a - TXOUTCLKPMA - TXOUTCLKPCS - TXPROGDIVCLK - - - choice_list_3179277f - QPLL0 - QPLL1 - CPLL - - - choice_list_556e59ba - 0 - 100 - 200 - 300 - 400 - 500 - 600 - 700 - 800 - 900 - 1000 - 1100 - 1200 - 1300 - 1400 - 1500 - 1600 - 1700 - 1800 - 1900 - 2000 - 2100 - 2200 - 2300 - 2400 - 2500 - 2600 - 2700 - 2800 - 2900 - 3000 - 3100 - 3200 - 3300 - 3400 - 3500 - 3600 - 3700 - 3800 - 3900 - 4000 - 4100 - 4200 - 4300 - 4400 - 4500 - 4600 - 4700 - 4800 - 4900 - 5000 - 5100 - 5200 - 5300 - 5400 - 5500 - 5600 - 5700 - 5800 - 5900 - 6000 - 6100 - 6200 - 6300 - 6400 - 6500 - 6600 - 6700 - 6800 - 6900 - 7000 - 7100 - 7200 - 7300 - 7400 - 7500 - 7600 - 7700 - 7800 - 7900 - 8000 - 8100 - 8200 - 8300 - 8400 - 8500 - 8600 - 8700 - 8800 - 8900 - 9000 - 9100 - 9200 - 9300 - 9400 - 9500 - 9600 - 9700 - 9800 - 9900 - 10000 - - - choice_list_6b979ebc - 250 - - - choice_list_7612b160 - X0Y8 - - - choice_list_98c4d361 - 257.8125 - - - choice_list_a0d11b39 - 100 - 200 - 250 - 300 - 350 - 400 - 500 - 550 - 600 - 700 - 800 - 850 - 900 - 950 - 1000 - 1100 - - - choice_list_a533ccf9 - 250 - 125 - 62.5 - - - choice_list_afcf1f92 - GTH - - - choice_list_b0901792 - 100 - 200 - 400 - - - choice_list_be18be20 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - - - choice_list_d3562949 - 100 - 100.6289308 - 101.2658228 - 101.910828 - 102.5641026 - 103.2258065 - 103.8961039 - 104.5751634 - 105.2631579 - 105.9602649 - 106.6666667 - 107.3825503 - 108.1081081 - 108.8435374 - 109.5890411 - 110.3448276 - 111.1111111 - 111.8881119 - 112.6760563 - 113.4751773 - 114.2857143 - 115.1079137 - 115.942029 - 116.7883212 - 117.6470588 - 118.5185185 - 119.4029851 - 120.3007519 - 121.2121212 - 122.1374046 - 123.0769231 - 124.0310078 - 125 - 125.984252 - 126.984127 - 128 - 129.0322581 - 130.0813008 - 131.147541 - 132.231405 - 133.3333333 - 134.4537815 - 135.5932203 - 136.7521368 - 137.9310345 - 139.1304348 - 140.3508772 - 141.5929204 - 142.8571429 - 144.1441441 - 145.4545455 - 146.7889908 - 148.1481481 - 149.5327103 - 150.9433962 - 152.3809524 - 153.8461538 - 155.3398058 - 156.8627451 - 158.4158416 - 160 - 161.6161616 - 163.2653061 - 164.9484536 - 166.6666667 - 168.4210526 - 170.212766 - 172.0430108 - 173.9130435 - 175.8241758 - 177.7777778 - 179.7752809 - 181.8181818 - 183.908046 - 186.0465116 - 188.2352941 - 190.4761905 - 192.7710843 - 195.1219512 - 197.5308642 - 200 - 201.2578616 - 202.5316456 - 203.8216561 - 205.1282051 - 206.4516129 - 207.7922078 - 209.1503268 - 210.5263158 - 211.9205298 - 213.3333333 - 214.7651007 - 216.2162162 - 217.6870748 - 219.1780822 - 220.6896552 - 222.2222222 - 223.7762238 - 225.3521127 - 226.9503546 - 228.5714286 - 230.2158273 - 231.884058 - 233.5766423 - 235.2941176 - 237.037037 - 238.8059701 - 240.6015038 - 242.4242424 - 244.2748092 - 246.1538462 - 248.0620155 - 250 - 251.9685039 - 253.968254 - 256 - 258.0645161 - 260.1626016 - 262.295082 - 264.4628099 - 266.6666667 - 268.907563 - 271.1864407 - 273.5042735 - 275.862069 - 278.2608696 - 280.7017544 - 283.1858407 - 285.7142857 - 288.2882883 - 290.9090909 - 293.5779817 - 296.2962963 - 299.0654206 - 300 - 301.8867925 - 303.7974684 - 304.7619048 - 305.7324841 - 307.6923077 - 309.6774194 - 310.6796117 - 311.6883117 - 313.7254902 - 315.7894737 - 316.8316832 - 317.8807947 - 320 - 322.147651 - 323.2323232 - 324.3243243 - 326.5306122 - 328.7671233 - 329.8969072 - 331.0344828 - 333.3333333 - 335.6643357 - 336.8421053 - 338.028169 - 340.4255319 - 342.8571429 - 344.0860215 - 345.323741 - 347.826087 - 350.3649635 - 351.6483516 - 352.9411765 - 355.5555556 - 358.2089552 - 359.5505618 - 360.9022556 - 363.6363636 - 366.4122137 - 367.816092 - 369.2307692 - 372.0930233 - 375 - 376.4705882 - 377.9527559 - 380.952381 - 384 - 385.5421687 - 387.0967742 - 390.2439024 - 393.442623 - 395.0617284 - 396.6942149 - 400 - 402.5157233 - 403.3613445 - 405.0632911 - 406.779661 - 407.6433121 - 410.2564103 - 412.9032258 - 413.7931034 - 415.5844156 - 417.3913043 - 418.3006536 - 421.0526316 - 423.8410596 - 424.7787611 - 426.6666667 - 428.5714286 - 429.5302013 - 432.4324324 - 435.3741497 - 436.3636364 - 438.3561644 - 440.3669725 - 441.3793103 - 444.4444444 - 447.5524476 - 448.5981308 - 450.7042254 - 452.8301887 - 453.9007092 - 457.1428571 - 460.4316547 - 461.5384615 - 463.7681159 - 466.0194175 - 467.1532847 - 470.5882353 - 474.0740741 - 475.2475248 - 477.6119403 - 480 - 481.2030075 - 484.8484848 - 488.5496183 - 489.7959184 - 492.3076923 - 494.8453608 - 496.124031 - 500 - 503.9370079 - 505.2631579 - 507.9365079 - 510.6382979 - 512 - 516.1290323 - 520.3252033 - 521.7391304 - 524.5901639 - 527.4725275 - 528.9256198 - 533.3333333 - 537.8151261 - 539.3258427 - 542.3728814 - 545.4545455 - 547.008547 - 551.7241379 - 556.5217391 - 558.1395349 - 561.4035088 - 564.7058824 - 566.3716814 - 571.4285714 - 576.5765766 - 578.313253 - 581.8181818 - 585.3658537 - 587.1559633 - 592.5925926 - 598.1308411 - 600 - 603.7735849 - 607.5949367 - 609.5238095 - 615.3846154 - 621.3592233 - 623.3766234 - 627.4509804 - 631.5789474 - 633.6633663 - 640 - 646.4646465 - 648.6486486 - 653.0612245 - 657.5342466 - 659.7938144 - 666.6666667 - 673.6842105 - 676.056338 - 680.8510638 - 685.7142857 - 688.172043 - 695.6521739 - 703.2967033 - 705.8823529 - 711.1111111 - 716.4179104 - 719.1011236 - 727.2727273 - 735.6321839 - 738.4615385 - 744.1860465 - 750 - 752.9411765 - 761.9047619 - 771.0843373 - 774.1935484 - 780.4878049 - 786.8852459 - 790.1234568 - 800 - 810.1265823 - 813.559322 - - - choice_list_e6469819 - 1 - 2 - 4 - - - choice_list_ed5e3eb0 - QPLL0 - - - choice_pairs_03018cc1 - 1 - 2 - 0 - - - choice_pairs_0c77e1fe - 0 - 1 - - - choice_pairs_1040277f - AVTT - FLOAT - GND - PROGRAMMABLE - - - choice_pairs_1436b008 - MULTI - SINGLE - - - choice_pairs_1ebf969f - None - GTH-10GBASE-KR - GTH-10GBASE-R - GTH-12G_SDI - GTH-1G_10G_25G_switchable - GTH-3G_SDI - GTH-Aurora_64B66B - GTH-Aurora_8B10B - GTH-Bandwidth_Engine - GTH-CAUI_10 - GTH-CEI_11G_SR - GTH-CPRI_10G - GTH-CPRI_10_1G - GTH-CPRI_3G - GTH-CPRI_6G - GTH-DisplayPort_1_62G - GTH-DisplayPort_2_7G - GTH-DisplayPort_5_4G - GTH-Gigabit_Ethernet - GTH-HDMI - GTH-HD_SDI - GTH-HMC_12_5G - GTH-Interlaken_10G - GTH-Interlaken_12_5G - GTH-Interlaken_6_25G - GTH-JESD204 - GTH-JESD204_3_125G - GTH-JESD204_6_375G - GTH-OTL4_10 - GTH-OTU2 - GTH-OTU2e - GTH-QSGMII - GTH-RXAUI - GTH-SATA - GTH-SRIO_Gen2 - GTH-XAUI - GTH-XLAUI - - - choice_pairs_40d02874 - 10GBASE_KR - CUSTOM - PCIE_GEN1_GEN2 - PCIE_GEN3 - QPI - - - choice_pairs_4e550952 - NONE - EXAMPLE_DESIGN - - - choice_pairs_7b0c3758 - RX - BOTH - TX - - - choice_pairs_85f99b7f - K28.1 - K28.5 - NONE - - - choice_pairs_8846c8f0 - RAW - 8B10B - 64B66B - 64B66B_CAUI - 64B66B_ASYNC - 64B66B_ASYNC_CAUI - 64B67B - 64B67B_CAUI - - - choice_pairs_88c85933 - 8B10B - 64B66B_ASYNC - 64B66B_ASYNC_CAUI - RAW - 64B66B - 64B66B_CAUI - 64B67B - 64B67B_CAUI - - - choice_pairs_93c2d4ee - CORE - EXAMPLE_DESIGN - - - choice_pairs_9c19f015 - 1 - 2 - - - choice_pairs_a537ddda - 0 - 1 - - - choice_pairs_aa541099 - AUTO - DFE - LPM - - - choice_pairs_ae574462 - OFF - PCS - PMA - AUTO - - - choice_pairs_b0974ef0 - 1 - 2 - 0 - - - choice_pairs_d4feb97d - DISABLE - ENABLE - - - choice_pairs_f05b8192 - CHANNEL - NAME - - - The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. - - - GT_TYPE - Transceiver type - For devices which contain more than one serial transceiver type, select the type of transceiver to configure - GTH - - - INTERNAL_GT_PRIM_TYPE - gthe3 - - - - false - - - - - - GT_REV - Transceiver revision - Select the serial transceiver silicon revision - 0 - - - GT_DIRECTION - Transmit and/or Receive direction - Enable transmit and/or receive - BOTH - - - RX_ENABLE - Enabled - Enable the receiver for use - true - - - - false - - - - - - TX_ENABLE - Enabled - Enable the transmitter for use - true - - - - false - - - - - - CHANNEL_ENABLE - Enable channel - Indicate whether this transceiver channel is instantiated and enabled for use - X0Y8 - - - TX_MASTER_CHANNEL - Master TX channel - Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 - - - - false - - - - - - RX_MASTER_CHANNEL - Master RX channel - Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 - - - - false - - - - - - INTERNAL_TOTAL_NUM_CHANNELS - Total number of channels - 1 - - - - false - - - - - - INTERNAL_TOTAL_NUM_COMMONS - Total number of commons required - 1 - - - - false - - - - - - LOCATE_COMMON - Include transceiver COMMON in the - If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. - CORE - - - INTERNAL_NUM_COMMONS_CORE - Number of commons in core - 1 - - - - false - - - - - - INTERNAL_NUM_COMMONS_EXAMPLE - Number of commons in example - 0 - - - - false - - - - - - INTERNAL_TX_USRCLK_FREQUENCY - 100.0000000 - - - - false - - - - - - INTERNAL_RX_USRCLK_FREQUENCY - 100.0000000 - - - - false - - - - - - RX_PPM_OFFSET - PPM offset between receiver and transmitter - Specify the PPM offset between received data and transmitted data - 0 - - - OOB_ENABLE - Enable Out of Band signaling (OOB)/Electrical Idle - Enable or disable Out of Band signaling (OOB)/Electrical Idle - false - - - - false - - - - - - RX_SSC_PPM - Spread spectrum clocking - Specify the spread spectrum clocking modulation in PPM - 0 - - - INS_LOSS_NYQ - Insertion loss at Nyquist (dB) - Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB - 20 - - - PCIE_CORECLK_FREQ - 250 - - - PCIE_USERCLK_FREQ - 250 - - - TX_LINE_RATE - Line rate (Gb/s) - Enter the transmitter line rate in Gb/s - 2 - - - TX_PLL_TYPE - PLL type - Select the transmitter PLL type - QPLL0 - - - TX_REFCLK_FREQUENCY - Actual Reference clock (MHz) - Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type - 125 - - - TX_DATA_ENCODING - Encoding - Select the encoding format for data transmission, or choose 'Raw' for no data encoding - 8B10B - - - TX_USER_DATA_WIDTH - User data width - Select the width at which the user logic will provide parallel data to the serial transceiver for transmission - 16 - - - TX_INT_DATA_WIDTH - Internal data width - Select the width of the serial transceiver internal transmitter data path - 20 - - - TX_BUFFER_MODE - Buffer - Select whether to enable or to bypass the transmitter buffer - 1 - - - TX_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection - 0 - - - - false - - - - - - TX_OUTCLK_SOURCE - TXOUTCLK source - Select the source of TXOUTCLK - TXOUTCLKPMA - - - TX_DIFF_SWING_EMPH_MODE - Differential swing and emphasis mode - Select the transmitter differential swing and emphasis mode for your application - CUSTOM - - - RX_LINE_RATE - Line rate (Gb/s) - Enter the receiver line rate in Gb/s - 2 - - - RX_PLL_TYPE - PLL type - Select the receiver PLL type - QPLL0 - - - RX_REFCLK_FREQUENCY - Actual Reference clock (MHz) - Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type - 125 - - - RX_DATA_DECODING - Decoding - Select the decoding format for data reception, or choose 'Raw' for no data decoding - 8B10B - - - RX_USER_DATA_WIDTH - User data width - Select the width at which the serial transceiver will provide received parallel data to the user logic - 16 - - - RX_INT_DATA_WIDTH - Internal data width - Select the width of the serial transceiver internal receiver data path - 20 - - - RX_BUFFER_MODE - Buffer - Select whether to enable or to bypass the receiver elastic buffer - 1 - - - RX_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection - 0 - - - - false - - - - - - RX_EQ_MODE - Equalization mode - Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. - AUTO - - - RX_JTOL_FC - Mask corner frequency (MHz) - Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. - 1.19976 - - - RX_JTOL_LF_SLOPE - Mask low frequency slope (dB/decade) - Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. - -20 - - - RX_OUTCLK_SOURCE - RXOUTCLK source - Select the source of RXOUTCLK - RXOUTCLKPMA - - - SIM_CPLL_CAL_BYPASS - 1 - - - PCIE_ENABLE - false - - - RX_TERMINATION - Termination - Select the receiver termination - PROGRAMMABLE - - - RX_TERMINATION_PROG_VALUE - Programmable termination voltage (mV) - Select the termination voltage (in mV) when in programmable mode - 800 - - - RX_COUPLING - Link coupling - Select the link coupling - AC - - - RX_BUFFER_BYPASS_MODE - Receiver elastic buffer bypass mode - Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode - MULTI - - - - false - - - - - - RX_BUFFER_RESET_ON_CB_CHANGE - Reset receiver elastic buffer on channel bonding change - Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL - ENABLE - - - - false - - - - - - RX_BUFFER_RESET_ON_COMMAALIGN - Reset receiver elastic buffer on comma alignment - Control whether the receiver elastic buffer is reset on comma alignment - DISABLE - - - RX_BUFFER_RESET_ON_RATE_CHANGE - Reset receiver elastic buffer on rate change - Control whether the receiver elastic buffer is reset on rate change - ENABLE - - - TX_BUFFER_RESET_ON_RATE_CHANGE - Reset transmitter buffer on rate change - Control whether the transmitter buffer is reset on rate change - ENABLE - - - RESET_SEQUENCE_INTERVAL - Reset sequence time interval (ns) - Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval - 0 - - - RX_COMMA_PRESET - Comma value preset - K28.5 - - - RX_COMMA_VALID_ONLY - Valid comma values for 8B/10B decoding - Select the range of comma characters decoded by the 8B/10B decoder - 0 - - - RX_COMMA_P_ENABLE - Detect plus comma - Indicate whether or not the specified bit pattern is detected as a plus comma - true - - - RX_COMMA_M_ENABLE - Detect minus comma - Indicate whether or not the specified bit pattern is detected as a minus comma - true - - - RX_COMMA_DOUBLE_ENABLE - Detect combined plus/minus (double-length) comma - Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence - false - - - RX_COMMA_P_VAL - Plus comma value - Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received - 0101111100 - - - RX_COMMA_M_VAL - Minus comma value - Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received - 1010000011 - - - RX_COMMA_MASK - Mask - Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" - 1111111111 - - - RX_COMMA_ALIGN_WORD - Alignment boundary - Select which data byte boundaries are allowed for comma alignment - 2 - - - RX_COMMA_SHOW_REALIGN_ENABLE - Show realign comma - Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency - true - - - RX_SLIDE_MODE - Manual alignment (RXSLIDE) mode - Select whether to enable manual alignment, and in what mode if enabled - OFF - - - RX_CB_NUM_SEQ - Enable and select number of sequences to use - Select whether to enable channel bonding, and how many sequences to use if enabled - 0 - - - - false - - - - - - RX_CB_LEN_SEQ - Length of each sequence - Select the number of characters in each channel bonding sequence - 1 - - - - false - - - - - - RX_CB_MAX_SKEW - Sequence maximum skew - Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence - 1 - - - - false - - - - - - RX_CB_MAX_LEVEL - Maximum channel bonding level to be used - Select the maximum channel bonding level that will be used in the system channel bonding topology - 1 - - - - false - - - - - - RX_CB_MASK - 00000000 - - - - false - - - - - - RX_CB_VAL - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - - - - false - - - - - - RX_CB_K - 00000000 - - - - false - - - - - - RX_CB_DISP - 00000000 - - - - false - - - - - - RX_CB_MASK_0_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_0 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_0 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_0 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_1 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_1 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_1 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_2 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_2 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_2 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_3 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_3 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_3 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_0 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_0 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_0 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_1 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_1 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_1 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_2 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_2 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_2 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_3 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_3 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_3 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CC_NUM_SEQ - Enable and select number of sequences to use - Select whether to enable clock correction, and how many sequences to use if enabled - 2 - - - RX_CC_LEN_SEQ - Length of each sequence - Select the number of characters in each channel clock correction sequence - 2 - - - RX_CC_PERIODICITY - Periodicity of the sequence (in bytes) - Specify the separation between clock correction sequences, in bytes - 5000 - - - RX_CC_KEEP_IDLE - Keep idle - Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received - ENABLE - - - RX_CC_PRECEDENCE - Precedence - Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time - ENABLE - - - - false - - - - - - RX_CC_REPEAT_WAIT - Minimum repetition - Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction - 0 - - - RX_CC_MASK - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - 00000000 - - - - false - - - - - - RX_CC_VAL - 00000000000000000000001011110000110001010000000000000000000000101111000001010000 - - - RX_CC_K - 00100010 - - - - false - - - - - - RX_CC_DISP - 00000000 - - - - false - - - - - - RX_CC_MASK_0_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_0 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_0_0 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_0_0 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_1 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_0_1 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_0_1 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - - false - - - - - - RX_CC_VAL_0_2 - Value - Specify the value for this clock correction sequence and pattern - 00000000 - - - - false - - - - - - RX_CC_K_0_2 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - - false - - - - - - RX_CC_DISP_0_2 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CC_MASK_0_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - - false - - - - - - RX_CC_VAL_0_3 - Value - Specify the value for this clock correction sequence and pattern - 00000000 - - - - false - - - - - - RX_CC_K_0_3 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - - false - - - - - - RX_CC_DISP_0_3 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CC_MASK_1_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_0 - Value - Specify the value for this clock correction sequence and pattern - 11000101 - - - RX_CC_K_1_0 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_1_0 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_1 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_1_1 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_1_1 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - - false - - - - - - RX_CC_VAL_1_2 - Value - Specify the value for this clock correction sequence and pattern - 00000000 - - - - false - - - - - - RX_CC_K_1_2 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - - false - - - - - - RX_CC_DISP_1_2 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CC_MASK_1_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - - false - - - - - - RX_CC_VAL_1_3 - Value - Specify the value for this clock correction sequence and pattern - 00000000 - - - - false - - - - - - RX_CC_K_1_3 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - - false - - - - - - RX_CC_DISP_1_3 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - ENABLE_OPTIONAL_PORTS - Enable optional ports - Indicate whether a port should be included - rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpmareset_in rxresetdone_out txresetdone_out - - - RX_REFCLK_SOURCE - Receiver reference clock source - Select a reference clock input to drive the PLL chosen for receiver operation - - - - TX_REFCLK_SOURCE - Transmitter reference clock source - Select a reference clock input to drive the PLL chosen for transmitter operation - - - - RX_RECCLK_OUTPUT - Drive recovered clock out of device - Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use - - - - LOCATE_RESET_CONTROLLER - Include reset controller in the - Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - LOCATE_TX_BUFFER_BYPASS_CONTROLLER - Include transmitter buffer bypass controller in the - If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - - false - - - - - - LOCATE_RX_BUFFER_BYPASS_CONTROLLER - Include receiver elastic buffer bypass controller in the - If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - - false - - - - - - LOCATE_IN_SYSTEM_IBERT_CORE - Include In-System IBERT core - Indicate whether or not the In-System IBERT core should be instantiated in the example design. - NONE - - - LOCATE_TX_USER_CLOCKING - Include simple transmitter user clocking network in the - Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. - EXAMPLE_DESIGN - - - LOCATE_RX_USER_CLOCKING - Include simple receiver user clocking network in the - Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. - EXAMPLE_DESIGN - - - LOCATE_USER_DATA_WIDTH_SIZING - Include user data width sizing in the - Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - ORGANIZE_PORTS_BY - In the example design, organize ports across multiple channels by - If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) - NAME - - - - false - - - - - - PRESET - Transceiver configuration preset - You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard - None - - - INTERNAL_PRESET - Transceiver configuration preset - None - - - INTERNAL_PORT_USAGE_UPDATED - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLEMENT_UPDATED - 14 - - - - false - - - - - - INTERNAL_CHANNEL_SITES_UPDATED - 3 - - - - false - - - - - - INTERNAL_CHANNEL_COLUMN_LOC_MAX - 96 - - - - false - - - - - - INTERNAL_RX_COMMA_PRESET_UPDATE - 8 - - - - false - - - - - - INTERNAL_UPDATE_IP_SYMBOL_drpclk_in - false - - - - false - - - - - - SECONDARY_QPLL_ENABLE - Enable secondary QPLL - Enable and configure the QPLL which is not used in this core configuration - false - - - SECONDARY_QPLL_LINE_RATE - Line rate of second core (Gb/s) - Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL - 10.3125 - - - - false - - - - - - SECONDARY_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection - 0 - - - - false - - - - - - SECONDARY_QPLL_REFCLK_FREQUENCY - Actual Reference clock frequency (MHz) - Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate - 257.8125 - - - - false - - - - - - TXPROGDIV_FREQ_ENABLE - Enable selectable TXOUTCLK frequency - Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency - false - - - - false - - - - - - TXPROGDIV_FREQ_SOURCE - Programmable divider clock source - Select which PLL source is used to generate the selectable TXOUTCLK frequency - QPLL0 - - - - false - - - - - - TXPROGDIV_FREQ_VAL - TXOUTCLK frequency (MHz) - Select the TXOUTCLK frequency to be generated by the TX programmable divider - 100 - - - - false - - - - - - SATA_TX_BURST_LEN - TX COM sequence burst length - Select the number of bursts that make up a SATA COM sequence - 15 - - - FREERUN_FREQUENCY - Free-running and DRP clock frequency (MHz) - Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface - 100 - - - INCLUDE_CPLL_CAL - 2 - - - USER_GTPOWERGOOD_DELAY_EN - Select 1 to enable powergood delay circuit - 1 - - - DISABLE_LOC_XDC - Select to disable generation of LOC constraints in xdc - 0 - - - ENABLE_COMMON_USRCLK - 0 - - - USB_ENABLE - false - - - PCIE_64BIT - false - - - PCIE_GEN4_EIOS - false - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGBYPASSB_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGMONITORENB_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGPDB_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGRCALOVRD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK00_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK01_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK10_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK11_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVD0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVD1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0PD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1PD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1RESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD2_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD3_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD4_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RCALENB_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0DATA_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0WIDTH_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1DATA_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1WIDTH_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONGPI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONPOWERUP_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDO_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDRDY_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBENABLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBGPI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBINTR_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBIOLMBRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMBRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMREGEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTDI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK1SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0FINALOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0TESTDATA_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1FINALOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1TESTDATA_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONGPO_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRSVDOUT0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDADDR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDEN_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDI_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDWE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTDO_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBTXUART_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CDRSTEPDIR_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CDRSTEPSQ_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CDRSTEPSX_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CFGRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CLKRSVD0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CLKRSVD1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLFREQLOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLLOCKDETCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLLOCKEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLPD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLREFCLKSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DMONFIFORESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DMONITORCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPADDR_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDI_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPWE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_ELPCALDVORWREN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_ELPCALPAORWREN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHICALDONE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANMODE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_FREQOS_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTHRXN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTHRXP_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRESETSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRSVD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRXRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRXRESETSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTTXRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTTXRESETSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_INCPCTRL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTYRXN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTYRXP_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LOOPBACK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LOOPRSVD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LPBKRXTXSEREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LPBKTXRXSEREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIEEQRXEQADAPTDONE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERSTIDLE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERSTTXSYNCSTART_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIEUSERRATEDONE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCSRSVDIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCSRSVDIN2_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FREQLOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FREQLOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RESETOVRD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RSTCLKENTX_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RX8B10BEN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXAFECFOKEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXBUFRESET_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDRFREQRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDRHOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDROVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDRRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDRRESETRSV_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHBONDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHBONDI_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHBONDLEVEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHBONDMASTER_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHBONDSLAVE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCKCALRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCKCALSTART_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCOMMADETEN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFEAGCCTRL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDCCFORCESTART_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFEAGCHOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFEAGCOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFECFOKFCNUM_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFECFOKFEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFECFOKFPULSE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFECFOKHOLD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFECFOKOVREN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFEKHHOLD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFEKHOVRDEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFELFHOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFELFOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFELPMRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP10HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP10OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP11HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP11OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP12HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP12OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP13HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP13OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP14HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP14OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP15HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP15OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP2HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP2OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP3HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP3OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP4HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP4OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP5HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP5OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP6HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP6OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP7HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP7OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP8HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP8OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP9HOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFETAP9OVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFEUTHOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFEUTOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFEVPHOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFEVPOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFEVSEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDFEXYDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDLYBYPASS_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDLYEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDLYOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDLYSRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXELECIDLEMODE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXEQTRAINING_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXGEARBOXSLIP_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLATCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLPMEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLPMGCHOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLPMGCOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLPMHFHOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLPMHFOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLPMLFHOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLPMLFKLOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLPMOSHOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLPMOSOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXMCOMMAALIGNEN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXMONITORSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOOBRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSCALRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSHOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTCFG_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTHOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTSTROBE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTTESTOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOUTCLKSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPCOMMAALIGNEN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPCSRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPHALIGN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPHALIGNEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPHDLYPD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPHDLYRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPHOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPLLCLKSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPMARESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPOLARITY_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPRBSCNTRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPRBSSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPROGDIVRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXQPIEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRATE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRATEMODE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIDE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPOUTCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPPMA_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSYNCALLIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSYNCIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSYNCMODE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSYSCLKSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXTERMINATION_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXUSERRDY_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXUSRCLK_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXUSRCLK2_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SIGVALIDCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TSTIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TX8B10BBYPASS_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TX8B10BEN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXBUFDIFFCTRL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXCOMINIT_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXCOMSAS_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXCOMWAKE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXCTRL0_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXCTRL1_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXCTRL2_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDATA_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDATAEXTENDRSVD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDCCFORCESTART_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDCCRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDEEMPH_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDETECTRX_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDIFFCTRL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDIFFPD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDLYBYPASS_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDLYEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDLYHOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDLYOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDLYSRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDLYUPDOWN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXELECIDLE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXELFORCESTART_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXHEADER_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXINHIBIT_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXLATCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXLFPSTRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXLFPSU2LPEXIT_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXLFPSU3WAKE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXMAINCURSOR_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXMARGIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXMUXDCDEXHOLD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXMUXDCDORWREN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXONESZEROS_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXOUTCLKSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPCSRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPDELECIDLEMODE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHALIGN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHALIGNEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHDLYPD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHDLYRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHDLYTSTCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHINIT_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPIPPMEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPIPPMOVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPIPPMPD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPIPPMSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPIPPMSTEPSIZE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPISOPD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPLLCLKSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPMARESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPOLARITY_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPOSTCURSOR_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPOSTCURSORINV_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPRBSFORCEERR_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPRBSSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPRECURSOR_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPRECURSORINV_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPROGDIVRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXQPIBIASEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXQPISTRONGPDOWN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXQPIWEAKPUP_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXRATE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXRATEMODE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSEQUENCE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSWING_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCALLIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCMODE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYSCLKSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXUSERRDY_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXUSRCLK_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXUSRCLK2_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTCE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTCEMASK_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTDIV_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTRESET_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTRSTMASK_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLFBCLKLOST_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLLOCK_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLREFCLKLOST_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DMONITOROUT_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DMONITOROUTCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDO_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPRDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANDATAERROR_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTHTXN_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTHTXP_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTPOWERGOOD_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLKMONITOR_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTYTXN_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTYTXP_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEGEN3_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEIDLE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLLPD_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLLRESET_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIESYNCTXSYNCDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIEUSERGEN3RDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIEUSERPHYSTATUSRST_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIEUSERRATESTART_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCSRSVDOUT_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PHYSTATUS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PINRSRVDAS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_POWERPRESENT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RESETEXCEPTION_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXBUFSTATUS_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXBYTEISALIGNED_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXBYTEREALIGN_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDRLOCK_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDRPHDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHANBONDSEQ_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHANISALIGNED_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHANREALIGN_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHBONDO_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCKCALDONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCLKCORCNT_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCOMINITDET_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCOMMADET_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCOMSASDET_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCOMWAKEDET_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCTRL0_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCTRL1_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCTRL2_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCTRL3_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDATA_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDATAEXTENDRSVD_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDATAVALID_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDLYSRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXELECIDLE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXHEADER_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXHEADERVALID_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLFPSTRESETDET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLFPSU2LPEXITDET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLFPSU3WAKEDET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXMONITOROUT_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTSTARTED_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTSTROBEDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTSTROBESTARTED_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOUTCLK_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOUTCLKFABRIC_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOUTCLKPCS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPHALIGNDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPHALIGNERR_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPMARESETDONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPRBSERR_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPRBSLOCKED_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPRGDIVRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXQPISENN_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXQPISENP_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRATEDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLKOUT_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIDERDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPOUTCLKRDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPPMARDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSTATUS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXVALID_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXBUFSTATUS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXCOMFINISH_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDCCDONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDLYSRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXOUTCLK_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXOUTCLKFABRIC_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXOUTCLKPCS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXQPISENN_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXQPISENP_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXRATEDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT - 0 - - - - false - - - - - - Component_Name - gth_xcku_x0y8 - - - - - UltraScale FPGAs Transceivers Wizard - 8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - diff --git a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_top.vhd b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_top.vhd deleted file mode 100644 index 59715c1..0000000 --- a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_top.vhd +++ /dev/null @@ -1,409 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -library unisim; -use unisim.vcomponents.all; - -entity gth_xcku_x0y8_top is - port ( - CLK_100 : in std_logic; - GTREFCLK : in std_logic; - USRCLK_FULL : out std_logic; - USRCLK_HALF : out std_logic; - - RESET_ALL : in std_logic; - RXPMARESET : in std_logic; - RXPCSRESET : in std_logic; - TXPMARESET : in std_logic; - TXPCSRESET : in std_logic; - - USRCLK_LOCKED : out std_logic; - INIT_DONE : out std_logic; - RXRESETDONE : out std_logic; - TXRESETDONE : out std_logic; - RXPMARESETDONE : out std_logic; - TXPMARESETDONE : out std_logic; - RXBYTEISALIGNED : out std_logic; - - RXN : in std_logic; - RXP : in std_logic; - TXN : out std_logic; - TXP : out std_logic; - - TXDATA : in std_logic_vector(7 downto 0); - TXCHARISK : in std_logic; - TXCHARDISPMODE : in std_logic; - TXCHARDISPVAL : in std_logic; - - RXDATA : out std_logic_vector(7 downto 0); - RXCHARISK : out std_logic; - RXCHARISCOMMA : out std_logic; - RXNOTINTABLE : out std_logic; - RXDISPERR : out std_logic - ); -end entity gth_xcku_x0y8_top; - -architecture behavioral of gth_xcku_x0y8_top is - component gth_xcku_init is - generic ( - P_FREERUN_FREQUENCY : integer := 100; - P_TX_TIMER_DURATION_US : integer := 30000; - P_RX_TIMER_DURATION_US : integer := 130000 - ); - port ( - clk_freerun_in : in std_logic; - reset_all_in : in std_logic; - tx_init_done_in : in std_logic; - rx_init_done_in : in std_logic; - rx_data_good_in : in std_logic; - reset_all_out : out std_logic := '0'; - reset_rx_out : out std_logic := '0'; - init_done_out : out std_logic := '0'; - retry_ctr_out : out std_logic_vector(3 downto 0) := x"0" - ); - end component; - - component gth_xcku_x0y8 - port ( - gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); - gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); - gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); - gtwiz_reset_all_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); - gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); - gtwiz_userdata_tx_in : in std_logic_vector(15 downto 0); - gtwiz_userdata_rx_out : out std_logic_vector(15 downto 0); - gtrefclk00_in : in std_logic_vector(0 downto 0); - qpll0outclk_out : out std_logic_vector(0 downto 0); - qpll0outrefclk_out : out std_logic_vector(0 downto 0); - gthrxn_in : in std_logic_vector(0 downto 0); - gthrxp_in : in std_logic_vector(0 downto 0); - rx8b10ben_in : in std_logic_vector(0 downto 0); - rxbufreset_in : in std_logic_vector(0 downto 0); - rxcdrreset_in : in std_logic_vector(0 downto 0); - rxcommadeten_in : in std_logic_vector(0 downto 0); - rxmcommaalignen_in : in std_logic_vector(0 downto 0); - rxpcommaalignen_in : in std_logic_vector(0 downto 0); - rxpcsreset_in : in std_logic_vector(0 downto 0); - rxpmareset_in : in std_logic_vector(0 downto 0); - rxusrclk_in : in std_logic_vector(0 downto 0); - rxusrclk2_in : in std_logic_vector(0 downto 0); - tx8b10ben_in : in std_logic_vector(0 downto 0); - txctrl0_in : in std_logic_vector(15 downto 0); - txctrl1_in : in std_logic_vector(15 downto 0); - txctrl2_in : in std_logic_vector(7 downto 0); - txpcsreset_in : in std_logic_vector(0 downto 0); - txpmareset_in : in std_logic_vector(0 downto 0); - txusrclk_in : in std_logic_vector(0 downto 0); - txusrclk2_in : in std_logic_vector(0 downto 0); - gthtxn_out : out std_logic_vector(0 downto 0); - gthtxp_out : out std_logic_vector(0 downto 0); - gtpowergood_out : out std_logic_vector(0 downto 0); - rxbufstatus_out : out std_logic_vector(2 downto 0); - rxbyteisaligned_out : out std_logic_vector(0 downto 0); - rxbyterealign_out : out std_logic_vector(0 downto 0); - rxclkcorcnt_out : out std_logic_vector(1 downto 0); - rxcommadet_out : out std_logic_vector(0 downto 0); - rxctrl0_out : out std_logic_vector(15 downto 0); - rxctrl1_out : out std_logic_vector(15 downto 0); - rxctrl2_out : out std_logic_vector(7 downto 0); - rxctrl3_out : out std_logic_vector(7 downto 0); - rxoutclk_out : out std_logic_vector(0 downto 0); - rxpmaresetdone_out : out std_logic_vector(0 downto 0); - rxresetdone_out : out std_logic_vector(0 downto 0); - txoutclk_out : out std_logic_vector(0 downto 0); - txpmaresetdone_out : out std_logic_vector(0 downto 0); - txresetdone_out : out std_logic_vector(0 downto 0) - ); - end component; - - signal reset_tx_done_i : std_logic; - signal reset_rx_done_i : std_logic; - signal userclk_tx_reset_i : std_logic := '0'; - signal txpmaresetdone_i : std_logic; - - signal usrclk : std_logic; - signal usrclk_double : std_logic; - - signal txdata_reg : std_logic_vector(7 downto 0); - signal txcharisk_reg : std_logic; - signal txchardispmode_reg : std_logic; - signal txchardispval_reg : std_logic; - - signal tx16data : std_logic_vector(15 downto 0); - signal tx16charisk : std_logic_vector(1 downto 0); - signal tx16chardispmode : std_logic_vector(1 downto 0); - signal tx16chardispval : std_logic_vector(1 downto 0); - - signal rxctrl0 : std_logic_vector(15 downto 0); - signal rxctrl1 : std_logic_vector(15 downto 0); - signal rxctrl2 : std_logic_vector(7 downto 0); - signal rxctrl3 : std_logic_vector(7 downto 0); - - signal rx16data : std_logic_vector(15 downto 0); - signal rx16charisk : std_logic_vector(1 downto 0); - signal rx16chariscomma : std_logic_vector(1 downto 0); - signal rx16notintable : std_logic_vector(1 downto 0); - signal rx16disperr : std_logic_vector(1 downto 0); - - signal rx16data_reg : std_logic_vector(15 downto 0); - signal rx16charisk_reg : std_logic_vector(1 downto 0); - signal rx16chariscomma_reg : std_logic_vector(1 downto 0); - signal rx16notintable_reg : std_logic_vector(1 downto 0); - signal rx16disperr_reg : std_logic_vector(1 downto 0); - - signal rxdata_i : std_logic_vector(7 downto 0); - signal rxcharisk_i : std_logic; - signal rxchariscomma_i : std_logic; - signal rxnotintable_i : std_logic; - signal rxdisperr_i : std_logic; - - signal usrclk_toggle : std_logic := '0'; - signal usrclk_toggle_reg : std_logic := '0'; - signal usrclk_phase : std_logic := '0'; - - signal reset_all_i : std_logic; - - signal txoutclk_int : std_logic; - signal usrclk_int : std_logic; - - signal usrclk_mmcm_fb : std_logic; - - signal usrclk_active_meta : std_logic := '0'; - signal usrclk_active : std_logic := '0'; - signal not_usrclk_active : std_logic; - - attribute ASYNC_REG : string; - attribute ASYNC_REG of usrclk_active_meta : signal is "true"; - attribute ASYNC_REG of usrclk_active : signal is "true"; -begin - USRCLK_FULL <= usrclk_double; - USRCLK_HALF <= usrclk; - - userclk_tx_reset_i <= not txpmaresetdone_i; - - TXPMARESETDONE <= txpmaresetdone_i; - - THE_INIT : gth_xcku_init - port map ( - clk_freerun_in => CLK_100, - reset_all_in => RESET_ALL, - tx_init_done_in => reset_tx_done_i, - rx_init_done_in => reset_rx_done_i, - rx_data_good_in => '1', - reset_all_out => reset_all_i, - reset_rx_out => open, - init_done_out => INIT_DONE, - retry_ctr_out => open - ); - - - process (usrclk) is - begin - if rising_edge(usrclk) then - usrclk_toggle <= not usrclk_toggle; - - rx16data_reg <= rx16data; - rx16charisk_reg <= rx16charisk; - rx16chariscomma_reg <= rx16chariscomma; - rx16notintable_reg <= rx16notintable; - rx16disperr_reg <= rx16disperr; - - tx16data <= TXDATA & txdata_reg; - tx16charisk <= TXCHARISK & txcharisk_reg; - tx16chardispmode <= TXCHARDISPMODE & txchardispmode_reg; - tx16chardispval <= TXCHARDISPVAL & txchardispval_reg; - end if; - end process; - - process (usrclk_double) is - begin - if rising_edge(usrclk_double) then - usrclk_toggle_reg <= usrclk_toggle; - usrclk_phase <= usrclk_toggle xor usrclk_toggle_reg; - - if usrclk_phase = '0' then - rxdata_i <= rx16data_reg(7 downto 0); - rxcharisk_i <= rx16charisk_reg(0); - rxchariscomma_i <= rx16chariscomma_reg(0); - rxnotintable_i <= rx16notintable_reg(0); - rxdisperr_i <= rx16disperr_reg(0); - else - rxdata_i <= rx16data_reg(15 downto 8); - rxcharisk_i <= rx16charisk_reg(1); - rxchariscomma_i <= rx16chariscomma_reg(1); - rxnotintable_i <= rx16notintable_reg(1); - rxdisperr_i <= rx16disperr_reg(1); - end if; - - txdata_reg <= TXDATA; - txcharisk_reg <= TXCHARISK; - txchardispmode_reg <= TXCHARDISPMODE; - txchardispval_reg <= TXCHARDISPVAL; - end if; - end process; - - RXDATA <= rxdata_i; - RXCHARISK <= rxcharisk_i; - RXCHARISCOMMA <= rxchariscomma_i; - RXNOTINTABLE <= rxnotintable_i; - RXDISPERR <= rxdisperr_i; - - - THE_GTH : gth_xcku_x0y8 - port map ( - gtwiz_userclk_tx_active_in(0) => usrclk_active, - gtwiz_userclk_rx_active_in(0) => usrclk_active, - gtwiz_reset_clk_freerun_in(0) => CLK_100, - gtwiz_reset_all_in(0) => reset_all_i, - gtwiz_reset_tx_pll_and_datapath_in(0) => '0', - gtwiz_reset_tx_datapath_in(0) => '0', - gtwiz_reset_rx_pll_and_datapath_in(0) => '0', - gtwiz_reset_rx_datapath_in(0) => '0', - gtwiz_reset_rx_cdr_stable_out => open, - gtwiz_reset_tx_done_out(0) => reset_tx_done_i, - gtwiz_reset_rx_done_out(0) => reset_rx_done_i, - gtwiz_userdata_tx_in => tx16data, - gtwiz_userdata_rx_out => rx16data, - gtrefclk00_in(0) => GTREFCLK, - qpll0outclk_out => open, - qpll0outrefclk_out => open, - gthrxn_in(0) => RXN, - gthrxp_in(0) => RXP, - rx8b10ben_in(0) => '1', - rxbufreset_in(0) => '0', - rxcdrreset_in(0) => '0', - rxcommadeten_in(0) => '1', - rxmcommaalignen_in(0) => '1', - rxpcommaalignen_in(0) => '1', - rxpcsreset_in(0) => RXPCSRESET, - rxpmareset_in(0) => RXPMARESET, - rxusrclk_in(0) => usrclk_int, - rxusrclk2_in(0) => usrclk_int, - tx8b10ben_in(0) => '1', - txctrl0_in(15 downto 2) => (others => '0'), - txctrl0_in(1 downto 0) => tx16chardispval, - txctrl1_in(15 downto 2) => (others => '0'), - txctrl1_in(1 downto 0) => tx16chardispmode, - txctrl2_in(7 downto 2) => (others => '0'), - txctrl2_in(1 downto 0) => tx16charisk, - txpcsreset_in(0) => TXPCSRESET, - txpmareset_in(0) => TXPMARESET, - txusrclk_in(0) => usrclk_int, - txusrclk2_in(0) => usrclk_int, - gthtxn_out(0) => TXN, - gthtxp_out(0) => TXP, - gtpowergood_out => open, - rxbufstatus_out => open, - rxbyteisaligned_out(0) => RXBYTEISALIGNED, - rxbyterealign_out => open, - rxclkcorcnt_out => open, - rxcommadet_out => open, - rxctrl0_out => rxctrl0, - rxctrl1_out => rxctrl1, - rxctrl2_out => rxctrl2, - rxctrl3_out => rxctrl3, - rxoutclk_out => open, - rxpmaresetdone_out(0) => RXPMARESETDONE, - rxresetdone_out(0) => RXRESETDONE, - txoutclk_out(0) => txoutclk_int, - txpmaresetdone_out(0) => txpmaresetdone_i, - txresetdone_out(0) => TXRESETDONE - ); - - rx16charisk <= rxctrl0(1 downto 0); - rx16notintable <= rxctrl1(1 downto 0); - rx16chariscomma <= rxctrl2(1 downto 0); - rx16disperr <= rxctrl3(1 downto 0); - - bufg_gt_usrclk_inst : BUFG_GT - port map ( - O => usrclk_int, - CE => '1', - CEMASK => '0', - CLR => userclk_tx_reset_i, - CLRMASK => '0', - DIV => "000", - I => txoutclk_int - ); - - - -- Indicate active helper block functionality when the BUFG_GT divider is - -- not held in reset - process (userclk_tx_reset_i, usrclk_int) is - begin - if userclk_tx_reset_i = '1' then - usrclk_active_meta <= '0'; - usrclk_active <= '0'; - elsif rising_edge(usrclk_int) then - usrclk_active_meta <= '1'; - usrclk_active <= usrclk_active_meta; - end if; - end process; - - not_usrclk_active <= not usrclk_active; - - - mmcme3_adv_usrclk : MMCME3_ADV - generic map ( - BANDWIDTH => "OPTIMIZED", - CLKOUT4_CASCADE => "FALSE", - COMPENSATION => "AUTO", - STARTUP_WAIT => "FALSE", - DIVCLK_DIVIDE => 1, - CLKFBOUT_MULT_F => 10.000, - CLKFBOUT_PHASE => 0.000, - CLKFBOUT_USE_FINE_PS => "FALSE", - CLKOUT0_DIVIDE_F => 10.000, - CLKOUT0_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT0_USE_FINE_PS => "FALSE", - CLKOUT1_DIVIDE => 5, - CLKOUT1_PHASE => 0.000, - CLKOUT1_DUTY_CYCLE => 0.500, - CLKOUT1_USE_FINE_PS => "FALSE", - CLKIN1_PERIOD => 10.000 - ) - port map ( - CLKFBOUT => usrclk_mmcm_fb, - CLKFBOUTB => open, - CLKOUT0 => usrclk, - CLKOUT0B => open, - CLKOUT1 => usrclk_double, - CLKOUT1B => open, - CLKOUT2 => open, - CLKOUT2B => open, - CLKOUT3 => open, - CLKOUT3B => open, - CLKOUT4 => open, - CLKOUT5 => open, - CLKOUT6 => open, - CLKFBIN => usrclk_mmcm_fb, - CLKIN1 => usrclk_int, - CLKIN2 => '0', - CLKINSEL => '1', - DADDR => "0000000", - DCLK => '0', - DEN => '0', - DI => x"0000", - DO => open, - DRDY => open, - DWE => '0', - CDDCDONE => open, - CDDCREQ => '0', - PSCLK => '0', - PSEN => '0', - PSINCDEC => '0', - PSDONE => open, - LOCKED => USRCLK_LOCKED, - CLKINSTOPPED => open, - CLKFBSTOPPED => open, - PWRDWN => '0', - RST => not_usrclk_active - ); -end architecture behavioral; diff --git a/media_interfaces/xcku/gtwizard_options.txt b/media_interfaces/xcku/gtwizard_options.txt index fcb7f63..2a74596 100644 --- a/media_interfaces/xcku/gtwizard_options.txt +++ b/media_interfaces/xcku/gtwizard_options.txt @@ -1,7 +1,7 @@ Tab "Basic": Columns "Transmitter" and "Receiver": Line rate (Gb/s): 2 - Actual Reference Clock (MHz): 125 + Actual Reference Clock (MHz): 100 Decoding: 8B/10B User data width: 16