From: Cahit <c.ugur@gsi.de>
Date: Fri, 23 Jan 2015 09:17:43 +0000 (+0100)
Subject: new fifo core with dynamic threshold
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=21c8aa29fffb74ad89bd744c1c1321a534b12029;p=trb3.git

new fifo core with dynamic threshold
---

diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd
index 73ca4c9..8b66550 100644
--- a/base/trb3_components.vhd
+++ b/base/trb3_components.vhd
@@ -110,6 +110,22 @@ package trb3_components is
       Full        : out std_logic);
   end component;  
 
+  component FIFO_DC_36x128_DynThr_OutReg is
+    port (
+      Data         : in  std_logic_vector(35 downto 0);
+      WrClock      : in  std_logic;
+      RdClock      : in  std_logic;
+      WrEn         : in  std_logic;
+      RdEn         : in  std_logic;
+      Reset        : in  std_logic;
+      RPReset      : in  std_logic;
+      AmFullThresh : in  std_logic_vector(6 downto 0);
+      Q            : out std_logic_vector(35 downto 0);
+      Empty        : out std_logic;
+      Full         : out std_logic;
+      AlmostFull   : out std_logic);
+  end component FIFO_DC_36x128_DynThr_OutReg;
+  
   component FIFO_DC_36x128_OutReg is
     port (
       Data       : in  std_logic_vector(35 downto 0);