From: hadeshyp Date: Tue, 9 Dec 2008 16:41:29 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~509 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=21feb108a9d75bccfac57224e84b284c5e1ef2bd;p=trbnet.git *** empty log message *** --- diff --git a/special/trb_net_bridge_etrax_apl.vhd b/special/trb_net_bridge_etrax_apl.vhd index 4c0e1bd..17938bc 100644 --- a/special/trb_net_bridge_etrax_apl.vhd +++ b/special/trb_net_bridge_etrax_apl.vhd @@ -47,12 +47,13 @@ end entity; --1c1 wr target address sender_target 16bit used --1c2 wr Errorbits sender_error 32bit used --1c3 w sender data fifo sender_data 16bit used ---1cF r status (0)transfer running sender_status 1bit used +--1c4 r sender fifo status (9..0 datacount, 16 full, 17 empty) +--1cF r status (0)transfer running sender_status 1bit used --received data ---2c3 r receiver data fifo, (20..18)type receiver_data 16bit used ---2c4 r number of received 32bit words receiver_counter 10bit used +--2c3 r receiver data fifo, (20..18)type receiver_data 16bit used +--2c4 r receiver fifo status (9..0 datacount, 16 full, 17 empty) --3c0 (7..0) seq_num apis_tatus @@ -74,13 +75,12 @@ architecture trb_net_bridge_etrax_apl_arch of trb_net_bridge_etrax_apl is signal fifo_pci_to_net_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); signal fifo_pci_to_net_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); signal next_APL_SEND_OUT : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); - + signal fifo_pci_to_net_data_count : std_logic_vector(10*2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_data_count : std_logic_vector(10*2**c_MUX_WIDTH-1 downto 0); signal sender_control : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); signal sender_target : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); signal sender_error : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); signal sender_status : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); - signal receiver_counter : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); - signal current_receiver_data : std_logic_vector(31 downto 0); signal api_status : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); signal channel_address : integer range 0 to 7; @@ -94,18 +94,16 @@ architecture trb_net_bridge_etrax_apl_arch of trb_net_bridge_etrax_apl is signal reg_CPU_READ : std_logic; signal reg_CPU_WRITE : std_logic; - signal last_reg_CPU_ADDRESS : std_logic_vector(11 downto 0); - signal tmp : std_logic_vector(11 downto 0); - signal last_fifo_read : std_logic; signal buf_CPU_DATAREADY_OUT : std_logic; signal b_CPU_DATAREADY_OUT : std_logic; -component trb_net16_fifo is + component trb_net16_fifo is generic ( USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + USE_DATA_COUNT : integer range 0 to 1 := c_NO; DEPTH : integer := 6 ); port ( @@ -118,10 +116,11 @@ component trb_net16_fifo is DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); PACKET_NUM_OUT : out std_logic_vector(1 downto 0); READ_ENABLE_IN : in std_logic; + DATA_COUNT_OUT : out std_logic_vector(9 downto 0); FULL_OUT : out std_logic; EMPTY_OUT : out std_logic ); -end component; + end component; begin @@ -147,9 +146,10 @@ begin channel_address <= conv_integer(reg_CPU_ADDRESS(6 downto 4)); comb_channel_address <= conv_integer(CPU_ADDRESS(6 downto 4)); - read_regs : process(sender_control, sender_target, sender_error, sender_status, - receiver_counter, reg_CPU_ADDRESS, reg_CPU_READ, reg_CPU_WRITE, api_status, - buf_CPU_DATA_OUT, reg_CPU_DATA_IN, channel_address,current_receiver_data, CTRL) + read_regs : process(sender_control, sender_target, sender_error, sender_status, fifo_net_to_pci_data_count, + fifo_pci_to_net_data_count, reg_CPU_ADDRESS, reg_CPU_READ, reg_CPU_WRITE, api_status, + fifo_net_to_pci_full, fifo_net_to_pci_empty, fifo_pci_to_net_full, fifo_pci_to_net_empty, + buf_CPU_DATA_OUT, reg_CPU_DATA_IN, channel_address, CTRL) begin next_CPU_DATA_OUT <= (others => '0'); -- if reg_CPU_RD = '1' then @@ -161,10 +161,14 @@ begin next_CPU_DATA_OUT <= sender_target(channel_address*32+31 downto channel_address*32); when x"12" => next_CPU_DATA_OUT <= sender_error(channel_address*32+31 downto channel_address*32); + when x"14" => + next_CPU_DATA_OUT <= x"0000" & fifo_pci_to_net_empty(channel_address) & fifo_pci_to_net_full(channel_address) + & "000000" & fifo_pci_to_net_data_count(channel_address*10+9 downto channel_address*10); when x"1F" => next_CPU_DATA_OUT <= sender_status(channel_address*32+31 downto channel_address*32); when x"24" => - next_CPU_DATA_OUT <= receiver_counter(channel_address*32+31 downto channel_address*32); + next_CPU_DATA_OUT <= x"0000" & fifo_net_to_pci_empty(channel_address) & fifo_net_to_pci_full(channel_address) + & "000000" & fifo_net_to_pci_data_count(channel_address*10+9 downto channel_address*10); when x"30" => next_CPU_DATA_OUT <= api_status(channel_address*32+31 downto channel_address*32); when others => @@ -201,7 +205,7 @@ begin -------------------------------- -- connection to API -------------------------------- - fifo_pci_to_net_read <= (others => '1'); --APL_READ_IN(i); --NOT CORRECT - last packet may be lost + fifo_pci_to_net_read <= APL_READ_IN; --NOT CORRECT - last packet may be lost gen_api_connect : for i in 0 to 2**(c_MUX_WIDTH)-1 generate APL_DTYPE_OUT(i*4+3 downto i*4) <= sender_control(i*32+3 downto i*32); @@ -251,6 +255,11 @@ begin STAT(26) <= fifo_net_to_pci_write(1); FIFO_NET_TO_PCI: trb_net16_fifo + generic map( + USE_VENDOR_CORES => c_YES, + USE_DATA_COUNT => c_YES, + DEPTH => 6 + ) port map( CLK => CLK, RESET => RESET, @@ -261,11 +270,17 @@ begin PACKET_NUM_IN => fifo_net_to_pci_din(32*i+17 downto 32*i+16), DATA_OUT => fifo_net_to_pci_dout(32*i+15 downto 32*i), PACKET_NUM_OUT => fifo_net_to_pci_dout(32*i+17 downto 32*i+16), + DATA_COUNT_OUT => fifo_net_to_pci_data_count(10*i+9 downto 10*i), full_out => fifo_net_to_pci_full(i), empty_out => fifo_net_to_pci_empty(i) ); FIFO_PCI_TO_NET: trb_net16_fifo + generic map( + USE_VENDOR_CORES => c_YES, + USE_DATA_COUNT => c_YES, + DEPTH => 6 + ) port map( CLK => CLK, RESET => RESET, @@ -276,6 +291,7 @@ begin PACKET_NUM_IN => reg_CPU_DATA_IN(17 downto 16), DATA_OUT => fifo_pci_to_net_dout(32*i+15 downto 32*i), PACKET_NUM_OUT => fifo_pci_to_net_dout(32*i+17 downto 32*i+16), + DATA_COUNT_OUT => fifo_pci_to_net_data_count(10*i+9 downto 10*i), full_out => fifo_pci_to_net_full(i), empty_out => fifo_pci_to_net_empty(i) ); diff --git a/xilinx/virtex4/trb_net16_fifo_arch.vhd b/xilinx/virtex4/trb_net16_fifo_arch.vhd index 2da24ca..66cc43a 100644 --- a/xilinx/virtex4/trb_net16_fifo_arch.vhd +++ b/xilinx/virtex4/trb_net16_fifo_arch.vhd @@ -7,7 +7,8 @@ use work.trb_net_std.all; entity trb_net16_fifo is generic ( - USE_VENDOR_CORES : integer range 0 to 1 := c_NO; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + USE_DATA_COUNT : integer range 0 to 1 := c_NO; DEPTH : integer := 6 ); port ( @@ -20,6 +21,7 @@ entity trb_net16_fifo is DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); PACKET_NUM_OUT : out std_logic_vector(1 downto 0); READ_ENABLE_IN : in std_logic; + DATA_COUNT_OUT : out std_logic_vector(9 downto 0); FULL_OUT : out std_logic; EMPTY_OUT : out std_logic ); @@ -101,22 +103,39 @@ attribute box_type of xilinx_fifo_18x64 : component is "black_box"; ); end component; + component xilinx_fifo_18x1k_datacount is + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + data_count: OUT std_logic_VECTOR(9 downto 0); + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic + ); + end component; + signal din, dout : std_logic_vector(c_DATA_WIDTH + 2-1 downto 0); + signal data_counter : std_logic_vector(9 downto 0); begin din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; din(c_DATA_WIDTH + 2 -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 2 - 1 downto c_DATA_WIDTH); + DATA_COUNT_OUT <= data_counter; - gen_FIFO6 : if DEPTH = 6 generate - fifo:xilinx_fifo_18x1k + gen_FIFO6_Count : if DEPTH = 6 and USE_DATA_COUNT = 1 generate + fifo:xilinx_fifo_18x1k_datacount port map ( clk => CLK, rd_en => READ_ENABLE_IN, wr_en => WRITE_ENABLE_IN, din => din, rst => RESET, + data_count => data_counter, dout => dout, full => FULL_OUT, empty => EMPTY_OUT @@ -124,6 +143,21 @@ begin end generate; + gen_FIFO6 : if DEPTH = 6 and USE_DATA_COUNT = 0 generate + fifo:xilinx_fifo_18x1k + port map ( + clk => CLK, + rd_en => READ_ENABLE_IN, + wr_en => WRITE_ENABLE_IN, + din => din, + rst => RESET, + dout => dout, + full => FULL_OUT, + empty => EMPTY_OUT + ); + data_counter <= (others => '0'); + end generate; + gen_OWN_CORES : if USE_VENDOR_CORES = c_NO generate gen_FIFO_LUT : if DEPTH < 6 generate fifo:xilinx_fifo_lut @@ -141,6 +175,7 @@ begin full => FULL_OUT, empty => EMPTY_OUT ); + data_counter <= (others => '0'); end generate; end generate; @@ -157,6 +192,7 @@ begin full => FULL_OUT, empty => EMPTY_OUT ); + data_counter <= (others => '0'); end generate; gen_FIFO2 : if DEPTH = 2 generate @@ -171,6 +207,7 @@ begin full => FULL_OUT, empty => EMPTY_OUT ); + data_counter <= (others => '0'); end generate; @@ -186,6 +223,7 @@ begin full => FULL_OUT, empty => EMPTY_OUT ); + data_counter <= (others => '0'); end generate; end generate; diff --git a/xilinx/virtex4/xilinx_fifo_18x1k_datacount.vhd b/xilinx/virtex4/xilinx_fifo_18x1k_datacount.vhd new file mode 100644 index 0000000..4bb5bd3 --- /dev/null +++ b/xilinx/virtex4/xilinx_fifo_18x1k_datacount.vhd @@ -0,0 +1,149 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_18x1k_datacount.vhd when simulating +-- the core, xilinx_fifo_18x1k_datacount. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY xilinx_fifo_18x1k_datacount IS + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + data_count: OUT std_logic_VECTOR(9 downto 0); + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +END xilinx_fifo_18x1k_datacount; + +ARCHITECTURE xilinx_fifo_18x1k_datacount_a OF xilinx_fifo_18x1k_datacount IS +-- synthesis translate_off +component wrapped_xilinx_fifo_18x1k_datacount + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + data_count: OUT std_logic_VECTOR(9 downto 0); + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_18x1k_datacount use entity XilinxCoreLib.fifo_generator_v4_2(behavioral) + generic map( + c_has_int_clk => 0, + c_rd_freq => 1, + c_wr_response_latency => 1, + c_has_srst => 0, + c_has_rd_data_count => 0, + c_din_width => 18, + c_has_wr_data_count => 0, + c_full_flags_rst_val => 1, + c_implementation_type => 0, + c_family => "virtex4", + c_use_embedded_reg => 0, + c_has_wr_rst => 0, + c_wr_freq => 1, + c_use_dout_rst => 1, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 1, + c_dout_width => 18, + c_rd_depth => 1024, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 10, + c_has_wr_ack => 0, + c_use_ecc => 0, + c_wr_ack_low => 0, + c_common_clock => 1, + c_rd_pntr_width => 10, + c_use_fwft_data_count => 0, + c_has_almost_empty => 0, + c_rd_data_count_width => 10, + c_enable_rlocs => 0, + c_wr_pntr_width => 10, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 10, + c_preload_regs => 0, + c_dout_rst_val => "0", + c_has_data_count => 1, + c_prog_full_thresh_negate_val => 1021, + c_wr_depth => 1024, + c_prog_empty_thresh_negate_val => 3, + c_prog_empty_thresh_assert_val => 2, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 1022, + c_use_fifo16_flags => 0, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => "1kx18", + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_xilinx_fifo_18x1k_datacount + port map ( + clk => clk, + din => din, + rd_en => rd_en, + rst => rst, + wr_en => wr_en, + data_count => data_count, + dout => dout, + empty => empty, + full => full); +-- synthesis translate_on + +END xilinx_fifo_18x1k_datacount_a; + diff --git a/xilinx/virtex4/xilinx_fifo_18x1k_datacount.xco b/xilinx/virtex4/xilinx_fifo_18x1k_datacount.xco new file mode 100644 index 0000000..6014d79 --- /dev/null +++ b/xilinx/virtex4/xilinx_fifo_18x1k_datacount.xco @@ -0,0 +1,81 @@ +############################################################## +# +# Xilinx Core Generator version J.40 +# Date: Tue Dec 9 10:58:01 2008 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc4vlx40 +SET devicefamily = virtex4 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = ff1148 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -11 +SET verilogsim = True +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.2 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=xilinx_fifo_18x1k_datacount +CSET data_count=true +CSET data_count_width=10 +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=2 +CSET empty_threshold_negate_value=3 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=1022 +CSET full_threshold_negate_value=1021 +CSET input_data_width=18 +CSET input_depth=1024 +CSET output_data_width=18 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=Standard_FIFO +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=10 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=10 +# END Parameters +GENERATE +# CRC: 44e959c7 +