From: Andreas Neiser Date: Wed, 15 Apr 2015 08:42:55 +0000 (+0200) Subject: ADC: Adding monitoring stuff for CFD variant of ADC firmware (untested so far) X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=22b2b4977c4a6e9ce93c0d7bd8dc0d7f13ab2d8b;p=daqtools.git ADC: Adding monitoring stuff for CFD variant of ADC firmware (untested so far) --- diff --git a/users/mainz_kph_a2/setup.sh b/users/mainz_kph_a2/setup.sh index c28fb42..193696e 100755 --- a/users/mainz_kph_a2/setup.sh +++ b/users/mainz_kph_a2/setup.sh @@ -77,30 +77,30 @@ trbcmd w 0x8000 0x8108 0x0578 ##### ADC ###### FPGA="0x0200" -trbcmd w $FPGA 0xa010 0xff #Buffer depth -trbcmd w $FPGA 0xa011 8 #Samples after trigger -trbcmd w $FPGA 0xa012 1 #Process blocks -trbcmd w $FPGA 0xa013 0x10028 #Trigger offset, invert -trbcmd w $FPGA 0xa014 40 #Readout offset -trbcmd w $FPGA 0xa015 0 #Downsampling -trbcmd w $FPGA 0xa016 8 #Baseline -trbcmd w $FPGA 0xa017 0 #Trigger Enable ch31-00 -trbcmd w $FPGA 0xa018 0 #Trigger Enable ch47-32 -trbcmd w $FPGA 0xa01a 0xfffffffe #Channel disable ch31-00, all channels except ch0 -trbcmd w $FPGA 0xa01b 0xffff #Channel disable ch47-32 -trbcmd w $FPGA 0xa01c 0 #Processing mode 0=BlockMode, 1=PSA, 2=CFD -trbcmd w $FPGA 0xa01d 0x340 #CFD delay is 3, CFD window 64=0x40 - -trbcmd w $FPGA 0xa020 1 #Sum values -trbcmd w $FPGA 0xa021 1 #Sum values -trbcmd w $FPGA 0xa022 1 #Sum values -trbcmd w $FPGA 0xa023 1 #Sum values -trbcmd w $FPGA 0xa024 0xff #word count -trbcmd w $FPGA 0xa025 0 #word count -trbcmd w $FPGA 0xa026 0 #word count -trbcmd w $FPGA 0xa027 0 #word count - -trbcmd w $FPGA 0xa000 0x100 #Reset Baseline +#trbcmd w $FPGA 0xa010 0xff #Buffer depth +#trbcmd w $FPGA 0xa011 8 #Samples after trigger +#trbcmd w $FPGA 0xa012 1 #Process blocks +#trbcmd w $FPGA 0xa013 0x10028 #Trigger offset, invert +#trbcmd w $FPGA 0xa014 40 #Readout offset +#trbcmd w $FPGA 0xa015 0 #Downsampling +#trbcmd w $FPGA 0xa016 8 #Baseline +#trbcmd w $FPGA 0xa017 0 #Trigger Enable ch31-00 +#trbcmd w $FPGA 0xa018 0 #Trigger Enable ch47-32 +#trbcmd w $FPGA 0xa01a 0xfffffffe #Channel disable ch31-00, all channels except ch0 +#trbcmd w $FPGA 0xa01b 0xffff #Channel disable ch47-32 +#trbcmd w $FPGA 0xa01c 0 #Processing mode 0=BlockMode, 1=PSA, 2=CFD +#trbcmd w $FPGA 0xa01d 0x340 #CFD delay is 3, CFD window 64=0x40 + +#trbcmd w $FPGA 0xa020 1 #Sum values +#trbcmd w $FPGA 0xa021 1 #Sum values +#trbcmd w $FPGA 0xa022 1 #Sum values +#trbcmd w $FPGA 0xa023 1 #Sum values +#trbcmd w $FPGA 0xa024 0xff #word count +#trbcmd w $FPGA 0xa025 0 #word count +#trbcmd w $FPGA 0xa026 0 #word count +#trbcmd w $FPGA 0xa027 0 #word count + +#trbcmd w $FPGA 0xa000 0x100 #Reset Baseline ##### CTS ####### diff --git a/users/mainz_kph_a2/setup_adc.sh b/users/mainz_kph_a2/setup_adc.sh new file mode 100755 index 0000000..c28fb42 --- /dev/null +++ b/users/mainz_kph_a2/setup_adc.sh @@ -0,0 +1,111 @@ +#!/bin/sh +# PATH should already be marked as exported... +PATH=${HOME}/trbsoft/bin:${PATH} +PATH=${HOME}/trbsoft/daqdata/bin:${PATH} +PATH=${HOME}/trbsoft/trbnettools/bin:${PATH} +export TRB3_SERVER=trb019 +export DAQOPSERVER=localhost:0 + +pgrep dnsmasq > /dev/null +if [[ $? != 0 ]]; then + echo "No DHCP server found, skipping setup (but exports done)." + return +fi + +pgrep trbnetd > /dev/null +if [[ $? = 0 ]]; then + echo "trbnetd already running, skipping setup (but exports done)." + return +fi +trbnetd + + +##### TRBNET ##### +# set the TRBNet addresses of the Endpoints +trbcmd s 0x9100000337edaa28 0 0x0200 +trbcmd s 0x1900000337dff228 1 0x0201 +trbcmd s 0xf700000337df5428 2 0x0202 +trbcmd s 0xe300000337def328 3 0x0203 +trbcmd s 0xe100000337dff928 5 0x8000 + +##### Ethernet and UDP ####### +trbcmd w 0x8000 0x8300 0x8000 +trbcmd w 0x8000 0x8301 0x00020001 +trbcmd w 0x8000 0x8302 0x00030062 +trbcmd w 0x8000 0x8303 0xea60 +trbcmd w 0x8000 0x8304 0x578 +trbcmd w 0x8000 0x8305 0x1 +trbcmd w 0x8000 0x8306 0x0 +trbcmd w 0x8000 0x8307 0x0 +trbcmd w 0x8000 0x8308 0xffffff +trbcmd w 0x8000 0x830b 0x7 +trbcmd w 0x8000 0x830d 0x0 + +#mac address of the EB +# 14:fe:b5:ec:10:9a (normandy) +#trbcmd w 0x8000 0x8100 0xb5ec109a # lower 4 bytes +#trbcmd w 0x8000 0x8101 0x14fe # upper byte +# 00:19:b9:0a:ad:e2 (a2trb) +trbcmd w 0x8000 0x8100 0xb90aade2 # lower 4 bytes +trbcmd w 0x8000 0x8101 0x0019 # upper byte + +# destination port and source IP and so on +trbcmd w 0x8000 0x8102 0xc0a80101 +trbcmd w 0x8000 0x8103 0xc350 +trbcmd w 0x8000 0x8104 0xdead8001 +trbcmd w 0x8000 0x8105 0x0230 +trbcmd w 0x8000 0x8106 0xc0a80072 +trbcmd w 0x8000 0x8107 0xc350 +trbcmd w 0x8000 0x8108 0x0578 + + +##### TDC ####### +#trbcmd w 0x0200 0xc800 0x00000001 ## logic analyser control register +#trbcmd w 0x0200 0xc801 0x000f0005 ## trigger window enable & trigger window width +#trbcmd w 0x0200 0xc802 0x00000000 ## channel 01-31 enable +#trbcmd w 0x0200 0xc803 0x00000000 ## channel 32-63 enable +#trbcmd w 0x0200 0xc804 0x00000080 ## no read out limit + + +#trbcmd w 0x0200 0xc2 0x0000ffff ## channel 01-31 enable + +#trbcmd w 0x8000 0xc800 0x00000001 # logic analyser control register +#trbcmd w 0x8000 0xc801 0x000f0005 # trigger window enable & trigger window width (off if MSB not set) +#trbcmd w 0x8000 0xc802 0x00000002 # channel 32- 1 enable (0 is reference time and always on) +#trbcmd w 0x8000 0xc803 0x00000000 # channel 64-33 enable +#trbcmd w 0x8000 0xc804 0x00000080 ## no read out limit + +##### ADC ###### +FPGA="0x0200" +trbcmd w $FPGA 0xa010 0xff #Buffer depth +trbcmd w $FPGA 0xa011 8 #Samples after trigger +trbcmd w $FPGA 0xa012 1 #Process blocks +trbcmd w $FPGA 0xa013 0x10028 #Trigger offset, invert +trbcmd w $FPGA 0xa014 40 #Readout offset +trbcmd w $FPGA 0xa015 0 #Downsampling +trbcmd w $FPGA 0xa016 8 #Baseline +trbcmd w $FPGA 0xa017 0 #Trigger Enable ch31-00 +trbcmd w $FPGA 0xa018 0 #Trigger Enable ch47-32 +trbcmd w $FPGA 0xa01a 0xfffffffe #Channel disable ch31-00, all channels except ch0 +trbcmd w $FPGA 0xa01b 0xffff #Channel disable ch47-32 +trbcmd w $FPGA 0xa01c 0 #Processing mode 0=BlockMode, 1=PSA, 2=CFD +trbcmd w $FPGA 0xa01d 0x340 #CFD delay is 3, CFD window 64=0x40 + +trbcmd w $FPGA 0xa020 1 #Sum values +trbcmd w $FPGA 0xa021 1 #Sum values +trbcmd w $FPGA 0xa022 1 #Sum values +trbcmd w $FPGA 0xa023 1 #Sum values +trbcmd w $FPGA 0xa024 0xff #word count +trbcmd w $FPGA 0xa025 0 #word count +trbcmd w $FPGA 0xa026 0 #word count +trbcmd w $FPGA 0xa027 0 #word count + +trbcmd w $FPGA 0xa000 0x100 #Reset Baseline + + +##### CTS ####### +trbcmd w 0x8000 0xa150 0x05f5e100 #set CTS pulser to 1Hz +#trbcmd setbit 0x8000 0xa101 0x2 #enable pulser channel 0 +trbcmd setbit 0x8000 0xa101 0x1 # enable external trigger module + +echo "Successfully setup TRB network" diff --git a/web/htdocs/addons/adc_cfd.pl b/web/htdocs/addons/adc_cfd.pl new file mode 100755 index 0000000..014c1b4 --- /dev/null +++ b/web/htdocs/addons/adc_cfd.pl @@ -0,0 +1,57 @@ +#!/usr/bin/perl +if ($ENV{'SERVER_SOFTWARE'} =~ /HTTPi/i) { + print "HTTP/1.0 200 OK\n"; + print "Content-type: text/html\r\n\r\n"; +} else { + use lib '..'; + use if (!($ENV{'SERVER_SOFTWARE'} =~ /HTTPi/i)), apacheEnv; + print "Content-type: text/html\n\n"; +} + +use CGI ':standard'; +use XML::LibXML; +use POSIX; +use CGI::Carp qw(fatalsToBrowser); + +use lib qw|../commands htdocs/commands|; +use xmlpage; + +my $page; + +$page->{title} = "ADC CFD AddOn"; +$page->{link} = "../"; + +my @setup; + +push(@setup,({name => "Control", + cmd => "ADC_CFD-0xfe4b-Control", + period => 1000, + address => 1})); + +push(@setup,({name => "Input", + cmd => "ADC_CFD-0xfe4b-InputHandler&ADC-0xfe4b-InvalidWords", + period => 1000, + address => 1})); + +push(@setup,({name => "BufferConfig", + cmd => "ADC_CFD-0xfe4b-BufferConfig", + period => 1000, + address => 1})); + +push(@setup,({name => "LastValues", + cmd => "ADC_CFD-0xfe4b-LastValues", + period => 1000, + address => 1})); + +push(@setup,({name => "Baseline", + cmd => "ADC_CFD-0xfe4b-Baseline", + period => 1000, + address => 1})); + + +xmlpage::initPage(\@setup,$page); + + + + +1; diff --git a/web/htdocs/index.pl b/web/htdocs/index.pl index 13b89b3..0b64274 100755 --- a/web/htdocs/index.pl +++ b/web/htdocs/index.pl @@ -95,6 +95,7 @@ The main documentation of the network can be found in these documents and locati
  • Billboard
  • CBM-MBS Receiver
  • 48ch sampling ADC +
  • 48ch sampling ADC CFD
  • Everything else diff --git a/xml-db/database/ADC_CFD.xml b/xml-db/database/ADC_CFD.xml new file mode 100644 index 0000000..54a59c6 --- /dev/null +++ b/xml-db/database/ADC_CFD.xml @@ -0,0 +1,118 @@ + + + Control and Status registers related to ADC AddOn, CFD variant + + + Configuration registers + + Stop writing to buffers + + Baseline calculation always on (not just when no signal found) + + + + + + Configuration of buffer handling + + Number of samples to output in DebugMode>0 + + + + + Delay of trigger for event readout + + + + + Settings of trigger signal generation + + Offset from the calculated baseline to be reached for signal detection + + + Selects positive (unset) or negative (set) signal inputs. + + + + + Averaging time for baseline calculation. 2**N samples are taken. Baseline is calculated from buffer output data, triggered events are suppressed. + + + + + Trigger enable for channels 31 - 0 + + + + Trigger enable for channels 47 - 32 + + + + Check incoming words for validity. Two accepted words can be specified. + + + + + + Channel disable for channels 31 - 0 + + + + Channel disable for channels 47 - 32 + + + + Debug data processing + + Normal CFD mode + Debug raw input + Debug subtracted input + Debug CFD signal + + + + Constant Fraction Discriminator config + + + + + + + + + + Counter of words from ADC + + + + + + + Last value read from ADC + + + + + + + The current calculated baseline of the ADC value + + + + + + + Number of words not matching the given pattern + + + + + +