From: Jan Michel Date: Fri, 18 Mar 2016 14:32:55 +0000 (+0100) Subject: Update trb3sc tools with additional register X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=23014614f5a1c8ba16fea8c07d0bdb2e6ab05db1;p=trb3sc.git Update trb3sc tools with additional register --- diff --git a/code/trb3sc_tools.vhd b/code/trb3sc_tools.vhd index 05ae113..c1cc614 100644 --- a/code/trb3sc_tools.vhd +++ b/code/trb3sc_tools.vhd @@ -29,7 +29,7 @@ entity trb3sc_tools is --LCD LCD_DATA_IN : in std_logic_vector(511 downto 0) := (others => '0'); - + ADDITIONAL_REG : out std_logic_vector(31 downto 0); --HDR_IO HEADER_IO : inout std_logic_vector(10 downto 1); @@ -63,8 +63,10 @@ end entity; architecture trb3sc_tools_arch of trb3sc_tools is -signal bus_debug_rx_out, bus_flash_rx_out, busflash_rx, busspi_rx, busadc_rx, bussed_rx, busuart_rx, busflashset_rx, busmon_rx, bustrig_rx : CTRLBUS_RX; -signal bus_debug_tx_in, bus_flash_tx_in, busflash_tx, busspi_tx, busadc_tx, bussed_tx, busuart_tx, busflashset_tx, busmon_tx, bustrig_tx : CTRLBUS_TX; +signal bus_debug_rx_out, bus_flash_rx_out, busflash_rx, busspi_rx, busadc_rx, bussed_rx, + busuart_rx, busflashset_rx, busmon_rx, bustrig_rx, busctrl_rx : CTRLBUS_RX; +signal bus_debug_tx_in, bus_flash_tx_in, busflash_tx, busspi_tx, busadc_tx, bussed_tx, + busuart_tx, busflashset_tx, busmon_tx, bustrig_tx, busctrl_tx : CTRLBUS_TX; signal spi_sdi, spi_sdo, spi_sck : std_logic; signal spi_cs : std_logic_vector(15 downto 0); @@ -77,6 +79,7 @@ signal flash_cs_s, flash_clk_s, flash_out_s : std_logic; signal debug_rx, debug_tx : std_logic; signal debug_status : std_logic_vector(31 downto 0); +signal additional_reg_i : std_logic_vector(31 downto 0); begin @@ -85,9 +88,11 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 8, - PORT_ADDRESSES => (0 => x"0000", 1 => x"0400", 2 => x"0480", 3 => x"0500", 4 => x"0600", 5 => x"0180", 6 => x"0f00", 7 => x"0f80", others => x"0000"), - PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 5, 3 => 1, 4 => 2, 5 => 4, 6 => 7, 7 => 7, others => 0), + PORT_NUMBER => 9, + PORT_ADDRESSES => (0 => x"0000", 1 => x"0400", 2 => x"0480", 3 => x"0500", 4 => x"0600", + 5 => x"0180", 6 => x"0f00", 7 => x"0f80", 8 => x"0580", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 5, 3 => 1, 4 => 2, + 5 => 4, 6 => 7, 7 => 7, 8 => 0, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -105,6 +110,7 @@ begin BUS_RX(5) => busflashset_rx, BUS_RX(6) => bustrig_rx, BUS_RX(7) => busmon_rx, + BUS_RX(8) => busctrl_rx, BUS_TX(0) => busflash_tx, BUS_TX(1) => busspi_tx, BUS_TX(2) => busadc_tx, @@ -113,7 +119,7 @@ begin BUS_TX(5) => busflashset_tx, BUS_TX(6) => bustrig_tx, BUS_TX(7) => busmon_tx, - + BUS_TX(8) => busctrl_tx, STAT_DEBUG => open ); @@ -243,7 +249,9 @@ end generate; SPI_CS_OUT <= spi_cs; SPI_CLK_OUT <= (others => spi_sck); SPI_MOSI_OUT <= (others => spi_sdo); - spi_sdi <= (HEADER_IO(4) and not spi_cs(8)) or (ADC_MISO and not spi_cs(7)) or or_all(SPI_MISO_IN and not spi_cs and x"fe7f"); + spi_sdi <= (HEADER_IO(4) and not spi_cs(8)) or + (ADC_MISO and not spi_cs(7)) or + or_all(SPI_MISO_IN and not spi_cs and x"fe7f"); ADC_CLK <= not spi_sck; ADC_CS <= spi_cs(7); @@ -252,7 +260,7 @@ end generate; busspi_tx.unknown <= '0'; end generate; - gen_no_uart : if INCLUDE_SPI = 0 generate + gen_no_spi : if INCLUDE_SPI = 0 generate busspi_tx.unknown <= busspi_rx.write or busspi_rx.read; busspi_tx.ack <= '0'; busspi_tx.nack <= '0'; busspi_tx.data <= (others => '0'); @@ -309,6 +317,7 @@ gen_nodebug : if INCLUDE_DEBUG_INTERFACE = 0 generate bus_debug_rx_out.addr <= (others => '0'); bus_debug_rx_out.data <= (others => '0'); debug_tx <= 'Z'; + debug_active <= '0'; end generate; --------------------------------------------------------------------------- @@ -370,6 +379,26 @@ gen_noSTATISTICS : if INCLUDE_STATISTICS = 0 generate busmon_tx.data <= (others => '0'); end generate; +--------------------------------------------------------------------------- +-- Additional control register +--------------------------------------------------------------------------- +proc_add_reg : process begin + wait until rising_edge(CLK); + busctrl_tx.ack <= '0'; + busctrl_tx.nack <= '0'; + busctrl_tx.unknown <= '0'; + + if busctrl_rx.read = '1' then + busctrl_tx.data(additional_reg_i'left downto 0) <= additional_reg_i; + busctrl_tx.ack <= '1'; + elsif busctrl_rx.write = '1' then + additional_reg_i <= busctrl_rx.data(additional_reg_i'left downto 0); + busctrl_tx.ack <= '1'; + end if; +end process; + + ADDITIONAL_REG <= additional_reg_i; + --------------------------------------------------------------------------- -- HEADER_IO ---------------------------------------------------------------------------