From: Jan Michel Date: Tue, 30 Sep 2014 13:50:25 +0000 (+0200) Subject: added 4 MHz clock output for Enpirion regulators X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2370197b93278a8a3c00098996bddb6aff2ded53;p=trb3.git added 4 MHz clock output for Enpirion regulators --- diff --git a/base/cores/pll_200_4.ipx b/base/cores/pll_200_4.ipx new file mode 100644 index 0000000..bb2e14c --- /dev/null +++ b/base/cores/pll_200_4.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/pll_200_4.lpc b/base/cores/pll_200_4.lpc new file mode 100644 index 0000000..391127a --- /dev/null +++ b/base/cores/pll_200_4.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.6 +ModuleName=pll_200_4 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/30/2014 +Time=15:30:30 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=200 +Div=50 +ClkOPBp=0 +Post=128 +U_OFrq=4 +OP_Tol=0.0 +OFrq=4.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=1 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq= +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=0.856080 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_200_4 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 4 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw diff --git a/base/cores/pll_200_4.vhd b/base/cores/pll_200_4.vhd new file mode 100644 index 0000000..1f0bdb5 --- /dev/null +++ b/base/cores/pll_200_4.vhd @@ -0,0 +1,99 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134 +-- Module Version: 5.6 +--/d/jspc29/lattice/diamond/3.2_x64/ispfpga/bin/lin64/scuba -w -n pll_200_4 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 4 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + +-- Tue Sep 30 15:30:30 2014 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_200_4 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_200_4 : entity is true; +end pll_200_4; + +architecture Structure of pll_200_4 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "4.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 128, CLKFB_DIV=> 1, CLKI_DIV=> 50, + FIN=> "200.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_200_4 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/trb3_gbe/compile_central_frankfurt.pl b/trb3_gbe/compile_central_frankfurt.pl index 404c505..d5c93bc 100755 --- a/trb3_gbe/compile_central_frankfurt.pl +++ b/trb3_gbe/compile_central_frankfurt.pl @@ -10,7 +10,7 @@ use strict; #Settings for this project my $TOPNAME = "trb3_central"; #Name of top-level entity #my $lattice_path = '/d/jspc29/lattice/diamond/2.01'; -my $lattice_path = '/d/jspc29/lattice/diamond/3.0_x64'; +my $lattice_path = '/d/jspc29/lattice/diamond/3.2_x64'; # my $synplify_path = '/d/jspc29/lattice/synplify/fpga_e201103/'; my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; diff --git a/trb3_gbe/config_default.vhd b/trb3_gbe/config_default.vhd index bb654bf..ba027b7 100644 --- a/trb3_gbe/config_default.vhd +++ b/trb3_gbe/config_default.vhd @@ -44,6 +44,9 @@ package config is --Include generic UART on clock RJ-45? constant INCLUDE_UART : integer := c_YES; +--Run power supply on internal 4 MHz clock source + constant USE_POWER_CLOCK : integer := c_YES; + ------------------------------------------------------------------------------ --End of design configuration ------------------------------------------------------------------------------ diff --git a/trb3_gbe/trb3_central.prj b/trb3_gbe/trb3_central.prj index f804983..57a7bea 100644 --- a/trb3_gbe/trb3_central.prj +++ b/trb3_gbe/trb3_central.prj @@ -230,6 +230,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4 add_file -vhdl -lib work "../base/code/input_to_trigger_logic.vhd" add_file -vhdl -lib work "../base/code/input_statistics.vhd" add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../base/cores/pll_200_4.vhd" add_file -vhdl -lib work "./trb3_central.vhd" diff --git a/trb3_gbe/trb3_central.vhd b/trb3_gbe/trb3_central.vhd index b9833e2..106c98b 100644 --- a/trb3_gbe/trb3_central.vhd +++ b/trb3_gbe/trb3_central.vhd @@ -366,6 +366,15 @@ gen_125 : if USE_125_MHZ = c_YES generate pll_lock <= '1'; end generate; +gen_power_clock : if USE_POWER_CLOCK = c_YES generate + PLL_ENPIRION : entity work.pll_200_4 + port map( + CLK => clk_raw_internal, + CLKOP => ENPIRION_CLOCK, + LOCK => open + ); +end generate; + gen_sync_clocks : if USE_RXCLOCK = c_YES generate clk_sys_i <= rx_clock_half;