From: hadeshyp Date: Tue, 22 Jun 2010 10:51:11 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=23ac3ed31e779aedb749327535571098780d61ec;p=ctsaddon.git *** empty log message *** --- 23ac3ed31e779aedb749327535571098780d61ec diff --git a/cts_fpga1.vhd b/cts_fpga1.vhd new file mode 100644 index 0000000..d468723 --- /dev/null +++ b/cts_fpga1.vhd @@ -0,0 +1,100 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +-- use work.trb_net16_hub_func.all; +use work.version.all; + +entity cts_fpga1 is + port( + --Clocks + CLK200_IN : in std_logic; + ADO_CLKOUT : out std_logic; + --Resets + RESET_FPGA_1 : in std_logic; + ADDON_RESET : in std_logic; + --To TRB + ADO_TTL : inout std_logic_vector(46 downto 0); + FS_PE : inout std_logic_vector(11 downto 5); + --To 2nd FPGA + FFC : inout std_logic_vector(23 downto 0); + --Trigger IO + LVDS_IN : in std_logic_vector(63 downto 0); + LVDS_OUT : out std_logic_vector(15 downto 0); + PECL_OUT : out std_logic_vector(2 downto 0); + RICH_CLK_OUT : out std_logic; + RICH_RESERVED_OUT : out std_logic; + RICH_TIMING_OUT : out std_logic; + RICH_TRIGGER_OUT : out std_logic; + --Flash + SPI_CLK_OUT : out std_logic; + SPI_CS_OUT : out std_logic; + SPI_SI_OUT : out std_logic; + SPI_SO_IN : in std_logic; + PROGRAMN_OUT : out std_logic; + --LED + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + TRB2_OK_LED : out std_logic; + TRB2_RX_LED : out std_logic; + TRB2_TX_LED : out std_logic; + TRB3_OK_LED : out std_logic; + TRB3_RX_LED : out std_logic; + TRB3_TX_LED : out std_logic; + --SFP + TRB2_LOS : out std_logic; + TRB2_MOD : inout std_logic_vector(2 downto 0); + TRB2_TX_DIS : out std_logic; + TRB3_LOS : out std_logic; + TRB3_MOD : inout std_logic_vector(2 downto 0); + TRB3_TX_DIS : out std_logic; + --Other + RS1 : out std_logic_vector(3 downto 0); + RS2 : out std_logic_vector(3 downto 0); + DIS1 : out std_logic_vector(2 downto 0); + DIS2 : out std_logic_vector(2 downto 0); + --Debug + TEST_LINE : out std_logic_vector(31 downto 0); + ); + + attribute syn_useioff : boolean; + attribute syn_useioff of SPI_CLK_OUT : signal is true; + attribute syn_useioff of SPI_CS_OUT : signal is true; + attribute syn_useioff of SPI_SO_IN : signal is true; + attribute syn_useioff of SPI_SI_OUT : signal is true; + attribute syn_useioff of ADO_TTL : signal is true; + attribute syn_useioff of LVDS_IN : signal is true; + attribute syn_useioff of LVDS_OUT : signal is true; + attribute syn_useioff of PECL_OUT : signal is true; + attribute syn_useioff of RICH_CLK_OUT : signal is true; + attribute syn_useioff of RICH_RESERVED_OUT : signal is true; + attribute syn_useioff of RICH_TIMING_OUT : signal is true; + attribute syn_useioff of RICH_TRIGGER_OUT : signal is true; + attribute syn_useioff of SPI_CLK_OUT : signal is true; + attribute syn_useioff of SPI_CS_OUT : signal is true; + attribute syn_useioff of SPI_SI_OUT : signal is true; + attribute syn_useioff of SPI_SO_IN : signal is true; + attribute syn_useioff of PROGRAMN_OUT : signal is false; + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TRB2_OK_LED : signal is false; + attribute syn_useioff of TRB2_RX_LED : signal is false; + attribute syn_useioff of TRB2_TX_LED : signal is false; + attribute syn_useioff of TRB3_OK_LED : signal is false; + attribute syn_useioff of TRB3_RX_LED : signal is false; + attribute syn_useioff of TRB3_TX_LED : signal is false; + attribute syn_useioff of TRB2_LOS : signal is false; + attribute syn_useioff of TRB2_MOD : signal is false; + attribute syn_useioff of TRB2_TX_DIS : signal is false; + attribute syn_useioff of TRB3_LOS : signal is false; + attribute syn_useioff of TRB3_MOD : signal is false; + attribute syn_useioff of TRB3_TX_DIS : signal is false; +end entity; +