From: Cahit Date: Mon, 4 May 2015 05:51:45 +0000 (+0200) Subject: changed calibration frequency to 33MHz X-Git-Tag: v2.3~83 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=24295a6419a0c432259ed2b73f3527d38f45a195;p=tdc.git changed calibration frequency to 33MHz --- diff --git a/base/cores/ecp3/PLL/generate_core.tcl b/base/cores/ecp3/PLL/generate_core.tcl index 1f59381..5122002 100644 --- a/base/cores/ecp3/PLL/generate_core.tcl +++ b/base/cores/ecp3/PLL/generate_core.tcl @@ -85,7 +85,7 @@ set Para(install_dir) $env(TOOLRTF) set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" set scuba "$Para(FPGAPath)/scuba" -set modulename "pll_in125_out100" +set modulename "pll_in125_out333" set lang "vhdl" set lpcfile "$Para(sbp_path)/$modulename.lpc" set arch "ep5c00" diff --git a/base/cores/ecp3/PLL/generate_ngd.tcl b/base/cores/ecp3/PLL/generate_ngd.tcl index 2321601..cf1605a 100644 --- a/base/cores/ecp3/PLL/generate_ngd.tcl +++ b/base/cores/ecp3/PLL/generate_ngd.tcl @@ -50,7 +50,7 @@ set Para(install_dir) $env(TOOLRTF) set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" -set Para(ModuleName) "pll_in125_out100" +set Para(ModuleName) "pll_in125_out333" set Para(Module) "PLL" set Para(libname) latticeecp3 set Para(arch_name) ep5c00 diff --git a/base/cores/ecp3/PLL/msg_file.log b/base/cores/ecp3/PLL/msg_file.log index db2ac06..65b2385 100644 --- a/base/cores/ecp3/PLL/msg_file.log +++ b/base/cores/ecp3/PLL/msg_file.log @@ -1,5 +1,5 @@ SCUBA, Version Diamond (64-bit) 3.4.0.80 -Fri Apr 24 12:22:35 2015 +Tue Apr 28 16:10:12 2015 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -9,20 +9,20 @@ Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. BEGIN SCUBA Module Synthesis - Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw - Circuit name : pll_in125_out100 + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out333 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 33.3 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + Circuit name : pll_in125_out333 Module type : pll Module Version : 5.7 Ports : Inputs : CLK Outputs : CLKOP, LOCK I/O buffer : not inserted - EDIF output : pll_in125_out100.edn - VHDL output : pll_in125_out100.vhd - VHDL template : pll_in125_out100_tmpl.vhd + EDIF output : pll_in125_out333.edn + VHDL output : pll_in125_out333.vhd + VHDL template : pll_in125_out333_tmpl.vhd VHDL purpose : for synthesis and simulation Bus notation : not used - Report output : pll_in125_out100.srp + Report output : pll_in125_out333.srp Estimated Resource Usage: END SCUBA Module Synthesis diff --git a/releases/tdc_v2.1.2/Channel_200.vhd b/releases/tdc_v2.1.2/Channel_200.vhd index 4a21070..66bf595 100644 --- a/releases/tdc_v2.1.2/Channel_200.vhd +++ b/releases/tdc_v2.1.2/Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-08-28 --- Last update: 2015-04-24 +-- Last update: 2015-04-29 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -105,10 +105,10 @@ architecture Channel_200 of Channel_200 is signal fifo_data_valid : std_logic; -- fsm - type FSM_WR is (WRITE_EPOCH_WORD, WRITE_DATA_WORD, WRITE_STOP_WORD_A, WRITE_STOP_WORD_B, + type FSM_WR is (IDLE, WRITE_DATA_WORD, WRITE_STOP_WORD_A, WRITE_STOP_WORD_B, WRITE_STOP_WORD_C, WRITE_STOP_WORD_D, WAIT_FOR_HIT, WAIT_FOR_VALIDITY, EXCEPTION); - signal FSM_WR_CURRENT : FSM_WR := WRITE_EPOCH_WORD; + signal FSM_WR_CURRENT : FSM_WR; signal FSM_WR_NEXT : FSM_WR; signal write_epoch_fsm : std_logic; signal write_epoch : std_logic := '0'; @@ -147,7 +147,7 @@ begin -- Channel_200 FC : Adder_304 port map ( CLK => CLK_200, - RESET => '0', --RESET_200, + RESET => RESET_200, DataA => data_a, DataB => data_b, ClkEn => ff_array_en, @@ -362,7 +362,7 @@ begin -- Channel_200 begin if rising_edge(CLK_200) then if RESET_200 = '1' then - FSM_WR_CURRENT <= WRITE_EPOCH_WORD; + FSM_WR_CURRENT <= IDLE; else FSM_WR_CURRENT <= FSM_WR_NEXT; write_epoch <= write_epoch_fsm; @@ -379,7 +379,7 @@ begin -- Channel_200 trg_win_end_tdc_flag, write_data_flag) begin - FSM_WR_NEXT <= WRITE_EPOCH_WORD; + FSM_WR_NEXT <= IDLE; write_epoch_fsm <= '0'; write_data_fsm <= '0'; write_stop_a_fsm <= '0'; @@ -388,7 +388,7 @@ begin -- Channel_200 fsm_wr_debug_fsm <= x"0"; case (FSM_WR_CURRENT) is - when WRITE_EPOCH_WORD => + when IDLE => if encoder_finished = '1' or write_data_flag = '1' then write_epoch_fsm <= '1'; write_data_flag_fsm <= '0'; @@ -397,7 +397,7 @@ begin -- Channel_200 FSM_WR_NEXT <= WRITE_STOP_WORD_A; else write_epoch_fsm <= '0'; - FSM_WR_NEXT <= WRITE_EPOCH_WORD; + FSM_WR_NEXT <= IDLE; end if; fsm_wr_debug_fsm <= x"1"; -- @@ -426,7 +426,7 @@ begin -- Channel_200 -- when WAIT_FOR_HIT => if epoch_cntr_updated = '1' and encoder_finished = '0' then - FSM_WR_NEXT <= WRITE_EPOCH_WORD; + FSM_WR_NEXT <= IDLE; elsif epoch_cntr_updated = '0' and encoder_finished = '1' then FSM_WR_NEXT <= WRITE_DATA_WORD; elsif epoch_cntr_updated = '1' and encoder_finished = '1' then @@ -464,14 +464,14 @@ begin -- Channel_200 -- when WRITE_STOP_WORD_D => write_stop_b_fsm <= '1'; - FSM_WR_NEXT <= WRITE_EPOCH_WORD; + FSM_WR_NEXT <= IDLE; if encoder_finished = '1' then write_data_flag_fsm <= '1'; end if; fsm_wr_debug_fsm <= x"5"; -- when others => - FSM_WR_NEXT <= WRITE_EPOCH_WORD; + FSM_WR_NEXT <= IDLE; write_epoch_fsm <= '0'; write_data_fsm <= '0'; write_stop_a_fsm <= '0'; diff --git a/releases/tdc_v2.1.2/Readout.vhd b/releases/tdc_v2.1.2/Readout.vhd index 234eac9..ff5319d 100644 --- a/releases/tdc_v2.1.2/Readout.vhd +++ b/releases/tdc_v2.1.2/Readout.vhd @@ -5,7 +5,7 @@ -- File : Readout.vhd -- Author : cugur@gsi.de -- Created : 2012-10-25 --- Last update: 2015-04-21 +-- Last update: 2015-04-29 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -462,7 +462,7 @@ begin -- behavioral when others => RD_NEXT <= IDLE; - rd_fsm_debug_fsm <= x"F"; + rd_fsm_debug_fsm <= x"0"; end case; end process RD_FSM_PROC; @@ -489,10 +489,11 @@ begin -- behavioral begin - WR_NEXT <= WR_CURRENT; - wr_ch_data_fsm <= '0'; - fifo_nr_wr_fsm <= 0; - wr_finished_fsm <= '0'; + WR_NEXT <= WR_CURRENT; + wr_ch_data_fsm <= '0'; + fifo_nr_wr_fsm <= 0; + wr_finished_fsm <= '0'; + wr_fsm_debug_fsm <= x"0"; case (WR_CURRENT) is when IDLE => @@ -547,7 +548,7 @@ begin -- behavioral -- when others => WR_NEXT <= IDLE; - wr_fsm_debug_fsm <= x"F"; + wr_fsm_debug_fsm <= x"0"; end case; end process WR_FSM; diff --git a/releases/tdc_v2.1.2/TDC.vhd b/releases/tdc_v2.1.2/TDC.vhd index 4460dec..2b48840 100644 --- a/releases/tdc_v2.1.2/TDC.vhd +++ b/releases/tdc_v2.1.2/TDC.vhd @@ -261,11 +261,12 @@ begin else cal_cntr <= std_logic_vector(unsigned(cal_cntr) + to_unsigned(1,3)); end if; - cal_cntr_start_sync <= calibration_on_5r; + cal_cntr_start_sync <= calibration_on; cal_cntr_start <= cal_cntr_start_sync; end if; end process CalibrationHitGenerate; + --hit_cal <= and_all(cal_cntr); hit_cal <= and_all(cal_cntr); ------------------------------------------------------------------------------- @@ -278,9 +279,9 @@ begin calibration_on_4r <= calibration_on_3r when rising_edge(CLK_READOUT); calibration_on_5r <= calibration_on_4r when rising_edge(CLK_READOUT); - HitSelectRef : process (calibration_on_5r, REFERENCE_TIME, hit_cal) is + HitSelectRef : process (calibration_on, REFERENCE_TIME, hit_cal) is begin - if calibration_on_5r = '0' then + if calibration_on = '0' then hit_in_s(0) <= REFERENCE_TIME; else hit_in_s(0) <= hit_cal; @@ -289,9 +290,9 @@ begin GEN_HitSelect : for i in 1 to CHANNEL_NUMBER-1 generate Double: if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 or (DOUBLE_EDGE_TYPE = 2 and (i mod 2 = 1)) generate - HitSelect : process (calibration_on_5r, HIT_IN, hit_cal, ch_invert) is + HitSelect : process (calibration_on, HIT_IN, hit_cal, ch_invert) is begin - if calibration_on_5r = '0' then + if calibration_on = '0' then if ch_invert(i) = '0' then hit_in_s(i) <= HIT_IN(i); else @@ -303,9 +304,9 @@ begin end process HitSelect; end generate Double; Single: if DOUBLE_EDGE_TYPE = 2 and (i mod 2 = 0) generate - HitSelect : process (calibration_on_5r, HIT_IN, hit_cal, ch_invert) is + HitSelect : process (calibration_on, HIT_IN, hit_cal, ch_invert) is begin - if calibration_on_5r = '0' then + if calibration_on = '0' then if ch_invert(i) = '0' then hit_in_s(i) <= HIT_IN(i); else @@ -780,17 +781,16 @@ begin UNKNOWN_ADDR_OUT => SRB_UNKNOWN_ADDR_OUT); -- basic info - status_registers_bus(0)(7 downto 0) <= (others => '0'); + status_registers_bus(0)(3 downto 0) <= readout_debug(3 downto 0); -- rd_fsm + status_registers_bus(0)(7 downto 4) <= readout_debug(7 downto 4); -- wr_fsm status_registers_bus(0)(15 downto 8) <= std_logic_vector(to_unsigned(CHANNEL_NUMBER-1, 8)); status_registers_bus(0)(16) <= REFERENCE_TIME when rising_edge(CLK_READOUT); status_registers_bus(0)(27 downto 17) <= TDC_VERSION(10 downto 0); status_registers_bus(0)(31 downto 28) <= TRG_TYPE_IN when rising_edge(CLK_READOUT); -- debug info - status_registers_bus(1)(3 downto 0) <= readout_debug(3 downto 0); -- rd_fsm - status_registers_bus(1)(7 downto 4) <= readout_debug(7 downto 4); -- wr_fsm - status_registers_bus(1)(11 downto 8) <= trg_handler_status_registers(23 downto 20); - status_registers_bus(2) <= (others => '0'); + status_registers_bus(1)(3 downto 0) <= trg_handler_status_registers(23 downto 20); + status_registers_bus(2) <= (others => '0'); -- trigger window status_registers_bus(3)(10 downto 0) <= TRG_WIN_PRE; diff --git a/releases/tdc_v2.1.2/TriggerHandler.vhd b/releases/tdc_v2.1.2/TriggerHandler.vhd index 9ffe22d..73531a4 100644 --- a/releases/tdc_v2.1.2/TriggerHandler.vhd +++ b/releases/tdc_v2.1.2/TriggerHandler.vhd @@ -4,7 +4,7 @@ -- File : TriggerHandler.vhd -- Author : Cahit Ugur c.ugur@gsi.de -- Created : 2013-03-13 --- Last update: 2015-04-21 +-- Last update: 2015-04-30 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -205,7 +205,7 @@ begin -- architecture behavioral end if; when COUNT_CALIBRATION => - if trg_win_cnt_r(5) = '1' then + if trg_win_cnt_r(6) = '1' then TrgWin_STATE <= WIN_END; else TrgWin_STATE <= COUNT_CALIBRATION; @@ -317,7 +317,7 @@ begin -- architecture behavioral trg_time <= EPOCH_COUNTER_IN & COARSE_COUNTER_IN; end if; if trg_pulse_tdc(0) = '1' then - TRG_TIME_OUT <= std_logic_vector(unsigned(trg_time) - to_unsigned(2, 39)); + TRG_TIME_OUT <= trg_time; --std_logic_vector(unsigned(trg_time) - to_unsigned(2, 39)); end if; end if; end process TriggerTime; diff --git a/releases/tdc_v2.1.2/tdc_components.vhd b/releases/tdc_v2.1.2/tdc_components.vhd index 42cf908..c14f603 100644 --- a/releases/tdc_v2.1.2/tdc_components.vhd +++ b/releases/tdc_v2.1.2/tdc_components.vhd @@ -534,4 +534,11 @@ package tdc_components is LOCK : out std_logic); end component pll_in125_out100; + component pll_in125_out333 is + port ( + CLK : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic); + end component pll_in125_out333; + end package tdc_components; diff --git a/releases/tdc_v2.1.2/trb3_periph_ADA.vhd b/releases/tdc_v2.1.2/trb3_periph_ADA.vhd index 4578b9a..08de91b 100644 --- a/releases/tdc_v2.1.2/trb3_periph_ADA.vhd +++ b/releases/tdc_v2.1.2/trb3_periph_ADA.vhd @@ -312,12 +312,17 @@ begin LOCK => pll_lock); - pll_calibration: entity work.pll_in125_out100 + --pll_calibration: entity work.pll_in125_out100 + -- port map ( + -- CLK => CLK_GPLL_LEFT, + -- CLKOP => osc_int, + -- LOCK => open); + + pll_calibration: entity work.pll_in125_out333 port map ( CLK => CLK_GPLL_LEFT, CLKOP => osc_int, LOCK => open); - --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA)