From: hadaq <hadaq>
Date: Wed, 27 Mar 2013 08:05:08 +0000 (+0000)
Subject: port interface is updated - cu
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=24dd0996ecbc4918b7920548b4515a061db68711;p=trb3.git

port interface is updated - cu
---

diff --git a/tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd b/tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd
index 66df513..bbadd10 100644
--- a/tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd
+++ b/tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd
@@ -5,7 +5,7 @@
 -- File       : LogicAnalyser.vhd
 -- Author     : cugur@gsi.de
 -- Created    : 2012-10-26
--- Last update: 2012-10-26
+-- Last update: 2013-03-27
 -------------------------------------------------------------------------------
 -- Description: 
 -------------------------------------------------------------------------------
@@ -21,8 +21,7 @@ use work.trb3_components.all;
 
 entity LogicAnalyser is
   generic (
-    CHANNEL_NUMBER : integer range 2 to 65;
-    STATUS_REG_NR  : integer range 0 to 6);
+    CHANNEL_NUMBER : integer range 2 to 65);
 
   port (
     CLK        : in  std_logic;