From: Ingo Froehlich Date: Thu, 13 Sep 2018 13:59:32 +0000 (+0200) Subject: tested X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=26a98851f498a7532b1263b53603656593232a33;p=trbnet.git tested --- diff --git a/media_interfaces/med_ecp3_sfp_sync_4.vhd b/media_interfaces/med_ecp3_sfp_sync_4.vhd index 66cc76e..b0dd941 100644 --- a/media_interfaces/med_ecp3_sfp_sync_4.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_4.vhd @@ -426,9 +426,23 @@ BUS_WRITER : process end case; end if; else - loc_BUS_TX.data <= mii_tx_i(0).data or mii_tx_i(1).data or mii_tx_i(2).data or mii_tx_i(3).data; - loc_BUS_TX.ack <= mii_tx_i(0).ack or mii_tx_i(1).ack or mii_tx_i(2).ack or mii_tx_i(3).ack; - loc_BUS_TX.unknown <= mii_tx_i(0).unknown and mii_tx_i(1).unknown and mii_tx_i(2).unknown and mii_tx_i(3).unknown; + if mii_tx_i(0).ack = '1' then + loc_BUS_TX.data <= mii_tx_i(0).data; + loc_BUS_TX.ack <= '1'; + loc_BUS_TX.unknown <= mii_tx_i(0).unknown; + elsif mii_tx_i(1).ack = '1' then + loc_BUS_TX.data <= mii_tx_i(1).data; + loc_BUS_TX.ack <= '1'; + loc_BUS_TX.unknown <= mii_tx_i(1).unknown; + elsif mii_tx_i(2).ack = '1' then + loc_BUS_TX.data <= mii_tx_i(2).data; + loc_BUS_TX.ack <= '1'; + loc_BUS_TX.unknown <= mii_tx_i(2).unknown; + elsif mii_tx_i(3).ack = '1' then + loc_BUS_TX.data <= mii_tx_i(3).data; + loc_BUS_TX.ack <= '1'; + loc_BUS_TX.unknown <= mii_tx_i(3).unknown; + end if; if loc_BUS_RX.read = '1' then if loc_BUS_RX.addr(4 downto 3) = "00" then mii_rx_i(0).read <= '1'; diff --git a/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd b/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd index dda7a55..7120edb 100644 --- a/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd @@ -401,9 +401,23 @@ BUS_WRITER : process end case; end if; else - loc_BUS_TX.data <= mii_tx_i(0).data or mii_tx_i(1).data or mii_tx_i(2).data or mii_tx_i(3).data; - loc_BUS_TX.ack <= mii_tx_i(0).ack or mii_tx_i(1).ack or mii_tx_i(2).ack or mii_tx_i(3).ack; - loc_BUS_TX.unknown <= mii_tx_i(0).unknown and mii_tx_i(1).unknown and mii_tx_i(2).unknown and mii_tx_i(3).unknown; + if mii_tx_i(0).ack = '1' then + loc_BUS_TX.data <= mii_tx_i(0).data; + loc_BUS_TX.ack <= '1'; + loc_BUS_TX.unknown <= mii_tx_i(0).unknown; + elsif mii_tx_i(1).ack = '1' then + loc_BUS_TX.data <= mii_tx_i(1).data; + loc_BUS_TX.ack <= '1'; + loc_BUS_TX.unknown <= mii_tx_i(1).unknown; + elsif mii_tx_i(2).ack = '1' then + loc_BUS_TX.data <= mii_tx_i(2).data; + loc_BUS_TX.ack <= '1'; + loc_BUS_TX.unknown <= mii_tx_i(2).unknown; + elsif mii_tx_i(3).ack = '1' then + loc_BUS_TX.data <= mii_tx_i(3).data; + loc_BUS_TX.ack <= '1'; + loc_BUS_TX.unknown <= mii_tx_i(3).unknown; + end if; if loc_BUS_RX.read = '1' then if loc_BUS_RX.addr(4 downto 3) = "00" then mii_rx_i(0).read <= '1'; diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd index db8045b..88d9ca7 100644 --- a/media_interfaces/sync/med_sync_control.vhd +++ b/media_interfaces/sync/med_sync_control.vhd @@ -115,12 +115,12 @@ signal DEBUG_RX_CONTROL_i : std_logic_vector(31 downto 0); signal STAT_RESET_i : std_logic_vector(31 downto 0); signal DEBUG_OUT_i : std_logic_vector(31 downto 0); -signal last_FORCE_CRC_ERROR_IN : std_logic; -signal crc_error_delay : std_logic_vector(3 downto 0) := "0000"; -signal tx_got_force_error : std_logic; -signal tx_got_force_error_100 : std_logic := '0'; -signal tx_force_crc_error : std_logic := '0'; -signal tx_force_pak_error : std_logic := '0'; +signal last_FORCE_CRC_ERROR_IN : std_logic := '0'; +signal crc_error_delay : std_logic_vector(3 downto 0) := "0000"; +signal tx_got_force_error : std_logic := '0'; +signal tx_got_force_error_100 : std_logic := '0'; +signal tx_force_crc_error : std_logic := '0'; +signal tx_force_pak_error : std_logic := '0'; begin @@ -259,7 +259,7 @@ PROC_REG : process begin case BUS_RX.addr(1 downto 0) is when "00" => BUS_TX.data <= x"00000" & "00" & tx_force_pak_error & tx_force_crc_error & crc_error_delay & "000" & force_crc_error; when "01" => BUS_TX.data <= request_retr_counter & start_retr_counter; - when "11" => BUS_TX.data <= x"000000" & DEBUG_RX_CONTROL_i(31 downto 24); + --when "11" => BUS_TX.data <= x"000000" & DEBUG_RX_CONTROL_i(31 downto 24); when others => BUS_TX.unknown <= '1'; end case; end if; @@ -312,8 +312,8 @@ THE_TX : tx_control TX_ALLOW_IN => tx_allow, RX_ALLOW_IN => rx_allow, - ENABLE_SEND_CHKSUM => '1', --SIM - --ENABLE_SEND_CHKSUM => MEDIA_INT2MED.ctrl_op(8), + --ENABLE_SEND_CHKSUM => '1', --SIM + ENABLE_SEND_CHKSUM => MEDIA_INT2MED.ctrl_op(8), --RESET_RETRANSMIT_IN => send_link_reset_i, RESET_RETRANSMIT_IN => '0', diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd index bac1f50..e6513ff 100644 --- a/media_interfaces/sync/rx_control.vhd +++ b/media_interfaces/sync/rx_control.vhd @@ -56,7 +56,9 @@ signal rx_state : rx_state_t; signal rx_state_bits : std_logic_vector(3 downto 0); signal rx_packet_num : std_logic_vector(2 downto 0); signal buf_rx_write_out : std_logic := '0'; -signal buf2_rx_write_out : std_logic := '0'; +signal buf2_rx_write_out : std_logic := '0'; +signal buf_RX_DATA_OUT : std_logic_vector(15 downto 0) := x"0000"; + signal rx_data : std_logic_vector(17 downto 0); signal ct_fifo_write : std_logic := '0'; @@ -95,9 +97,7 @@ signal pulse_good : std_logic; signal pulse_bad : std_logic; signal got_pulse_good : std_logic := '0'; signal got_pulse_bad : std_logic := '0'; - -signal last_got_pulse_good : std_logic := '0'; -signal last_got_pulse_bad : std_logic := '0'; +signal last_got_pulse_bad : std_logic := '0'; signal pulse_good_100 : std_logic; signal pulse_bad_100 : std_logic; @@ -106,7 +106,7 @@ signal latched_pulse_good_100 : unsigned(1 downto 0) := "00"; signal waiting_for_retr : std_logic := '0'; signal good_pos_counter : std_logic_vector(7 downto 0) := (others => '0'); signal num_pakets : unsigned(3 downto 0) := (others => '0'); -signal reg_num_pakets : unsigned(3 downto 0) := (others => '0'); +--signal reg_num_pakets : unsigned(3 downto 0) := (others => '0'); signal num_read_words : unsigned(2 downto 0) := (others => '0'); signal use_crc : std_logic := '0'; @@ -116,10 +116,10 @@ signal load_use_crc : std_logic := '0'; signal load_use_crc_sys : std_logic := '0'; signal disable_crc : std_logic := '0'; -signal num_crc : unsigned(3 downto 0) := (others => '0'); -signal num_pak : unsigned(3 downto 0) := (others => '0'); -signal resub_mode : std_logic := '0'; -signal reset_retrans : std_logic; +signal num_crc : unsigned(3 downto 0) := (others => '0'); +signal num_pak : unsigned(3 downto 0) := (others => '0'); +signal resub_mode : std_logic := '0'; +signal reset_retrans : std_logic; signal force_crc_error_int : std_logic := '0'; signal force_crc_error_200 : std_logic := '0'; @@ -134,22 +134,16 @@ begin ---------------------------------------------------------------------- ---ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty and (pulse_good_100 or got_pulse_good or pulse_bad_100 or got_pulse_bad or not use_crc); -- when rising_edge(CLK_100); ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty and (got_pulse_good or got_pulse_bad or not use_crc); - ---buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty and (((pulse_good_100 or got_pulse_good) and not (pulse_bad_100 or got_pulse_bad)) or not use_crc) ---buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty and not got_pulse_bad --- when rising_edge(CLK_100); -RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) when rising_edge(CLK_100); -RX_WRITE_OUT <= buf2_rx_write_out; -RX_PACKET_NUMBER_OUT <= rx_packet_num; +buf_RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) when rising_edge(CLK_100); +RX_DATA_OUT <= buf_RX_DATA_OUT; +RX_WRITE_OUT <= buf2_rx_write_out; +RX_PACKET_NUMBER_OUT <= rx_packet_num when rising_edge(CLK_100); last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_100); last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_100); last_use_crc <= use_crc when rising_edge(CLK_100); -last_got_pulse_good <= got_pulse_good when rising_edge(CLK_100); ---last_got_pulse_bad <= got_pulse_bad when rising_edge(CLK_100); reset_retrans <= RESET_RETRANSMIT_IN when rising_edge(CLK_100); load_use_crc_sys <= load_use_crc when rising_edge(CLK_100); @@ -204,7 +198,6 @@ process begin --with the fresh new paket after resubmit --(see also pulse_bad in GET_RETR) if (pulse_good_100 = '1' or latched_pulse_good_100 /= "00") and got_pulse_bad = '1' and num_read_words /= "010" and ct_fifo_data_out(16) = '1' then - buf2_rx_write_out <= '1'; buf_rx_write_out <= '1'; got_pulse_good <= '1'; got_pulse_bad <= '0'; @@ -213,15 +206,22 @@ process begin last_got_pulse_bad <= '0'; else --thats like it should work in normal mode: - last_got_pulse_bad <= got_pulse_bad; - buf2_rx_write_out <= buf_rx_write_out; buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty and not got_pulse_bad; if last_got_pulse_bad = '1' then buf_rx_write_out <= '0'; end if; + last_got_pulse_bad <= got_pulse_bad; end if; - - if last_use_crc = '0' and buf_rx_write_out = '1' then + + if send_link_reset_i = '1' or reset_retrans = '1' then + good_pos_counter <= (others => '0'); + got_pulse_good <= '0'; + got_pulse_bad <= '0'; + num_read_words <= "000"; + latched_pulse_good_100 <= "00"; + latched_pulse_bad_100 <= "00"; + use_crc <= '0'; + elsif last_use_crc = '0' and buf_rx_write_out = '1' then good_pos_counter <= std_logic_vector(unsigned(good_pos_counter)+1); elsif pulse_good_100 = '1' then good_pos_counter <= std_logic_vector(unsigned(good_pos_counter)+5); @@ -236,12 +236,17 @@ process begin rx_packet_num <= std_logic_vector(unsigned(rx_packet_num)+1); end if; end if; +end process; - if send_link_reset_i = '1' or reset_retrans = '1' then - good_pos_counter <= (others => '0'); +process begin + wait until rising_edge(CLK_100); + if (pulse_good_100 = '1' or latched_pulse_good_100 /= "00") and got_pulse_bad = '1' and num_read_words /= "010" and ct_fifo_data_out(16) = '1' then + buf2_rx_write_out <= '1'; + else + buf2_rx_write_out <= buf_rx_write_out; end if; end process; - + ---------------------------------------------------------------------- -- Clock Domain Transfer @@ -388,12 +393,12 @@ PROC_RX_FSM : process begin if (crc_q /= reg_rx_data_in or (force_crc_error_200 = '1' and CRC_ERROR_DELAY_cnt = "0000") or waiting_for_retr = '1' - --- or num_pakets /= 5 + or num_pakets /= 5 or force_crc_error_int = '1') and disable_crc = '0' then -- bad - if force_crc_error_int = '1' then --debug - reg_num_pakets <= reg_num_pakets + 1; - end if; + --if force_crc_error_int = '1' then --debug + -- reg_num_pakets <= reg_num_pakets + 1; + --end if; pulse_bad <= '1'; if waiting_for_retr = '0' then --if crc_q /= reg_rx_data_in then --debug @@ -487,13 +492,13 @@ PROC_RX_FSM : process begin send_link_reset_i <= '0'; end if; - if reset_retrans = '1' then - load_use_crc <= '0'; - crc_reset <= '1'; - waiting_for_retr <= '0'; - num_pakets <= (others => '0'); - resub_mode <= '0'; - end if; +-- if reset_retrans = '1' then +-- load_use_crc <= '0'; +-- crc_reset <= '1'; +-- waiting_for_retr <= '0'; +-- num_pakets <= (others => '0'); +-- resub_mode <= '0'; +-- end if; end process; @@ -589,8 +594,8 @@ DEBUG_OUT(23 downto 20) <= (others => '0'); --DEBUG_OUT(27 downto 24) <= num_crc; DEBUG_OUT(24) <= force_crc_error_int when rising_edge(clk_100); DEBUG_OUT(25) <= use_crc; -DEBUG_OUT(27 downto 26) <= (others => '0'); -DEBUG_OUT(31 downto 28) <= std_logic_vector(reg_num_pakets) when rising_edge(clk_100); +DEBUG_OUT(31 downto 26) <= (others => '0'); +--DEBUG_OUT(31 downto 28) <= std_logic_vector(reg_num_pakets) when rising_edge(clk_100); -- DEBUG_OUT(23 downto 16) <= rx_data(7 downto 0); diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd index 369513c..8d8dbdf 100644 --- a/media_interfaces/sync/tx_control.vhd +++ b/media_interfaces/sync/tx_control.vhd @@ -327,8 +327,8 @@ begin when SEND_START_H => --TX_DATA_OUT <= std_logic_vector(ram_read_addr); - TX_DATA_OUT <= x"FF"; -- - current_state <= SEND_DATA_L; --- + TX_DATA_OUT <= x"FF"; --not used + current_state <= SEND_DATA_L; resub_mode <= '1'; when SEND_REQUEST_L =>