From: Michael Boehmer Date: Tue, 1 Nov 2022 20:11:37 +0000 (+0100) Subject: shifted data stream in ARP handler fixed. Reason unknown. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=27aba52e02d86b2bbf3dec6b114b14b983669b8a;p=trbnet.git shifted data stream in ARP handler fixed. Reason unknown. --- diff --git a/gbe_trb/base/gbe_frame_receiver.vhd b/gbe_trb/base/gbe_frame_receiver.vhd index 8b5967a..61fea34 100644 --- a/gbe_trb/base/gbe_frame_receiver.vhd +++ b/gbe_trb/base/gbe_frame_receiver.vhd @@ -39,8 +39,6 @@ entity gbe_frame_receiver is FR_FRAME_VALID_OUT : out std_logic; -- interconnect to gbe_receive_control FR_GET_FRAME_IN : in std_logic; -- interconnect to gbe_receive_control FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); -- interconnect to gbe_receive_control - FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0); -- interconnect to gbe_receive_control - FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); -- interconnect to gbe_receive_control FR_PS_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -- FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); @@ -92,8 +90,8 @@ architecture gbe_frame_receiver_arch of gbe_frame_receiver is signal rec_fifo_empty : std_logic; signal rec_fifo_full : std_logic; - signal sizes_fifo_full : std_logic; - signal sizes_fifo_empty : std_logic; +-- signal sizes_fifo_full : std_logic; +-- signal sizes_fifo_empty : std_logic; signal remove_ctr : unsigned(7 downto 0); signal new_frame : std_logic; @@ -123,22 +121,19 @@ architecture gbe_frame_receiver_arch of gbe_frame_receiver is signal fr_dest_udp : std_logic_vector(15 downto 0); signal fr_src_udp : std_logic_vector(15 downto 0); signal fr_frame_size : std_logic_vector(15 downto 0); - signal fr_frame_proto : std_logic_vector(15 downto 0); signal fr_dest_mac : std_logic_vector(47 downto 0); signal fr_src_mac : std_logic_vector(47 downto 0); - signal fr_ip_proto : std_logic_vector(7 downto 0); signal fr_ps : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - signal xxx0 : std_logic_vector(7 downto 0); - signal xxx1 : std_logic_vector(7 downto 0); - signal oob_register_0_int : std_logic_vector(31 downto 0); signal oob_register_1_int : std_logic_vector(31 downto 0); signal oob_register_2_int : std_logic_vector(31 downto 0); signal oob_register_3_int : std_logic_vector(31 downto 0); signal oob_write : std_logic; - signal proto_select_x : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal oob_select_x : std_logic; + signal oob_select : std_logic; + signal proto_select : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); signal set_proto_x : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); @@ -178,8 +173,10 @@ begin begin if ( RESET = '1' ) then filter_current_state <= IDLE; + oob_select <= '0'; elsif( rising_edge(CLK) ) then filter_current_state <= filter_next_state; + oob_select <= oob_select_x; end if; end process PROC_FILTER_FSM; @@ -187,6 +184,7 @@ begin saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN) begin set_proto_x <= (others => '0'); + oob_select_x <= '0'; case filter_current_state is @@ -274,6 +272,7 @@ begin set_proto_x(2) <= '1'; when others => filter_next_state <= DROP_FRAME; + oob_select_x <= '1'; end case; else filter_next_state <= REMOVE_UDP; @@ -308,21 +307,6 @@ begin end case; end process PROC_FILTER_TRANSITIONS; - -- determine the protocol handler for later usage - -- ARP - proto_select_x(0) <= '1' when ( (saved_frame_type = x"0806") ) else '0'; - -- DHCP - proto_select_x(1) <= '1' when ( (saved_frame_type = x"0800") and (saved_proto = x"11") and (saved_dest_udp = x"0044") ) else '0'; - -- SCTRL - proto_select_x(2) <= '1' when ( (saved_frame_type = x"0800") and (saved_proto = x"11") and (saved_dest_udp = x"6590") ) else '0'; - -- ??? - proto_select_x(3) <= '0'; - -- ICMP - proto_select_x(4) <= '1' when ( (saved_frame_type = x"0800") and (saved_proto = x"01") ) else '0'; - -- FWD??? - proto_select_x(5) <= '0'; - -- TO BE INCLUDED INTO FSM!!! - -- protocol selection PROC_PROTO_SEL: process( CLK, RESET ) begin @@ -526,10 +510,11 @@ begin end if; end process PROC_KILLER_PING; + -- BROKEN!!! PROC_SECRET_FRAME: process( CLK ) begin if( rising_edge(CLK) ) then - if( (filter_current_state = DELAY) and + if( (oob_select = '1') and (saved_proto = x"11") and (saved_frame_type = x"0800") and (saved_dest_udp = x"d903") and @@ -582,27 +567,11 @@ begin end if; end process PROC_RX_FIFO_SYNC; - THE_SIZES_FIFO: entity work.fifo_512x32 - port map( - Data(15 downto 0) => rx_bytes_ctr, - Data(31 downto 16) => saved_frame_type, - WrClock => CLK, - RdClock => CLK, - WrEn => frame_valid_q, - RdEn => FR_GET_FRAME_IN, - Reset => RESET, - RPReset => RESET, - Q(15 downto 0) => fr_frame_size, - Q(31 downto 16) => fr_frame_proto, - Empty => sizes_fifo_empty, - Full => sizes_fifo_full - ); - THE_MACS_FIFO: entity work.fifo_512x72 port map( Data(47 downto 0) => saved_src_mac, Data(63 downto 48) => saved_src_udp, - Data(71 downto 64) => (others => '0'), + Data(71 downto 64) => rx_bytes_ctr(7 downto 0), --(others => '0'), WrClock => CLK, RdClock => CLK, WrEn => frame_valid_q, @@ -611,7 +580,7 @@ begin RPReset => RESET, Q(47 downto 0) => fr_src_mac, Q(63 downto 48) => fr_src_udp, - Q(71 downto 64) => xxx0, --open, + Q(71 downto 64) => fr_frame_size(7 downto 0), --open, Empty => open, Full => open ); @@ -620,7 +589,6 @@ begin port map( Data(47 downto 0) => saved_dest_mac, Data(63 downto 48) => saved_dest_udp, --- Data(71 downto 64) => (others => '0'), Data(69 downto 64) => proto_select, Data(71 downto 70) => (others => '0'), WrClock => CLK, @@ -631,9 +599,8 @@ begin RPReset => RESET, Q(47 downto 0) => fr_dest_mac, Q(63 downto 48) => fr_dest_udp, --- Q(71 downto 64) => xxx1, --open, - Q(69 downto 64) => fr_ps, --open, - Q(71 downto 70) => xxx1(1 downto 0), --open, + Q(69 downto 64) => fr_ps, + Q(71 downto 70) => open, Empty => open, Full => open ); @@ -642,7 +609,7 @@ begin port map( Data(31 downto 0) => saved_src_ip, Data(63 downto 32) => saved_dest_ip, - Data(71 downto 64) => saved_proto, + Data(71 downto 64) => rx_bytes_ctr(15 downto 8), --saved_proto, WrClock => CLK, RdClock => CLK, WrEn => frame_valid_q, @@ -651,7 +618,7 @@ begin RPReset => RESET, Q(31 downto 0) => fr_src_ip, Q(63 downto 32) => fr_dest_ip, - Q(71 downto 64) => fr_ip_proto, + Q(71 downto 64) => fr_frame_size(15 downto 8), --open, Empty => open, Full => open ); @@ -661,19 +628,16 @@ begin if( rising_edge(CLK) ) then FR_SRC_IP_ADDRESS_OUT <= fr_src_ip; FR_DEST_IP_ADDRESS_OUT <= fr_dest_ip; - FR_IP_PROTOCOL_OUT <= fr_ip_proto; FR_DEST_UDP_PORT_OUT <= fr_dest_udp; FR_DEST_MAC_ADDRESS_OUT <= fr_dest_mac; FR_SRC_MAC_ADDRESS_OUT <= fr_src_mac; FR_SRC_UDP_PORT_OUT <= fr_src_udp; - FR_FRAME_PROTO_OUT <= fr_frame_proto; FR_FRAME_SIZE_OUT <= fr_frame_size; FR_Q_OUT <= fr_q; FR_PS_OUT <= fr_ps; -- delayed_frame_valid <= MAC_RX_EOF_IN; delayed_frame_valid_q <= delayed_frame_valid; --- proto_select <= proto_select_x; end if; end process PROC_SYNC; diff --git a/gbe_trb/base/gbe_logic_wrapper.vhd b/gbe_trb/base/gbe_logic_wrapper.vhd index b16e447..a9647d6 100644 --- a/gbe_trb/base/gbe_logic_wrapper.vhd +++ b/gbe_trb/base/gbe_logic_wrapper.vhd @@ -109,7 +109,7 @@ architecture gbe_logic_wrapper_arch of gbe_logic_wrapper is signal fr_get_frame : std_logic; signal mc_transmit_done : std_logic; - signal fr_frame_proto : std_logic_vector(15 downto 0); +-- signal fr_frame_proto : std_logic_vector(15 downto 0); signal rc_frame_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); signal mc_type : std_logic_vector(15 downto 0); @@ -149,7 +149,7 @@ architecture gbe_logic_wrapper_arch of gbe_logic_wrapper is signal ft_tx_empty : std_logic; signal ft_start_of_packet : std_logic; - signal fr_ip_proto : std_logic_vector(7 downto 0); +-- signal fr_ip_proto : std_logic_vector(7 downto 0); signal mc_ip_proto : std_logic_vector(7 downto 0); signal mc_ident : std_logic_vector(15 downto 0); @@ -170,7 +170,34 @@ architecture gbe_logic_wrapper_arch of gbe_logic_wrapper is signal fr_ps_int : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -begin + signal dbg_main : std_logic_vector(63 downto 0); + + begin + +--------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------- +-- DEBUG_OUT(31 downto 0) <= (others => '0'); + -- TX + DEBUG_OUT(31 downto 28) <= dbg_main(7 downto 4); + DEBUG_OUT(27) <= '0'; + DEBUG_OUT(26) <= mc_transmit_done; + DEBUG_OUT(25) <= mc_transmit_ctrl; + DEBUG_OUT(24) <= mc_wr_en; + DEBUG_OUT(23 downto 20) <= dbg_main(15 downto 12); + DEBUG_OUT(19 downto 16) <= dbg_main(11 downto 8); +-- DEBUG_OUT(23 downto 16) <= mc_data(7 downto 0); + -- RX + DEBUG_OUT(15) <= rc_loading_done; + DEBUG_OUT(14) <= rc_frame_ready; + DEBUG_OUT(13) <= rc_frame_proto(4); -- ICMP + DEBUG_OUT(12) <= rc_frame_proto(1); -- DHCP + DEBUG_OUT(11) <= rc_frame_proto(0); -- ARP + DEBUG_OUT(10) <= fr_get_frame; + DEBUG_OUT(9) <= fr_frame_valid; + DEBUG_OUT(8) <= fr_rd_en; + DEBUG_OUT(7 downto 0) <= rc_q(7 downto 0); +--------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------- fc_ihl_version <= x"45"; fc_tos <= x"10"; @@ -255,8 +282,9 @@ begin FWD_READY_OUT => FWD_READY_OUT, FWD_FULL_OUT => FWD_FULL_OUT, -- - DEBUG_OUT(15 downto 0) => DEBUG_OUT(31 downto 16), - DEBUG_OUT(63 downto 16) => open, + DEBUG_OUT => dbg_main, +-- DEBUG_OUT(15 downto 0) => open, +-- DEBUG_OUT(63 downto 16) => open, -- MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen ); @@ -352,8 +380,6 @@ begin FR_FRAME_VALID_IN => fr_frame_valid, FR_GET_FRAME_OUT => fr_get_frame, FR_FRAME_SIZE_IN => fr_frame_size, - FR_FRAME_PROTO_IN => fr_frame_proto, - FR_IP_PROTOCOL_IN => fr_ip_proto, FR_PS_IN => fr_ps_int, FR_SRC_MAC_ADDRESS_IN => fr_src_mac, FR_DEST_MAC_ADDRESS_IN => fr_dest_mac, @@ -401,13 +427,7 @@ begin FR_FRAME_VALID_OUT => fr_frame_valid, FR_GET_FRAME_IN => fr_get_frame, FR_FRAME_SIZE_OUT => fr_frame_size, - FR_FRAME_PROTO_OUT => fr_frame_proto, - FR_IP_PROTOCOL_OUT => fr_ip_proto, FR_PS_OUT => fr_ps_int, --- FR_ALLOWED_TYPES_IN => (others => '1'), --fr_allowed_types, --- FR_ALLOWED_IP_IN => (others => '1'), --fr_allowed_ip, --- FR_ALLOWED_UDP_IN => (others => '1'), --fr_allowed_udp, --- FR_VLAN_ID_IN => (others => '0'), --vlan_id, -- FR_SRC_MAC_ADDRESS_OUT => fr_src_mac, FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac, @@ -425,7 +445,7 @@ begin MONITOR_RX_FRAMES_OUT => monitor_rx_frames, MONITOR_DROPPED_OUT => monitor_dropped, -- - DEBUG_OUT(15 downto 0) => DEBUG_OUT(15 downto 0), --open + DEBUG_OUT(15 downto 0) => open, DEBUG_OUT(31 downto 16) => open ); diff --git a/gbe_trb/base/gbe_main_control.vhd b/gbe_trb/base/gbe_main_control.vhd index c364922..4b1c52c 100644 --- a/gbe_trb/base/gbe_main_control.vhd +++ b/gbe_trb/base/gbe_main_control.vhd @@ -133,7 +133,6 @@ architecture gbe_main_control_arch of gbe_main_control is signal redirect_current_state, redirect_next_state : redirect_states; attribute syn_encoding of redirect_current_state : signal is "onehot"; - signal disable_redirect : std_logic; signal ps_wr_en_q : std_logic; signal ps_wr_en_qq : std_logic; @@ -141,8 +140,10 @@ architecture gbe_main_control_arch of gbe_main_control is attribute syn_preserve : boolean; attribute syn_keep : boolean; - attribute syn_keep of link_state, state, redirect_state, dhcp_done : signal is true; - attribute syn_preserve of link_state, state, redirect_state, dhcp_done : signal is true; + attribute syn_keep of link_state, redirect_state, dhcp_done : signal is true; + attribute syn_preserve of link_state, redirect_state, dhcp_done : signal is true; +-- attribute syn_keep of link_state, state, redirect_state, dhcp_done : signal is true; +-- attribute syn_preserve of link_state, state, redirect_state, dhcp_done : signal is true; signal mc_busy : std_logic; signal incl_dhcp : std_logic; @@ -155,9 +156,8 @@ begin DEBUG_OUT(15 downto 12) <= link_state; DEBUG_OUT(11 downto 8) <= redirect_state; - DEBUG_OUT(7) <= '0'; - DEBUG_OUT(6) <= disable_redirect; - DEBUG_OUT(5 downto 0) <= RC_FRAME_PROTO_IN; + DEBUG_OUT(7 downto 4) <= flow_state; + DEBUG_OUT(3 downto 0) <= (others => '0'); THE_PROTOCOL_SELECTOR: entity work.gbe_protocol_selector generic map( @@ -238,31 +238,9 @@ begin TC_DATA_OUT <= tc_data; - -- gk 07.11.11 - -- do not select any response constructors when dropping a frame -- proto_select <= RC_FRAME_PROTO_IN when disable_redirect = '0' else (others => '0'); proto_select <= RC_FRAME_PROTO_IN; - -- gk 07.11.11 - -- we do not answer at all, unless we are in either ACTIVE or GET_ADDRESS state. - -- in GET_ADDRESS state, we only answer on DHCP frames. - PROC_DISABLE_REDIRECT: process( CLK, RESET ) - begin - if ( RESET = '1' ) then - disable_redirect <= '0'; - elsif( rising_edge(CLK) ) then - if( redirect_current_state = CHECK_TYPE ) then - if ( (link_current_state /= ACTIVE) and (link_current_state /= GET_ADDRESS) ) then - disable_redirect <= '1'; - elsif( (link_current_state = GET_ADDRESS) and (RC_FRAME_PROTO_IN /= "10") ) then -- (UDP, DHCP) - disable_redirect <= '1'; - else - disable_redirect <= '0'; - end if; - end if; - end if; - end process PROC_DISABLE_REDIRECT; - -- warning PROC_SYNC: process( CLK ) begin diff --git a/gbe_trb/base/gbe_receive_control.vhd b/gbe_trb/base/gbe_receive_control.vhd index 2e3d504..99c521c 100644 --- a/gbe_trb/base/gbe_receive_control.vhd +++ b/gbe_trb/base/gbe_receive_control.vhd @@ -1,204 +1,185 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.gbe_protocols.all; - -entity gbe_receive_control is - port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - -- signals to/from frame_receiver - RC_DATA_IN : in std_logic_vector(8 downto 0); - FR_RD_EN_OUT : out std_logic; - FR_FRAME_VALID_IN : in std_logic; - FR_GET_FRAME_OUT : out std_logic; - FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - FR_FRAME_PROTO_IN : in std_logic_vector(15 downto 0); - FR_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); - FR_PS_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - -- signals to/from main controller - RC_RD_EN_IN : in std_logic; - RC_Q_OUT : out std_logic_vector(8 downto 0); - RC_FRAME_WAITING_OUT : out std_logic; - RC_LOADING_DONE_IN : in std_logic; - RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - -- statistics - FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0); - BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0); - -- - DEBUG_OUT : out std_logic_vector(63 downto 0) - ); -end gbe_receive_control; - -architecture gbe_receive_control_arch of gbe_receive_control is - - attribute syn_encoding : string; - - type load_states is (IDLE, PREPARE, WAIT_ONE, READY); - signal load_current_state, load_next_state : load_states; - attribute syn_encoding of load_current_state : signal is "onehot"; - - signal frames_received_ctr : unsigned(31 downto 0); - signal frames_readout_ctr : unsigned(31 downto 0); - signal bytes_rec_ctr : unsigned(31 downto 0); - - signal state : std_logic_vector(3 downto 0); - signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - signal reset_prioritizer : std_logic; - - -- debug only - signal saved_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - -begin - - FR_RD_EN_OUT <= RC_RD_EN_IN; - RC_Q_OUT <= RC_DATA_IN; - RC_FRAME_SIZE_OUT <= FR_FRAME_SIZE_IN; - RC_SRC_MAC_ADDRESS_OUT <= FR_SRC_MAC_ADDRESS_IN; - RC_DEST_MAC_ADDRESS_OUT <= FR_DEST_MAC_ADDRESS_IN; - RC_SRC_IP_ADDRESS_OUT <= FR_SRC_IP_ADDRESS_IN; - RC_DEST_IP_ADDRESS_OUT <= FR_DEST_IP_ADDRESS_IN; - RC_SRC_UDP_PORT_OUT <= FR_SRC_UDP_PORT_IN; - RC_DEST_UDP_PORT_OUT <= FR_DEST_UDP_PORT_IN; - --- protocol_prioritizer: entity work.gbe_protocol_prioritizer --- port map( --- CLK => CLK, --- RESET => reset_prioritizer, --- -- --- FRAME_TYPE_IN => FR_FRAME_PROTO_IN, --- PROTOCOL_CODE_IN => FR_IP_PROTOCOL_IN, --- UDP_PROTOCOL_IN => FR_DEST_UDP_PORT_IN, --- -- --- CODE_OUT => proto_code --- ); --- --- reset_prioritizer <= '1' when load_current_state = IDLE else '0'; --- --- RC_FRAME_PROTO_OUT <= proto_code; -- no more ones as the incorrect value, last slot for Trash - - RC_FRAME_PROTO_OUT <= FR_PS_IN when (load_current_state /= IDLE) else (others => '0'); - - LOAD_MACHINE_PROC: process( CLK, RESET ) - begin - if ( RESET = '1' ) then - load_current_state <= IDLE; - elsif( rising_edge(CLK) ) then - load_current_state <= load_next_state; - end if; - end process LOAD_MACHINE_PROC; - - LOAD_MACHINE: process( load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN ) - begin - case load_current_state is - - when IDLE => - state <= x"1"; - if( frames_readout_ctr /= frames_received_ctr ) then -- frame is still waiting in frame_receiver - load_next_state <= PREPARE; - else - load_next_state <= IDLE; - end if; - - when PREPARE => -- prepare frame size - state <= x"2"; - load_next_state <= WAIT_ONE; - - when WAIT_ONE => - load_next_state <= READY; - - when READY => -- wait for reading out the whole frame - state <= x"3"; - if( RC_LOADING_DONE_IN = '1' ) then - load_next_state <= IDLE; - else - load_next_state <= READY; - end if; - - end case; - end process LOAD_MACHINE; - - process( CLK ) - begin - if( rising_edge(CLK) ) then - if( load_current_state = PREPARE ) then - FR_GET_FRAME_OUT <= '1'; - else - FR_GET_FRAME_OUT <= '0'; - end if; - - if( (load_current_state = READY) and (RC_LOADING_DONE_IN = '0') ) then - RC_FRAME_WAITING_OUT <= '1'; - else - RC_FRAME_WAITING_OUT <= '0'; - end if; - end if; - end process; - - FRAMES_REC_CTR_PROC: process( CLK, RESET ) - begin - if ( RESET = '1' ) then - frames_received_ctr <= (others => '0'); - elsif( rising_edge(CLK) ) then - if( FR_FRAME_VALID_IN = '1' ) then - frames_received_ctr <= frames_received_ctr + 1; - end if; - end if; - end process FRAMES_REC_CTR_PROC; - - FRAMES_READOUT_CTR_PROC: process( CLK, RESET ) - begin - if ( RESET = '1' ) then - frames_readout_ctr <= (others => '0'); - elsif( rising_edge(CLK) ) then - if( RC_LOADING_DONE_IN = '1' ) then - frames_readout_ctr <= frames_readout_ctr + 1; - end if; - end if; - end process FRAMES_READOUT_CTR_PROC; - - -- debug only - BYTES_REC_CTR_PROC : process( CLK ) - begin - if ( RESET = '1' ) then - bytes_rec_ctr <= (others => '0'); - elsif( rising_edge(CLK) ) then - if( FR_FRAME_VALID_IN = '1' ) then - bytes_rec_ctr <= bytes_rec_ctr + unsigned(FR_FRAME_SIZE_IN); - end if; - end if; - end process BYTES_REC_CTR_PROC; - - SAVED_PROTO_PROC : process( CLK ) - begin - if( rising_edge(CLK) ) then - if( load_current_state = READY ) then - if( and_all(proto_code) = '0' ) then - saved_proto <= proto_code; - else - saved_proto <= (others => '0'); - end if; - else - saved_proto <= saved_proto; - end if; - end if; - end process SAVED_PROTO_PROC; - -end gbe_receive_control_arch; +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.gbe_protocols.all; + +entity gbe_receive_control is + port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + -- signals to/from frame_receiver + RC_DATA_IN : in std_logic_vector(8 downto 0); + FR_RD_EN_OUT : out std_logic; + FR_FRAME_VALID_IN : in std_logic; + FR_GET_FRAME_OUT : out std_logic; + FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + FR_PS_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + -- signals to/from main controller + RC_RD_EN_IN : in std_logic; + RC_Q_OUT : out std_logic_vector(8 downto 0); + RC_FRAME_WAITING_OUT : out std_logic; + RC_LOADING_DONE_IN : in std_logic; + RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + -- statistics + FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0); + BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0); + -- + DEBUG_OUT : out std_logic_vector(63 downto 0) + ); +end gbe_receive_control; + +architecture gbe_receive_control_arch of gbe_receive_control is + + attribute syn_encoding : string; + + type load_states is (IDLE, PREPARE, WAIT_ONE, READY); + signal load_current_state, load_next_state : load_states; + attribute syn_encoding of load_current_state : signal is "onehot"; + + signal frames_received_ctr : unsigned(31 downto 0); + signal frames_readout_ctr : unsigned(31 downto 0); + signal bytes_rec_ctr : unsigned(31 downto 0); + + signal state : std_logic_vector(3 downto 0); + signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal reset_prioritizer : std_logic; + + -- debug only + signal saved_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + +begin + + FR_RD_EN_OUT <= RC_RD_EN_IN; + RC_Q_OUT <= RC_DATA_IN; + RC_FRAME_SIZE_OUT <= FR_FRAME_SIZE_IN; + RC_SRC_MAC_ADDRESS_OUT <= FR_SRC_MAC_ADDRESS_IN; + RC_DEST_MAC_ADDRESS_OUT <= FR_DEST_MAC_ADDRESS_IN; + RC_SRC_IP_ADDRESS_OUT <= FR_SRC_IP_ADDRESS_IN; + RC_DEST_IP_ADDRESS_OUT <= FR_DEST_IP_ADDRESS_IN; + RC_SRC_UDP_PORT_OUT <= FR_SRC_UDP_PORT_IN; + RC_DEST_UDP_PORT_OUT <= FR_DEST_UDP_PORT_IN; + RC_FRAME_PROTO_OUT <= FR_PS_IN when (load_current_state /= IDLE) else (others => '0'); + + LOAD_MACHINE_PROC: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + load_current_state <= IDLE; + elsif( rising_edge(CLK) ) then + load_current_state <= load_next_state; + end if; + end process LOAD_MACHINE_PROC; + + LOAD_MACHINE: process( load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN ) + begin + case load_current_state is + + when IDLE => + state <= x"1"; + if( frames_readout_ctr /= frames_received_ctr ) then -- frame is still waiting in frame_receiver + load_next_state <= PREPARE; + else + load_next_state <= IDLE; + end if; + + when PREPARE => -- prepare frame size + state <= x"2"; + load_next_state <= WAIT_ONE; + + when WAIT_ONE => + load_next_state <= READY; + + when READY => -- wait for reading out the whole frame + state <= x"3"; + if( RC_LOADING_DONE_IN = '1' ) then + load_next_state <= IDLE; + else + load_next_state <= READY; + end if; + + end case; + end process LOAD_MACHINE; + + process( CLK ) + begin + if( rising_edge(CLK) ) then + if( load_current_state = PREPARE ) then + FR_GET_FRAME_OUT <= '1'; + else + FR_GET_FRAME_OUT <= '0'; + end if; + + if( (load_current_state = READY) and (RC_LOADING_DONE_IN = '0') ) then + RC_FRAME_WAITING_OUT <= '1'; + else + RC_FRAME_WAITING_OUT <= '0'; + end if; + end if; + end process; + + FRAMES_REC_CTR_PROC: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + frames_received_ctr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( FR_FRAME_VALID_IN = '1' ) then + frames_received_ctr <= frames_received_ctr + 1; + end if; + end if; + end process FRAMES_REC_CTR_PROC; + + FRAMES_READOUT_CTR_PROC: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + frames_readout_ctr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( RC_LOADING_DONE_IN = '1' ) then + frames_readout_ctr <= frames_readout_ctr + 1; + end if; + end if; + end process FRAMES_READOUT_CTR_PROC; + + -- debug only + BYTES_REC_CTR_PROC : process( CLK ) + begin + if ( RESET = '1' ) then + bytes_rec_ctr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( FR_FRAME_VALID_IN = '1' ) then + bytes_rec_ctr <= bytes_rec_ctr + unsigned(FR_FRAME_SIZE_IN); + end if; + end if; + end process BYTES_REC_CTR_PROC; + + SAVED_PROTO_PROC : process( CLK ) + begin + if( rising_edge(CLK) ) then + if( load_current_state = READY ) then + if( and_all(proto_code) = '0' ) then + saved_proto <= proto_code; + else + saved_proto <= (others => '0'); + end if; + else + saved_proto <= saved_proto; + end if; + end if; + end process SAVED_PROTO_PROC; + +end gbe_receive_control_arch; diff --git a/gbe_trb/protocols/gbe_response_constructor_ARP.vhd b/gbe_trb/protocols/gbe_response_constructor_ARP.vhd index 8937b4e..6e26a70 100644 --- a/gbe_trb/protocols/gbe_response_constructor_ARP.vhd +++ b/gbe_trb/protocols/gbe_response_constructor_ARP.vhd @@ -151,10 +151,12 @@ begin PROC_DATA_CTR: process( CLK, RESET ) begin if ( RESET = '1' ) then - data_ctr <= 1; + data_ctr <= 0; +-- data_ctr <= 1; elsif( rising_edge(CLK) ) then if ( (dissect_current_state = IDLE) and (PS_WR_EN_IN = '0') ) then - data_ctr <= 1; + data_ctr <= 0; +-- data_ctr <= 1; elsif( dissect_current_state = WAIT_FOR_LOAD ) then data_ctr <= 1; elsif( dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' ) then