From: Peter Lemmens Date: Wed, 4 Sep 2013 10:05:28 +0000 (+0200) Subject: Added a module to fake a start-of-burst signal with a 2.4us period X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=284804339ad29178b272d4f175f93d4e9c154980;p=soda.git Added a module to fake a start-of-burst signal with a 2.4us period --- diff --git a/soda_source.ldf b/soda_source.ldf index 4f9bd9f..149b52b 100644 --- a/soda_source.ldf +++ b/soda_source.ldf @@ -299,6 +299,12 @@ + + + + + + diff --git a/soda_source/soda_source_syn.prj b/soda_source/soda_source_syn.prj index 288ce95..315b355 100644 --- a/soda_source/soda_source_syn.prj +++ b/soda_source/soda_source_syn.prj @@ -1,13 +1,14 @@ #-- Synopsys, Inc. #-- Version G-2012.09L-1 #-- Project file /local/lemmens/lattice/soda/soda_source/soda_source_syn.prj -#-- Written on Thu Aug 8 09:58:23 2013 +#-- Written on Tue Sep 3 13:13:24 2013 #project files add_file -vhdl -lib work "/usr/local/diamond/2.1_x64/cae_library/synthesis/vhdl/ecp3.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/version.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_components.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_source.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_d8crc8.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_packet_builder.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_packet_handler.vhd" @@ -103,7 +104,6 @@ add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/trb_net16_f add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_logic.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_flash_and_fpga_reload.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/soda_source.vhd" #implementation: "soda_source" diff --git a/source/soda_SOB_faker.vhd b/source/soda_SOB_faker.vhd new file mode 100644 index 0000000..bd01282 --- /dev/null +++ b/source/soda_SOB_faker.vhd @@ -0,0 +1,51 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use ieee.std_logic_unsigned.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.soda_components.all; + +entity soda_start_of_burst_faker is + generic( + cCLOCK_PERIOD : natural range 1 to 20 := 5; -- clock-period in ns + cBURST_PERIOD : natural := 2400 -- burst-period in ns + ); + port( + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + SODA_BURST_PULSE_OUT : out std_logic := '0' + ); +end soda_start_of_burst_faker; + +architecture Behavioral of soda_start_of_burst_faker is + + constant cCLOCKS_PER_BURST : std_logic_vector(15 downto 0) := conv_std_logic_vector((cBURST_PERIOD / cCLOCK_PERIOD) - 1, 16); + + signal burst_counter_S : std_logic_vector(15 downto 0) := (others => '0'); -- from super-burst-nr-generator + + +begin + + burst_pulse_edge_proc : process(SYSCLK) + begin + if rising_edge(SYSCLK) then + if (RESET='1') then + burst_counter_S <= cCLOCKS_PER_BURST; + SODA_BURST_PULSE_OUT <= '0'; + elsif (burst_counter_S=0) then + burst_counter_S <= cCLOCKS_PER_BURST; + SODA_BURST_PULSE_OUT <= '1'; + else + burst_counter_S <= burst_counter_S - 1; + SODA_BURST_PULSE_OUT <= '0'; + end if; + end if; + end process; + + +end Behavioral; diff --git a/source/soda_components.vhd b/source/soda_components.vhd index 2b63a24..9ac5969 100644 --- a/source/soda_components.vhd +++ b/source/soda_components.vhd @@ -9,34 +9,46 @@ use work.trb_net16_hub_func.all; package soda_components is + constant c_HUB_CHILDREN : natural range 1 to 4 := 2; + type t_HUB_DLM is array(c_HUB_CHILDREN-1 downto 0) of std_logic; + type t_HUB_DLM_WORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0); + type t_PACKET_TYPE_SENT is (c_NO_PACKET, c_CMD_PACKET, c_BST_PACKET); + type t_PACKET_TYPE_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of t_PACKET_TYPE_SENT; + type t_HUB_BIT_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic; + type t_HUB_BYTE_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0); + type t_HUB_WORD_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(31 downto 0); + - component super_burst_generator + component soda_superburst_generator generic( BURST_COUNT : integer range 1 to 64 := 16 -- number of bursts to be counted between super-bursts ); port( - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; --Internal Connection - SODA_BURST_PULSE_IN : in std_logic := '0'; -- - START_OF_SUPERBURST : out std_logic := '0'; - SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0') + SODA_BURST_PULSE_IN : in std_logic := '0'; -- + START_OF_SUPERBURST : out std_logic := '0'; + SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0') ); end component; component soda_packet_builder port( - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; --Internal Connection - SODA_CMD_STROBE_IN : in std_logic := '0'; -- - START_OF_SUPERBURST : in std_logic := '0'; - SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); - SODA_CMD_WORD_IN : in std_logic_vector(31 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit + LINK_PHASE : natural range 0 to 1 := 0; + SODA_CMD_STROBE_IN : in std_logic := '0'; -- + START_OF_SUPERBURST : in std_logic := '0'; + SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); + SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit + EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + TIME_CAL_OUT : out std_logic := '0'; -- TX_DLM_OUT : out std_logic := '0'; -- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0') ); @@ -49,21 +61,28 @@ package soda_components is CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; --Internal Connection - RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); - RX_DLM_IN : in std_logic - ); + START_OF_SUPERBURST : out std_logic := '0'; + SUPER_BURST_NR : out std_logic_vector(30 downto 0) := (others => '0'); + SODA_CMD_VALID_S : out std_logic := '0'; + SODA_CMD_WORD_S : out std_logic_vector(30 downto 0) := (others => '0'); + EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + CRC_VALID_OUT : out std_logic := '0'; + CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + RX_DLM_IN : in std_logic; + RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0') + ); end component; component soda_d8crc8 -- crc-calculator/checker port( - clock : in std_logic; - reset : in std_logic; - soc : in std_logic; - data : in std_logic_vector(7 downto 0); - data_valid : in std_logic; - eoc : in std_logic; - crc : out std_logic_vector(7 downto 0); - crc_valid : out std_logic + CLOCK : in std_logic; + RESET : in std_logic; + SOC_IN : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + DATA_VALID_IN : in std_logic; + EOC_IN : in std_logic; + CRC_OUT : out std_logic_vector(7 downto 0); + CRC_VALID_OUT : out std_logic ); end component; @@ -89,38 +108,131 @@ package soda_components is SODA_READ_IN : in std_logic := '0'; SODA_WRITE_IN : in std_logic := '0'; SODA_ACK_OUT : out std_logic := '0'; - LEDS_ACT_OUT : out std_logic; LEDS_OUT : out std_logic_vector(3 downto 0); - SPARE_LINE : in std_logic_vector(5 downto 0); TEST_LINE : out std_logic_vector(15 downto 0); -- Status lines STAT : out std_logic_vector(31 downto 0) -- DEBUG ); end component; - -component spi_flash_and_fpga_reload - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - BUS_ADDR_IN : in std_logic_vector(8 downto 0); - BUS_READ_IN : in std_logic; - BUS_WRITE_IN : in std_logic; - BUS_DATAREADY_OUT : out std_logic; - BUS_WRITE_ACK_OUT : out std_logic; - BUS_UNKNOWN_ADDR_OUT : out std_logic; - BUS_NO_MORE_DATA_OUT : out std_logic; - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); - - DO_REBOOT_IN : in std_logic; - PROGRAMN : out std_logic; - - SPI_CS_OUT : out std_logic; - SPI_SCK_OUT : out std_logic; - SPI_SDO_OUT : out std_logic; - SPI_SDI_IN : in std_logic - ); -end component; + + component soda_hub + port( + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + -- SINGLE DUBPLEX LINK TO THE TOP + RXTOP_DLM_IN : in std_logic; + RXTOP_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); + TXTOP_DLM_OUT : out std_logic; + TXTOP_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + -- MULTIPLE DUPLEX LINKS TO THE BOTTOM + RXBTM_DLM_IN : in t_HUB_DLM; -- typedef in soda_components.vhd + RXBTM_DLM_WORD_IN : in t_HUB_DLM_WORD; -- typedef in soda_components.vhd + TXBTM_DLM_OUT : out t_HUB_DLM; -- typedef in soda_components.vhd + TXBTM_DLM_WORD_OUT : out t_HUB_DLM_WORD; -- typedef in soda_components.vhd + + SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); + SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); + SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); + SODA_READ_IN : in std_logic := '0'; + SODA_WRITE_IN : in std_logic := '0'; + SODA_ACK_OUT : out std_logic := '0'; + STAT : out std_logic_vector(31 downto 0) := (others => '0') -- DEBUG + ); + end component; + + component soda_client -- box containing soda_source components + port( + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); + RX_DLM_IN : in std_logic; + TX_DLM_OUT : out std_logic; + TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + + SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); + SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); + SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); + SODA_READ_IN : in std_logic := '0'; + SODA_WRITE_IN : in std_logic := '0'; + SODA_ACK_OUT : out std_logic := '0'; + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component; + + component soda_reply_pkt_builder + port( + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + START_OF_SUPERBURST : in std_logic := '0'; + SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); + SODA_CMD_STROBE_IN : in std_logic := '0'; -- + SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit + TX_DLM_OUT : out std_logic := '0'; -- + TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0') + ); + end component; + + component soda_reply_handler + port( + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + LAST_PACKET : in t_PACKET_TYPE_SENT := c_NO_PACKET; + EXPECTED_REPLY_IN : in std_logic_vector(7 downto 0) := (others => '0'); + RX_DLM_IN : in std_logic := '0'; + RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); + REPLY_VALID_OUT : out std_logic := '0'; + REPLY_OK_OUT : out std_logic := '0' + ); + end component; + + component soda_calibration_timer + port( + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + START_CALIBRATION : in std_logic := '0'; + END_CALIBRATION : in std_logic := '0'; + CALIB_VALID_OUT : out std_logic := '0'; -- + CALIB_TIME_OUT : out std_logic_vector(7 downto 0) := (others => '0') + ); + end component; + + component spi_flash_and_fpga_reload + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + BUS_ADDR_IN : in std_logic_vector(8 downto 0); + BUS_READ_IN : in std_logic; + BUS_WRITE_IN : in std_logic; + BUS_DATAREADY_OUT : out std_logic; + BUS_WRITE_ACK_OUT : out std_logic; + BUS_UNKNOWN_ADDR_OUT : out std_logic; + BUS_NO_MORE_DATA_OUT : out std_logic; + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + + DO_REBOOT_IN : in std_logic; + PROGRAMN : out std_logic; + + SPI_CS_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + SPI_SDO_OUT : out std_logic; + SPI_SDI_IN : in std_logic + ); + end component; end package; diff --git a/source/soda_d8crc8.vhd b/source/soda_d8crc8.vhd index ff37754..faaec31 100644 --- a/source/soda_d8crc8.vhd +++ b/source/soda_d8crc8.vhd @@ -41,64 +41,93 @@ use work.soda_components.all; entity soda_d8crc8 is port( - CLOCK : in std_logic; - RESET : in std_logic; - SOC : in std_logic; - DATA : in std_logic_vector(7 downto 0); - DATA_VALID : in std_logic; - EOC : in std_logic; - CRC : out std_logic_vector(7 downto 0); - CRC_VALID : out std_logic + CLOCK : in std_logic; + RESET : in std_logic; + SOC_IN : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + DATA_VALID_IN : in std_logic; + EOC_IN : in std_logic; + CRC_OUT : out std_logic_vector(7 downto 0); + CRC_VALID_OUT : out std_logic ); end soda_d8crc8; architecture behavioral of soda_d8crc8 is - signal crc_r: std_logic_vector(7 downto 0); - signal crc_c: std_logic_vector(7 downto 0); - signal crc_i: std_logic_vector(7 downto 0); - signal crc_const: std_logic_vector(7 downto 0) := "00000000"; + signal crc_r : std_logic_vector(7 downto 0); + signal crc_c : std_logic_vector(7 downto 0); + signal crc_i : std_logic_vector(7 downto 0); + signal crc_const : std_logic_vector(7 downto 0) := "00000000"; + signal crc_valid_out_S : std_logic :='0'; begin - crc_i<= crc_const when soc = '1' else + crc_i<= crc_const when SOC_IN = '1' else crc_r; - crc_c(0) <= DATA(0) xor DATA(3) xor DATA(4) xor crc_i(0) xor crc_i(4) xor DATA(6) xor crc_i(3) xor crc_i(6); - crc_c(1) <= data(1) xor DATA(4) xor DATA(5) xor crc_i(1) xor crc_i(5) xor DATA(7) xor crc_i(4) xor crc_i(7); - crc_c(2) <= DATA(2) xor DATA(5) xor DATA(6) xor crc_i(2) xor crc_i(6) xor crc_i(5); - crc_c(3) <= DATA(3) xor DATA(6) xor DATA(7) xor crc_i(3) xor crc_i(7) xor crc_i(6); - crc_c(4) <= DATA(0) xor DATA(7) xor crc_i(7) xor DATA(3) xor crc_i(0) xor DATA(6) xor crc_i(3) xor crc_i(6); - crc_c(5) <= DATA(0) xor DATA(1) xor crc_i(1) xor DATA(7) xor crc_i(7) xor DATA(3) xor crc_i(0) xor DATA(6) xor crc_i(3) xor crc_i(6); - crc_c(6) <= DATA(1) xor DATA(2) xor crc_i(2) xor DATA(4) xor crc_i(1) xor DATA(7) xor crc_i(4) xor crc_i(7); - crc_c(7) <= DATA(2) xor DATA(3) xor crc_i(3) xor DATA(5) xor crc_i(2) xor crc_i(5); + crc_c(0) <= DATA_IN(0) xor DATA_IN(3) xor DATA_IN(4) xor crc_i(0) xor crc_i(4) xor DATA_IN(6) xor crc_i(3) xor crc_i(6); + crc_c(1) <= DATA_IN(1) xor DATA_IN(4) xor DATA_IN(5) xor crc_i(1) xor crc_i(5) xor DATA_IN(7) xor crc_i(4) xor crc_i(7); + crc_c(2) <= DATA_IN(2) xor DATA_IN(5) xor DATA_IN(6) xor crc_i(2) xor crc_i(6) xor crc_i(5); + crc_c(3) <= DATA_IN(3) xor DATA_IN(6) xor DATA_IN(7) xor crc_i(3) xor crc_i(7) xor crc_i(6); + crc_c(4) <= DATA_IN(0) xor DATA_IN(7) xor crc_i(7) xor DATA_IN(3) xor crc_i(0) xor DATA_IN(6) xor crc_i(3) xor crc_i(6); + crc_c(5) <= DATA_IN(0) xor DATA_IN(1) xor crc_i(1) xor DATA_IN(7) xor crc_i(7) xor DATA_IN(3) xor crc_i(0) xor DATA_IN(6) xor crc_i(3) xor crc_i(6); + crc_c(6) <= DATA_IN(1) xor DATA_IN(2) xor crc_i(2) xor DATA_IN(4) xor crc_i(1) xor DATA_IN(7) xor crc_i(4) xor crc_i(7); + crc_c(7) <= DATA_IN(2) xor DATA_IN(3) xor crc_i(3) xor DATA_IN(5) xor crc_i(2) xor crc_i(5); - crc_gen_process : process(clock, reset) +-- crc_gen_process : process(CLOCK, RESET) +-- begin +-- if(RESET = '1') then +-- crc_r <= "00000000" ; +-- elsif rising_edge(CLOCK) then +-- if(DATA_VALID_IN = '1') then +-- crc_r <= crc_c; +-- end if; +-- end if; +-- end process crc_gen_process; + + crc_gen_process : process(CLOCK, RESET) begin - if(reset = '1') then - crc_r <= "00000000" ; - elsif rising_edge(clock) then - if(DATA_valid = '1') then - crc_r <= crc_c; + if rising_edge(CLOCK) then + if (RESET = '1') then + crc_r <= "00000000" ; + elsif (DATA_VALID_IN = '1') then + crc_r <= crc_c; + elsif (crc_valid_out_S='1') then + crc_r <= "00000000" ; end if; end if; end process crc_gen_process; - - crc_valid_gen : process(clock, reset) + crc_valid_gen : process(CLOCK, RESET) begin - if(reset = '1') then - CRC_VALID <= '0'; - elsif rising_edge(clock) then - if(DATA_valid = '1' and EOC = '1') then - CRC_VALID <= '1'; + if rising_edge(CLOCK) then + if (RESET = '1') then + crc_valid_out_S <= '0'; + elsif (DATA_VALID_IN = '1' and EOC_IN = '1') then + crc_valid_out_S <= '1'; else - CRC_VALID <= '0'; + crc_valid_out_S <= '0'; end if; end if; end process crc_valid_gen; - CRC <= crc_r; + +-- crc_valid_gen : process(CLOCK, RESET) +-- begin +-- if(RESET = '1') then +-- CRC_VALID_OUT <= '0'; +-- elsif rising_edge(CLOCK) then +-- if(DATA_VALID_IN = '1' and EOC_IN = '1') then +-- CRC_VALID_OUT <= '1'; +-- else +-- CRC_VALID_OUT <= '0'; +-- end if; +-- end if; +-- end process crc_valid_gen; +-- + + CRC_VALID_OUT <= crc_valid_out_S; + CRC_OUT <= crc_r; end behavioral; \ No newline at end of file diff --git a/source/soda_packet_builder.vhd b/source/soda_packet_builder.vhd index ec4f11a..145ffd8 100644 --- a/source/soda_packet_builder.vhd +++ b/source/soda_packet_builder.vhd @@ -9,44 +9,29 @@ use work.trb_net16_hub_func.all; use work.soda_components.all; entity soda_packet_builder is -port( - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; - --Internal Connection - SODA_CMD_STROBE_IN : in std_logic := '0'; -- - START_OF_SUPERBURST : in std_logic := '0'; - SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); - SODA_CMD_WORD_IN : in std_logic_vector(31 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit - TX_DLM_OUT : out std_logic := '0'; -- - TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0') + port( + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + LINK_PHASE : natural range 0 to 1 := 0; + SODA_CMD_STROBE_IN : in std_logic := '0'; -- + START_OF_SUPERBURST : in std_logic := '0'; + SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); + SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit + EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + TIME_CAL_OUT : out std_logic := '0'; + TX_DLM_OUT : out std_logic := '0'; -- + TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0') ); end soda_packet_builder; architecture Behavioral of soda_packet_builder is ---component soda_d8crc8 --- port( --- clock : in std_logic; --- reset : in std_logic; --- soc : in std_logic; --- data : in std_logic_vector(7 downto 0); --- data_valid : in std_logic; --- eoc : in std_logic; --- crc : out std_logic_vector(7 downto 0); --- crc_valid : out std_logic --- ); ---end component; - --- constant c_K287 : std_logic_vector(7 downto 0) := x"FB"; - - signal clk_S : std_logic; - signal rst_S : std_logic; signal soda_cmd_strobe_S : std_logic; - signal start_of_superburst_S : std_logic; signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator - signal soda_cmd_word_S : std_logic_vector(31 downto 0) := (others => '0'); -- from slowcontrol + signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0'); -- from slowcontrol signal soda_pkt_word_S : std_logic_vector(7 downto 0) := (others => '0'); signal soda_pkt_valid_S : std_logic; @@ -58,80 +43,95 @@ architecture Behavioral of soda_packet_builder is signal crc_out_S : std_logic_vector(7 downto 0) := (others => '0'); signal crc_valid_S : std_logic; - type packet_state_type is ( c_RST, c_IDLE, c_ERROR, - c_STD1, c_STD2, c_STD3, c_STD4, c_STD5, c_STD6, c_STD7, c_STD8, - c_CMD1, c_CMD2, c_CMD3, c_CMD4, c_CMD5, c_CMD6, c_CMD7, c_CMD8 + type packet_state_type is ( c_IDLE, c_ERROR, + c_WAIT4BST1, c_BST1, c_BST2, c_BST3, c_BST4, c_BST5, c_BST6, c_BST7, c_BST8, + c_WAIT4CMD1, c_CMD1, c_CMD2, c_CMD3, c_CMD4, c_CMD5, c_CMD6, c_CMD7, c_CMD8 ); signal packet_state_S : packet_state_type := c_IDLE; --- signal packet_state_S : packet_state_type := c_IDLE; begin tx_crc8: soda_d8crc8 port map( - clock => clk_S, - reset => rst_S, - soc => soc_S, - data => crc_datain_S, - data_valid => crc_data_valid_S, - eoc => eoc_S, - crc => crc_out_S, - crc_valid => crc_valid_S + CLOCK => SYSCLK, + RESET => RESET, + SOC_IN => soc_S, + DATA_IN => crc_datain_S, + DATA_VALID_IN => crc_data_valid_S, + EOC_IN => eoc_S, + CRC_OUT => crc_out_S, + CRC_VALID_OUT => crc_valid_S ); - clk_S <= SYSCLK; - rst_S <= RESET; soda_cmd_strobe_S <= SODA_CMD_STROBE_IN; soda_cmd_word_S <= SODA_CMD_WORD_IN; - start_of_superburst_S <= START_OF_SUPERBURST; super_burst_nr_S <= SUPER_BURST_NR_IN; TX_DLM_WORD_OUT <= soda_pkt_word_S; TX_DLM_OUT <= soda_pkt_valid_S; --- packet_state_S <= packet_state_S; - packet_fsm_proc : process(clk_S, rst_S, packet_state_S, crc_valid_S, start_of_superburst_S, soda_cmd_strobe_S) + packet_fsm_proc : process(SYSCLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S) begin - if rising_edge(clk_S) then - if (rst_S='1') then - packet_state_S <= c_RST; + if rising_edge(SYSCLK) then + if (RESET='1') then + packet_state_S <= c_IDLE; else case packet_state_S is - when c_RST => - if (start_of_superburst_S='1') then - packet_state_S <= c_STD1; + when c_IDLE => + if (START_OF_SUPERBURST='1') then + if (LINK_PHASE=0) then + packet_state_S <= c_BST1; + else + packet_state_S <= c_WAIT4BST1; + end if; elsif (soda_cmd_strobe_S='1') then - packet_state_S <= c_CMD1; + if (LINK_PHASE=0) then + packet_state_S <= c_CMD1; + else + packet_state_S <= c_WAIT4CMD1; + end if; else packet_state_S <= c_IDLE; end if; - when c_IDLE => - if (start_of_superburst_S='1') then - packet_state_S <= c_STD1; - elsif (soda_cmd_strobe_S='1') then - packet_state_S <= c_CMD1; +-- when c_IDLE => +-- if (START_OF_SUPERBURST='1') then +-- packet_state_S <= c_BST1; +-- elsif (soda_cmd_strobe_S='1') then +-- packet_state_S <= c_CMD1; +-- end if; + when c_WAIT4BST1 => + if (LINK_PHASE=0) then + packet_state_S <= c_BST1; + else + packet_state_S <= c_WAIT4BST1; end if; - when c_STD1 => - packet_state_S <= c_STD2; - when c_STD2 => - packet_state_S <= c_STD3; - when c_STD3 => - packet_state_S <= c_STD4; - when c_STD4 => - packet_state_S <= c_STD5; - when c_STD5 => - packet_state_S <= c_STD6; - when c_STD6 => - packet_state_S <= c_STD7; - when c_STD7 => - packet_state_S <= c_STD8; - when c_STD8 => + when c_BST1 => + packet_state_S <= c_BST2; + when c_BST2 => + packet_state_S <= c_BST3; + when c_BST3 => + packet_state_S <= c_BST4; + when c_BST4 => + packet_state_S <= c_BST5; + when c_BST5 => + packet_state_S <= c_BST6; + when c_BST6 => + packet_state_S <= c_BST7; + when c_BST7 => + packet_state_S <= c_BST8; + when c_BST8 => if (soda_cmd_strobe_S='0') then packet_state_S <= c_IDLE; else packet_state_S <= c_CMD1; end if; + when c_WAIT4CMD1 => + if (LINK_PHASE=0) then + packet_state_S <= c_CMD1; + else + packet_state_S <= c_WAIT4CMD1; + end if; when c_CMD1 => packet_state_S <= c_CMD2; when c_CMD2 => @@ -161,64 +161,72 @@ begin end if; end process; - soda_packet_fill_proc : process(clk_S, packet_state_S) + soda_packet_fill_proc : process(SYSCLK, packet_state_S) begin - if rising_edge(clk_S) then + if rising_edge(SYSCLK) then case packet_state_S is when c_IDLE => - soda_pkt_valid_S <= '0'; - soda_pkt_word_S <= (others=>'0'); - when c_STD1 => - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= '1' & super_burst_nr_S(30 downto 24); - when c_STD2 => - soda_pkt_valid_S <= '0'; - when c_STD3 => - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= super_burst_nr_S(23 downto 16); - when c_STD4 => - soda_pkt_valid_S <= '0'; - when c_STD5 => - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= super_burst_nr_S(15 downto 8); - when c_STD6 => - soda_pkt_valid_S <= '0'; - when c_STD7 => - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= super_burst_nr_S(7 downto 0); - when c_STD8 => - soda_pkt_valid_S <= '0'; + TIME_CAL_OUT <= '0'; + soda_pkt_valid_S <= '0'; + soda_pkt_word_S <= (others=>'0'); + when c_WAIT4BST1 => -- no need to do anything just yet. + when c_BST1 => + soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= '1' & super_burst_nr_S(30 downto 24); + when c_BST2 => + soda_pkt_valid_S <= '0'; + when c_BST3 => + soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= super_burst_nr_S(23 downto 16); + when c_BST4 => + soda_pkt_valid_S <= '0'; + when c_BST5 => + soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= super_burst_nr_S(15 downto 8); + when c_BST6 => + soda_pkt_valid_S <= '0'; + when c_BST7 => + soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= super_burst_nr_S(7 downto 0); + EXPECTED_REPLY_OUT <= super_burst_nr_S(7 downto 0); + when c_BST8 => + soda_pkt_valid_S <= '0'; + when c_WAIT4CMD1 => -- no need to do anything just yet. when c_CMD1 => - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24); + soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24); when c_CMD2 => - soda_pkt_valid_S <= '0'; + soda_pkt_valid_S <= '0'; when c_CMD3 => - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= soda_cmd_word_S(23 downto 16); + soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= soda_cmd_word_S(23 downto 16); when c_CMD4 => - soda_pkt_valid_S <= '0'; + soda_pkt_valid_S <= '0'; when c_CMD5 => - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= soda_cmd_word_S(15 downto 8); + soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= soda_cmd_word_S(15 downto 8); when c_CMD6 => - soda_pkt_valid_S <= '0'; + soda_pkt_valid_S <= '0'; when c_CMD7 => - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= crc_out_S; + soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= crc_out_S; + EXPECTED_REPLY_OUT <= crc_out_S; + TIME_CAL_OUT <= '1'; when c_CMD8 => - soda_pkt_valid_S <= '0'; + TIME_CAL_OUT <= '0'; + soda_pkt_valid_S <= '0'; when others => - soda_pkt_valid_S <= '0'; - soda_pkt_word_S <= (others=>'0'); + TIME_CAL_OUT <= '0'; + soda_pkt_valid_S <= '0'; + soda_pkt_word_S <= (others=>'0'); end case; end if; end process; - crc_gen_proc : process(clk_S, packet_state_S) + crc_gen_proc : process(SYSCLK, packet_state_S) begin - if rising_edge(clk_S) then + if rising_edge(SYSCLK) then case packet_state_S is when c_IDLE => crc_data_valid_S <= '0'; diff --git a/source/soda_packet_handler.vhd b/source/soda_packet_handler.vhd index 17ab0da..eb07be1 100644 --- a/source/soda_packet_handler.vhd +++ b/source/soda_packet_handler.vhd @@ -9,150 +9,110 @@ use work.trb_net16_hub_func.all; use work.soda_components.all; entity soda_packet_handler is -port( - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; - --Internal Connection - RX_DLM_IN : in std_logic; - RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); - TX_DLM_IN : out std_logic; - TX_DLM_WORD_IN : out std_logic_vector(7 downto 0) := (others => '0') + port( + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + START_OF_SUPERBURST : out std_logic := '0'; + SUPER_BURST_NR : out std_logic_vector(30 downto 0) := (others => '0'); + SODA_CMD_VALID_S : out std_logic := '0'; + SODA_CMD_WORD_S : out std_logic_vector(30 downto 0) := (others => '0'); + EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + CRC_VALID_OUT : out std_logic := '0'; + CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + RX_DLM_IN : in std_logic; + RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0') ); end soda_packet_handler; architecture Behavioral of soda_packet_handler is --- component soda_d8crc8 --- port( --- clock : in std_logic; --- reset : in std_logic; --- soc : in std_logic; --- data : in std_logic_vector(7 downto 0); --- data_valid : in std_logic; --- eoc : in std_logic; --- crc : out std_logic_vector(7 downto 0); --- crc_valid : out std_logic --- ); --- end component; - - constant c_K287 : std_logic_vector(7 downto 0) := x"FB"; - - signal clk_S : std_logic; - signal rst_S : std_logic; - signal rx_dlm_in_S : std_logic; - signal rx_dlm_word_in_S : std_logic_vector(7 downto 0) := (others => '0'); - signal soda_cmd_strobe_S : std_logic; - signal start_of_superburst_S : std_logic; - signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator - signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0'); -- from slowcontrol - signal soda_pkt_word_S : std_logic_vector(31 downto 0) := (others => '0'); - signal soda_pkt_valid_S : std_logic; + signal soda_pkt_word_S : std_logic_vector(31 downto 0) := (others => '0'); + signal soda_pkt_valid_S : std_logic := '0'; type packet_state_type is ( c_RST, c_IDLE, c_ERROR, c_SODA_PKT1, c_SODA_PKT2, c_SODA_PKT3, c_SODA_PKT4, c_SODA_PKT5, c_SODA_PKT6, c_SODA_PKT7, c_SODA_PKT8 ); signal packet_state_S : packet_state_type := c_IDLE; - - signal soc_S : std_logic := '1'; - signal eoc_S : std_logic := '0'; - signal crc_data_valid_S : std_logic := '0'; +-- crc-checker signals -- + signal soc_S : std_logic; + signal eoc_S : std_logic; + signal crc_valid_in_s : std_logic; signal crc_datain_S : std_logic_vector(7 downto 0) := (others => '0'); signal crc_tmp_S : std_logic_vector(7 downto 0) := (others => '0'); signal crc_out_S : std_logic_vector(7 downto 0) := (others => '0'); - signal crc_valid_S : std_logic := '0'; - - signal crc_check_S : std_logic := '0'; - signal crc_check_valid_S : std_logic := '0'; + signal crc_valid_out_S : std_logic; + signal crc_check_ok_s : std_logic; begin - rx_crc8: soda_d8crc8 - port map( - clock => clk_S, - reset => rst_S, - soc => soc_S, - data => crc_datain_S, - data_valid => crc_data_valid_S, - eoc => eoc_S, - crc => crc_out_S, - crc_valid => crc_valid_S - ); - - clk_S <= SYSCLK; - rst_S <= RESET; - --- packet_state_S <= packet_state_S; - - rx_dlm_in_S <= RX_DLM_IN; - rx_dlm_word_in_S <= RX_DLM_WORD_IN; - - packet_fsm_proc : process(clk_S) + packet_fsm_proc : process(SYSCLK) begin - if rising_edge(clk_S) then - if (rst_S='1') then + if rising_edge(SYSCLK) then + if (RESET='1') then packet_state_S <= c_RST; else case packet_state_S is when c_RST => - if (rx_dlm_in_S='1') then -- received K27.7 #1 + if (RX_DLM_IN='1') then -- received K28.7 #1 packet_state_S <= c_SODA_PKT1; else packet_state_S <= c_IDLE; end if; when c_IDLE => - if (rx_dlm_in_S='1') then -- received K27.7 #1 + if (RX_DLM_IN='1') then -- received K28.7 #1 packet_state_S <= c_SODA_PKT1; else packet_state_S <= c_IDLE; end if; when c_SODA_PKT1 => - if (rx_dlm_in_S='0') then -- possibly received data-byte + if (RX_DLM_IN='0') then -- possibly received data-byte packet_state_S <= c_SODA_PKT2; else packet_state_S <= c_ERROR; end if; when c_SODA_PKT2 => - if (rx_dlm_in_S='1') then -- received K27.7 #2 + if (RX_DLM_IN='1') then -- received K28.7 #2 packet_state_S <= c_SODA_PKT3; else packet_state_S <= c_ERROR; end if; when c_SODA_PKT3 => - if (rx_dlm_in_S='0') then -- possibly received data-byte + if (RX_DLM_IN='0') then -- possibly received data-byte packet_state_S <= c_SODA_PKT4; else packet_state_S <= c_ERROR; end if; when c_SODA_PKT4 => - if (rx_dlm_in_S='1') then -- received K27.7 #3 + if (RX_DLM_IN='1') then -- received K28.7 #3 packet_state_S <= c_SODA_PKT5; else packet_state_S <= c_ERROR; end if; when c_SODA_PKT5 => - if (rx_dlm_in_S='0') then -- possibly received data-byte + if (RX_DLM_IN='0') then -- possibly received data-byte packet_state_S <= c_SODA_PKT6; else packet_state_S <= c_ERROR; end if; when c_SODA_PKT6 => - if (rx_dlm_in_S='1') then -- received K27.7 #4 + if (RX_DLM_IN='1') then -- received K28.7 #4 packet_state_S <= c_SODA_PKT7; else packet_state_S <= c_ERROR; -- else do nothing end if; when c_SODA_PKT7 => - if (rx_dlm_in_S='1') or (crc_valid_S = '0') or not(crc_out_S = RX_DLM_WORD_IN) then - packet_state_S <= c_ERROR; -- if there's an unexpected K27.7 or no valid CRC-output or the CRC-check doesn't match + if (RX_DLM_IN='1') then + packet_state_S <= c_ERROR; -- if there's an unexpected K28.7 there's too much data else packet_state_S <= c_SODA_PKT8; end if; when c_SODA_PKT8 => - if (rx_dlm_in_S='1') then -- received K27.7 #4+1... must be another packet coming in.... + if (RX_DLM_IN='1') then -- received K28.7 #4+1... must be another packet coming in.... packet_state_S <= c_SODA_PKT1; else packet_state_S <= c_IDLE; @@ -166,109 +126,125 @@ begin end if; end process; - soda_packet_collector_proc : process(clk_S, packet_state_S) + soda_packet_collector_proc : process(SYSCLK, packet_state_S) begin - if rising_edge(clk_S) then + if rising_edge(SYSCLK) then case packet_state_S is when c_RST => - soda_pkt_valid_S <= '0'; + START_OF_SUPERBURST <= '0'; + soda_cmd_valid_S <= '0'; + soda_pkt_valid_S <= '0'; soda_pkt_word_S <= (others=>'0'); when c_IDLE => - soda_pkt_valid_S <= '0'; + START_OF_SUPERBURST <= '0'; + soda_cmd_valid_S <= '0'; + soda_pkt_valid_S <= '0'; soda_pkt_word_S <= (others=>'0'); when c_SODA_PKT1 => soda_pkt_word_S(31 downto 24) <= RX_DLM_WORD_IN; when c_SODA_PKT2 => - -- do nothing -- disregard k27.7 + -- do nothing -- disregard K28.7 when c_SODA_PKT3 => soda_pkt_word_S(23 downto 16) <= RX_DLM_WORD_IN; when c_SODA_PKT4 => - -- do nothing -- disregard k27.7 + -- do nothing -- disregard K28.7 when c_SODA_PKT5 => soda_pkt_word_S(15 downto 8) <= RX_DLM_WORD_IN; when c_SODA_PKT6 => - -- do nothing -- disregard k27.7 + -- do nothing -- disregard K28.7 when c_SODA_PKT7 => soda_pkt_word_S(7 downto 0) <= RX_DLM_WORD_IN; -- get transmitted CRC when c_SODA_PKT8 => + soda_pkt_valid_S <= '1'; + EXPECTED_REPLY_OUT <= soda_pkt_word_S(7 downto 0); + if (soda_pkt_word_S(31)= '1') then + START_OF_SUPERBURST <= '1'; + SUPER_BURST_NR <= soda_pkt_word_S(30 downto 0); + else + soda_cmd_valid_S <= '1'; + soda_cmd_word_S <= soda_pkt_word_S(30 downto 0); + end if; when others => + START_OF_SUPERBURST <= '0'; soda_pkt_valid_S <= '0'; soda_pkt_word_S <= (others=>'0'); + soda_cmd_valid_S <= '0'; + soda_cmd_word_S <= (others=>'0'); end case; - if (soda_pkt_valid_S ='1') then - if (soda_pkt_word_S(31) = '1') then - super_burst_nr_S <= soda_pkt_word_S(30 downto 0); - start_of_superburst_S <= '1'; - else - soda_cmd_word_S <= soda_pkt_word_S(30 downto 0); - soda_cmd_strobe_S <= '1'; - end if; - else - start_of_superburst_S <= '0'; - soda_cmd_strobe_S <= '0'; - end if; end if; end process; - crc_check_proc : process(clk_S, packet_state_S) - begin - if rising_edge(clk_S) then - case packet_state_S is - when c_RST => - soc_S <= '1'; - eoc_S <= '0'; - crc_check_valid_S <= '0'; - when c_IDLE => - crc_data_valid_S <= '0'; - crc_datain_S <= (others=>'0'); - soc_S <= '1'; - eoc_S <= '0'; - when c_SODA_PKT1 => - crc_data_valid_S <= '1'; - crc_datain_S <= RX_DLM_WORD_IN; - soc_S <= '0'; - when c_SODA_PKT2 => - crc_data_valid_S <= '0'; - crc_datain_S <= (others=>'0'); - when c_SODA_PKT3 => - crc_data_valid_S <= '1'; - crc_datain_S <= RX_DLM_WORD_IN; - when c_SODA_PKT4 => - crc_data_valid_S <= '0'; - crc_datain_S <= (others=>'0'); - when c_SODA_PKT5 => - crc_data_valid_S <= '1'; - crc_datain_S <= RX_DLM_WORD_IN; - eoc_S <= '1'; - when c_SODA_PKT6 => - crc_data_valid_S <= '0'; - crc_datain_S <= (others=>'0'); - eoc_S <= '0'; - when c_SODA_PKT7 => - crc_data_valid_S <= '0'; - crc_datain_S <= (others=>'0'); - if ((crc_valid_S = '1') and (crc_out_S = RX_DLM_WORD_IN)) then - crc_check_S <= '1'; - else - crc_check_S <= '0'; - end if; - crc_check_valid_S <= '1'; - when c_SODA_PKT8 => - crc_data_valid_S <= '0'; - crc_datain_S <= (others=>'0'); - soc_S <= '0'; - eoc_S <= '0'; - crc_check_S <= '0'; - crc_check_valid_S <= '0'; - when others => - crc_data_valid_S <= '0'; - crc_datain_S <= (others=>'0'); - soc_S <= '0'; - eoc_S <= '0'; - crc_check_valid_S <= '0'; - end case; - end if; + crc_check_proc : process(SYSCLK, packet_state_S) + begin + if rising_edge(SYSCLK) then + case packet_state_S is + when c_RST=> + CRC_VALID_OUT <= '0'; + CRC_DATA_OUT<= (others => '0'); + soc_S <= '1'; + eoc_S <= '0'; + CRC_VALID_OUT <= '0'; + when c_IDLE => + CRC_VALID_OUT <= '0'; + CRC_DATA_OUT<= (others => '0'); + crc_valid_in_S<= '0'; + crc_datain_S<= (others=>'0'); + soc_S <= '1'; + eoc_S <= '0'; + when c_SODA_PKT1=> + crc_valid_in_S<= '1'; + crc_datain_S<=RX_DLM_WORD_IN; + if (RX_DLM_WORD_IN(7)='0') then -- only calculate crc if it's a command packet + soc_S <= '0'; + end if; + when c_SODA_PKT2=> + crc_valid_in_S<= '0'; + crc_datain_S<= (others=>'0'); + when c_SODA_PKT3=> + crc_valid_in_S<= '1'; + crc_datain_S<= RX_DLM_WORD_IN; + when c_SODA_PKT4=> + crc_valid_in_S<= '0'; + crc_datain_S<= (others=>'0'); + when c_SODA_PKT5=> + crc_valid_in_S<= '1'; + crc_datain_S<= RX_DLM_WORD_IN; + if (soc_S='0') then -- only terminate crc claculation if it is running + eoc_S <= '1'; + end if; + when c_SODA_PKT6=> + crc_valid_in_S<= '0'; + crc_datain_S<= (others=>'0'); + eoc_S <= '0'; + when c_SODA_PKT7=> + crc_valid_in_S<= '0'; + crc_datain_S<= (others=>'0'); + if ((crc_valid_out_S = '1') and (crc_out_S = RX_DLM_WORD_IN)) then + crc_check_ok_S<= '1'; + else + crc_check_ok_S<= '0'; + end if; + CRC_VALID_OUT <= '1'; + when c_SODA_PKT8=> + CRC_VALID_OUT <= crc_valid_out_S; + CRC_DATA_OUT<= crc_out_S; + crc_valid_in_S<= '0'; + crc_datain_S<= (others=>'0'); +--soc_S <= '0'; + eoc_S <= '0'; + crc_check_ok_S<= '0'; + CRC_VALID_OUT <= '0'; + when others => + CRC_VALID_OUT <= '0'; + CRC_DATA_OUT<= (others => '0'); + crc_valid_in_S<= '0'; + crc_datain_S<= (others=>'0'); + soc_S <= '0'; + eoc_S <= '0'; + CRC_VALID_OUT <= '0'; + end case; + end if; end process; end architecture; \ No newline at end of file diff --git a/source/soda_superburst_gen.vhd b/source/soda_superburst_gen.vhd index 5f76529..7ba315b 100644 --- a/source/soda_superburst_gen.vhd +++ b/source/soda_superburst_gen.vhd @@ -10,7 +10,7 @@ use work.trb_net_components.all; use work.trb_net16_hub_func.all; use work.soda_components.all; -entity soda_superburst_gen is +entity soda_superburst_generator is generic( BURST_COUNT : natural range 1 to 256 := 16 -- number of bursts to be counted between super-bursts ); @@ -24,9 +24,9 @@ entity soda_superburst_gen is START_OF_SUPERBURST : out std_logic := '0'; SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0') ); -end soda_superburst_gen; +end soda_superburst_generator; -architecture Behavioral of soda_superburst_gen is +architecture Behavioral of soda_superburst_generator is constant cBURST_COUNT : std_logic_vector(7 downto 0) := conv_std_logic_vector(BURST_COUNT - 1,8); diff --git a/source/trb3_periph_sodasource.vhd b/source/trb3_periph_sodasource.vhd index d84ed9b..46a0581 100644 --- a/source/trb3_periph_sodasource.vhd +++ b/source/trb3_periph_sodasource.vhd @@ -196,7 +196,7 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is --SODA signal soda_ack : std_logic; - signal soda_nack : std_logic; +-- signal soda_nack : std_logic; signal soda_write : std_logic; signal soda_read : std_logic; signal soda_data_in : std_logic_vector(31 downto 0); @@ -415,71 +415,72 @@ THE_HUB : trb_net16_hub_base CLK => clk_sys_i, RESET => reset_i, - DAT_ADDR_IN => regio_addr_out, - DAT_DATA_IN => regio_data_out, - DAT_DATA_OUT => regio_data_in, - DAT_READ_ENABLE_IN => regio_read_enable_out, - DAT_WRITE_ENABLE_IN => regio_write_enable_out, - DAT_TIMEOUT_IN => regio_timeout_out, - DAT_DATAREADY_OUT => regio_dataready_in, - DAT_WRITE_ACK_OUT => regio_write_ack_in, - DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, - DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, - - --Bus Handler (SPI Memory) - BUS_READ_ENABLE_OUT(0) => spimem_read_en, - BUS_WRITE_ENABLE_OUT(0) => spimem_write_en, - BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in, - BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr, - BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open, - BUS_TIMEOUT_OUT(0) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out, - BUS_DATAREADY_IN(0) => spimem_dataready_out, - BUS_WRITE_ACK_IN(0) => spimem_write_ack_out, - BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out, - BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out, + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, - - --SCI first Media Interface + BUS_READ_ENABLE_OUT(0) => spimem_read_en, BUS_READ_ENABLE_OUT(1) => sci1_read, + BUS_READ_ENABLE_OUT(2) => sci2_read, + BUS_READ_ENABLE_OUT(3) => soda_read, + + BUS_WRITE_ENABLE_OUT(0) => spimem_write_en, BUS_WRITE_ENABLE_OUT(1) => sci1_write, + BUS_WRITE_ENABLE_OUT(2) => sci2_write, + BUS_WRITE_ENABLE_OUT(3) => soda_write, + + BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in, BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in, BUS_DATA_OUT(1*32+31 downto 1*32+8) => open, - BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr, - BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out, - BUS_DATAREADY_IN(1) => sci1_ack, - BUS_WRITE_ACK_IN(1) => sci1_ack, - BUS_NO_MORE_DATA_IN(1) => '0', - BUS_UNKNOWN_ADDR_IN(1) => '0', - - --SCI soda test Media Interface - BUS_READ_ENABLE_OUT(2) => sci2_read, - BUS_WRITE_ENABLE_OUT(2) => sci2_write, BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in, BUS_DATA_OUT(2*32+31 downto 2*32+8) => open, + BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in, + + BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open, + BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open, BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr, BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open, - BUS_TIMEOUT_OUT(2) => open, - BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out, - BUS_DATAREADY_IN(2) => sci2_ack, - BUS_WRITE_ACK_IN(2) => sci2_ack, - BUS_NO_MORE_DATA_IN(2) => '0', - BUS_UNKNOWN_ADDR_IN(2) => sci2_nack, - - --soda Slow-control Interface - BUS_READ_ENABLE_OUT(3) => soda_read, - BUS_WRITE_ENABLE_OUT(3) => soda_write, - BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in, BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr, BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open, + + BUS_TIMEOUT_OUT(0) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_TIMEOUT_OUT(2) => open, BUS_TIMEOUT_OUT(3) => open, + + BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out, + BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out, + BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out, BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out, + + BUS_DATAREADY_IN(0) => spimem_dataready_out, + BUS_DATAREADY_IN(1) => sci1_ack, + BUS_DATAREADY_IN(2) => sci2_ack, BUS_DATAREADY_IN(3) => soda_ack, + + BUS_WRITE_ACK_IN(0) => spimem_write_ack_out, + BUS_WRITE_ACK_IN(1) => sci1_ack, + BUS_WRITE_ACK_IN(2) => sci2_ack, BUS_WRITE_ACK_IN(3) => soda_ack, + + BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_NO_MORE_DATA_IN(2) => '0', BUS_NO_MORE_DATA_IN(3) => '0', - BUS_UNKNOWN_ADDR_IN(3) => soda_nack, + + BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out, + BUS_UNKNOWN_ADDR_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(2) => sci2_nack, + BUS_UNKNOWN_ADDR_IN(3) => '0', STAT_DEBUG => open ); @@ -583,8 +584,6 @@ THE_SODA_SOURCE : soda_source CLK_EN => '1', --Internal Connection SODA_BURST_PULSE_IN => SOB_S, - SODA_CMD_STROBE_IN => soda_cmd_strobe_S, - SODA_CMD_WORD_IN => soda_cmd_word_S, RX_DLM_WORD_IN => rx_dlm_word, RX_DLM_IN => rx_dlm_i, @@ -597,15 +596,13 @@ THE_SODA_SOURCE : soda_source SODA_READ_IN => soda_read, SODA_WRITE_IN => soda_write, SODA_ACK_OUT => soda_ack, - LEDS_ACT_OUT => open, LEDS_OUT => soda_leds, - SPARE_LINE => open, - TEST_LINE => open, + TEST_LINE => TEST_LINE(15 downto 0), STAT => open ); ---end soda_source; - + + --------------------------------------------------------------------------- -- LED ---------------------------------------------------------------------------