From: Cahit Date: Mon, 28 Aug 2017 16:40:36 +0000 (+0200) Subject: added missing files to tdc_v2.3 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=284f574086b31f9983b09e8b8f8b45a72caa681f;p=tdc.git added missing files to tdc_v2.3 --- diff --git a/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd b/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd new file mode 100644 index 0000000..8e2f389 --- /dev/null +++ b/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd @@ -0,0 +1,1215 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.8.0.115.3 +-- Module Version: 3.5 +--/opt/lattice/diamond/3.8_x64/ispfpga/bin/lin64/scuba -w -n Adder_288 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type add -width 64 -unsigned -output_reg -enable -pipeline 0 -fdc /home/cugur/Projects/TDC_on_TRB3/tdc/base/cores/ecp5/TDC/Adder_288/clarity/Adder_288/Adder_288.fdc + +-- Wed Dec 21 21:27:16 2016 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity Adder_288 is + port ( + DataA : in std_logic_vector(287 downto 0); + DataB : in std_logic_vector(287 downto 0); + Clk : in std_logic; + Reset : in std_logic; + ClkEn : in std_logic; + Result : out std_logic_vector(287 downto 0)); +end Adder_288; + +architecture Structure of Adder_288 is + + -- internal signal declarations + signal r0_sum : std_logic_vector(287 downto 0); + signal tsum : std_logic_vector(287 downto 0); + signal co : std_logic_vector(143 downto 0); + signal scuba_vhi : std_logic; + signal scuba_vlo : std_logic; + + attribute GSR : string; + attribute GSR of FF_287 : label is "ENABLED"; + attribute GSR of FF_286 : label is "ENABLED"; + attribute GSR of FF_285 : label is "ENABLED"; + attribute GSR of FF_284 : label is "ENABLED"; + attribute GSR of FF_283 : label is "ENABLED"; + attribute GSR of FF_282 : label is "ENABLED"; + attribute GSR of FF_281 : label is "ENABLED"; + attribute GSR of FF_280 : label is "ENABLED"; + attribute GSR of FF_279 : label is "ENABLED"; + attribute GSR of FF_278 : label is "ENABLED"; + attribute GSR of FF_277 : label is "ENABLED"; + attribute GSR of FF_276 : label is "ENABLED"; + attribute GSR of FF_275 : label is "ENABLED"; + attribute GSR of FF_274 : label is "ENABLED"; + attribute GSR of FF_273 : label is "ENABLED"; + attribute GSR of FF_272 : label is "ENABLED"; + attribute GSR of FF_271 : label is "ENABLED"; + attribute GSR of FF_270 : label is "ENABLED"; + attribute GSR of FF_269 : label is "ENABLED"; + attribute GSR of FF_268 : label is "ENABLED"; + attribute GSR of FF_267 : label is "ENABLED"; + attribute GSR of FF_266 : label is "ENABLED"; + attribute GSR of FF_265 : label is "ENABLED"; + attribute GSR of FF_264 : label is "ENABLED"; + attribute GSR of FF_263 : label is "ENABLED"; + attribute GSR of FF_262 : label is "ENABLED"; + attribute GSR of FF_261 : label is "ENABLED"; + attribute GSR of FF_260 : label is "ENABLED"; + attribute GSR of FF_259 : label is "ENABLED"; + attribute GSR of FF_258 : label is "ENABLED"; + attribute GSR of FF_257 : label is "ENABLED"; + attribute GSR of FF_256 : label is "ENABLED"; + attribute GSR of FF_255 : label is "ENABLED"; + attribute GSR of FF_254 : label is "ENABLED"; + attribute GSR of FF_253 : label is "ENABLED"; + attribute GSR of FF_252 : label is "ENABLED"; + attribute GSR of FF_251 : label is "ENABLED"; + attribute GSR of FF_250 : label is "ENABLED"; + attribute GSR of FF_249 : label is "ENABLED"; + attribute GSR of FF_248 : label is "ENABLED"; + attribute GSR of FF_247 : label is "ENABLED"; + attribute GSR of FF_246 : label is "ENABLED"; + attribute GSR of FF_245 : label is "ENABLED"; + attribute GSR of FF_244 : label is "ENABLED"; + attribute GSR of FF_243 : label is "ENABLED"; + attribute GSR of FF_242 : label is "ENABLED"; + attribute GSR of FF_241 : label is "ENABLED"; + attribute GSR of FF_240 : label is "ENABLED"; + attribute GSR of FF_239 : label is "ENABLED"; + attribute GSR of FF_238 : label is "ENABLED"; + attribute GSR of FF_237 : label is "ENABLED"; + attribute GSR of FF_236 : label is "ENABLED"; + attribute GSR of FF_235 : label is "ENABLED"; + attribute GSR of FF_234 : label is "ENABLED"; + attribute GSR of FF_233 : label is "ENABLED"; + attribute GSR of FF_232 : label is "ENABLED"; + attribute GSR of FF_231 : label is "ENABLED"; + attribute GSR of FF_230 : label is "ENABLED"; + attribute GSR of FF_229 : label is "ENABLED"; + attribute GSR of FF_228 : label is "ENABLED"; + attribute GSR of FF_227 : label is "ENABLED"; + attribute GSR of FF_226 : label is "ENABLED"; + attribute GSR of FF_225 : label is "ENABLED"; + attribute GSR of FF_224 : label is "ENABLED"; + attribute GSR of FF_223 : label is "ENABLED"; + attribute GSR of FF_222 : label is "ENABLED"; + attribute GSR of FF_221 : label is "ENABLED"; + attribute GSR of FF_220 : label is "ENABLED"; + attribute GSR of FF_219 : label is "ENABLED"; + attribute GSR of FF_218 : label is "ENABLED"; + attribute GSR of FF_217 : label is "ENABLED"; + attribute GSR of FF_216 : label is "ENABLED"; + attribute GSR of FF_215 : label is "ENABLED"; + attribute GSR of FF_214 : label is "ENABLED"; + attribute GSR of FF_213 : label is "ENABLED"; + attribute GSR of FF_212 : label is "ENABLED"; + attribute GSR of FF_211 : label is "ENABLED"; + attribute GSR of FF_210 : label is "ENABLED"; + attribute GSR of FF_209 : label is "ENABLED"; + attribute GSR of FF_208 : label is "ENABLED"; + attribute GSR of FF_207 : label is "ENABLED"; + attribute GSR of FF_206 : label is "ENABLED"; + attribute GSR of FF_205 : label is "ENABLED"; + attribute GSR of FF_204 : label is "ENABLED"; + attribute GSR of FF_203 : label is "ENABLED"; + attribute GSR of FF_202 : label is "ENABLED"; + attribute GSR of FF_201 : label is "ENABLED"; + attribute GSR of FF_200 : label is "ENABLED"; + attribute GSR of FF_199 : label is "ENABLED"; + attribute GSR of FF_198 : label is "ENABLED"; + attribute GSR of FF_197 : label is "ENABLED"; + attribute GSR of FF_196 : label is "ENABLED"; + attribute GSR of FF_195 : label is "ENABLED"; + attribute GSR of FF_194 : label is "ENABLED"; + attribute GSR of FF_193 : label is "ENABLED"; + attribute GSR of FF_192 : label is "ENABLED"; + attribute GSR of FF_191 : label is "ENABLED"; + attribute GSR of FF_190 : label is "ENABLED"; + attribute GSR of FF_189 : label is "ENABLED"; + attribute GSR of FF_188 : label is "ENABLED"; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + FF_287 : FD1P3DX + port map (D => tsum(287), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(287)); + FF_286 : FD1P3DX + port map (D => tsum(286), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(286)); + FF_285 : FD1P3DX + port map (D => tsum(285), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(285)); + FF_284 : FD1P3DX + port map (D => tsum(284), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(284)); + FF_283 : FD1P3DX + port map (D => tsum(283), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(283)); + FF_282 : FD1P3DX + port map (D => tsum(282), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(282)); + FF_281 : FD1P3DX + port map (D => tsum(281), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(281)); + FF_280 : FD1P3DX + port map (D => tsum(280), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(280)); + FF_279 : FD1P3DX + port map (D => tsum(279), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(279)); + FF_278 : FD1P3DX + port map (D => tsum(278), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(278)); + FF_277 : FD1P3DX + port map (D => tsum(277), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(277)); + FF_276 : FD1P3DX + port map (D => tsum(276), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(276)); + FF_275 : FD1P3DX + port map (D => tsum(275), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(275)); + FF_274 : FD1P3DX + port map (D => tsum(274), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(274)); + FF_273 : FD1P3DX + port map (D => tsum(273), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(273)); + FF_272 : FD1P3DX + port map (D => tsum(272), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(272)); + FF_271 : FD1P3DX + port map (D => tsum(271), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(271)); + FF_270 : FD1P3DX + port map (D => tsum(270), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(270)); + FF_269 : FD1P3DX + port map (D => tsum(269), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(269)); + FF_268 : FD1P3DX + port map (D => tsum(268), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(268)); + FF_267 : FD1P3DX + port map (D => tsum(267), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(267)); + FF_266 : FD1P3DX + port map (D => tsum(266), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(266)); + FF_265 : FD1P3DX + port map (D => tsum(265), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(265)); + FF_264 : FD1P3DX + port map (D => tsum(264), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(264)); + FF_263 : FD1P3DX + port map (D => tsum(263), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(263)); + FF_262 : FD1P3DX + port map (D => tsum(262), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(262)); + FF_261 : FD1P3DX + port map (D => tsum(261), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(261)); + FF_260 : FD1P3DX + port map (D => tsum(260), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(260)); + FF_259 : FD1P3DX + port map (D => tsum(259), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(259)); + FF_258 : FD1P3DX + port map (D => tsum(258), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(258)); + FF_257 : FD1P3DX + port map (D => tsum(257), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(257)); + FF_256 : FD1P3DX + port map (D => tsum(256), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(256)); + FF_255 : FD1P3DX + port map (D => tsum(255), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(255)); + FF_254 : FD1P3DX + port map (D => tsum(254), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(254)); + FF_253 : FD1P3DX + port map (D => tsum(253), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(253)); + FF_252 : FD1P3DX + port map (D => tsum(252), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(252)); + FF_251 : FD1P3DX + port map (D => tsum(251), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(251)); + FF_250 : FD1P3DX + port map (D => tsum(250), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(250)); + FF_249 : FD1P3DX + port map (D => tsum(249), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(249)); + FF_248 : FD1P3DX + port map (D => tsum(248), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(248)); + FF_247 : FD1P3DX + port map (D => tsum(247), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(247)); + FF_246 : FD1P3DX + port map (D => tsum(246), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(246)); + FF_245 : FD1P3DX + port map (D => tsum(245), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(245)); + FF_244 : FD1P3DX + port map (D => tsum(244), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(244)); + FF_243 : FD1P3DX + port map (D => tsum(243), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(243)); + FF_242 : FD1P3DX + port map (D => tsum(242), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(242)); + FF_241 : FD1P3DX + port map (D => tsum(241), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(241)); + FF_240 : FD1P3DX + port map (D => tsum(240), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(240)); + FF_239 : FD1P3DX + port map (D => tsum(239), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(239)); + FF_238 : FD1P3DX + port map (D => tsum(238), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(238)); + FF_237 : FD1P3DX + port map (D => tsum(237), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(237)); + FF_236 : FD1P3DX + port map (D => tsum(236), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(236)); + FF_235 : FD1P3DX + port map (D => tsum(235), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(235)); + FF_234 : FD1P3DX + port map (D => tsum(234), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(234)); + FF_233 : FD1P3DX + port map (D => tsum(233), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(233)); + FF_232 : FD1P3DX + port map (D => tsum(232), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(232)); + FF_231 : FD1P3DX + port map (D => tsum(231), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(231)); + FF_230 : FD1P3DX + port map (D => tsum(230), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(230)); + FF_229 : FD1P3DX + port map (D => tsum(229), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(229)); + FF_228 : FD1P3DX + port map (D => tsum(228), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(228)); + FF_227 : FD1P3DX + port map (D => tsum(227), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(227)); + FF_226 : FD1P3DX + port map (D => tsum(226), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(226)); + FF_225 : FD1P3DX + port map (D => tsum(225), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(225)); + FF_224 : FD1P3DX + port map (D => tsum(224), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(224)); + FF_223 : FD1P3DX + port map (D => tsum(223), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(223)); + FF_222 : FD1P3DX + port map (D => tsum(222), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(222)); + FF_221 : FD1P3DX + port map (D => tsum(221), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(221)); + FF_220 : FD1P3DX + port map (D => tsum(220), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(220)); + FF_219 : FD1P3DX + port map (D => tsum(219), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(219)); + FF_218 : FD1P3DX + port map (D => tsum(218), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(218)); + FF_217 : FD1P3DX + port map (D => tsum(217), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(217)); + FF_216 : FD1P3DX + port map (D => tsum(216), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(216)); + FF_215 : FD1P3DX + port map (D => tsum(215), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(215)); + FF_214 : FD1P3DX + port map (D => tsum(214), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(214)); + FF_213 : FD1P3DX + port map (D => tsum(213), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(213)); + FF_212 : FD1P3DX + port map (D => tsum(212), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(212)); + FF_211 : FD1P3DX + port map (D => tsum(211), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(211)); + FF_210 : FD1P3DX + port map (D => tsum(210), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(210)); + FF_209 : FD1P3DX + port map (D => tsum(209), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(209)); + FF_208 : FD1P3DX + port map (D => tsum(208), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(208)); + FF_207 : FD1P3DX + port map (D => tsum(207), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(207)); + FF_206 : FD1P3DX + port map (D => tsum(206), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(206)); + FF_205 : FD1P3DX + port map (D => tsum(205), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(205)); + FF_204 : FD1P3DX + port map (D => tsum(204), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(204)); + FF_203 : FD1P3DX + port map (D => tsum(203), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(203)); + FF_202 : FD1P3DX + port map (D => tsum(202), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(202)); + FF_201 : FD1P3DX + port map (D => tsum(201), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(201)); + FF_200 : FD1P3DX + port map (D => tsum(200), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(200)); + FF_199 : FD1P3DX + port map (D => tsum(199), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(199)); + FF_198 : FD1P3DX + port map (D => tsum(198), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(198)); + FF_197 : FD1P3DX + port map (D => tsum(197), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(197)); + FF_196 : FD1P3DX + port map (D => tsum(196), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(196)); + FF_195 : FD1P3DX + port map (D => tsum(195), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(195)); + FF_194 : FD1P3DX + port map (D => tsum(194), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(194)); + FF_193 : FD1P3DX + port map (D => tsum(193), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(193)); + FF_192 : FD1P3DX + port map (D => tsum(192), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(192)); + FF_191 : FD1P3DX + port map (D => tsum(191), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(191)); + FF_190 : FD1P3DX + port map (D => tsum(190), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(190)); + FF_189 : FD1P3DX + port map (D => tsum(189), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(189)); + FF_188 : FD1P3DX + port map (D => tsum(188), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(188)); + FF_187 : FD1P3DX + port map (D => tsum(187), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(187)); + FF_186 : FD1P3DX + port map (D => tsum(186), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(186)); + FF_185 : FD1P3DX + port map (D => tsum(185), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(185)); + FF_184 : FD1P3DX + port map (D => tsum(184), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(184)); + FF_183 : FD1P3DX + port map (D => tsum(183), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(183)); + FF_182 : FD1P3DX + port map (D => tsum(182), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(182)); + FF_181 : FD1P3DX + port map (D => tsum(181), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(181)); + FF_180 : FD1P3DX + port map (D => tsum(180), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(180)); + FF_179 : FD1P3DX + port map (D => tsum(179), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(179)); + FF_178 : FD1P3DX + port map (D => tsum(178), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(178)); + FF_177 : FD1P3DX + port map (D => tsum(177), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(177)); + FF_176 : FD1P3DX + port map (D => tsum(176), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(176)); + FF_175 : FD1P3DX + port map (D => tsum(175), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(175)); + FF_174 : FD1P3DX + port map (D => tsum(174), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(174)); + FF_173 : FD1P3DX + port map (D => tsum(173), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(173)); + FF_172 : FD1P3DX + port map (D => tsum(172), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(172)); + FF_171 : FD1P3DX + port map (D => tsum(171), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(171)); + FF_170 : FD1P3DX + port map (D => tsum(170), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(170)); + FF_169 : FD1P3DX + port map (D => tsum(169), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(169)); + FF_168 : FD1P3DX + port map (D => tsum(168), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(168)); + FF_167 : FD1P3DX + port map (D => tsum(167), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(167)); + FF_166 : FD1P3DX + port map (D => tsum(166), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(166)); + FF_165 : FD1P3DX + port map (D => tsum(165), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(165)); + FF_164 : FD1P3DX + port map (D => tsum(164), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(164)); + FF_163 : FD1P3DX + port map (D => tsum(163), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(163)); + FF_162 : FD1P3DX + port map (D => tsum(162), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(162)); + FF_161 : FD1P3DX + port map (D => tsum(161), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(161)); + FF_160 : FD1P3DX + port map (D => tsum(160), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(160)); + FF_159 : FD1P3DX + port map (D => tsum(159), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(159)); + FF_158 : FD1P3DX + port map (D => tsum(158), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(158)); + FF_157 : FD1P3DX + port map (D => tsum(157), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(157)); + FF_156 : FD1P3DX + port map (D => tsum(156), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(156)); + FF_155 : FD1P3DX + port map (D => tsum(155), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(155)); + FF_154 : FD1P3DX + port map (D => tsum(154), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(154)); + FF_153 : FD1P3DX + port map (D => tsum(153), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(153)); + FF_152 : FD1P3DX + port map (D => tsum(152), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(152)); + FF_151 : FD1P3DX + port map (D => tsum(151), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(151)); + FF_150 : FD1P3DX + port map (D => tsum(150), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(150)); + FF_149 : FD1P3DX + port map (D => tsum(149), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(149)); + FF_148 : FD1P3DX + port map (D => tsum(148), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(148)); + FF_147 : FD1P3DX + port map (D => tsum(147), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(147)); + FF_146 : FD1P3DX + port map (D => tsum(146), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(146)); + FF_145 : FD1P3DX + port map (D => tsum(145), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(145)); + FF_144 : FD1P3DX + port map (D => tsum(144), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(144)); + FF_143 : FD1P3DX + port map (D => tsum(143), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(143)); + FF_142 : FD1P3DX + port map (D => tsum(142), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(142)); + FF_141 : FD1P3DX + port map (D => tsum(141), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(141)); + FF_140 : FD1P3DX + port map (D => tsum(140), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(140)); + FF_139 : FD1P3DX + port map (D => tsum(139), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(139)); + FF_138 : FD1P3DX + port map (D => tsum(138), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(138)); + FF_137 : FD1P3DX + port map (D => tsum(137), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(137)); + FF_136 : FD1P3DX + port map (D => tsum(136), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(136)); + FF_135 : FD1P3DX + port map (D => tsum(135), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(135)); + FF_134 : FD1P3DX + port map (D => tsum(134), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(134)); + FF_133 : FD1P3DX + port map (D => tsum(133), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(133)); + FF_132 : FD1P3DX + port map (D => tsum(132), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(132)); + FF_131 : FD1P3DX + port map (D => tsum(131), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(131)); + FF_130 : FD1P3DX + port map (D => tsum(130), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(130)); + FF_129 : FD1P3DX + port map (D => tsum(129), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(129)); + FF_128 : FD1P3DX + port map (D => tsum(128), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(128)); + FF_127 : FD1P3DX + port map (D => tsum(127), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(127)); + FF_126 : FD1P3DX + port map (D => tsum(126), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(126)); + FF_125 : FD1P3DX + port map (D => tsum(125), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(125)); + FF_124 : FD1P3DX + port map (D => tsum(124), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(124)); + FF_123 : FD1P3DX + port map (D => tsum(123), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(123)); + FF_122 : FD1P3DX + port map (D => tsum(122), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(122)); + FF_121 : FD1P3DX + port map (D => tsum(121), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(121)); + FF_120 : FD1P3DX + port map (D => tsum(120), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(120)); + FF_119 : FD1P3DX + port map (D => tsum(119), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(119)); + FF_118 : FD1P3DX + port map (D => tsum(118), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(118)); + FF_117 : FD1P3DX + port map (D => tsum(117), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(117)); + FF_116 : FD1P3DX + port map (D => tsum(116), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(116)); + FF_115 : FD1P3DX + port map (D => tsum(115), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(115)); + FF_114 : FD1P3DX + port map (D => tsum(114), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(114)); + FF_113 : FD1P3DX + port map (D => tsum(113), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(113)); + FF_112 : FD1P3DX + port map (D => tsum(112), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(112)); + FF_111 : FD1P3DX + port map (D => tsum(111), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(111)); + FF_110 : FD1P3DX + port map (D => tsum(110), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(110)); + FF_109 : FD1P3DX + port map (D => tsum(109), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(109)); + FF_108 : FD1P3DX + port map (D => tsum(108), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(108)); + FF_107 : FD1P3DX + port map (D => tsum(107), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(107)); + FF_106 : FD1P3DX + port map (D => tsum(106), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(106)); + FF_105 : FD1P3DX + port map (D => tsum(105), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(105)); + FF_104 : FD1P3DX + port map (D => tsum(104), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(104)); + FF_103 : FD1P3DX + port map (D => tsum(103), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(103)); + FF_102 : FD1P3DX + port map (D => tsum(102), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(102)); + FF_101 : FD1P3DX + port map (D => tsum(101), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(101)); + FF_100 : FD1P3DX + port map (D => tsum(100), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(100)); + FF_99 : FD1P3DX + port map (D => tsum(99), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(99)); + FF_98 : FD1P3DX + port map (D => tsum(98), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(98)); + FF_97 : FD1P3DX + port map (D => tsum(97), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(97)); + FF_96 : FD1P3DX + port map (D => tsum(96), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(96)); + FF_95 : FD1P3DX + port map (D => tsum(95), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(95)); + FF_94 : FD1P3DX + port map (D => tsum(94), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(94)); + FF_93 : FD1P3DX + port map (D => tsum(93), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(93)); + FF_92 : FD1P3DX + port map (D => tsum(92), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(92)); + FF_91 : FD1P3DX + port map (D => tsum(91), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(91)); + FF_90 : FD1P3DX + port map (D => tsum(90), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(90)); + FF_89 : FD1P3DX + port map (D => tsum(89), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(89)); + FF_88 : FD1P3DX + port map (D => tsum(88), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(88)); + FF_87 : FD1P3DX + port map (D => tsum(87), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(87)); + FF_86 : FD1P3DX + port map (D => tsum(86), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(86)); + FF_85 : FD1P3DX + port map (D => tsum(85), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(85)); + FF_84 : FD1P3DX + port map (D => tsum(84), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(84)); + FF_83 : FD1P3DX + port map (D => tsum(83), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(83)); + FF_82 : FD1P3DX + port map (D => tsum(82), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(82)); + FF_81 : FD1P3DX + port map (D => tsum(81), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(81)); + FF_80 : FD1P3DX + port map (D => tsum(80), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(80)); + FF_79 : FD1P3DX + port map (D => tsum(79), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(79)); + FF_78 : FD1P3DX + port map (D => tsum(78), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(78)); + FF_77 : FD1P3DX + port map (D => tsum(77), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(77)); + FF_76 : FD1P3DX + port map (D => tsum(76), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(76)); + FF_75 : FD1P3DX + port map (D => tsum(75), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(75)); + FF_74 : FD1P3DX + port map (D => tsum(74), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(74)); + FF_73 : FD1P3DX + port map (D => tsum(73), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(73)); + FF_72 : FD1P3DX + port map (D => tsum(72), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(72)); + FF_71 : FD1P3DX + port map (D => tsum(71), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(71)); + FF_70 : FD1P3DX + port map (D => tsum(70), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(70)); + FF_69 : FD1P3DX + port map (D => tsum(69), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(69)); + FF_68 : FD1P3DX + port map (D => tsum(68), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(68)); + FF_67 : FD1P3DX + port map (D => tsum(67), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(67)); + FF_66 : FD1P3DX + port map (D => tsum(66), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(66)); + FF_65 : FD1P3DX + port map (D => tsum(65), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(65)); + FF_64 : FD1P3DX + port map (D => tsum(64), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(64)); + FF_63 : FD1P3DX + port map (D => tsum(63), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(63)); + FF_62 : FD1P3DX + port map (D => tsum(62), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(62)); + FF_61 : FD1P3DX + port map (D => tsum(61), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(61)); + FF_60 : FD1P3DX + port map (D => tsum(60), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(60)); + FF_59 : FD1P3DX + port map (D => tsum(59), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(59)); + FF_58 : FD1P3DX + port map (D => tsum(58), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(58)); + FF_57 : FD1P3DX + port map (D => tsum(57), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(57)); + FF_56 : FD1P3DX + port map (D => tsum(56), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(56)); + FF_55 : FD1P3DX + port map (D => tsum(55), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(55)); + FF_54 : FD1P3DX + port map (D => tsum(54), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(54)); + FF_53 : FD1P3DX + port map (D => tsum(53), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(53)); + FF_52 : FD1P3DX + port map (D => tsum(52), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(52)); + FF_51 : FD1P3DX + port map (D => tsum(51), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(51)); + FF_50 : FD1P3DX + port map (D => tsum(50), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(50)); + FF_49 : FD1P3DX + port map (D => tsum(49), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(49)); + FF_48 : FD1P3DX + port map (D => tsum(48), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(48)); + FF_47 : FD1P3DX + port map (D => tsum(47), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(47)); + FF_46 : FD1P3DX + port map (D => tsum(46), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(46)); + FF_45 : FD1P3DX + port map (D => tsum(45), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(45)); + FF_44 : FD1P3DX + port map (D => tsum(44), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(44)); + FF_43 : FD1P3DX + port map (D => tsum(43), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(43)); + FF_42 : FD1P3DX + port map (D => tsum(42), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(42)); + FF_41 : FD1P3DX + port map (D => tsum(41), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(41)); + FF_40 : FD1P3DX + port map (D => tsum(40), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(40)); + FF_39 : FD1P3DX + port map (D => tsum(39), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(39)); + FF_38 : FD1P3DX + port map (D => tsum(38), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(38)); + FF_37 : FD1P3DX + port map (D => tsum(37), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(37)); + FF_36 : FD1P3DX + port map (D => tsum(36), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(36)); + FF_35 : FD1P3DX + port map (D => tsum(35), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(35)); + FF_34 : FD1P3DX + port map (D => tsum(34), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(34)); + FF_33 : FD1P3DX + port map (D => tsum(33), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(33)); + FF_32 : FD1P3DX + port map (D => tsum(32), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(32)); + FF_31 : FD1P3DX + port map (D => tsum(31), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(31)); + FF_30 : FD1P3DX + port map (D => tsum(30), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(30)); + FF_29 : FD1P3DX + port map (D => tsum(29), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(29)); + FF_28 : FD1P3DX + port map (D => tsum(28), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(28)); + FF_27 : FD1P3DX + port map (D => tsum(27), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(27)); + FF_26 : FD1P3DX + port map (D => tsum(26), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(26)); + FF_25 : FD1P3DX + port map (D => tsum(25), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(25)); + FF_24 : FD1P3DX + port map (D => tsum(24), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(24)); + FF_23 : FD1P3DX + port map (D => tsum(23), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(23)); + FF_22 : FD1P3DX + port map (D => tsum(22), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(22)); + FF_21 : FD1P3DX + port map (D => tsum(21), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(21)); + FF_20 : FD1P3DX + port map (D => tsum(20), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(20)); + FF_19 : FD1P3DX + port map (D => tsum(19), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(19)); + FF_18 : FD1P3DX + port map (D => tsum(18), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(18)); + FF_17 : FD1P3DX + port map (D => tsum(17), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(17)); + FF_16 : FD1P3DX + port map (D => tsum(16), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(16)); + FF_15 : FD1P3DX + port map (D => tsum(15), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(15)); + FF_14 : FD1P3DX + port map (D => tsum(14), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(14)); + FF_13 : FD1P3DX + port map (D => tsum(13), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(13)); + FF_12 : FD1P3DX + port map (D => tsum(12), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(12)); + FF_11 : FD1P3DX + port map (D => tsum(11), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(11)); + FF_10 : FD1P3DX + port map (D => tsum(10), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(10)); + FF_9 : FD1P3DX + port map (D => tsum(9), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(9)); + FF_8 : FD1P3DX + port map (D => tsum(8), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(8)); + FF_7 : FD1P3DX + port map (D => tsum(7), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(7)); + FF_6 : FD1P3DX + port map (D => tsum(6), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(6)); + FF_5 : FD1P3DX + port map (D => tsum(5), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(5)); + FF_4 : FD1P3DX + port map (D => tsum(4), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(4)); + FF_3 : FD1P3DX + port map (D => tsum(3), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(3)); + FF_2 : FD1P3DX + port map (D => tsum(2), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(2)); + FF_1 : FD1P3DX + port map (D => tsum(1), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(1)); + FF_0 : FD1P3DX + port map (D => tsum(0), SP => ClkEn, CK => Clk, CD => Reset, + Q => r0_sum(0)); + + GEN_0_ADD : CCU2C + generic map (INJECT1_1 => "NO", INJECT1_0 => "NO", INIT1 => X"66AA", + INIT0 => X"9002") +-- INIT0 => X"66AA") + port map (A0 => DataA(0), A1 => DataA(1), B0 => DataB(0), B1 => DataB(1), + C0 => scuba_vhi, C1 => scuba_vhi, D0 => scuba_vhi, D1 => scuba_vhi, + CIN => 'X', S0 => tsum(0), S1 => tsum(1), COUT => co(0)); + + GEN : for i in 1 to 143 generate + ADD : CCU2C + generic map (INJECT1_1 => "NO", INJECT1_0 => "NO", INIT1 => X"66AA", + INIT0 => X"66AA") + port map (A0 => DataA(2*i), A1 => DataA(2*i+1), B0 => DataB(2*i), B1 => DataB(2*i+1), + C0 => scuba_vhi, C1 => scuba_vhi, D0 => scuba_vhi, D1 => scuba_vhi, + CIN => co(i-1), S0 => tsum(2*i), S1 => tsum(2*i+1), COUT => co(i)); + end generate GEN; + + scuba_vhi_inst : VHI + port map (Z => scuba_vhi); + + scuba_vlo_inst : VLO + port map (Z => scuba_vlo); + + Result <= r0_sum; +end Structure; diff --git a/releases/tdc_v2.3/Channel_200.vhd b/releases/tdc_v2.3/Channel_200.vhd index 3b3a490..1049c74 100644 --- a/releases/tdc_v2.3/Channel_200.vhd +++ b/releases/tdc_v2.3/Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-08-28 --- Last update: 2016-03-23 +-- Last update: 2017-04-22 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -65,9 +65,9 @@ architecture Channel_200 of Channel_200 is end component; -- carry chain - signal data_a : std_logic_vector(303 downto 0); - signal data_b : std_logic_vector(303 downto 0); - signal result : std_logic_vector(303 downto 0); + signal data_a : std_logic_vector(287 downto 0); + signal data_b : std_logic_vector(287 downto 0); + signal result : std_logic_vector(287 downto 0); signal ff_array_en : std_logic; -- hit detection @@ -112,7 +112,7 @@ architecture Channel_200 of Channel_200 is signal epoch_cntr : std_logic_vector(27 downto 0) := (others => '0'); signal epoch_cntr_r : std_logic_vector(27 downto 0) := (others => '0'); signal epoch_cntr_updated : std_logic := '0'; - signal epoch_value : std_logic_vector(35 downto 0); + signal epoch_value : std_logic_vector(35 downto 0) := (others => '0'); -- ring bugger signal ringBuffer_data_out : std_logic_vector(35 downto 0); @@ -149,6 +149,7 @@ architecture Channel_200 of Channel_200 is signal trg_win_end_tdc_flag_fsm : std_logic; signal trg_win_end_tdc_flag : std_logic := '0'; signal trg_win_end_tdc : std_logic := '0'; + signal trg_cntr : std_logic_vector(7 downto 0) := (others => '0'); signal fsm_wr_debug_fsm : std_logic_vector(3 downto 0); signal fsm_wr_debug : std_logic_vector(3 downto 0); @@ -159,34 +160,58 @@ architecture Channel_200 of Channel_200 is ----------------------------------------------------------------------------- -- debug - signal data_cnt_total : integer range 0 to 2147483647 := 0; - signal data_cnt_event : integer range 0 to 255 := 0; - signal epoch_cnt_total : integer range 0 to 65535 := 0; - signal epoch_cnt_event : integer range 0 to 127 := 0; + signal data_cnt_total : integer range 0 to 2147483647 := 0; + signal data_cnt_event : integer range 0 to 255 := 0; + signal epoch_cnt_total : integer range 0 to 65535 := 0; + signal epoch_cnt_event : integer range 0 to 127 := 0; + signal trg_win_end_tdc_pipe : std_logic_vector(31 downto 0) := (others => '0'); ----------------------------------------------------------------------------- attribute syn_keep : boolean; attribute syn_keep of ff_array_en : signal is true; - + begin -- Channel_200 - GEN_TrgWinEndTdcDist : if SIMULATION = 0 generate + GEN_TrgWinEndTdcDist : if SIMULATION = 0 and TDC_DATA_FORMAT /= 15 generate TrgWinEndTdcDist : FD1P3IX port map (D => '1', SP => TRG_WIN_END_TDC_IN, CK => CLK_200, CD => trg_win_end_tdc, Q => trg_win_end_tdc); + TheTriggerCounter : up_counter + generic map ( + NUMBER_OF_BITS => 8) + port map ( + CLK => CLK_200, + RESET => RESET_200, + COUNT_OUT => trg_cntr, + UP_IN => trg_win_end_tdc); + end generate GEN_TrgWinEndTdcDist; + GEN_TrgWinEndTdcDist_Chain : if SIMULATION = 0 and TDC_DATA_FORMAT = 15 generate + TrgWinEndTdcDist : FD1P3IX + port map (D => '1', + SP => TRG_WIN_END_TDC_IN, + CK => CLK_200, + CD => trg_win_end_tdc_pipe(0), + Q => trg_win_end_tdc_pipe(0)); + trg_win_end_tdc_pipe(31 downto 1) <= trg_win_end_tdc_pipe (30 downto 0) when rising_edge(CLK_200); + trg_win_end_tdc <= trg_win_end_tdc_pipe(31); + end generate GEN_TrgWinEndTdcDist_Chain; + GEN_TrgWinEndTdcDist_Sim : if SIMULATION = 1 generate - trg_win_end_tdc <= TRG_WIN_END_TDC_IN when rising_edge(CLK_200); + trg_win_end_tdc_pipe(0) <= TRG_WIN_END_TDC_IN when rising_edge(CLK_200); + trg_win_end_tdc_pipe(31 downto 1) <= trg_win_end_tdc_pipe (30 downto 0) when rising_edge(CLK_200); + trg_win_end_tdc <= trg_win_end_tdc_pipe(31); + end generate GEN_TrgWinEndTdcDist_Sim; SimAdderYes : if SIMULATION = c_YES generate --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition - FC : Adder_304 + FC : Adder_288 port map ( CLK => CLK_200, RESET => '0', @@ -194,12 +219,12 @@ begin -- Channel_200 DataB => data_b, ClkEn => ff_array_en, Result => result); - data_a <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFc030c0F"&x"7FFFFFF"; - data_b <= x"000000000000000000000000000000000000000000000000000000000000000000000"& HIT_IN & x"000000"&"00" & not(HIT_IN); + data_a <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFc00000F"&x"EFFFF"; + data_b <= x"0000000000000000000000000000000000000000000000000000000000000000000"&"000"&HIT_IN&x"000"&"000"&HIT_IN; end generate SimAdderYes; SimAdderNo : if SIMULATION = c_NO generate --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition - FC : Adder_304 + FC : Adder_288 port map ( CLK => CLK_200, RESET => '0', @@ -207,8 +232,8 @@ begin -- Channel_200 DataB => data_b, ClkEn => ff_array_en, Result => result); - data_a <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"&x"EFFF"; - data_b <= x"000000000000000000000000000000000000000000000000000000000000000000000000"&"000"&HIT_IN&x"00"&"000"¬(HIT_IN); + data_a <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"&x"EFFFF"; + data_b <= x"0000000000000000000000000000000000000000000000000000000000000000000"&"000"&HIT_IN&x"000"&"000"&HIT_IN; end generate SimAdderNo; ff_array_en <= not(hit_detect or hit_detect_r); -- or hit_detect_2r); @@ -815,8 +840,11 @@ begin -- Channel_200 end case; end process FSM_DATA_OUTPUT; - FIFO_DATA_OUT <= fifo_data; - FIFO_DATA_VALID_OUT <= fifo_data_valid; +--FIFO_DATA_OUT <= fifo_data; +--FIFO_DATA_VALID_OUT <= fifo_data_valid; + + FIFO_DATA_OUT <= fifo_data when rising_edge(CLK_100); + FIFO_DATA_VALID_OUT <= fifo_data_valid when rising_edge(CLK_100); ------------------------------------------------------------------------------- -- DEBUG @@ -828,7 +856,8 @@ begin -- Channel_200 --CHANNEL_200_DEBUG_OUT(18) <= ringBuffer_rd_en; --CHANNEL_200_DEBUG_OUT(23 downto 19) <= (others => '0'); -- CHANNEL_200_DEBUG_OUT(0) <= ff_array_en; - CHANNEL_200_DEBUG_OUT(23 downto 0) <= (others => '0'); + CHANNEL_200_DEBUG_OUT(15 downto 0) <= (others => '0'); + CHANNEL_200_DEBUG_OUT(23 downto 16) <= trg_cntr; CHANNEL_200_DEBUG_OUT(27 downto 24) <= fsm_rd_debug; CHANNEL_200_DEBUG_OUT(31 downto 28) <= fsm_wr_debug; diff --git a/releases/tdc_v2.3/Encoder_288_Bit.vhd b/releases/tdc_v2.3/Encoder_288_Bit.vhd index 1f0a875..9ffb423 100644 --- a/releases/tdc_v2.3/Encoder_288_Bit.vhd +++ b/releases/tdc_v2.3/Encoder_288_Bit.vhd @@ -4,7 +4,7 @@ -- File : Encoder_288_Bit.vhd -- Author : Cahit Ugur -- Created : 2011-11-28 --- Last update: 2016-03-23 +-- Last update: 2017-04-08 ------------------------------------------------------------------------------- -- Description: Encoder for 288 bits ------------------------------------------------------------------------------- @@ -59,36 +59,52 @@ architecture behavioral of Encoder_288_Bit is ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- - signal P_lut : std_logic_vector(35 downto 0); - signal P_one : std_logic_vector(35 downto 0); - signal P_mux : std_logic_vector(34 downto 0); - signal mux_control : std_logic_vector(5 downto 0); - signal mux_control_reg : std_logic_vector(5 downto 0); - signal mux_control_2reg : std_logic_vector(5 downto 0); - signal mux_control_3reg : std_logic_vector(5 downto 0); - signal interval_reg : std_logic_vector(8 downto 0); - signal interval_decimal : std_logic_vector(2 downto 0); - signal decimal_code_f : std_logic_vector(8 downto 0); - signal decimal_code_r : std_logic_vector(8 downto 0); - signal address : std_logic_vector(9 downto 0); - signal address_r : std_logic_vector(9 downto 0); - signal q_reg : std_logic_vector(7 downto 0); - signal info : std_logic_vector(1 downto 0); - signal info_reg : std_logic_vector(1 downto 0); - signal info_2reg : std_logic_vector(1 downto 0); - signal info_3reg : std_logic_vector(1 downto 0); + signal P_lut : std_logic_vector(35 downto 0); + signal P_one : std_logic_vector(35 downto 0); + signal P_mux : std_logic_vector(34 downto 0); + signal mux_control : std_logic_vector(5 downto 0); + signal mux_control_reg : std_logic_vector(5 downto 0); + signal mux_control_2reg : std_logic_vector(5 downto 0); + signal mux_control_3reg : std_logic_vector(5 downto 0); + signal interval_reg : std_logic_vector(8 downto 0); + signal interval_decimal : std_logic_vector(2 downto 0); + signal decimal_code_f : std_logic_vector(8 downto 0); + signal decimal_code_r : std_logic_vector(8 downto 0); + signal address : std_logic_vector(9 downto 0); + signal address_r : std_logic_vector(9 downto 0); + signal q_reg : std_logic_vector(7 downto 0); + signal info : std_logic_vector(1 downto 0); + signal info_reg : std_logic_vector(1 downto 0); + signal info_2reg : std_logic_vector(1 downto 0); + signal info_3reg : std_logic_vector(1 downto 0); -- - signal conv_finished : std_logic; - signal thermocode : std_logic_vector(288 downto 0); - signal thermocode_r : std_logic_vector(287 downto 0); - signal start_pipeline : std_logic_vector(10 downto 0) := (others => '0'); - signal chain_pipeline : std_logic_vector(18 downto 0) := (others => '0'); + signal conv_finished : std_logic; + signal thermocode : std_logic_vector(288 downto 0); + signal thermocode_r : std_logic_vector(287 downto 0); + signal thermocode_tmp : std_logic_vector(287 downto 0); + signal start_pipeline : std_logic_vector(10 downto 0) := (others => '0'); + signal chain_pipeline : std_logic_vector(18 downto 0) := (others => '0'); --debug + type std_logic_vector_array_288 is array(integer range <>) of std_logic_vector(287 downto 0); type std_logic_vector_array_10 is array(integer range <>) of std_logic_vector(9 downto 0); - signal decimal_code_i : std_logic_vector_array_10(0 to 3); - signal chain : std_logic_vector(15 downto 0); - signal chain_valid : std_logic; - + signal decimal_code_i : std_logic_vector_array_10(0 to 3); + signal chain : std_logic_vector(15 downto 0); + signal chain_valid : std_logic; + signal start_in_r : std_logic := '0'; + signal start_in_2r : std_logic := '0'; + signal thermocode_array : std_logic_vector_array_288(0 to 1); + signal thermocode_r1 : std_logic_vector(287 downto 0); + signal thermocode_f1 : std_logic_vector(287 downto 0); + signal thermocode_r2 : std_logic_vector(287 downto 0); + signal thermocode_f2 : std_logic_vector(287 downto 0); + signal start_r : std_logic := '0'; + signal start_f : std_logic := '0'; + signal chain_r : std_logic_vector(15 downto 0); + signal chain_f : std_logic_vector(15 downto 0); + type CHAIN_FSM_TYPE is (IDLE, LEADING_EDGE, LEADING_EDGE_2ND, TRAILING_EDGE); + signal STATE_CURRENT, STATE_NEXT : CHAIN_FSM_TYPE; + + attribute syn_keep : boolean; attribute syn_keep of mux_control : signal is true; attribute syn_keep of mux_control_reg : signal is true; @@ -164,7 +180,8 @@ begin end if; end process Interval_Selection; - The_ROM : entity work.ROM_encoder_3 +-- The_ROM : entity work.ROM_encoder_3 --SIMULATION + The_ROM : entity work.ROM_encoder_4 --REAL port map ( Address => address, OutClock => CLK, @@ -227,6 +244,7 @@ begin -- DEBUG DATA FORMATS ------------------------------------------------------------------------------- DATA_FORMAT_13 : if TDC_DATA_FORMAT = 13 generate + -- purpose: write decimal value and the chain SampleThermocode : process (CLK) is begin if rising_edge(CLK) then -- rising clock edge @@ -252,11 +270,10 @@ begin chain_pipeline(0) <= '0'; end if; - FINISHED_OUT <= conv_finished; - decimal_code_r <= mux_control_3reg & interval_decimal; - decimal_code_f <= decimal_code_r; - conv_finished <= start_pipeline(5); - chain_pipeline(18 downto 1) <= chain_pipeline(17 downto 0); + FINISHED_OUT <= conv_finished; + decimal_code_r <= mux_control_3reg & interval_decimal; + decimal_code_f <= decimal_code_r; + conv_finished <= start_pipeline(5); end if; end process Decimal_Code_Calculation; -- @@ -270,15 +287,18 @@ begin tmp(j) := tmp(j) or (thermocode_r(i*16+j) and chain_pipeline(i+1)); end loop; end loop; - chain <= tmp; - chain_valid <= or_all(chain_pipeline(18 downto 1)); - CHAIN_DATA_OUT <= chain; - CHAIN_VALID_OUT <= chain_valid; + chain <= tmp; + chain_pipeline(18 downto 1) <= chain_pipeline(17 downto 0); + chain_valid <= or_all(chain_pipeline(18 downto 1)); + CHAIN_DATA_OUT <= chain; + CHAIN_VALID_OUT <= chain_valid; end if; end process Chain_Readout; +-- end generate DATA_FORMAT_13; - +------------------------------------------------------------------------------- DATA_FORMAT_14 : if TDC_DATA_FORMAT = 14 generate + -- purpose: Decimal_Code_Calculation : process (CLK) begin if rising_edge(CLK) then @@ -313,34 +333,110 @@ begin end if; end process Decimal_Code_Calculation; end generate DATA_FORMAT_14; - +------------------------------------------------------------------------------- DATA_FORMAT_15 : if TDC_DATA_FORMAT = 15 generate - SampleThermocode : process (CLK) is + FSM_CHAIN_SEQUENTIAL: process (CLK) is begin - if rising_edge(CLK) then -- rising clock edge - if START_IN = '1' then - thermocode_r <= THERMOCODE_IN; + -- Outputs to be registered + if rising_edge(CLK) then -- rising clock edge + if RESET = '1' then + STATE_CURRENT <= IDLE; + else + STATE_CURRENT <= STATE_NEXT; end if; - end if; - end process SampleThermocode; --- - Chain_Readout : process (CLK) - variable tmp : std_logic_vector(15 downto 0); - begin - if rising_edge(CLK) then - tmp := (others => '0'); - make_mux : for i in 0 to 17 loop - make_mux_2 : for j in 0 to 15 loop - tmp(j) := tmp(j) or (thermocode_r(i*16+j) and chain_pipeline(i)); - end loop; - end loop; - chain <= tmp; - chain_valid <= or_all(chain_pipeline(17 downto 0)); - CHAIN_DATA_OUT <= chain; + thermocode_r1 <= thermocode_f1; + thermocode_r2 <= thermocode_f2; + start_r <= start_f; + chain_r <= chain_f; + + chain_pipeline(18 downto 0) <= chain_pipeline(17 downto 0) & start_r; + chain_valid <= or_all(chain_pipeline(16 downto 0)) or start_r; + CHAIN_DATA_OUT <= chain_r; CHAIN_VALID_OUT <= chain_valid; - chain_pipeline(17 downto 0) <= chain_pipeline(16 downto 0) & START_IN; end if; - end process Chain_Readout; + -- Outputs not to be registered + + end process FSM_CHAIN_SEQUENTIAL; + + FSM_CHAIN_COMBINATIONAL : process (STATE_CURRENT, START_IN, THERMOCODE_IN, chain_pipeline, chain_valid, thermocode_r1, thermocode_r2) is + begin + -- Default values + STATE_NEXT <= STATE_CURRENT; + thermocode_f1 <= (others => '0'); + thermocode_f2 <= thermocode_r2; + start_f <= '0'; + chain_f <= (others => '0'); + + case STATE_CURRENT is + when IDLE => + if START_IN = '1' then + STATE_NEXT <= LEADING_EDGE; + thermocode_f1 <= THERMOCODE_IN; + start_f <= '1'; + end if; + + when LEADING_EDGE => + if START_IN = '1' then + STATE_NEXT <= LEADING_EDGE_2ND; + thermocode_f2 <= THERMOCODE_IN; + elsif chain_pipeline(18) = '1' then + STATE_NEXT <= IDLE; + end if; + chain_f <= thermocode_r1(15 downto 0); + thermocode_f1 <= x"0000" & thermocode_r1(287 downto 16); + + when LEADING_EDGE_2ND => + if chain_valid = '0' then + STATE_NEXT <= TRAILING_EDGE; + start_f <= '1'; + end if; + chain_f <= thermocode_r1(15 downto 0); + thermocode_f1 <= x"0000" & thermocode_r1(287 downto 16); + + when TRAILING_EDGE => + if chain_valid = '0' and start_r = '0'then + STATE_NEXT <= IDLE; + end if; + chain_f <= thermocode_r2(15 downto 0); + thermocode_f2 <= x"0000" & thermocode_r2(287 downto 16); + + when others => + STATE_NEXT <= IDLE; + end case; + end process FSM_CHAIN_COMBINATIONAL; + + + + +-- SampleThermocode : process (CLK) is +-- begin +-- if rising_edge(CLK) then -- rising clock edge +-- if START_IN = '1' then +-- thermocode_tmp <= THERMOCODE_IN; +-- end if; +-- if chain_pipeline = "0000000000000000001" or chain_pipeline = "1000000000000000000"then +-- thermocode_r <= thermocode_tmp; +-- end if; +-- end if; +-- end process SampleThermocode; +---- +-- Chain_Readout : process (CLK) +-- variable tmp : std_logic_vector(15 downto 0); +-- begin +-- if rising_edge(CLK) then +-- tmp := (others => '0'); +-- make_mux : for i in 0 to 17 loop +-- make_mux_2 : for j in 0 to 15 loop +-- tmp(j) := tmp(j) or (thermocode_r(i*16+j) and chain_pipeline(i+1)); +-- end loop; +-- end loop; +-- chain <= tmp; +-- chain_valid <= or_all(chain_pipeline(18 downto 1)); +-- CHAIN_DATA_OUT <= chain; +-- CHAIN_VALID_OUT <= chain_valid; +-- chain_pipeline(18 downto 0) <= chain_pipeline(17 downto 0) & START_IN; +-- end if; +-- end process Chain_Readout; end generate DATA_FORMAT_15; ------------------------------------------------------------------------------- diff --git a/releases/tdc_v2.3/ROM_encoder_ecp5.vhd b/releases/tdc_v2.3/ROM_encoder_ecp5.vhd index 0b05144..15d512f 120000 --- a/releases/tdc_v2.3/ROM_encoder_ecp5.vhd +++ b/releases/tdc_v2.3/ROM_encoder_ecp5.vhd @@ -1 +1 @@ -rom_encoder/ecp5/ROM_encoder_3/ROM_encoder_3.vhd \ No newline at end of file +rom_encoder/ecp5/ROM_encoder_4/ROM_encoder_4.vhd \ No newline at end of file diff --git a/releases/tdc_v2.3/Readout_record.vhd b/releases/tdc_v2.3/Readout_record.vhd index 9e84741..e92d0bc 100644 --- a/releases/tdc_v2.3/Readout_record.vhd +++ b/releases/tdc_v2.3/Readout_record.vhd @@ -5,7 +5,7 @@ -- File : Readout_record.vhd -- Author : cugur@gsi.de -- Created : 2012-10-25 --- Last update: 2016-03-22 +-- Last update: 2016-07-24 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -460,13 +460,11 @@ begin -- behavioral RD_NEXT <= SEND_TRG_RELEASE_C; readout_fsm <= '1'; rd_fsm_debug_fsm <= x"A"; - when SEND_TRG_RELEASE_C => RD_NEXT <= SEND_TRG_RELEASE_D; data_finished_fsm <= '1'; readout_fsm <= '1'; rd_fsm_debug_fsm <= x"B"; - when SEND_TRG_RELEASE_D => RD_NEXT <= IDLE; trg_release_fsm <= '1'; diff --git a/releases/tdc_v2.3/dirich_tdc_constraints.lpf b/releases/tdc_v2.3/dirich_tdc_constraints.lpf index 1973a26..e93f3c9 100644 --- a/releases/tdc_v2.3/dirich_tdc_constraints.lpf +++ b/releases/tdc_v2.3/dirich_tdc_constraints.lpf @@ -5,20 +5,20 @@ ## DELAY LINE and HIT BUFFER PLACEMENTS ## ############################################################################## ############################################################################## -UGROUP "Ref_Ch" BBOX 1 36 +UGROUP "Ref_Ch" BBOX 1 36 BLKNAME THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC ; -LOCATE UGROUP "Ref_Ch" SITE "R11C44D" ; +LOCATE UGROUP "Ref_Ch" SITE "R8C44D" ; UGROUP "hitBuf_ref" BBOX 1 1 BLKNAME THE_TDC/hit_mux_ref ; -LOCATE UGROUP "hitBuf_ref" SITE "R12C45D" ; +LOCATE UGROUP "hitBuf_ref" SITE "R9C45D" ; UGROUP "Ref_ff_en" BBOX 1 1 BLKNAME THE_TDC/ReferenceChannel/Channel200/ff_array_en_1_i ; -LOCATE UGROUP "Ref_ff_en" SITE "R12C62D" ; +LOCATE UGROUP "Ref_ff_en" SITE "R9C62D" ; # -UGROUP "FC_1" BBOX 1 36 +UGROUP "FC_1" BBOX 1 36 BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200/SimAdderNo.FC ; LOCATE UGROUP "FC_1" SITE "R11C2D" ; @@ -31,7 +31,7 @@ UGROUP "ff_en_1" BBOX 1 1 ; LOCATE UGROUP "ff_en_1" SITE "R12C20D" ; # -UGROUP "FC_2" BBOX 1 36 +UGROUP "FC_2" BBOX 1 36 BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel200/SimAdderNo.FC ; LOCATE UGROUP "FC_2" SITE "R13C2D" ; @@ -44,7 +44,7 @@ UGROUP "ff_en_2" BBOX 1 1 ; LOCATE UGROUP "ff_en_2" SITE "R14C20D" ; # -UGROUP "FC_3" BBOX 1 36 +UGROUP "FC_3" BBOX 1 36 BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel200/SimAdderNo.FC ; LOCATE UGROUP "FC_3" SITE "R30C2D" ; @@ -57,7 +57,7 @@ UGROUP "ff_en_3" BBOX 1 1 ; LOCATE UGROUP "ff_en_3" SITE "R31C20D" ; # -UGROUP "FC_4" BBOX 1 36 +UGROUP "FC_4" BBOX 1 36 BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel200/SimAdderNo.FC ; LOCATE UGROUP "FC_4" SITE "R32C2D" ; @@ -385,28 +385,28 @@ LOCATE UGROUP "ff_en_28" SITE "R81C104D" ; UGROUP "FC_29" BBOX 1 36 BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel200/SimAdderNo.FC ; -LOCATE UGROUP "FC_29" SITE "R71C44D" ; +LOCATE UGROUP "FC_29" SITE "R11C44D" ; UGROUP "hitBuf_29" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.29.hit_mux_ch ; -LOCATE UGROUP "hitBuf_29" SITE "R72C45D" ; +LOCATE UGROUP "hitBuf_29" SITE "R12C45D" ; UGROUP "ff_en_29" BBOX 1 1 BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel200/ff_array_en_1_i ; -LOCATE UGROUP "ff_en_29" SITE "R72C62D" ; +LOCATE UGROUP "ff_en_29" SITE "R12C62D" ; # UGROUP "FC_30" BBOX 1 36 BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel200/SimAdderNo.FC ; -LOCATE UGROUP "FC_30" SITE "R73C44D" ; +LOCATE UGROUP "FC_30" SITE "R13C44D" ; UGROUP "hitBuf_30" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.30.hit_mux_ch ; -LOCATE UGROUP "hitBuf_30" SITE "R74C45D" ; +LOCATE UGROUP "hitBuf_30" SITE "R14C45D" ; UGROUP "ff_en_30" BBOX 1 1 BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel200/ff_array_en_1_i ; -LOCATE UGROUP "ff_en_30" SITE "R74C62D" ; +LOCATE UGROUP "ff_en_30" SITE "R14C62D" ; # UGROUP "FC_31" BBOX 1 36 BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel200/SimAdderNo.FC @@ -421,7 +421,7 @@ UGROUP "ff_en_31" BBOX 1 1 ; LOCATE UGROUP "ff_en_31" SITE "R91C62D" ; # -UGROUP "FC_32" BBOX 1 36 +UGROUP "FC_32" BBOX 1 36 BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel200/SimAdderNo.FC ; LOCATE UGROUP "FC_32" SITE "R92C44D" ; @@ -436,7 +436,7 @@ LOCATE UGROUP "ff_en_32" SITE "R93C62D" ; ############################################################################## ## CHANNEL PLACEMENTS ## ############################################################################## -UGROUP "EF_LT1" BBOX 23 45 +UGROUP "EF_LT1" BBOX 23 42 BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.1.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel200 @@ -447,7 +447,7 @@ UGROUP "EF_LT1" BBOX 23 45 BLKNAME THE_TDC/GEN_Channels.4.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LT1" SITE "R11C2D" ; -UGROUP "EF_LT2" BBOX 23 45 +UGROUP "EF_LT2" BBOX 23 42 BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.5.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel200 @@ -458,7 +458,7 @@ UGROUP "EF_LT2" BBOX 23 45 BLKNAME THE_TDC/GEN_Channels.8.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LT2" SITE "R35C2D" ; -UGROUP "EF_LB2" BBOX 23 45 +UGROUP "EF_LB2" BBOX 23 42 BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.9.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel200 @@ -469,14 +469,14 @@ UGROUP "EF_LB2" BBOX 23 45 BLKNAME THE_TDC/GEN_Channels.12.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LB2" SITE "R59C2D" ; -UGROUP "EF_LB1" BBOX 13 45 +UGROUP "EF_LB1" BBOX 13 42 BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.13.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.14.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LB1" SITE "R81C2D" ; -UGROUP "EF_RT1" BBOX 23 45 +UGROUP "EF_RT1" BBOX 23 42 BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.17.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel200 @@ -486,8 +486,8 @@ UGROUP "EF_RT1" BBOX 23 45 BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.20.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_RT1" SITE "R11C80D" ; -UGROUP "EF_RT2" BBOX 23 45 +LOCATE UGROUP "EF_RT1" SITE "R11C83D" ; +UGROUP "EF_RT2" BBOX 23 42 BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.21.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel200 @@ -497,8 +497,8 @@ UGROUP "EF_RT2" BBOX 23 45 BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.24.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_RT2" SITE "R35C80D" ; -UGROUP "EF_RB2" BBOX 23 45 +LOCATE UGROUP "EF_RT2" SITE "R35C83D" ; +UGROUP "EF_RB2" BBOX 23 42 BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.25.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel200 @@ -508,25 +508,30 @@ UGROUP "EF_RB2" BBOX 23 45 BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.28.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_RB2" SITE "R59C80D" ; -UGROUP "EF_RB1" BBOX 13 45 +LOCATE UGROUP "EF_RB2" SITE "R59C83D" ; +UGROUP "EF_RB1" BBOX 13 42 BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.15.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.16.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_RB1" SITE "R81C80D" ; -UGROUP "EF_CB1" BBOX 30 33 - BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.29.Channels/Buffer_128.The_Buffer - BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.30.Channels/Buffer_128.The_Buffer +LOCATE UGROUP "EF_RB1" SITE "R81C83D" ; +UGROUP "EF_CB1" BBOX 13 39 BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.31.Channels/Buffer_128.The_Buffer + BLKNAME THE_TDC/GEN_Channels.31.Channels/Buffer_32.The_Buffer BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.32.Channels/Buffer_128.The_Buffer + BLKNAME THE_TDC/GEN_Channels.32.Channels/Buffer_32.The_Buffer + ; +LOCATE UGROUP "EF_CB1" SITE "R81C44D" ; +UGROUP "EF_CT1" BBOX 21 39 + BLKNAME THE_TDC/ReferenceChannel/Channel200 + BLKNAME THE_TDC/ReferenceChannel/Buffer_32.The_Buffer + BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels.29.Channels/Buffer_32.The_Buffer + BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels.30.Channels/Buffer_32.The_Buffer ; -LOCATE UGROUP "EF_CB1" SITE "R64C47D" ; +LOCATE UGROUP "EF_CT1" SITE "R2C44D" ; ############################################################################# ## Stretcher ############################################################################# @@ -597,4 +602,4 @@ MULTICYCLE FROM CELL "THE_ENDPOINT/THE_ENDPOINT/genbuffers.0.geniobuf.gentrgapi. #MULTICYCLE FROM CELL "THE_TDC/calibration_on*" TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*" 3.000000 X ; #MULTICYCLE FROM CELL "THE_TDC/calibration_on*" TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/SimAdderNo.FC/FF*" 3.000000 X ; -#MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS ; +MAXDELAY NET "THE_TDC/hit_in_i*" 1.000000 nS ; diff --git a/releases/tdc_v2.3/dirich_trbnet_constraints.lpf b/releases/tdc_v2.3/dirich_trbnet_constraints.lpf index 82cb006..1d5dc0d 100644 --- a/releases/tdc_v2.3/dirich_trbnet_constraints.lpf +++ b/releases/tdc_v2.3/dirich_trbnet_constraints.lpf @@ -21,13 +21,13 @@ MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30.000000 -REGION "REGION_SPI" "R18C60D" 8 18 DEVSIZE; +REGION "REGION_SPI" "R21C60D" 8 18 DEVSIZE; LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "REGION_SPI"; LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI"; -REGION "REGION_TRBNET" "R2C47D" 85 33 DEVSIZE; +REGION "REGION_TRBNET" "R23C44D" 46 39 DEVSIZE; LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/MPLEX/MUX_group" REGION "REGION_TRBNET"; #LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.0.geniobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; diff --git a/releases/tdc_v2.3/tdc_components.vhd b/releases/tdc_v2.3/tdc_components.vhd index 8b0835b..9aabf2a 100644 --- a/releases/tdc_v2.3/tdc_components.vhd +++ b/releases/tdc_v2.3/tdc_components.vhd @@ -392,6 +392,16 @@ package tdc_components is Result : out std_logic_vector(303 downto 0)); end component; + component Adder_288 is + port ( + DataA : in std_logic_vector(287 downto 0); + DataB : in std_logic_vector(287 downto 0); + Clk : in std_logic; + Reset : in std_logic; + ClkEn : in std_logic; + Result : out std_logic_vector(287 downto 0)); + end component Adder_288; + component Encoder_304_Bit is port ( RESET : in std_logic;