From: hadaq <hadaq>
Date: Fri, 21 Jan 2011 23:23:53 +0000 (+0000)
Subject: new pexor firware, register definition has changed, do not use for older systems
X-Git-Tag: v6.0~167
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=28ba4c18ac70cf34b94fec9a4eaa1f91e4e8f247;p=trbnettools.git

new pexor firware, register definition has changed, do not use for older systems
---

diff --git a/libtrbnet/trbnet.c b/libtrbnet/trbnet.c
index f7a94d0..048ab00 100644
--- a/libtrbnet/trbnet.c
+++ b/libtrbnet/trbnet.c
@@ -1,4 +1,4 @@
-const char trbnet_version[] = "$Revision: 3.0 $";
+const char trbnet_version[] = "$Revision: 4.0 $";
 
 #include <stdlib.h>
 #include <signal.h>
@@ -65,11 +65,10 @@ static int pexorFileHandle  = -1;
 /* Channel Registers */
 
 /* Registers inside Virtex FPGA -> TRBnet endpoint (channel N) */
-#define CHANNEL_N_START_WRITE            0x0100
+#define CHANNEL_N_SENDER_CONTROL         0x0100
 #define CHANNEL_N_TARGET_ADDRESS         0x0101
 #define CHANNEL_N_SENDER_ERROR           0x0102
 #define CHANNEL_N_SENDER_DATA            0x0103
-#define CHANNEL_N_SENDER_FIFO_STATUS     0x0104
 #define CHANNEL_N_SENDER_STATUS          0x010f
 #define CHANNEL_N_RECEIVER_DATA          0x0203
 #define CHANNEL_N_RECEIVER_FIFO_STATUS   0x0204
@@ -80,7 +79,6 @@ static int pexorFileHandle  = -1;
 #define CHANNEL_0_TARGET_ADDRESS         0x0111
 #define CHANNEL_0_SENDER_ERROR           0x0112
 #define CHANNEL_0_SENDER_DATA            0x0113
-#define CHANNEL_0_SENDER_FIFO_STATUS     0x0114
 #define CHANNEL_0_SENDER_TRIGGER_INFO    0x0115
 #define CHANNEL_0_SENDER_STATUS          0x011f
 #define CHANNEL_0_RECEIVER_DATA          0x0213
@@ -92,7 +90,6 @@ static int pexorFileHandle  = -1;
 #define CHANNEL_1_TARGET_ADDRESS         0x0131
 #define CHANNEL_1_SENDER_ERROR           0x0132
 #define CHANNEL_1_SENDER_DATA            0x0133
-#define CHANNEL_1_SENDER_FIFO_STATUS     0x0134
 #define CHANNEL_1_SENDER_STATUS          0x013f
 #define CHANNEL_1_RECEIVER_DATA          0x0233
 #define CHANNEL_1_RECEIVER_FIFO_STATUS   0x0234
@@ -103,7 +100,6 @@ static int pexorFileHandle  = -1;
 #define CHANNEL_2_TARGET_ADDRESS         0x0151
 #define CHANNEL_2_SENDER_ERROR           0x0152
 #define CHANNEL_2_SENDER_DATA            0x0153
-#define CHANNEL_2_SENDER_FIFO_STATUS     0x0154
 #define CHANNEL_2_SENDER_STATUS          0x015f
 #define CHANNEL_2_RECEIVER_DATA          0x0253
 #define CHANNEL_2_RECEIVER_FIFO_STATUS   0x0254
@@ -114,7 +110,6 @@ static int pexorFileHandle  = -1;
 #define CHANNEL_3_TARGET_ADDRESS         0x0171
 #define CHANNEL_3_SENDER_ERROR           0x0172
 #define CHANNEL_3_SENDER_DATA            0x0173
-#define CHANNEL_3_SENDER_FIFO_STATUS     0x0174
 #define CHANNEL_3_SENDER_STATUS          0x017f
 #define CHANNEL_3_RECEIVER_DATA          0x0273
 #define CHANNEL_3_RECEIVER_FIFO_STATUS   0x0274
@@ -1351,13 +1346,20 @@ int trb_register_read(uint16_t trb_address,
   }
 
   /* Build package and start transfer */
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+#endif
   write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ);
+#else
+  write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
+                  (uint32_t)trb_address << 16 | CMD_REGISTER_READ);
+#endif
 
   /* DEBUG INFO */
   if (trb_debug > 0) {
@@ -1399,14 +1401,21 @@ int trb_registertime_read(uint16_t trb_address,
   }
 
   /* Build package and start transfer */
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+#endif
   write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ);
-
+#else
+  write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, 
+                  (uint32_t)trb_address << 16 | CMD_REGISTER_READ);
+#endif
+  
   /* DEBUG INFO */
   if (trb_debug > 0) {
     fprintf(stderr, "CMD_REGISTER_READ started.\n");
@@ -1460,14 +1469,21 @@ int trb_register_read_mem(uint16_t trb_address,
   }
 
   /* Build package and start transfer */
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+#endif
   write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, length);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ_MEM);
-
+#else
+  write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
+                  (uint32_t)trb_address << 16 | CMD_REGISTER_READ_MEM);
+#endif
+  
   /* DEBUG INFO */
   if (trb_debug > 0) {
     fprintf(stderr, "CMD_REGISTER_READ_MEM started.\n");
@@ -1531,13 +1547,20 @@ int trb_registertime_read_mem(uint16_t trb_address,
   }
 
   /* Build package and start transfer */
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+#endif
   write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, length);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ_MEM);
+#else
+  write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
+                  (uint32_t)trb_address << 16 | CMD_REGISTER_READ_MEM);
+#endif
 
   /* DEBUG INFO */
   if (trb_debug > 0) {
@@ -1588,13 +1611,20 @@ int trb_register_write(uint16_t trb_address,
   }
 
   /* Build package */
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+#endif
   write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, (value >> 16) & 0xffff);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, value & 0xffff);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE);
+#else
+  write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, 
+                  (uint32_t)trb_address << 16 | CMD_REGISTER_WRITE);
+#endif
 
   /* DEBUG INFO */
   if (trb_debug > 0) {
@@ -1646,7 +1676,9 @@ int trb_register_write_mem(uint16_t trb_address,
     }
     
     /* Build package */
+#ifndef PEXOR
     write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+#endif
     write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
     if (option == 0) {
       write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address + ctr);        
@@ -1662,7 +1694,12 @@ int trb_register_write_mem(uint16_t trb_address,
       write32_to_FPGA(CHANNEL_3_SENDER_DATA, data[ctr] & 0xffff);
       write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
     }
+#ifndef PEXOR
     write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE_MEM);
+#else
+    write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, 
+                    (uint32_t)trb_address << 16 | CMD_REGISTER_WRITE_MEM);
+#endif
     
     /* DEBUG INFO */
     if (trb_debug > 0) {
@@ -1699,13 +1736,20 @@ int trb_read_uid(uint16_t trb_address,
   }
 
   /* Build package and start transfer */
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+#endif
   write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, NET_READUNIQUEID);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_NETADMINISTRATION);
+#else
+  write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
+                  (uint32_t)trb_address << 16 | CMD_NETADMINISTRATION);
+#endif
 
   /* DEBUG INFO */
   if (trb_debug > 0) {
@@ -1753,7 +1797,9 @@ int trb_set_address(uint64_t uid,
   }
 
   /* Build package and start transfer */
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, 0xffff); /* always broadcast */
+#endif
   write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, NET_SETADDRESS);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, (uint16_t)(uid));
@@ -1763,8 +1809,12 @@ int trb_set_address(uint64_t uid,
   write32_to_FPGA(CHANNEL_3_SENDER_DATA,  endpoint);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA,  trb_address);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_NETADMINISTRATION);
-
+#else
+  write32_to_FPGA(CHANNEL_3_SENDER_CONTROL,
+                  (uint32_t)trb_address << 16 | CMD_NETADMINISTRATION);
+#endif
   /* DEBUG INFO */
   if (trb_debug > 0) {
     fprintf(stderr, "CMD_SETADDRESS started.\n");
@@ -1922,7 +1972,9 @@ int trb_send_trigger_rich(uint8_t trg_input,
   write32_to_FPGA(CHANNEL_0_SENDER_TRIGGER_INFO, (trg_info >> 8) & 0xffff);
   
   /* Prepare slowcontrol channel */
+#ifndef PEXOR
   write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, 0x0000fffb); /* RICH Subnet only */
+#endif
   write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x0020);
   write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000 | (0x01 << trg_input));