From: Jan Michel <j.michel@gsi.de>
Date: Fri, 11 Aug 2017 15:01:22 +0000 (+0200)
Subject: Update hubaddon design
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=28f7ff203afc0a926a356e404e3871d431970afd;p=trb3sc.git

Update hubaddon design
---

diff --git a/hubaddon/config.vhd b/hubaddon/config.vhd
index 1e9bd04..385ebc3 100644
--- a/hubaddon/config.vhd
+++ b/hubaddon/config.vhd
@@ -27,7 +27,7 @@ package config is
     constant INCLUDE_UART           : integer  := c_YES;
     constant INCLUDE_SPI            : integer  := c_YES;
     constant INCLUDE_LCD            : integer  := c_YES;
-    constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO;
+    constant INCLUDE_DEBUG_INTERFACE: integer  := c_YES;
 
     --input monitor and trigger generation logic
     constant INCLUDE_TRIGGER_LOGIC  : integer  := c_NO;
diff --git a/hubaddon/trb3sc_hubaddon.prj b/hubaddon/trb3sc_hubaddon.prj
index 9e224de..bea4539 100644
--- a/hubaddon/trb3sc_hubaddon.prj
+++ b/hubaddon/trb3sc_hubaddon.prj
@@ -68,6 +68,10 @@ add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
 add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd"
diff --git a/hubaddon/trb3sc_hubaddon.vhd b/hubaddon/trb3sc_hubaddon.vhd
index 4e65326..f6fc3f0 100644
--- a/hubaddon/trb3sc_hubaddon.vhd
+++ b/hubaddon/trb3sc_hubaddon.vhd
@@ -197,7 +197,8 @@ THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync
     IS_SYNC_SLAVE   => c_YES
     )
   port map(
-    CLK                => clk_full_osc,
+    CLK_REF_FULL       => clk_full_osc, --med2int(0).clk_full,
+    CLK_INTERNAL_FULL  => clk_full_osc,
     SYSCLK             => clk_sys,
     RESET              => reset_i,
     CLEAR              => clear_i,
@@ -234,8 +235,9 @@ THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_4
     IS_USED         => (c_YES,c_YES ,c_YES ,c_YES)
     )
   port map(
-    CLK                => clk_full_osc,
-    SYSCLK             => clk_sys,
+    CLK_REF_FULL       => clk_full_osc, --med2int(0).clk_full,
+    CLK_INTERNAL_FULL  => clk_full_osc,
+    SYSCLK        => clk_sys,
     RESET              => reset_i,
     CLEAR              => clear_i,
     
@@ -252,11 +254,11 @@ THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_4
     TX_DLM_WORD        => open,
     
     --SFP Connection
-    --SFP Connection
-    SD_RXD_P_IN        => SERDES_RX(5 downto 2),
-    SD_RXD_N_IN        => SERDES_RX(9 downto 6),
-    SD_TXD_P_OUT       => SERDES_TX(5 downto 2),
-    SD_TXD_N_OUT       => SERDES_TX(9 downto 6),
+--     --SFP Connection
+--     SD_RXD_P_IN        => SERDES_RX(5 downto 2),
+--     SD_RXD_N_IN        => SERDES_RX(9 downto 6),
+--     SD_TXD_P_OUT       => SERDES_TX(5 downto 2),
+--     SD_TXD_N_OUT       => SERDES_TX(9 downto 6),
     SD_PRSNT_N_IN(3 downto 2) => HUB_MOD0(2 downto 1),
     SD_PRSNT_N_IN(1 downto 0) => HUB_MOD0(4 downto 3),
     SD_LOS_IN(3 downto 2)     => HUB_LOS(2 downto 1),