From: Manuel Penschuck Date: Mon, 7 Oct 2013 14:35:02 +0000 (+0200) Subject: TX Gear added, however still buggy X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=29c11d8a60ebd628e5ed9a000f13ed73668712b5;p=trb3.git TX Gear added, however still buggy --- diff --git a/cbmnet/.kateconfig b/cbmnet/.kateconfig new file mode 100644 index 0000000..8224436 --- /dev/null +++ b/cbmnet/.kateconfig @@ -0,0 +1 @@ +kate: space-indent on; indent-width 3; tab-width 3; replace-tabs on; diff --git a/cbmnet/code/cbmnet_phy_ecp3.vhd b/cbmnet/code/cbmnet_phy_ecp3.vhd index 0ad5677..a105c0c 100644 --- a/cbmnet/code/cbmnet_phy_ecp3.vhd +++ b/cbmnet/code/cbmnet_phy_ecp3.vhd @@ -42,7 +42,7 @@ entity cbmnet_phy_ecp3 is SD_TXD_P_OUT : out std_logic := '0'; SD_TXD_N_OUT : out std_logic := '0'; - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place,entity '1' = no SFP mounted) SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable @@ -72,7 +72,8 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal clk_125_i : std_logic; -- in FEE mode, driven by recovered clock, in Master mode, driven by local clock signal rclk_250_i : std_logic; -- recovered word clock signal rclk_125_i : std_logic; -- rclk_250_i divided by two. aligned s.t. the rising edge corresponds to the lower received word - + signal clk_tx_full_i : std_logic; -- 250 MHz clock generated by the serdes's TX-PLL + signal rst_i : std_logic; -- High-active reset driven by external logic signal rst_n_i : std_logic; -- Low-active version of rst_i @@ -96,9 +97,11 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal rx_serdes_rst_i : std_logic; signal rx_pcs_rst_i : std_logic; + + -- data - signal tx_data_i : std_logic_vector(17 downto 0); -- data to send using SERDES - signal rx_data_i : std_logic_vector( 8 downto 0); -- received by SERDES + signal tx_data_to_serdes_i : std_logic_vector( 8 downto 0); -- received by SERDES + signal rx_data_from_serdes_i : std_logic_vector( 8 downto 0); -- received by SERDES -- status & control interface (and obtained info) signal sci_ch_i : std_logic_vector(3 downto 0); @@ -137,7 +140,16 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal gear_to_rm_rst_i : std_logic; -- gear keeps CBMNet ready manager reset until gear locked successfully signal gear_to_rm_n_rst_i : std_logic; -- inverted version of above - signal rx_data_buf_i : std_logic_vector(17 downto 0); -- 16(+2) bit word generated by gear + signal rx_data_from_gear_i : std_logic_vector(17 downto 0); -- 16(+2) bit word generated by gear + + signal rx_data_i : std_logic_vector(17 downto 0); -- in the front end this signal is identical to rx_data_from_gear_i + -- otherwise a clock domain crossing from rclk_125_i to clk_125_local is + -- necessary. this signal will no exhibit a deterministic latency !!!!!! + -- (however, this is no problem, as the clock master will no receive DLMs) + + signal tx_data_i : std_logic_vector(17 downto 0); -- 16(+2) bit word generated fed to gear + signal tx_gear_reset_i : std_logic; + -- CBMNet Ready Managers signal rm_rx_ready_i : std_logic; @@ -161,6 +173,10 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is -- Stats signal stat_reconnect_counter_i : unsigned(15 downto 0); -- counts the number of RX-serdes resets since last external reset + signal tx_data_debug_i : std_logic_vector(17 downto 0); + signal tx_data_debug_state_i : std_logic; + + begin clk_125_local <= CLK; CLK_RX_HALF_OUT <= rclk_125_i; @@ -196,13 +212,13 @@ begin rx_full_clk_ch0 => rclk_250_i, rx_half_clk_ch0 => open, -- recovered (and correctly aligned) 125 MHz clock is generated by gear - tx_full_clk_ch0 => open, + tx_full_clk_ch0 => clk_tx_full_i, tx_half_clk_ch0 => open, fpga_rxrefclk_ch0 => clk_125_local, + fpga_txrefclk => clk_125_i, -- RESETS - fpga_txrefclk => clk_125_i, rst_qd_c => rst_qd_i, serdes_rst_qd_c => serdes_rst_qd_i, -- always 0 tx_serdes_rst_c => tx_serdes_rst_i, -- always 0 @@ -214,16 +230,16 @@ begin rx_pwrup_ch0_c => '1', -- TX DATA PORT - txdata_ch0 => tx_data_i(15 downto 0), - tx_k_ch0 => tx_data_i(17 downto 16), + txdata_ch0 => tx_data_to_serdes_i(7 downto 0), + tx_k_ch0 => tx_data_to_serdes_i(8), - tx_force_disp_ch0 => "00", - tx_disp_sel_ch0 => "00", + tx_force_disp_ch0 => '0', + tx_disp_sel_ch0 => '0', tx_div2_mode_ch0_c => '0', -- RX DATA PORT - rxdata_ch0 => rx_data_i(7 downto 0), - rx_k_ch0 => rx_data_i(8), + rxdata_ch0 => rx_data_from_serdes_i(7 downto 0), + rx_k_ch0 => rx_data_from_serdes_i(8), rx_disp_err_ch0 => open, rx_cv_err_ch0 => rx_dec_error_i, @@ -247,7 +263,7 @@ begin SCI_RD => sci_read_i, SCI_WRN => sci_write_i ); - + tx_serdes_rst_i <= '0'; --no function serdes_rst_qd_i <= '0'; --included in rst_qd_i @@ -284,7 +300,6 @@ begin TX_PCS_RST_CH_C => tx_pcs_rst_i, STATE_OUT => tx_rst_fsm_state_i ); - --tx_data_i <= "01" & x"00" & CBMNET_READY_CHAR0; proc_rst_fsms_ready: process is begin wait until rising_edge(clk_125_local); @@ -299,20 +314,49 @@ begin end if; end process; - THE_GEAR: CBMNET_PHY_GEAR port map ( - -- SERDES PORT - CLK_250_IN => rclk_250_i, -- in std_logic; - PCS_READY_IN => rx_rst_fsm_ready_i, -- in std_logic; - SERDES_RESET_OUT=> gear_to_fsm_rst_i, -- out std_logic; - DATA_IN => rx_data_i, -- in std_logic_vector( 8 downto 0); - - -- RM PORT - RM_RESET_IN => rm_rx_to_gear_reset_i, -- in std_logic; - CLK_125_OUT => rclk_125_i, -- out std_logic; - RESET_OUT => gear_to_rm_rst_i, -- out std_logic; - DATA_OUT => rx_data_buf_i -- out std_logic_vector(17 downto 0) + THE_RX_GEAR: CBMNET_PHY_RX_GEAR port map ( + -- SERDES PORT + CLK_250_IN => rclk_250_i, -- in std_logic; + PCS_READY_IN => rx_rst_fsm_ready_i, -- in std_logic; + SERDES_RESET_OUT=> gear_to_fsm_rst_i, -- out std_logic; + DATA_IN => rx_data_from_serdes_i, -- in std_logic_vector( 8 downto 0); + + -- RM PORT + RM_RESET_IN => rm_rx_to_gear_reset_i, -- in std_logic; + CLK_125_OUT => rclk_125_i, -- out std_logic; + RESET_OUT => gear_to_rm_rst_i, -- out std_logic; + DATA_OUT => rx_data_from_gear_i -- out std_logic_vector(17 downto 0) ); + rx_data_i <= rx_data_from_gear_i when rising_edge(clk_125_local) or (IS_SYNC_SLAVE = c_YES); + + THE_TX_GEAR: CBMNET_PHY_TX_GEAR port map ( + CLK_250_IN => clk_tx_full_i, -- in std_logic; + CLK_125_IN => clk_125_i, -- in std_logic; + RESET_IN => tx_gear_reset_i, -- in std_logic; + + DATA_IN => tx_data_i, -- in std_logic_vector(17 downto 0) + + DATA_OUT => tx_data_to_serdes_i -- out std_logic_vector(8 downto 0); + ); + tx_gear_reset_i <= not tx_rst_fsm_ready_i; + + process is begin + wait until rising_edge(clk_tx_full_i); + + tx_data_debug_state_i <= not tx_data_debug_state_i; + + if tx_data_debug_state_i = '1' then + tx_data_debug_i(7 downto 0) <= tx_data_to_serdes_i(7 downto 0); + tx_data_debug_i(16) <= tx_data_to_serdes_i(8); + + else + tx_data_debug_i(15 downto 8) <= tx_data_to_serdes_i(7 downto 0); + tx_data_debug_i(17) <= tx_data_to_serdes_i(8); + + end if; + end process; + ------------------------------------------------- -- CBMNet Ready Modules ------------------------------------------------- @@ -323,7 +367,7 @@ begin res_n => gear_to_rm_n_rst_i, ready_MGT2RM => '1', - rxdata_in(17 downto 0) => rx_data_buf_i, + rxdata_in(17 downto 0) => rx_data_i, rxdata_in(19 downto 18) => "00", tx_ready => rm_tx_ready_i, tx_almost_ready => rm_tx_almost_ready_i, @@ -447,7 +491,7 @@ begin led_rx_i <= not gear_to_rm_rst_i; led_tx_i <= tx_rst_fsm_ready_i; - if (led_timer_i(20) = '1') or (rx_data_buf_i(17 downto 16) = "10" and rx_data_buf_i(15 downto 0) = x"fcce") then + if (led_timer_i(20) = '1') or (rx_data_i(17 downto 16) = "10" and rx_data_i(15 downto 0) = x"fcce") then led_rx_i <= '0'; end if; @@ -510,7 +554,7 @@ begin DEBUG_OUT(27 downto 24) <= gear_to_fsm_rst_i & barrel_shifter_misaligned_i & SD_PRSNT_N_IN & SD_LOS_IN; DEBUG_OUT(31 downto 28) <= rst_qd_i & rx_serdes_rst_i & tx_pcs_rst_i & rx_pcs_rst_i; - DEBUG_OUT(51 downto 32) <= "00" & rx_data_buf_i; + DEBUG_OUT(51 downto 32) <= "00" & rx_data_i; DEBUG_OUT(59 downto 52) <= rx_rst_fsm_state_i & tx_rst_fsm_state_i; DEBUG_OUT(63 downto 60) <= SERDES_ready & rm_rx_ready_i & rm_tx_ready_i & rm_tx_almost_ready_i; @@ -518,14 +562,14 @@ begin DEBUG_OUT(103 downto 100) <= wa_position_i(3 downto 0); DEBUG_OUT(107 downto 104) <= "00" & rm_rx_to_gear_reset_i & gear_to_rm_rst_i; - DEBUG_OUT(127 downto 112) <= STD_LOGIC_VECTOR(stat_reconnect_counter_i); + DEBUG_OUT(127 downto 108) <= "00" & tx_data_debug_i; --STD_LOGIC_VECTOR(stat_reconnect_counter_i); -- STAT_OP REGISTER - STAT_OP(8 downto 0) <= rx_data_i; + STAT_OP(8 downto 0) <= tx_data_to_serdes_i; STAT_OP(9) <= rclk_250_i; STAT_OP(10) <= clk_125_i; - STAT_OP(11) <= rx_cdr_lol_i; + STAT_OP(11) <= clk_tx_full_i; STAT_OP(12) <= rx_los_low_i; STAT_OP(13) <= lsm_status_i; STAT_OP(14) <= rx_serdes_rst_i; diff --git a/cbmnet/code/cbmnet_phy_pkg.vhd b/cbmnet/code/cbmnet_phy_pkg.vhd index 253083c..6201dc0 100644 --- a/cbmnet/code/cbmnet_phy_pkg.vhd +++ b/cbmnet/code/cbmnet_phy_pkg.vhd @@ -54,7 +54,7 @@ package cbmnet_phy_pkg is ----------------------------------------------------------------------------------------------------------------------- -- INTERNAL ----------------------------------------------------------------------------------------------------------------------- - component CBMNET_PHY_GEAR is + component CBMNET_PHY_RX_GEAR is port ( -- SERDES PORT CLK_250_IN : in std_logic; @@ -70,6 +70,17 @@ package cbmnet_phy_pkg is ); end component; + component CBMNET_PHY_TX_GEAR is + port ( + CLK_250_IN : in std_logic; + CLK_125_IN : in std_logic; + RESET_IN : in std_logic; + + DATA_IN : in std_logic_vector(17 downto 0); + + DATA_OUT : out std_logic_vector(8 downto 0) + ); + end component; COMPONENT cbmnet_sfp1 PORT( @@ -78,10 +89,10 @@ package cbmnet_phy_pkg is sci_sel_ch0 : IN std_logic; txiclk_ch0 : IN std_logic; fpga_rxrefclk_ch0 : IN std_logic; - txdata_ch0 : IN std_logic_vector(15 downto 0); - tx_k_ch0 : IN std_logic_vector(1 downto 0); - tx_force_disp_ch0 : IN std_logic_vector(1 downto 0); - tx_disp_sel_ch0 : IN std_logic_vector(1 downto 0); + txdata_ch0 : IN std_logic_vector(7 downto 0); + tx_k_ch0 : IN std_logic; + tx_force_disp_ch0 : IN std_logic; + tx_disp_sel_ch0 : IN std_logic; rx_serdes_rst_ch0_c : IN std_logic; sb_felb_ch0_c : IN std_logic; sb_felb_rst_ch0_c : IN std_logic; diff --git a/cbmnet/code/cbmnet_phy_gear.vhd b/cbmnet/code/cbmnet_phy_rx_gear.vhd similarity index 94% rename from cbmnet/code/cbmnet_phy_gear.vhd rename to cbmnet/code/cbmnet_phy_rx_gear.vhd index acc6e02..f8f16a0 100644 --- a/cbmnet/code/cbmnet_phy_gear.vhd +++ b/cbmnet/code/cbmnet_phy_rx_gear.vhd @@ -9,7 +9,7 @@ library work; use work.cbmnet_interface_pkg.all; use work.cbmnet_phy_pkg.all; -entity CBMNET_PHY_GEAR is +entity CBMNET_PHY_RX_GEAR is port ( -- SERDES PORT CLK_250_IN : in std_logic; @@ -25,10 +25,7 @@ entity CBMNET_PHY_GEAR is ); end entity; -architecture CBMNET_PHY_GEAR_ARCH of CBMNET_PHY_GEAR is - attribute HGROUP : string; - attribute HGROUP of CBMNET_PHY_GEAR_ARCH : architecture is "cbmnet_phy_gear"; - +architecture CBMNET_PHY_RX_GEAR_ARCH of CBMNET_PHY_RX_GEAR is type FSM_STATES_T is (FSM_START, FSM_WAIT_FOR_LOCK, FSM_RESET, FSM_DELAY, FSM_LOCKED); signal fsm_i, fsm_next_i : FSM_STATES_T; @@ -56,7 +53,7 @@ begin end process; - process(fsm_i, indi_alignment_i, indi_misalignment_i) is begin + process(fsm_i, timeout_i, indi_alignment_i, indi_misalignment_i, RM_RESET_IN) is begin fsm_next_i <= fsm_i; SERDES_RESET_OUT <= '0'; @@ -158,4 +155,4 @@ begin indi_misalignment_i <= '1' when data_out_buf_i(17 downto 16) = "10" and data_out_buf_i(7 downto 0) = x"00" and (data_out_buf_i(15 downto 8) = CBMNET_READY_CHAR0 or data_out_buf_i(15 downto 8) = CBMNET_READY_CHAR1 or data_out_buf_i(15 downto 8) = CBMNET_ALIGN_CHAR) else '0'; -end architecture CBMNET_PHY_GEAR_ARCH; \ No newline at end of file +end architecture CBMNET_PHY_RX_GEAR_ARCH; \ No newline at end of file diff --git a/cbmnet/code/cbmnet_phy_tx_gear.vhd b/cbmnet/code/cbmnet_phy_tx_gear.vhd new file mode 100644 index 0000000..def3e40 --- /dev/null +++ b/cbmnet/code/cbmnet_phy_tx_gear.vhd @@ -0,0 +1,71 @@ +LIBRARY IEEE; + USE IEEE.std_logic_1164.ALL; + USE IEEE.numeric_std.all; + +library work; + use work.trb_net_std.all; + use work.trb_net_components.all; + use work.med_sync_define.all; + use work.cbmnet_interface_pkg.all; + use work.cbmnet_phy_pkg.all; + +entity CBMNET_PHY_TX_GEAR is + port ( + -- SERDES PORT + CLK_250_IN : in std_logic; + CLK_125_IN : in std_logic; + RESET_IN : in std_logic; + + DATA_IN : in std_logic_vector(17 downto 0); + + DATA_OUT : out std_logic_vector(8 downto 0) + ); +end entity; + +architecture CBMNET_PHY_TX_GEAR_ARCH of CBMNET_PHY_TX_GEAR is + type FSM_STATES is (FSM_WAIT, FSM_HIGH, FSM_LOW); + signal fsm_i : FSM_STATES; + + signal data_in_buf125_i : std_logic_vector(17 downto 0); + signal low_data_i : std_logic_vector(8 downto 0); + + signal clk_125_xfer_i : std_logic := '0'; + signal clk_125_xfer_buf_i : std_logic := '0'; + signal clk_125_xfer_del_i : std_logic := '0'; + + +begin + process is begin + wait until rising_edge(CLK_250_IN); + + clk_125_xfer_buf_i <= clk_125_xfer_i; + clk_125_xfer_del_i <= clk_125_xfer_buf_i; + + case fsm_i is + when FSM_WAIT => + if clk_125_xfer_buf_i /= clk_125_xfer_del_i then + fsm_i <= FSM_HIGH; + end if; + + when FSM_HIGH => + DATA_OUT <= data_in_buf125_i(17) & data_in_buf125_i(15 downto 8); + low_data_i <= data_in_buf125_i(16) & data_in_buf125_i( 7 downto 0); + fsm_i <= FSM_LOW; + + when FSM_LOW => + DATA_OUT <= low_data_i; + fsm_i <= FSM_HIGH; + end case; + + if RESET_IN = '1' then + fsm_i <= FSM_WAIT; + end if; + end process; + + process is begin + wait until rising_edge(CLK_125_IN); + + data_in_buf125_i <= DATA_IN; + clk_125_xfer_i <= not clk_125_xfer_i; + end process; +end architecture CBMNET_PHY_TX_GEAR_ARCH; diff --git a/cbmnet/compile_periph_frankfurt.pl b/cbmnet/compile_periph_frankfurt.pl index 939fd0d..ec29757 100755 --- a/cbmnet/compile_periph_frankfurt.pl +++ b/cbmnet/compile_periph_frankfurt.pl @@ -31,7 +31,7 @@ if ($build_master and $build_slave) { system "xterm -e './compile_periph_frankfurt.pl s; read' &"; sleep 5; system "xterm -e './compile_periph_frankfurt.pl w; read' &"; - exit; + wait; } diff --git a/cbmnet/cores/cbmnet_sfp1.ipx b/cbmnet/cores/cbmnet_sfp1.ipx index e916173..ddf2037 100644 --- a/cbmnet/cores/cbmnet_sfp1.ipx +++ b/cbmnet/cores/cbmnet_sfp1.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/cbmnet/cores/cbmnet_sfp1.lpc b/cbmnet/cores/cbmnet_sfp1.lpc index 26fe511..e784386 100644 --- a/cbmnet/cores/cbmnet_sfp1.lpc +++ b/cbmnet/cores/cbmnet_sfp1.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=cbmnet_sfp1 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=10/02/2013 -Time=13:50:31 +Date=10/05/2013 +Time=12:37:58 [Parameters] Verilog=0 @@ -51,15 +51,15 @@ _tx_data_rate0=FULL _tx_data_rate1=FULL _tx_data_rate2=FULL _tx_data_rate3=FULL -_tx_data_width0=16 +_tx_data_width0=8 _tx_data_width1=8 _tx_data_width2=8 _tx_data_width3=8 -_tx_fifo0=ENABLED +_tx_fifo0=DISABLED _tx_fifo1=ENABLED _tx_fifo2=ENABLED _tx_fifo3=ENABLED -_tx_ficlk_rate0=125.0 +_tx_ficlk_rate0=250.0 _tx_ficlk_rate1=250.0 _tx_ficlk_rate2=250.0 _tx_ficlk_rate3=250.0 diff --git a/cbmnet/cores/cbmnet_sfp1.pp b/cbmnet/cores/cbmnet_sfp1.pp index 331b4db..fafb6ef 100644 --- a/cbmnet/cores/cbmnet_sfp1.pp +++ b/cbmnet/cores/cbmnet_sfp1.pp @@ -4,9 +4,9 @@ #define _ch0_protocol "G8B10B" #define _ch0_ldr "DISABLED" #define _ch0_tx_data_rate "FULL" -#define _ch0_tx_data_width "16" -#define _ch0_tx_fifo "ENABLED" -#define _ch0_tx_ficlk_rate 125.0 +#define _ch0_tx_data_width "8" +#define _ch0_tx_fifo "DISABLED" +#define _ch0_tx_ficlk_rate 250.0 #define _ch0_rx_datarange "MEDHIGH" #define _ch0_rx_data_rate "FULL" #define _ch0_rxrefclk_rate "125.0" @@ -185,7 +185,4 @@ #define _sci_int_port "DISABLED" #define _refck2core "DISABLED" #define _circuit_name cbmnet_sfp1 -#define _lang vhdl - -#include #include diff --git a/cbmnet/cores/cbmnet_sfp1.readme b/cbmnet/cores/cbmnet_sfp1.readme index 234f2ef..45d0fd7 100644 --- a/cbmnet/cores/cbmnet_sfp1.readme +++ b/cbmnet/cores/cbmnet_sfp1.readme @@ -65,10 +65,10 @@ attribute nopad of sci_sel_ch0 : IN std_logic; txiclk_ch0 : IN std_logic; fpga_rxrefclk_ch0 : IN std_logic; - txdata_ch0 : IN std_logic_vector(15 downto 0); - tx_k_ch0 : IN std_logic_vector(1 downto 0); - tx_force_disp_ch0 : IN std_logic_vector(1 downto 0); - tx_disp_sel_ch0 : IN std_logic_vector(1 downto 0); + txdata_ch0 : IN std_logic_vector(7 downto 0); + tx_k_ch0 : IN std_logic; + tx_force_disp_ch0 : IN std_logic; + tx_disp_sel_ch0 : IN std_logic; rx_serdes_rst_ch0_c : IN std_logic; sb_felb_ch0_c : IN std_logic; sb_felb_rst_ch0_c : IN std_logic; diff --git a/cbmnet/cores/cbmnet_sfp1.txt b/cbmnet/cores/cbmnet_sfp1.txt index c2333bb..68a1af7 100644 --- a/cbmnet/cores/cbmnet_sfp1.txt +++ b/cbmnet/cores/cbmnet_sfp1.txt @@ -17,12 +17,12 @@ REFCK_MULT "20X" #REFCLK_RATE 125.0 CH0_RX_DATA_RATE "FULL" CH0_TX_DATA_RATE "FULL" -CH0_TX_DATA_WIDTH "16" +CH0_TX_DATA_WIDTH "8" CH0_RX_DATA_WIDTH "8" CH0_TX_FIFO "ENABLED" CH0_RX_FIFO "DISABLED" CH0_TDRV "0" -#CH0_TX_FICLK_RATE 125.0 +#CH0_TX_FICLK_RATE 250.0 #CH0_RXREFCLK_RATE "125.0" #CH0_RX_FICLK_RATE 250.0 CH0_TX_PRE "DISABLED" diff --git a/cbmnet/cores/cbmnet_sfp1.vhd b/cbmnet/cores/cbmnet_sfp1.vhd index 7c936a7..3c2b4ed 100644 --- a/cbmnet/cores/cbmnet_sfp1.vhd +++ b/cbmnet/cores/cbmnet_sfp1.vhd @@ -1544,10 +1544,10 @@ entity cbmnet_sfp1 is tx_full_clk_ch0 : out std_logic; tx_half_clk_ch0 : out std_logic; fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); + txdata_ch0 : in std_logic_vector (7 downto 0); + tx_k_ch0 : in std_logic; + tx_force_disp_ch0 : in std_logic; + tx_disp_sel_ch0 : in std_logic; rxdata_ch0 : out std_logic_vector (7 downto 0); rx_k_ch0 : out std_logic; rx_disp_err_ch0 : out std_logic; @@ -2213,21 +2213,21 @@ port map ( FF_TX_D_0_5 => txdata_ch0(5), FF_TX_D_0_6 => txdata_ch0(6), FF_TX_D_0_7 => txdata_ch0(7), - FF_TX_D_0_8 => tx_k_ch0(0), - FF_TX_D_0_9 => tx_force_disp_ch0(0), - FF_TX_D_0_10 => tx_disp_sel_ch0(0), + FF_TX_D_0_8 => tx_k_ch0, + FF_TX_D_0_9 => tx_force_disp_ch0, + FF_TX_D_0_10 => tx_disp_sel_ch0, FF_TX_D_0_11 => fpsc_vlo, - FF_TX_D_0_12 => txdata_ch0(8), - FF_TX_D_0_13 => txdata_ch0(9), - FF_TX_D_0_14 => txdata_ch0(10), - FF_TX_D_0_15 => txdata_ch0(11), - FF_TX_D_0_16 => txdata_ch0(12), - FF_TX_D_0_17 => txdata_ch0(13), - FF_TX_D_0_18 => txdata_ch0(14), - FF_TX_D_0_19 => txdata_ch0(15), - FF_TX_D_0_20 => tx_k_ch0(1), - FF_TX_D_0_21 => tx_force_disp_ch0(1), - FF_TX_D_0_22 => tx_disp_sel_ch0(1), + FF_TX_D_0_12 => fpsc_vlo, + FF_TX_D_0_13 => fpsc_vlo, + FF_TX_D_0_14 => fpsc_vlo, + FF_TX_D_0_15 => fpsc_vlo, + FF_TX_D_0_16 => fpsc_vlo, + FF_TX_D_0_17 => fpsc_vlo, + FF_TX_D_0_18 => fpsc_vlo, + FF_TX_D_0_19 => fpsc_vlo, + FF_TX_D_0_20 => fpsc_vlo, + FF_TX_D_0_21 => fpsc_vlo, + FF_TX_D_0_22 => fpsc_vlo, FF_TX_D_0_23 => fpsc_vlo, FF_RX_D_0_0 => rxdata_ch0(0), FF_RX_D_0_1 => rxdata_ch0(1),