From: hadeshyp <hadeshyp>
Date: Fri, 23 Jul 2010 19:59:11 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~216
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2a0f3dbcc344c08558dd3fdf04899530756b095a;p=trbnet.git

*** empty log message ***
---

diff --git a/media_interfaces/trb_net16_med_ecp_fot.vhd b/media_interfaces/trb_net16_med_ecp_fot.vhd
index 2049747..78c88a9 100644
--- a/media_interfaces/trb_net16_med_ecp_fot.vhd
+++ b/media_interfaces/trb_net16_med_ecp_fot.vhd
@@ -644,7 +644,7 @@ begin
     STAT_OP(9 downto 0)   <= FSM_STAT_OP(9 downto 0);
     STAT_OP(10) <= rx_led;
     STAT_OP(11) <= tx_led;
-    STAT_OP(12) <= FSM_STAT_OP(12);
+    STAT_OP(12) <= link_error(1) and not send_reset_words_q and tx_allow;
     STAT_OP(13) <= make_trbnet_reset_q;
     STAT_OP(14) <= FSM_STAT_OP(14);
     STAT_OP(15) <= send_reset_words_q;
diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd
index efe22f2..1191b08 100644
--- a/trb_net16_endpoint_hades_full.vhd
+++ b/trb_net16_endpoint_hades_full.vhd
@@ -271,6 +271,10 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full
   signal reg_timing_trigger : std_logic;
   signal trigger_timing_rising : std_logic;
   signal last_reg_timing_trigger : std_logic;
+  signal timing_trigger_missing_stat : std_logic;
+
+  signal link_error_i            : std_logic;
+
 
   component edge_to_pulse is
     port (
@@ -775,8 +779,9 @@ begin
   proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, trigger_number_match, temperature, int_trigger_num)
     begin
       buf_COMMON_STAT_REG_IN               <= REGIO_COMMON_STAT_REG_IN;
---       buf_COMMON_STAT_REG_IN(4)            <= not trigger_number_match;
---       buf_COMMON_STAT_REG_IN(8)            <= timing_trigger_missing;
+      buf_COMMON_STAT_REG_IN(4)            <= not trigger_number_match;
+      buf_COMMON_STAT_REG_IN(8)            <= timing_trigger_missing_stat;
+      buf_COMMON_STAT_REG_IN(15)            <= link_error_i;
       if REGIO_USE_1WIRE_INTERFACE = c_YES then
         buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature;
       end if;
@@ -784,6 +789,23 @@ begin
       buf_COMMON_STAT_REG_IN(127 downto 64) <= stat_lvl1_handler;
     end process;
 
+
+
+  REG_LINK_ERROR : process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if buf_REGIO_COMMON_CTRL_REG_OUT(4) = '1' then
+          link_error_i <= '0';
+        elsif MED_STAT_OP_IN(15) = '0' and MED_STAT_OP_IN(13) = '0' and MED_STAT_OP_IN(7 downto 4) = "0111" then
+          link_error_i <= '1';
+        end if;
+
+        if LVL1_TRG_RECEIVED_OUT_falling = '1' then
+          timing_trigger_missing_stat <= timing_trigger_missing;
+        end if;
+      end if;
+    end process;
+
 -------------------------------------------------
 -- Check LVL1 trigger number
 -------------------------------------------------
@@ -881,7 +903,7 @@ begin
     begin
       if rising_edge(CLK) then
         last_reg_timing_trigger <= reg_timing_trigger;
-        trigger_timing_rising   <= reg_timing_trigger and not last_reg_timing_trigger;
+        trigger_timing_rising   <= reg_timing_trigger and not last_reg_timing_trigger and buf_REGIO_COMMON_CTRL_REG_OUT(95);
 
         last_LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT;
         LVL1_TRG_RECEIVED_OUT_rising <= buf_LVL1_TRG_RECEIVED_OUT and not last_LVL1_TRG_RECEIVED_OUT;
@@ -895,7 +917,7 @@ begin
           got_timing_trigger <= '1';
         elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') then
           got_timingless_trigger <= '1';
-        elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and not (buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1')) then
+        elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and not (buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') and got_timing_trigger = '0') then
           timing_trigger_missing <= '1';
         end if;
       end if;
@@ -928,6 +950,8 @@ begin
 --       end if;
 --     end process;
 
+
+
 -------------------------------------------------
 -- Connect Outputs
 -------------------------------------------------