From: Jan Michel Date: Fri, 2 Feb 2018 10:48:38 +0000 (+0100) Subject: Fix placement of logic in regions. Fix detection of length of reference time signal. X-Git-Tag: v2.3~20 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2a2a67ac4a7c3bc5c33e902b094bfdbc79bc9e50;p=tdc.git Fix placement of logic in regions. Fix detection of length of reference time signal. --- diff --git a/releases/tdc_v2.3/Channel_200.vhd b/releases/tdc_v2.3/Channel_200.vhd index db10ded..e502607 100644 --- a/releases/tdc_v2.3/Channel_200.vhd +++ b/releases/tdc_v2.3/Channel_200.vhd @@ -172,7 +172,7 @@ architecture Channel_200 of Channel_200 is attribute syn_keep of trg_win_end_tdc : signal is true; attribute syn_hier : string; - attribute syn_hier of Channel_200 : architecture is "firm"; + attribute syn_hier of Channel_200 : architecture is "fixed"; begin -- Channel_200 diff --git a/releases/tdc_v2.3/TriggerHandler.vhd b/releases/tdc_v2.3/TriggerHandler.vhd index 7ea901f..f0271f5 100644 --- a/releases/tdc_v2.3/TriggerHandler.vhd +++ b/releases/tdc_v2.3/TriggerHandler.vhd @@ -106,7 +106,7 @@ begin -- architecture behavioral -- accept trigger if it is longer than 100 ns if RESET_TDC = '1' then trg_pulse_tdc(i) <= '0'; - elsif trg_length(i) = to_unsigned(20, 5) then + elsif trg_length(i) = to_unsigned(15, 5) then trg_pulse_tdc(i) <= '1'; else trg_pulse_tdc(i) <= '0'; diff --git a/releases/tdc_v2.3/trb3_periph_ADA.vhd b/releases/tdc_v2.3/trb3_periph_ADA.vhd index 98442ba..6d03c53 100644 --- a/releases/tdc_v2.3/trb3_periph_ADA.vhd +++ b/releases/tdc_v2.3/trb3_periph_ADA.vhd @@ -229,8 +229,8 @@ begin -- SD_RXD_N_IN => SERDES_INT_RX(3), -- SD_TXD_P_OUT => SERDES_INT_TX(2), -- SD_TXD_N_OUT => SERDES_INT_TX(3), - SD_REFCLK_P_IN => open, - SD_REFCLK_N_IN => open, +-- SD_REFCLK_P_IN => open, +-- SD_REFCLK_N_IN => open, SD_PRSNT_N_IN => FPGA5_COMM(0), SD_LOS_IN => FPGA5_COMM(0), SD_TXDIS_OUT => FPGA5_COMM(2),