From: hadeshyp Date: Wed, 7 Jul 2010 11:56:20 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2a43554c6f1df6446b3d3959313763be187e641c;p=mdcoep.git *** empty log message *** --- diff --git a/compile_frankfurt.pl b/compile_frankfurt.pl index 223acc5..01b8e44 100755 --- a/compile_frankfurt.pl +++ b/compile_frankfurt.pl @@ -13,15 +13,15 @@ use warnings; use strict; my $lattice_path = '/d/sugar/lattice/ispLEVER8.0/isptools/'; -my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/'; - +#my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/'; +my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/'; #my $synplify_path = '/home/hadaq/bin/'; use FileHandle; $ENV{'SYNPLIFY'}="$synplify_path"; $ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; -$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de"; +$ENV{'LM_LICENSE_FILE'}="27000\@localhost"; my $TOPNAME="mdc_oepb"; @@ -61,9 +61,9 @@ $fh->close; system("env| grep LM_"); #$c=$synplify_path."synplify_pro -batch $TOPNAME".".prj"; #$c=$synplify_path."synplify_pro_oem -batch $TOPNAME".".prj"; -my $r=""; -my $c="$synplify_path/bin/synpwrap -Pro -prj $TOPNAME".".prj"; -$r=execute($c, "do_not_exit" ); +#my $c="$synplify_path/bin/synpwrap -Pro -prj $TOPNAME".".prj"; +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj"; +my $r=execute($c, "do_not_exit" ); chdir "workdir"; diff --git a/design2/data_handler.vhd b/design2/data_handler.vhd index 5f108fa..81b0a99 100644 --- a/design2/data_handler.vhd +++ b/design2/data_handler.vhd @@ -22,7 +22,7 @@ entity data_handler is SEND_DEBUG_INFORMATION_IN : in std_logic; --0: off, 1: on SELECT_DATA_FORMAT_IN : in std_logic; --0: compressed, 1: normal SEND_DUMMY_DATA_IN : in std_logic; --0: normal, 1: dummy - DUMMY_DATA_CONFIG : in std_logic_vector(15 downto 0); --11..0: number of debug words + DUMMY_DATA_CONFIG_IN : in std_logic_vector(15 downto 0); --11..0: number of debug words --Data Input from FEE DATA_BUS_IN : in std_logic_vector(23 downto 0); DATA_VALID_IN : in std_logic; @@ -56,6 +56,12 @@ architecture arch of data_handler is signal dummy_counter : unsigned(11 downto 0); + signal stored_hit_1 : std_logic; + signal stored_hit_0buf : std_logic; + signal stored_hit_1buf : std_logic; + + signal data_buffer : std_logic_vector(31 downto 0); + begin ------------------------------------------------------------------------------- @@ -68,6 +74,9 @@ begin current_state <= IDLE; data_write_i <= '0'; data_finished_i <= '0'; + stored_hit_1 <= '0'; + stored_hit_1buf <= '0'; + stored_hit_0buf <= '0'; else data_write_i <= '0'; data_finished_i <= '0'; @@ -75,6 +84,11 @@ begin case current_state is when IDLE => + stored_hit_1 <= '0'; + stored_hit_1buf <= '0'; + stored_hit_0buf <= '0'; + data_buffer <= (others => '0'); + data_i <= (others => '0'); if START_READOUT_IN = '1' then if SEND_DUMMY_DATA_IN = '1' then current_state <= SEND_DUMMY; @@ -96,22 +110,64 @@ begin current_state <= FINISH; end if; - when SEND_DATA => --NOT IMPLEMENTED - data_i(31 downto 29) <= "000"; - data_i(28 downto 22) <= DATA_BUS_IN(18 downto 12); - data_i(21) <= DATA_BUS_IN(11); - data_i(20 downto 11) <= (others => '0'); - data_i(10 downto 0) <= DATA_BUS_IN(10 downto 0); - data_write_i <= DATA_VALID_IN; + when SEND_DATA => + if stored_hit_1buf = '1' then --additional hit 1 stored + data_i <= data_buffer; + stored_hit_1buf <= '0'; + stored_hit_1 <= '1'; + elsif stored_hit_0buf = '1' then --additional hit 0 stored + data_i <= data_buffer; + stored_hit_0buf <= '0'; + data_write_i <= '1'; + elsif data_write_i = '1' then + if DATA_BUS_IN(11) = '1' and stored_hit_1 = '0' then -- hit 1, nothing stored + data_i(31 downto 29) <= "100"; + data_i(28 downto 22) <= DATA_BUS_IN(18 downto 12); + data_i(21 downto 11) <= DATA_BUS_IN(10 downto 0); + data_i(10 downto 0) <= (others => '0'); + stored_hit_1 <= '1'; + elsif DATA_BUS_IN(11) = '1' and stored_hit_1 = '1' then -- last channel had only hit 1 + data_buffer(31 downto 29) <= "100"; + data_buffer(28 downto 22) <= DATA_BUS_IN(18 downto 12); + data_buffer(21 downto 11) <= DATA_BUS_IN(10 downto 0); + data_buffer(10 downto 0) <= (others => '0'); + data_write_i <= '1'; + stored_hit_1buf <= '1'; + stored_hit_1 <= '0'; + elsif DATA_BUS_IN(11) = '0' and stored_hit_1 = '1' then -- hit 0, hit1 stored + if DATA_BUS_IN(18 downto 12) = data_i(28 downto 22) then + data_i(10 downto 0) <= DATA_BUS_IN(10 downto 0); + data_write_i <= '1'; + stored_hit_1 <= '0'; + else --hit 1 and hit 0 from different channels + data_i(10 downto 0) <= (others => '0'); + data_write_i <= '1'; + stored_hit_1 <= '0'; + data_buffer(31 downto 29) <= "100"; + data_buffer(28 downto 22) <= DATA_BUS_IN(18 downto 12); + data_buffer(21 downto 11) <= (others => '0'); + data_buffer(10 downto 0) <= DATA_BUS_IN(10 downto 0); + stored_hit_0buf <= '1'; + end if; + elsif DATA_BUS_IN(11) = '0' and stored_hit_1 = '0' then -- single / additional hit 0 + data_i(31 downto 29) <= "100"; + data_i(28 downto 22) <= DATA_BUS_IN(18 downto 12); + data_i(21 downto 11) <= (others => '0'); + data_i(10 downto 0) <= DATA_BUS_IN(10 downto 0); + data_write_i <= '1'; + stored_hit_1 <= '0'; + end if; + end if; + if FINISHED_READOUT_IN = '1' then current_state <= FINISH; end if; when SEND_DUMMY => - if dummy_counter < unsigned(DUMMY_DATA_CONFIG(11 downto 0)) then - data_i(31 downto 30) <= "01"; - data_i(29 downto 12) <= (others => '0'); - data_i(11 downto 0) <= dummy_counter; + if dummy_counter < unsigned(DUMMY_DATA_CONFIG_IN(11 downto 0)) then + data_i(31 downto 29) <= "010"; + data_i(28 downto 12) <= (others => '0'); + data_i(11 downto 0) <= std_logic_vector(dummy_counter); data_write_i <= '1'; dummy_counter <= dummy_counter + to_unsigned(1,1); else diff --git a/design2/mdc_control.vhd b/design2/mdc_control.vhd index 2512159..b68f159 100644 --- a/design2/mdc_control.vhd +++ b/design2/mdc_control.vhd @@ -82,7 +82,7 @@ architecture arch of mdc_control is signal add_in_i : std_logic_vector(8 downto 0); signal aod_in_i : std_logic; signal dst_in_i : std_logic; - + signal rsv_in_i : std_logic; signal trigger_i : std_logic; signal trigger_timing : std_logic; signal trigger_pseudo_timing : std_logic; @@ -92,7 +92,8 @@ architecture arch of mdc_control is signal trigger_begin_run : std_logic; signal trigger_reg_pulse_i : std_logic; - signal reset_readout_logic_i : std_logic; + signal reset_trigger_logic_i : std_logic; + signal reset_mbo_logic_i : std_logic; signal motherboard_type_i : std_logic_vector( 3 downto 0); signal data_format_i : std_logic; signal data_debug_i : std_logic; @@ -110,6 +111,7 @@ architecture arch of mdc_control is signal cal1_loaded_i : std_logic; signal token_missing_i : std_logic; signal token_back_i : std_logic; + signal token_missing_reg_i : std_logic; signal data_bus_i : std_logic_vector(23 downto 0); signal data_bus_valid_i : std_logic; @@ -168,7 +170,7 @@ begin PULSE_PSEUDO_TIMING : process(CLK) begin if rising_edge(CLK) then - if reset_readout_logic_i = '1' then + if reset_trigger_logic_i = '1' then trg_pulse_counter <= (others => '0'); trigger_pseudo_tmg_long <= '0'; elsif trg_pulse_counter = 0 then @@ -191,7 +193,7 @@ begin the_trigger_handler : trigger_handler port map( CLK => CLK, - RESET => reset_readout_logic_i, + RESET => reset_trigger_logic_i, TRG_BEGRUN_IN => trigger_begin_run, --LVL1 trigger LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN, @@ -227,7 +229,7 @@ begin the_data_handler : data_handler port map( CLK => CLK, - RESET => reset_readout_logic_i, + RESET => reset_trigger_logic_i, --LVL1 LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN, LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN, @@ -239,7 +241,7 @@ begin SELECT_DATA_FORMAT_IN => data_format_i, SEND_DEBUG_INFORMATION_IN => data_debug_i, SEND_DUMMY_DATA_IN => data_dummy_i, - DUMMY_DATA_CONFIG => dummy_data_config_i, + DUMMY_DATA_CONFIG_IN => dummy_data_config_i, --Data Input from FEE DATA_BUS_IN => data_bus_i, DATA_VALID_IN => data_bus_valid_i, @@ -257,12 +259,12 @@ begin the_tdc_readout : tdc_readout port map( CLK => CLK, - RESET => reset_readout_logic_i, + RESET => reset_trigger_logic_i, --MBO A_ADD_IN => add_in_i, A_AOD_IN => aod_in_i, A_DST_IN => dst_in_i, - A_RESERV_IN => A_RESERVE, + A_RESERV_IN => rsv_in_i, --Control START_READOUT_IN => start_readout_i, TOKEN_IN => A_RDO, @@ -281,7 +283,7 @@ begin the_control_line_hander : control_line_handle port map( CLK => CLK, - RESET => reset_readout_logic_i, + RESET => reset_mbo_logic_i, --MBO A_ADD => add_out_i, A_AOD => aod_out_i, @@ -403,7 +405,8 @@ process(CLK) PROC_REG_SETTINGS : process(CLK) begin if rising_edge(CLK) then - reset_readout_logic_i <= RESET or COMMON_CTRL_REG_IN(0); + reset_mbo_logic_i <= RESET or COMMON_CTRL_REG_IN(0); + reset_trigger_logic_i <= RESET or COMMON_CTRL_REG_IN(1); motherboard_type_i <= CTRL_REG_IN(7 downto 4); dummy_data_config_i <= CTRL_REG_IN(63 downto 48); trigger_pseudo_timing <= COMMON_CTRL_REG_IN(16); @@ -419,7 +422,6 @@ process(CLK) -- I/O ------------------------------------------------------------------------------- - databus_output_enable <= '1'; PROC_OUTPUT_SYNC : process(CLK) begin @@ -443,6 +445,7 @@ process(CLK) add_in_i <= A_ADD; aod_in_i <= A_AOD; dst_in_i <= A_DST; + rsv_in_i <= A_RESERVE; end if; end process; @@ -456,6 +459,16 @@ process(CLK) debug_control_i(31 downto 3) <= (others => '0'); DEBUG_OUT <= debug_control_i; - COMMON_STAT_REG_OUT <= (others => '0'); + + process(CLK) + begin + if rising_edge(CLK) then + token_missing_reg_i <= (token_missing_i or token_missing_reg_i) and not reset_mbo_logic_i; + + COMMON_STAT_REG_OUT <= (others => '0'); + COMMON_STAT_REG_OUT(6) <= not debug_ctrl_line_handle_i(8); + COMMON_STAT_REG_OUT(7) <= token_missing_reg_i; + end if; + end process; end architecture; \ No newline at end of file diff --git a/design2/mdc_oepb_pack.vhd b/design2/mdc_oepb_pack.vhd index 128c515..b5ffc63 100644 --- a/design2/mdc_oepb_pack.vhd +++ b/design2/mdc_oepb_pack.vhd @@ -73,7 +73,7 @@ package mdc_oepb_pack is SEND_DEBUG_INFORMATION_IN : in std_logic; --0: off, 1: on SELECT_DATA_FORMAT_IN : in std_logic; --0: compressed, 1: normal SEND_DUMMY_DATA_IN : in std_logic; --0: normal, 1: dummy - DUMMY_DATA_CONFIG : in std_logic_vector(15 downto 0); --11..0: number of debug words + DUMMY_DATA_CONFIG_IN : in std_logic_vector(15 downto 0); --11..0: number of debug words --Data Input from FEE DATA_BUS_IN : in std_logic_vector(23 downto 0); DATA_VALID_IN : in std_logic; diff --git a/design2/trigger_begrun_state.vhd b/design2/trigger_begrun_state.vhd index 93cf627..72a9fe9 100644 --- a/design2/trigger_begrun_state.vhd +++ b/design2/trigger_begrun_state.vhd @@ -222,7 +222,7 @@ begin -- Begrun Trigger ------------------------------------------------------------------------------- when load_data_mode_state => - next_output_enable <= '0'; + next_output_enable <= '1'; if start_load_tdc_settings_i = '1' then next_state <= load_tdc_data_state; next_do_tdc_begrun_i <= '1'; diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd index 586848d..f3c9e74 100644 --- a/mdc_oepb.vhd +++ b/mdc_oepb.vhd @@ -29,8 +29,6 @@ use work.version.all; -- 0xc0 0x0010 -> select short -- 0xc0 0x0020 -> select long -- 0xc1 0x0ABC0000 -> x"ABC" number of test data words --- 0xc1 0x10000000 -> x"1" external cms --- 0xc1 0x00000000 -> x"0" internal generated cms --------------------------------------------------------------------- ---------------------------------------------------------------------