From: Adrian Weber Date: Tue, 24 May 2022 10:46:04 +0000 (+0200) Subject: add a multiplicity trigger logic for the 32 input channels X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2aa48eb15491aa6d61281a2e0dfcef924cdf0afc;p=dirich.git add a multiplicity trigger logic for the 32 input channels --- diff --git a/dirich/code/stretched_OR_trigger.vhd b/dirich/code/stretched_OR_trigger.vhd new file mode 100644 index 0000000..897ff46 --- /dev/null +++ b/dirich/code/stretched_OR_trigger.vhd @@ -0,0 +1,56 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library work; + use work.trb_net_std.all; + +entity stretched_OR_trigger is +port( + CLK : in std_logic; + RESET : in std_logic; + + INPUT : in std_logic; + OUTPUT : out std_logic; + + STRETCH : in std_logic_vector(3 downto 0) := x"0" +); +end entity; + +architecture behaviour of stretched_OR_trigger is + signal or_long : std_logic := '0'; + signal active : std_logic := '1'; + signal cnt : unsigned (3 downto 0) := x"0"; + +begin + + or_long <= (or_long or INPUT) and active; + OUTPUT <= INPUT when STRETCH = x"0" else + or_long; + + THE_TRIGGER_CONTROL : process + begin + wait until rising_edge(CLK); + + if RESET = '1' then + active <= '1'; + cnt <= x"0"; + else + active <= '1'; + + if or_long = '1' then -- trigger is high + cnt <= cnt + 1; + end if; + + -- deactivate high signal of trigger after configured delay + -- 1 stretch bit = 10ns + -- stretch from 10 to 150ns + -- Stretch begins with first clock edge, but signal is async high. + -- So stretch of 10ns could be between 10.00ns to 19.99ns long, etc. + if std_logic_vector(cnt) >= STRETCH then + active <= '0'; + cnt <= x"0"; + end if; + end if; + end process; + +end architecture; diff --git a/dirich/code/stretched_OR_trigger_multi.vhd b/dirich/code/stretched_OR_trigger_multi.vhd new file mode 100644 index 0000000..63a52a3 --- /dev/null +++ b/dirich/code/stretched_OR_trigger_multi.vhd @@ -0,0 +1,115 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.std_logic_unsigned.all; +library work; + use work.trb_net_std.all; + +entity stretched_OR_trigger_multi is +port( + CLK : in std_logic; + RESET : in std_logic; + + INPUT : in std_logic_vector(31 downto 0); + OUTPUT : out std_logic; + OUTPUT_UNSTRCHD : out std_logic; + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX +); +end entity; + +architecture behaviour of stretched_OR_trigger_multi is + + signal stretched_input : std_logic_vector (31 downto 0) := x"00000000"; + signal multiplicity : std_logic_vector ( 4 downto 0) := "00000"; + signal sum_stretched_input : std_logic_vector (5 downto 0) := "000000"; + signal trigger_direct : std_logic := '0'; + signal trigger_stretch : std_logic := '0'; + + signal stretch : std_logic_vector(3 downto 0) := "0000"; + signal stretch_trigSign : std_logic_vector(3 downto 0) := "0000"; +begin + + + GEN_STRETCH : for i in 0 to 31 generate + THE_TRIGGER_Stretch : entity work.stretched_OR_trigger + port map ( + CLK => CLK, + RESET => RESET, + INPUT => INPUT(i), + OUTPUT => stretched_input(i), + STRETCH => stretch + ); + end generate GEN_STRETCH; + + + sum_stretched_input <= ("00000" & stretched_input( 0)) + ("00000" & stretched_input( 1)) + + ("00000" & stretched_input( 2)) + ("00000" & stretched_input( 3)) + + ("00000" & stretched_input( 4)) + ("00000" & stretched_input( 5)) + + ("00000" & stretched_input( 6)) + ("00000" & stretched_input( 7)) + + ("00000" & stretched_input( 8)) + ("00000" & stretched_input( 9)) + + ("00000" & stretched_input(10)) + ("00000" & stretched_input(11)) + + ("00000" & stretched_input(12)) + ("00000" & stretched_input(13)) + + ("00000" & stretched_input(14)) + ("00000" & stretched_input(15)) + + ("00000" & stretched_input(16)) + ("00000" & stretched_input(17)) + + ("00000" & stretched_input(18)) + ("00000" & stretched_input(19)) + + ("00000" & stretched_input(20)) + ("00000" & stretched_input(21)) + + ("00000" & stretched_input(22)) + ("00000" & stretched_input(23)) + + ("00000" & stretched_input(24)) + ("00000" & stretched_input(25)) + + ("00000" & stretched_input(26)) + ("00000" & stretched_input(27)) + + ("00000" & stretched_input(28)) + ("00000" & stretched_input(29)) + + ("00000" & stretched_input(30)) + ("00000" & stretched_input(31)); + + + trigger_direct <= '1' when multiplicity <= std_logic_vector(sum_stretched_input) else + '0'; + + + THE_TRIGGER_SIGNAL_Stretch : entity work.stretched_OR_trigger + port map ( + CLK => CLK, + RESET => RESET, + INPUT => trigger_direct, + OUTPUT => trigger_stretch, + STRETCH => stretch_trigSign + ); + + OUTPUT <= trigger_stretch; + OUTPUT_UNSTRCHD <= trigger_direct; + + proc_reg : process + begin + wait until rising_edge(CLK); + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.unknown <= '0'; + + if BUS_RX.write = '1' then + BUS_TX.ack <= '1'; + case BUS_RX.addr(0 downto 0) is + when "0" => + stretch <= BUS_RX.data(3 downto 0); + stretch_trigSign <= BUS_RX.data(7 downto 4); + multiplicity <= BUS_RX.data(20 downto 16); + + when others => + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + end case; + elsif BUS_RX.read = '1' then + BUS_TX.ack <= '1'; + case BUS_RX.addr(0 downto 0) is + when "0" => BUS_TX.data( 3 downto 0) <= stretch; + BUS_TX.data( 7 downto 4) <= stretch_trigSign; + BUS_TX.data(15 downto 8) <= (others => '0'); + BUS_TX.data(20 downto 16) <= multiplicity; + BUS_TX.data(31 downto 21) <= (others => '0'); + + when others => BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + end case; + end if; + end process; + +end architecture; diff --git a/dirich/config.vhd b/dirich/config.vhd index 9bee225..37e1887 100644 --- a/dirich/config.vhd +++ b/dirich/config.vhd @@ -53,8 +53,8 @@ package config is --input monitor and trigger generation logic constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2 constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 - constant TRIG_GEN_INPUT_NUM : integer := 32; - constant TRIG_GEN_OUTPUT_NUM : integer := 2; + constant TRIG_GEN_INPUT_NUM : integer := 1; + constant TRIG_GEN_OUTPUT_NUM : integer := 1; constant MONITOR_INPUT_NUM : integer := 32; --Retransmission diff --git a/dirich/config_compile_giessen.pl b/dirich/config_compile_giessen.pl index 2b62a22..ea020a7 100644 --- a/dirich/config_compile_giessen.pl +++ b/dirich/config_compile_giessen.pl @@ -11,7 +11,7 @@ lattice_path => '/usr/local/diamond/3.11_x64/', synplify_path => '/usr/local/diamond/3.11_x64/synpbase', synplify_command => "synpwrap -fg -options", -nodelist_file => '../nodelist_frankfurt.txt', +nodelist_file => '../nodelist_giessen.txt', pinout_file => 'dirich2', par_options => '../par.p2t', diff --git a/dirich/config_compile_gsi.pl b/dirich/config_compile_gsi.pl index 2125f1e..f15f1d1 100644 --- a/dirich/config_compile_gsi.pl +++ b/dirich/config_compile_gsi.pl @@ -11,7 +11,7 @@ synplify_path => '/opt/synplicity/K-2015.09', #synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", -nodelist_file => '../nodes_lxhadeb07.txt', +nodelist_file => '../nodelist_giessen.txt', pinout_file => 'dirich', par_options => '../par.p2t', diff --git a/dirich/dirich.prj b/dirich/dirich.prj index f4f4dfa..b1a2af7 100644 --- a/dirich/dirich.prj +++ b/dirich/dirich.prj @@ -216,6 +216,9 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_ #add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd" +## trigger Input signal_sync +add_file -vhdl -lib work "./code/stretched_OR_trigger.vhd" +add_file -vhdl -lib work "./code/stretched_OR_trigger_multi.vhd" add_file -vhdl -lib work "./dirich.vhd" #add_file -fpga_constraint "./synplify.fdc" diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd index 114eaf5..2f67518 100644 --- a/dirich/dirich.vhd +++ b/dirich/dirich.vhd @@ -83,8 +83,8 @@ architecture dirich_arch of dirich is signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 0); - signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX; - signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX; + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in , bus_sigTrigger_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, bus_sigTrigger_rx : CTRLBUS_RX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -111,6 +111,8 @@ architecture dirich_arch of dirich is attribute syn_preserve of GSR_N : signal is true; signal link_stat_in_reg : std_logic; + + signal signal_trigger_out, signal_trigger_unstretched : std_logic; component usrmclk @@ -174,7 +176,7 @@ THE_CAL_PLL : entity work.pll_in3125_out50 THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync generic map( SERDES_NUM => 0, - USE_RETRANSMISSION => USE_RETRANSMISSION, + --USE_RETRANSMISSION => USE_RETRANSMISSION, IS_SYNC_SLAVE => c_YES ) port map( @@ -264,9 +266,9 @@ THE_CAL_PLL : entity work.pll_in3125_out50 THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 5, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"c000", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, others => 0), + PORT_NUMBER => 6, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"c000", 5 => x"e000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, 5 => 1, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -281,11 +283,13 @@ THE_CAL_PLL : entity work.pll_in3125_out50 BUS_RX(2) => bustc_rx, --Clock switch BUS_RX(3) => busthresh_rx, BUS_RX(4) => bustdc_rx, + BUS_RX(5) => bus_sigTrigger_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, BUS_TX(2) => bustc_tx, BUS_TX(3) => busthresh_tx, BUS_TX(4) => bustdc_tx, + BUS_TX(5) => bus_sigTrigger_tx, STAT_DEBUG => open ); @@ -322,8 +326,8 @@ THE_CAL_PLL : entity work.pll_in3125_out50 ADC_CLK => ADC_SCLK, --Trigger & Monitor MONITOR_INPUTS => INPUT, - TRIG_GEN_INPUTS => INPUT, - TRIG_GEN_OUTPUTS => SIG(4 downto 3), + --TRIG_GEN_INPUTS => INPUT, + TRIG_GEN_OUTPUTS => open,--SIG(4 downto 3), --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol @@ -366,15 +370,35 @@ gen_DAC : if DIRICH_VERSION = 2 generate spi_miso(1 downto 0) <= MISO_IN; end generate; + +--------------------------------------------------------------------------- +-- Trigger +--------------------------------------------------------------------------- +THE_INPUT_TRIGGER : entity work.stretched_OR_trigger_multi +port map ( + CLK => clk_sys, + RESET => reset_i, + INPUT => INPUT(32 downto 1), + OUTPUT => signal_trigger_out, + OUTPUT_UNSTRCHD => signal_trigger_unstretched, + + BUS_RX => bus_sigTrigger_rx, + BUS_TX => bus_sigTrigger_tx +); + +SIG(3) <= signal_trigger_out; +SIG(4) <= signal_trigger_unstretched; --------------------------------------------------------------------------- -- I/O --------------------------------------------------------------------------- --Debug UART - hdr_io(8) <= TEST_LINE(1); + hdr_io(8) <= TEST_LINE(1); TEST_LINE(2) <= hdr_io(9); - + +--Debug_triggerSignalFromInput + --TEST_LINE(3) <= signal_trigger_out; -- TEST_LINE(8 downto 1) <= hdr_io(7 downto 0); -- TEST_LINE(14 downto 11) <= time_counter(31 downto 28); -- TEST_LINE(14 downto 1) <= med2int(0).stat_op(13) & clear_i & reset_i & debug_clock_reset(10 downto 6) & "00" & link_stat_out & link_stat_in_reg & debug_clock_reset(1 downto 0) ; diff --git a/dirich/nodelist_giessen.txt b/dirich/nodelist_giessen.txt new file mode 100644 index 0000000..371f726 --- /dev/null +++ b/dirich/nodelist_giessen.txt @@ -0,0 +1,7 @@ +// nodes file for parallel place&route + + +[fb07pc-u102325] +SYSTEM = linux +CORENUM = 12 +WORKDIR = /home/adrian/trbvhdl/dirich/dirich_trigger/workdir diff --git a/dirich/par.p2t b/dirich/par.p2t index 90aad2c..424d026 100644 --- a/dirich/par.p2t +++ b/dirich/par.p2t @@ -2,12 +2,14 @@ #-y -l 5 #-m nodelist.txt # Controlled by the compile.pl script. -#-n 1 # Controlled by the compile.pl script. +#-n 2 # Controlled by the compile.pl script. -s 10 --t 12 +-t 1 #12 #36 +#-t 85 -c 2 -e 2 -i 10 +# -t 20 was good #-exp parPlcInLimit=0 #-exp parPlcInNeighborSize=1 #General PAR Command Line Options