From: Adrian Weber Date: Mon, 27 Aug 2018 12:09:03 +0000 (+0200) Subject: clean up of Calibration -AW X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2b15e35858bbd9c6aa85d441ea55cf4da2dcef31;p=dirich.git clean up of Calibration -AW --- diff --git a/combiner_calib/code_EBR/Cal_Limits_v2.vhd b/combiner_calib/code_EBR/Cal_Limits_v2.vhd index 37fde06..fa13586 100644 --- a/combiner_calib/code_EBR/Cal_Limits_v2.vhd +++ b/combiner_calib/code_EBR/Cal_Limits_v2.vhd @@ -10,81 +10,66 @@ entity Cal_Limits_v2 is locBufDepth : integer := 7 ); port ( - CLK : in std_logic; - cal_Limit_reg : in unsigned(19 downto 0); - DIN : in std_logic_vector(31 downto 0); - DIN_ready : in std_logic; - DIN_type : in std_logic_vector( 3 downto 0); - min_curr_in : in std_logic_vector( 9 downto 0); - max_curr_in : in std_logic_vector( 9 downto 0); - min_next_in : in std_logic_vector( 9 downto 0); - max_next_in : in std_logic_vector( 9 downto 0); - FPGA : in std_logic_vector( 3 downto 0); - FPGA_next : in std_logic_vector( 3 downto 0); - chnl : in std_logic_vector( 6 downto 0); - chnl_next : in std_logic_vector( 6 downto 0); - Do_Cal_in : in std_logic; - chnl_cnt_in : in unsigned(19 downto 0); - write_curr : out std_logic; - write_next : out std_logic; - min_next : out std_logic_vector( 9 downto 0); - max_next : out std_logic_vector( 9 downto 0); - min_curr : out std_logic_vector( 9 downto 0); - max_curr : out std_logic_vector( 9 downto 0); - min_out : out std_logic_vector( 9 downto 0); - max_out : out std_logic_vector( 9 downto 0); - Delta : out std_logic_vector( 9 downto 0); - FPGA_out : out std_logic_vector( 3 downto 0); - chnl_out : out std_logic_vector( 6 downto 0); - FPGA_out_curr : out std_logic_vector( 3 downto 0); - chnl_out_curr : out std_logic_vector( 6 downto 0); - DOUT : out std_logic_vector(31 downto 0); - DOUT_ready : out std_logic; - DOUT_type : out std_logic_vector( 3 downto 0); - Do_Cal_out : out std_logic; - chnl_cnt_out : out unsigned (19 downto 0); --:="00000000000000000000"; - write_chnl_cnt : out std_logic; - chnl_out_write : out std_logic_vector( 6 downto 0); - FPGA_out_write : out std_logic_vector( 3 downto 0); - chnl_out_write_cnt : out std_logic_vector( 6 downto 0); - FPGA_out_write_cnt : out std_logic_vector( 3 downto 0); - cal_Limit_set : out unsigned (19 downto 0); - BUS_Flash_value : in std_logic_vector(27 downto 0); - Flash_flag : in std_logic; - Debug_Data_min : out std_logic_vector(31 downto 0); - Debug_Data_max : out std_logic_vector(31 downto 0) + CLK : in std_logic; + cal_Limit_reg : in unsigned(19 downto 0); + DIN : in std_logic_vector(31 downto 0); + DIN_ready : in std_logic; + DIN_type : in std_logic_vector( 3 downto 0); + min_curr_in : in std_logic_vector( 9 downto 0); + max_curr_in : in std_logic_vector( 9 downto 0); + min_next_in : in std_logic_vector( 9 downto 0); + max_next_in : in std_logic_vector( 9 downto 0); + FPGA : in std_logic_vector( 3 downto 0); + chnl : in std_logic_vector( 6 downto 0); + Do_Cal_in : in std_logic; + chnl_cnt_in : in unsigned(19 downto 0); + BUS_Flash_value : in std_logic_vector(27 downto 0); + Flash_flag : in std_logic; + write_curr : out std_logic; + write_next : out std_logic; + min_next : out std_logic_vector( 9 downto 0); + max_next : out std_logic_vector( 9 downto 0); + min_curr : out std_logic_vector( 9 downto 0); + max_curr : out std_logic_vector( 9 downto 0); + min_out : out std_logic_vector( 9 downto 0); + max_out : out std_logic_vector( 9 downto 0); + Delta : out std_logic_vector( 9 downto 0); + FPGA_out : out std_logic_vector( 3 downto 0); + chnl_out : out std_logic_vector( 6 downto 0); + FPGA_out_curr : out std_logic_vector( 3 downto 0); + chnl_out_curr : out std_logic_vector( 6 downto 0); + FPGA_out_write : out std_logic_vector( 3 downto 0); + chnl_out_write : out std_logic_vector( 6 downto 0); + FPGA_out_write_cnt : out std_logic_vector( 3 downto 0); + chnl_out_write_cnt : out std_logic_vector( 6 downto 0); + DOUT : out std_logic_vector(31 downto 0); + DOUT_ready : out std_logic; + DOUT_type : out std_logic_vector( 3 downto 0); + Do_Cal_out : out std_logic; + chnl_cnt_out : out unsigned (19 downto 0); --:="00000000000000000000"; + write_chnl_cnt : out std_logic; + cal_Limit_set : out unsigned (19 downto 0)--; +-- Debug_Data_min : out std_logic_vector(31 downto 0); +-- Debug_Data_max : out std_logic_vector(31 downto 0) ); end Cal_Limits_v2; architecture Behavioral of Cal_Limits_v2 is - signal FPGA_i : std_logic_vector( 3 downto 0); signal Delta_i : std_logic_vector( 9 downto 0) := "0110110100"; - signal min_curr_i : std_logic_vector( 9 downto 0); - signal max_curr_i : std_logic_vector( 9 downto 0); - signal min_next_i : std_logic_vector( 9 downto 0); - signal max_next_i : std_logic_vector( 9 downto 0); - signal min_curr_ii : std_logic_vector( 9 downto 0); - signal max_curr_ii : std_logic_vector( 9 downto 0); - signal min_next_ii : std_logic_vector( 9 downto 0); - signal max_next_ii : std_logic_vector( 9 downto 0); signal cnt_i : unsigned(19 downto 0):="00000000000000000000"; - signal cnt_ii : unsigned(19 downto 0):="00000000000000000000"; - signal chnl_i : std_logic_vector( 6 downto 0); - signal use_old : std_logic:='0'; signal cal_Limit : unsigned(19 downto 0):="00011000011010100000";--"00011000011010100000"; - + type array2D is array (1 downto 0, 0 to 64) of std_logic_vector(19 downto 0); --(FPGA)(channel) - signal def_value : array2D := (others => ("10000000010000000010","10000000100000000010","10000000110000000010","10000001000000000010", - "10000001010000000010","10000001100000000010","10000001110000000010","10000010000000000010", - "10000010010000000010","10000010100000000010","10000010110000000010","10000011000000000010", - "10000011010000000010","10000011100000000010", others => "11111000010000001111" )); + signal def_value : array2D := (others => ("10000000010000000010","10000000100000000010","10000000110000000010","10000001000000000010", + "10000001010000000010","10000001100000000010","10000001110000000010","10000010000000000010", + "10000010010000000010","10000010100000000010","10000010110000000010","10000011000000000010", + "10000011010000000010","10000011100000000010", others => "11111000010000001111" )); type bit_2D is array (16 downto 0, 63 downto 0) of std_logic; --(channel) - signal dflt_i : bit_2D := (others => (others => '1')); - - - type tLocalBuffer is array ( (locBufDepth-1) downto 0) of std_logic_vector(31 downto 0); --(Flag [31])(reserved [30] )(FPGA [29:26])(channel [25:20])(Max [19:10])(Min [9:0]) + signal dflt_i : bit_2D := (others => (others => '1')); + + type tLocalBuffer is array ( (locBufDepth-1) downto 0) of std_logic_vector(31 downto 0); --(Flag [31])(reserved [30] )(FPGA [29:26])(channel [25:20])(Max [19:10])(Min [9:0]) signal EBRcntr : tLocalBuffer := (others =>(others => '0')); signal EBRbufCurr : tLocalBuffer := (others =>(others => '0')); signal EBRbufNext : tLocalBuffer := (others =>(x"3FF00"&b"00" & b"11" & x"FF")); @@ -97,8 +82,8 @@ architecture Behavioral of Cal_Limits_v2 is signal min_next_in_r : std_logic_vector( 9 downto 0):= "1111111111"; signal max_next_in_r : std_logic_vector( 9 downto 0):= "0000000000"; signal FPGA_r : std_logic_vector( 3 downto 0):= "0000"; - signal chnl_r : std_logic_vector( 6 downto 0); - signal Do_Cal_in_r : std_logic; + signal chnl_r : std_logic_vector( 6 downto 0); + signal Do_Cal_in_r : std_logic; begin @@ -150,13 +135,9 @@ begin EBRcntr(locBufDepth-1) <= x"00000000"; end if; - --sync following processes with cnt_i + --sync following processes with cnt_i fpga_r <= FPGA; - --FPGA_i <= fpga_r; - chnl_r <= chnl; - --chnl_i <= chnl_r; - DIN_r <= DIN; DIN_ready_r <= DIN_ready; DIN_type_r <= DIN_type; @@ -227,8 +208,6 @@ begin else min_out <= EBRNext_Min_v; max_out <= EBRNext_Max_v; - min_curr_i <= EBRNext_Min_v; - max_curr_i <= EBRNext_Max_v; min_curr <= EBRNext_Min_v; max_curr <= EBRNext_Max_v; if (unsigned(EBRNext_Min_v) < unsigned(EBRNext_Max_v)) then @@ -257,8 +236,6 @@ begin max_out <= def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10); min_curr <= def_value(0,to_integer(unsigned(chnl_r)))( 9 downto 0); max_curr <= def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10); - min_curr_i <= def_value(0,to_integer(unsigned(chnl_r)))( 9 downto 0); - max_curr_i <= def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10); Delta_i <= std_logic_vector(unsigned(def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10)) - unsigned(def_value(0,to_integer(unsigned(chnl_r)))(9 downto 0))); EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10) & def_value(0,to_integer(unsigned(chnl_r)))( 9 downto 0); else @@ -267,8 +244,6 @@ begin --max_out <= b"0000000000"; min_curr <= b"0000000000"; max_curr <= b"0000000000"; - min_curr_i <= b"0000000000"; - max_curr_i <= b"0000000000"; Delta_i <= b"0000000000"; EBRbufCurr(locBufDepth-1) <= x"00000000"; end if; @@ -278,8 +253,6 @@ begin max_out <= "1000000000"; min_curr <= "0000000100"; max_curr <= "1000000000"; - min_curr_i <= "0000000100"; - max_curr_i <= "1000000000"; Delta_i <= "0111111011";--"0111111110"; if Do_Cal_in_r = '1' then EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & "1000000000" & "0000000100"; @@ -288,9 +261,6 @@ begin end if; end if;--default value - min_curr_ii <= min_curr_i; - max_curr_ii <= max_curr_i; - -------------------------------------------------------------- ----------------------------- NEXT ------------------------- @@ -300,15 +270,15 @@ begin if cnt_i /= to_unsigned(0,20) then --next memory if unsigned(DIN_r(21 downto 12)) >= unsigned(EBRNext_Max_v) then EBRNext_Max_v := DIN_r(21 downto 12); - Debug_Data_max <= DIN_r; + --Debug_Data_max <= DIN_r; if unsigned(DIN_r(21 downto 12)) < unsigned(EBRNext_Min_v) then EBRNext_Min_v := DIN_r(21 downto 12); - Debug_Data_min <= DIN_r; + --Debug_Data_min <= DIN_r; end if; else if unsigned(DIN_r(21 downto 12)) < unsigned(EBRNext_Min_v) then EBRNext_Min_v := DIN_r(21 downto 12); - Debug_Data_min <= DIN_r; + --Debug_Data_min <= DIN_r; end if; end if; else diff --git a/combiner_calib/code_EBR/Calc_output.vhd b/combiner_calib/code_EBR/Calc_output.vhd index ba627b6..7eef4cc 100644 --- a/combiner_calib/code_EBR/Calc_output.vhd +++ b/combiner_calib/code_EBR/Calc_output.vhd @@ -13,15 +13,13 @@ entity calc_output is undershoot_in : in std_logic := '0'; slope : in std_logic_vector(11 downto 0); factor : in std_logic_vector( 9 downto 0); - FPGA_in : in std_logic_vector( 3 downto 0); DOUT : out std_logic_vector(31 downto 0); DOUT_ready : out std_logic; DOUT_type : out std_logic_vector( 3 downto 0); do_cal_out : out std_logic; overshoot_out : out std_logic := '0'; undershoot_out : out std_logic := '0'; - Cal_Data_out : out std_logic_vector(21 downto 0); - FPGA_out : out std_logic_vector( 3 downto 0) + Cal_Data_out : out std_logic_vector(21 downto 0) ); end calc_output; @@ -38,7 +36,6 @@ begin do_cal_out <= do_cal_in; overshoot_out <= overshoot_in; undershoot_out <= undershoot_in; - FPGA_out <= FPGA_in; end if; end process; diff --git a/combiner_calib/code_EBR/Calibration.vhd b/combiner_calib/code_EBR/Calibration.vhd index 119a0ed..29e0da6 100644 --- a/combiner_calib/code_EBR/Calibration.vhd +++ b/combiner_calib/code_EBR/Calibration.vhd @@ -33,131 +33,81 @@ entity TDC_Calibration is end TDC_Calibration; architecture Behavioral of TDC_Calibration is - signal Dout_int : std_logic_vector(21 downto 0); - signal DIN_i_Mem : std_logic_vector(31 downto 0) := (others => '0'); - signal DIN_i_Mem_ready : std_logic; - signal DIN_i_Mem_type : std_logic_vector( 3 downto 0); - signal Default_val_Mem : std_logic; - signal DIN_o_Lim : std_logic_vector(31 downto 0) := (others => '0'); - signal DIN_o_Lim_ready : std_logic; - signal DIN_o_Lim_type : std_logic_vector( 3 downto 0); - signal min_out_Lim : std_logic_vector( 9 downto 0) := (others => '1'); - signal max_out_Lim : std_logic_vector( 9 downto 0) := (others => '0'); - signal Delta_Lim : std_logic_vector( 9 downto 0) := "0110110100"; - signal min_next_Lim : std_logic_vector( 9 downto 0) := (others => '1'); - signal max_next_Lim : std_logic_vector( 9 downto 0) := (others => '0'); - signal min_curr_Lim : std_logic_vector( 9 downto 0) := (others => '1'); - signal max_curr_Lim : std_logic_vector( 9 downto 0) := (others => '0'); - signal FPGA_Lim : std_logic_vector( 3 downto 0) ; - signal chnl_Lim : std_logic_vector( 6 downto 0) := (others => '0'); - signal do_cal_LIM : std_logic; - signal DIN_o_LUT : std_logic_vector(31 downto 0) := (others => '0'); - signal DIN_o_LUT_ready : std_logic; - signal DIN_o_LUT_type : std_logic_vector( 3 downto 0); - signal min_out_LUT : std_logic_vector( 9 downto 0) := (others => '0'); - signal max_out_LUT : std_logic_vector( 9 downto 0) := (others => '1'); - signal Delta_LUT : std_logic_vector( 9 downto 0) := (others => '0'); - signal slope_LUT : std_logic_vector(11 downto 0) := (others => '0'); - signal cal_flag_LUT : std_logic := '0'; - signal cal_flag_LUT_out : std_logic := '0'; - signal FPGA_LUT : std_logic_vector( 3 downto 0); - signal read_next : std_logic; - signal write_next : std_logic; - signal read_vld_next : std_logic; - signal write_vld_next : std_logic; - signal FPGA_next : std_logic_vector( 3 downto 0); - signal chnl_next : std_logic_vector( 6 downto 0); - signal min_next : std_logic_vector( 9 downto 0):= "1111111111"; - signal max_next : std_logic_vector( 9 downto 0); - signal min_in_next : std_logic_vector( 9 downto 0); - signal max_in_next : std_logic_vector( 9 downto 0); - signal read_curr : std_logic; - signal write_curr : std_logic; - signal FPGA_curr : std_logic_vector( 3 downto 0); - signal chnl_curr : std_logic_vector( 6 downto 0); - signal min_curr : std_logic_vector( 9 downto 0); - signal max_curr : std_logic_vector( 9 downto 0); - signal min_in_curr : std_logic_vector( 9 downto 0); - signal max_in_curr : std_logic_vector( 9 downto 0); - signal factor : std_logic_vector( 9 downto 0); - signal DIN_o_cnt : std_logic_vector(31 downto 0); - signal DIN_o_cnt_ready : std_logic; - signal DIN_o_cnt_type : std_logic_vector( 3 downto 0); - signal FPGA_o_cnt : std_logic_vector( 3 downto 0); - signal read_cal_cnt : std_logic; - signal read_dflt_cnt : std_logic; - signal chnl_read_cnt : std_logic_vector( 6 downto 0); - signal write_cal_cnt : std_logic; - signal write_dflt_cnt : std_logic; - signal dflt_cnt_in : std_logic; - signal dflt_cnt_out : std_logic; - signal cal_cnt_in : unsigned(19 downto 0); - signal cal_cnt_out : unsigned(19 downto 0); - signal FPGA_cnt_val : std_logic_vector( 3 downto 0); - signal chnl_cnt_val : std_logic_vector( 6 downto 0); - signal DIN_o_cnt_val : std_logic_vector(31 downto 0); - signal DIN_o_cnt_val_ready : std_logic; - signal DIN_o_cnt_val_type : std_logic_vector( 3 downto 0); - signal DIN_MemCurr_data : std_logic_vector(31 downto 0); - signal DIN_MemCurr_ready : std_logic; - signal DIN_MemCurr_type : std_logic_vector( 3 downto 0); - signal Do_Cal_read_cnt : std_logic; - signal Do_Cal_compare_old : std_logic; - signal DIN_out_data_compare_old : std_logic_vector(31 downto 0); - signal DIN_out_ready_compare_old : std_logic; - signal DIN_out_type_compare_old : std_logic_vector( 3 downto 0); - signal read_compare_old : std_logic; - signal CHNL_out_compare_old : std_logic_vector( 6 downto 0); - signal FPGA_out_compare_old : std_logic_vector( 3 downto 0); - signal CHNL_out_Memory : std_logic_vector( 6 downto 0); - signal FPGA_out_Memory : std_logic_vector( 3 downto 0); - signal Do_Cal_Memory : std_logic; - signal write_chnl_cnt : std_logic; - signal new_data_Memory : std_logic; - signal chnl_out_write : std_logic_vector( 6 downto 0); - signal FPGA_out_write : std_logic_vector( 3 downto 0); - signal BUS_do_Cal : std_logic := '1'; - signal overshoot_LUT : std_logic := '0'; - signal undershoot_LUT : std_logic := '0'; - signal Cal_Limit_reg : unsigned(19 downto 0) := "00011000011010100000"; - signal cal_Limit_set : unsigned(19 downto 0); - signal Do_cal_CalcOut : std_logic := '0'; - signal FPGA_CalcOut : std_logic_vector( 3 downto 0); - signal DIN_o_CalcOut : std_logic_vector(31 downto 0); - signal DIN_o_CalcOut_ready : std_logic; - signal DIN_o_CalcOut_type : std_logic_vector( 3 downto 0); - signal overshoot_CalcOut : std_logic := '0'; - signal undershoot_CalcOut : std_logic := '0'; - signal Bus_Chnl : std_logic_vector( 6 downto 0); - signal Bus_FPGA : std_logic_vector( 3 downto 0); - signal Bus_min : std_logic_vector( 9 downto 0); - signal Bus_max : std_logic_vector( 9 downto 0); - signal FPGA_out_curr : std_logic_vector( 3 downto 0); - signal chnl_out_curr : std_logic_vector( 6 downto 0); - signal BUS_Flash_value : std_logic_vector(27 downto 0); - signal Flash_flag : std_logic; + signal Dout_int : std_logic_vector(21 downto 0); + signal DIN_i_Mem : std_logic_vector(31 downto 0) := (others => '0'); + signal DIN_i_Mem_ready : std_logic; + signal DIN_i_Mem_type : std_logic_vector( 3 downto 0); + signal DIN_o_Lim : std_logic_vector(31 downto 0) := (others => '0'); + signal DIN_o_Lim_ready : std_logic; + signal DIN_o_Lim_type : std_logic_vector( 3 downto 0); + signal min_out_Lim : std_logic_vector( 9 downto 0) := (others => '1'); + signal max_out_Lim : std_logic_vector( 9 downto 0) := (others => '0'); + signal Delta_Lim : std_logic_vector( 9 downto 0) := "0110110100"; + signal min_next_Lim : std_logic_vector( 9 downto 0) := (others => '1'); + signal max_next_Lim : std_logic_vector( 9 downto 0) := (others => '0'); + signal min_curr_Lim : std_logic_vector( 9 downto 0) := (others => '1'); + signal max_curr_Lim : std_logic_vector( 9 downto 0) := (others => '0'); + signal FPGA_Lim : std_logic_vector( 3 downto 0) ; + signal chnl_Lim : std_logic_vector( 6 downto 0) := (others => '0'); + signal do_cal_LIM : std_logic; + signal DIN_o_LUT : std_logic_vector(31 downto 0) := (others => '0'); + signal DIN_o_LUT_ready : std_logic; + signal DIN_o_LUT_type : std_logic_vector( 3 downto 0); + signal min_out_LUT : std_logic_vector( 9 downto 0) := (others => '0'); + signal max_out_LUT : std_logic_vector( 9 downto 0) := (others => '1'); + signal slope_LUT : std_logic_vector(11 downto 0) := (others => '0'); + signal cal_flag_LUT_out : std_logic := '0'; + signal write_next : std_logic; + signal min_next : std_logic_vector( 9 downto 0):= "1111111111"; + signal max_next : std_logic_vector( 9 downto 0); + signal write_curr : std_logic; + signal min_curr : std_logic_vector( 9 downto 0); + signal max_curr : std_logic_vector( 9 downto 0); + signal factor : std_logic_vector( 9 downto 0); + signal DIN_o_cnt : std_logic_vector(31 downto 0); + signal DIN_o_cnt_ready : std_logic; + signal DIN_o_cnt_type : std_logic_vector( 3 downto 0); + signal FPGA_o_cnt : std_logic_vector( 3 downto 0); + signal chnl_read_cnt : std_logic_vector( 6 downto 0); + signal cal_cnt_in : unsigned(19 downto 0); + signal cal_cnt_out : unsigned(19 downto 0); + signal DIN_o_cnt_val : std_logic_vector(31 downto 0); + signal DIN_o_cnt_val_ready : std_logic; + signal DIN_o_cnt_val_type : std_logic_vector( 3 downto 0); + signal DIN_MemCurr_data : std_logic_vector(31 downto 0); + signal DIN_MemCurr_ready : std_logic; + signal DIN_MemCurr_type : std_logic_vector( 3 downto 0); + signal Do_Cal_read_cnt : std_logic; + signal CHNL_out_Memory : std_logic_vector( 6 downto 0); + signal FPGA_out_Memory : std_logic_vector( 3 downto 0); + signal Do_Cal_Memory : std_logic; + signal write_chnl_cnt : std_logic; + signal chnl_out_write : std_logic_vector( 6 downto 0); + signal FPGA_out_write : std_logic_vector( 3 downto 0); + signal BUS_do_Cal : std_logic := '1'; + signal overshoot_LUT : std_logic := '0'; + signal undershoot_LUT : std_logic := '0'; + signal Cal_Limit_reg : unsigned(19 downto 0) := "00011000011010100000"; + signal cal_Limit_set : unsigned(19 downto 0); + signal Do_cal_CalcOut : std_logic := '0'; + signal DIN_o_CalcOut : std_logic_vector(31 downto 0); + signal DIN_o_CalcOut_ready : std_logic; + signal DIN_o_CalcOut_type : std_logic_vector( 3 downto 0); + signal overshoot_CalcOut : std_logic := '0'; + signal undershoot_CalcOut : std_logic := '0'; + signal Bus_Chnl : std_logic_vector( 6 downto 0); + signal Bus_FPGA : std_logic_vector( 3 downto 0); + signal Bus_min : std_logic_vector( 9 downto 0); + signal Bus_max : std_logic_vector( 9 downto 0); + signal FPGA_out_curr : std_logic_vector( 3 downto 0); + signal chnl_out_curr : std_logic_vector( 6 downto 0); + signal BUS_Flash_value : std_logic_vector(27 downto 0); + signal Flash_flag : std_logic; + signal chnl_out_write_cnt : std_logic_vector( 6 downto 0); + signal FPGA_out_write_cnt : std_logic_vector( 3 downto 0); - signal DIN_MemCurr_data_r : std_logic_vector(31 downto 0); - signal DIN_MemCurr_ready_r : std_logic; - signal DIN_MemCurr_type_r : std_logic_vector( 3 downto 0); - --signal min_curr_r : std_logic_vector(); - --signal max_curr_r : std_logic_vector(); - signal min_next_r : std_logic_vector( 9 downto 0); - signal max_next_r : std_logic_vector( 9 downto 0); - signal FPGA_out_Memory_r : std_logic_vector( 3 downto 0); - signal FPGA_out_compare_old_r : std_logic_vector( 3 downto 0); - signal CHNL_out_Memory_r : std_logic_vector( 6 downto 0); - signal CHNL_out_compare_old_r : std_logic_vector( 6 downto 0); - signal Do_Cal_Memory_r : std_logic; - signal cal_cnt_out_r : unsigned(19 downto 0); - signal new_data_Memory_r : std_logic; - signal BUS_Flash_value_r : std_logic_vector(27 downto 0); - signal Flash_flag_r : std_logic; - signal chnl_out_write_cnt : std_logic_vector(6 downto 0); - signal FPGA_out_write_cnt : std_logic_vector(3 downto 0); - - signal docal_debug_out, docal_debug_in: unsigned(31 downto 0); - signal Debug_Data_min, Debug_Data_max : std_logic_vector(31 downto 0); + signal docal_debug_out, docal_debug_in : unsigned(31 downto 0); + signal Debug_Data_min, Debug_Data_max : std_logic_vector(31 downto 0); begin @@ -222,147 +172,104 @@ begin end process; - read_cntr : entity work.read_cnt port map( - CLK => CLK, - RESET => RESET, - chnl => chnl_read_cnt, - FPGA_out => FPGA_o_cnt, - FPGA_in => FPGA_in, - DIN => DIN_i_Mem, - DIN_ready => DIN_i_Mem_ready, - DIN_type => DIN_i_Mem_type, - DOUT => DIN_o_cnt, - DOUT_ready => DIN_o_cnt_ready, - DOUT_type => DIN_o_cnt_type, - Do_Cal => Do_Cal_read_cnt + CLK => CLK, + RESET => RESET, + chnl => chnl_read_cnt, + FPGA_out => FPGA_o_cnt, + FPGA_in => FPGA_in, + DIN => DIN_i_Mem, + DIN_ready => DIN_i_Mem_ready, + DIN_type => DIN_i_Mem_type, + DOUT => DIN_o_cnt, + DOUT_ready => DIN_o_cnt_ready, + DOUT_type => DIN_o_cnt_type, + Do_Cal => Do_Cal_read_cnt, + FPGA_cnt_mntr => open, + FPGA_mntr => open ); - ent_compare_old : entity work.compare_old - port map( - CLK => CLK, - DIN => DIN_o_cnt, - DIN_ready => DIN_o_cnt_ready, - DIN_type => DIN_o_cnt_type, - FPGA_in => FPGA_o_cnt, - CHNL_in => chnl_read_cnt, - Do_Cal_in => Do_Cal_read_cnt, - CHNL_out => CHNL_out_compare_old, - FPGA_out => FPGA_out_compare_old, - DOUT => DIN_out_data_compare_old, - DOUT_ready => DIN_out_ready_compare_old, - DOUT_type => DIN_out_type_compare_old, - Do_Cal_out => Do_Cal_compare_old, - read => read_compare_old - ); - ent_cnt_val : entity work.cnt_val port map( CLK => CLK, RESET => RESET, - read => read_compare_old, write => write_chnl_cnt, - FPGA_read => FPGA_out_compare_old, - chnl_read => CHNL_out_compare_old, + FPGA_read => FPGA_o_cnt, + chnl_read => chnl_read_cnt, FPGA_write => FPGA_out_write_cnt, chnl_write => chnl_out_write_cnt, cal_cnt => cal_cnt_in, cal_cnt_out => cal_cnt_out, - DIN => DIN_out_data_compare_old, - DIN_ready => DIN_out_ready_compare_old, - DIN_type => DIN_out_type_compare_old, + DIN => DIN_o_cnt, + DIN_ready => DIN_o_cnt_ready, + DIN_type => DIN_o_cnt_type, DOUT => DIN_o_cnt_val, DOUT_ready => DIN_o_cnt_val_ready, - DOUT_type => DIN_o_cnt_val_type, - FPGA_out => open, - CHNL_out => open + DOUT_type => DIN_o_cnt_val_type--, +-- FPGA_out => open, +-- CHNL_out => open ); - ent_dflt_val : entity work.dflt_val - port map( - CLK => CLK, - read => read_compare_old, - FPGA_read => FPGA_out_compare_old, - chnl_read => CHNL_out_compare_old, - dflt_out => Default_val_Mem - ); - +-- ent_dflt_val : entity work.dflt_val +-- port map( +-- CLK => CLK, +-- read => read_compare_old, +-- FPGA_read => FPGA_o_cnt, +-- chnl_read => chnl_read_cnt, +-- dflt_out => Default_val_Mem +-- ); +-- Mem_next : entity work.Memory port map( CLK => CLK, RESET => RESET, - read => read_compare_old, write => write_next, - FPGA_read => FPGA_out_compare_old, - chnl_read => CHNL_out_compare_old, + FPGA_read => FPGA_o_cnt, + chnl_read => chnl_read_cnt, FPGA_write => FPGA_out_write, chnl_write => chnl_out_write, min => min_next_Lim, max => max_next_Lim, min_out => min_next, max_out => max_next, - Do_Cal_in => Do_Cal_compare_old, - DIN => DIN_out_data_compare_old, - DIN_ready => DIN_out_ready_compare_old, - DIN_type => DIN_out_type_compare_old + DIN => DIN_o_cnt, + DIN_ready => DIN_o_cnt_ready, + DIN_type => DIN_o_cnt_type ); Mem_curr : entity work.Memory_curr port map( CLK => CLK, RESET => RESET, - read => read_compare_old, write => write_curr, - FPGA_read => FPGA_out_compare_old, - chnl_read => CHNL_out_compare_old, + FPGA_read => FPGA_o_cnt, + chnl_read => chnl_read_cnt, FPGA_write => FPGA_out_curr, chnl_write => chnl_out_curr, min => min_curr_Lim, max => max_curr_Lim, min_out => min_curr, max_out => max_curr, - Do_Cal_in => Do_Cal_compare_old, - DIN => DIN_out_data_compare_old, - DIN_ready => DIN_out_ready_compare_old, - DIN_type => DIN_out_type_compare_old, + Do_Cal_in => Do_Cal_read_cnt, + DIN => DIN_o_cnt, + DIN_ready => DIN_o_cnt_ready, + DIN_type => DIN_o_cnt_type, DOUT => DIN_MemCurr_data, DOUT_ready => DIN_MemCurr_ready, DOUT_type => DIN_MemCurr_type, FPGA_out => FPGA_out_Memory, CHNL_out => CHNL_out_Memory, - Do_Cal_out => Do_Cal_Memory, - new_data => new_data_Memory + Do_Cal_out => Do_Cal_Memory ); --- THE_delay_Cal_Limits_2 : process --- begin --- wait until rising_edge(CLK); --- DIN_MemCurr_data_r <= DIN_MemCurr_data; --- DIN_MemCurr_ready_r <= DIN_MemCurr_ready; --- DIN_MemCurr_type_r <= DIN_MemCurr_type; --- --min_curr_r <= min_curr; --- --max_curr_r <= max_curr; --- min_next_r <= min_next; --- max_next_r <= max_next; --- FPGA_out_Memory_r <= FPGA_out_Memory; --- FPGA_out_compare_old_r <= FPGA_out_compare_old; --- CHNL_out_Memory_r <= CHNL_out_Memory; --- CHNL_out_compare_old_r <= CHNL_out_compare_old; --- Do_Cal_Memory_r <= Do_Cal_Memory; --- cal_cnt_out_r <= cal_cnt_out; --- new_data_Memory_r <= new_data_Memory; --- BUS_Flash_value_r <= BUS_Flash_value; --- Flash_flag_r <= Flash_flag; --- end process; - Cal_Limits : entity work.Cal_Limits_v2 generic map( cal_Limit_gen => "00000010011100010000" -- 10k - ) + ) port map( CLK => CLK, cal_Limit_reg => Cal_Limit_reg, @@ -374,11 +281,11 @@ begin min_next_in => min_next, max_next_in => max_next, FPGA => FPGA_out_Memory, - FPGA_next => FPGA_out_compare_old, chnl => CHNL_out_Memory, - chnl_next => CHNL_out_compare_old, Do_Cal_in => Do_Cal_Memory, chnl_cnt_in => cal_cnt_out, + BUS_Flash_value => BUS_Flash_value, + Flash_flag => Flash_flag, write_curr => write_curr, write_next => write_next, min_next => min_next_Lim, @@ -390,25 +297,24 @@ begin Delta => Delta_Lim, FPGA_out => FPGA_Lim, chnl_out => chnl_Lim, + FPGA_out_curr => FPGA_out_curr, + chnl_out_curr => chnl_out_curr, + FPGA_out_write => FPGA_out_write, + chnl_out_write => chnl_out_write, + FPGA_out_write_cnt => FPGA_out_write_cnt, + chnl_out_write_cnt => chnl_out_write_cnt, DOUT => DIN_o_Lim, DOUT_ready => DIN_o_Lim_ready, DOUT_type => DIN_o_Lim_type, Do_Cal_out => do_cal_LIM, chnl_cnt_out => cal_cnt_in, write_chnl_cnt => write_chnl_cnt, - chnl_out_write => chnl_out_write, - FPGA_out_write => FPGA_out_write, - chnl_out_write_cnt => chnl_out_write_cnt, - FPGA_out_write_cnt => FPGA_out_write_cnt, - FPGA_out_curr => FPGA_out_curr, - chnl_out_curr => chnl_out_curr, - cal_Limit_set => cal_Limit_set, - BUS_Flash_value => BUS_Flash_value, - Flash_flag => Flash_flag, - Debug_Data_min => Debug_Data_min, - Debug_Data_max => Debug_Data_max + cal_Limit_set => cal_Limit_set--, + --Debug_Data_min => Debug_Data_min, + --Debug_Data_max => Debug_Data_max ); - + + LUTs : entity work.LUT port map( CLK => CLK, @@ -419,7 +325,6 @@ begin min_in => min_out_Lim, max_in => max_out_Lim, do_cal_in => do_cal_LIM, - FPGA_in => FPGA_Lim, min_out => min_out_LUT, max_out => max_out_LUT, DOUT => DIN_o_LUT, @@ -429,8 +334,7 @@ begin do_cal_out => cal_flag_LUT_out, factor => factor, overshoot => overshoot_LUT, - undershoot => undershoot_LUT, - FPGA_out => FPGA_LUT + undershoot => undershoot_LUT ); Calc_Output : entity work.calc_output @@ -444,15 +348,13 @@ begin undershoot_in => undershoot_LUT, slope => slope_LUT, factor => factor, - FPGA_in => FPGA_LUT, DOUT => DIN_o_CalcOut, DOUT_ready => DIN_o_CalcOut_ready, DOUT_type => DIN_o_CalcOut_type, do_cal_out => Do_cal_CalcOut, overshoot_out => overshoot_CalcOut, undershoot_out => undershoot_CalcOut, - Cal_Data_out => Dout_int, - FPGA_out => FPGA_CalcOut + Cal_Data_out => Dout_int ); THE_Enable : process diff --git a/combiner_calib/code_EBR/LUT.vhd b/combiner_calib/code_EBR/LUT.vhd index 3128a13..b32bbf0 100644 --- a/combiner_calib/code_EBR/LUT.vhd +++ b/combiner_calib/code_EBR/LUT.vhd @@ -14,7 +14,6 @@ entity LUT is min_in : in std_logic_vector( 9 downto 0); max_in : in std_logic_vector( 9 downto 0); do_cal_in : in std_logic; - FPGA_in : in std_logic_vector( 3 downto 0); min_out : out std_logic_vector( 9 downto 0); max_out : out std_logic_vector( 9 downto 0); DOUT : out std_logic_vector(31 downto 0); @@ -24,8 +23,7 @@ entity LUT is do_cal_out : out std_logic; factor : out std_logic_vector( 9 downto 0); overshoot : out std_logic := '0'; - undershoot : out std_logic := '0'; - FPGA_out : out std_logic_vector( 3 downto 0) + undershoot : out std_logic := '0' ); end entity; @@ -107,7 +105,6 @@ begin DOUT <= DIN; DOUT_ready <= DIN_ready; DOUT_type <= DIN_type; - FPGA_out <= FPGA_in; end if; end process; diff --git a/combiner_calib/code_EBR/Memory.vhd b/combiner_calib/code_EBR/Memory.vhd index 66a577a..93eedc5 100644 --- a/combiner_calib/code_EBR/Memory.vhd +++ b/combiner_calib/code_EBR/Memory.vhd @@ -6,7 +6,6 @@ entity Memory is Port ( CLK : in std_logic; RESET : in std_logic; - read : in std_logic; write : in std_logic; FPGA_read : in std_logic_vector( 3 downto 0); chnl_read : in std_logic_vector( 6 downto 0); @@ -14,7 +13,6 @@ entity Memory is chnl_write : in std_logic_vector( 6 downto 0); Min : in std_logic_vector( 9 downto 0); Max : in std_logic_vector( 9 downto 0); - Do_Cal_in : in std_logic; DIN : in std_logic_vector(31 downto 0); DIN_ready : in std_logic; DIN_type : in std_logic_vector( 3 downto 0); @@ -27,8 +25,6 @@ architecture Behavioral of Memory is signal Max_EBR_out : std_logic_vector(9 downto 0) := "0000000000"; signal Min_EBR_out : std_logic_vector(9 downto 0) := "1111111111"; signal Q_col, Q_col_r : std_logic_vector(20 downto 0) :='0' & x"003FF"; - signal chnl_r, chnl_2r : std_logic_vector( 6 downto 0); - signal fpga_r, fpga_2r : std_logic_vector( 3 downto 0); signal Q_i1 : std_logic_vector(5 downto 0); signal Q_i2 : std_logic_vector(9 downto 0); @@ -72,16 +68,6 @@ begin ); --- mem : process (CLK,read,write) --- begin --- if rising_edge(CLK) then --- if (Do_Cal_in = '1') then --- Max_out <= Max_EBR_out; --- Min_out <= Min_EBR_out; --- end if; --- end if; --- end process; - RW_handler : process (CLK) begin if rising_edge(CLK) then diff --git a/combiner_calib/code_EBR/Memory_curr.vhd b/combiner_calib/code_EBR/Memory_curr.vhd index 954f651..ba8c8fc 100644 --- a/combiner_calib/code_EBR/Memory_curr.vhd +++ b/combiner_calib/code_EBR/Memory_curr.vhd @@ -6,7 +6,6 @@ entity Memory_curr is port ( CLK : in std_logic; RESET : in std_logic; - read : in std_logic; write : in std_logic; FPGA_read : in std_logic_vector( 3 downto 0); chnl_read : in std_logic_vector( 6 downto 0); @@ -20,7 +19,6 @@ entity Memory_curr is DIN_type : in std_logic_vector( 3 downto 0); Min_out : out std_logic_vector( 9 downto 0):= "1111111111"; Max_out : out std_logic_vector( 9 downto 0):= "0000000000"; - new_data : out std_logic; DOUT : out std_logic_vector(31 downto 0); DOUT_ready : out std_logic; DOUT_type : out std_logic_vector( 3 downto 0); @@ -104,28 +102,28 @@ begin Min_out <= Min_EBR_out; Max_out <= Max_EBR_out; end if; - Q_col_r <= Q_col; + Q_col_r <= Q_col; -- Delay to sync with EBR output DIN_r <= DIN; DIN_2r <= DIN_r; DOUT <= DIN_2r; - - DIN_ready_r <= DIN_ready; - DIN_ready_2r <= DIN_ready_r; - DOUT_ready <= DIN_ready_2r; - - DIN_type_r <= DIN_type; - DIN_type_2r <= DIN_type_r; - DOUT_type <= DIN_type_2r; - - fpga_r <= FPGA_read; - fpga_2r <= fpga_r; - FPGA_out <= fpga_2r; - + + DIN_ready_r <= DIN_ready; + DIN_ready_2r <= DIN_ready_r; + DOUT_ready <= DIN_ready_2r; + + DIN_type_r <= DIN_type; + DIN_type_2r <= DIN_type_r; + DOUT_type <= DIN_type_2r; + + fpga_r <= FPGA_read; + fpga_2r <= fpga_r; + FPGA_out <= fpga_2r; + chnl_r <= chnl_read; chnl_2r <= chnl_r; CHNL_out <= chnl_2r; - + Do_Cal_in_r <= Do_Cal_in; Do_Cal_in_2r <= Do_Cal_in_r; Do_Cal_out <= Do_Cal_in_2r; diff --git a/combiner_calib/code_EBR/cnt_val.vhd b/combiner_calib/code_EBR/cnt_val.vhd index 7f461f2..cc239c2 100644 --- a/combiner_calib/code_EBR/cnt_val.vhd +++ b/combiner_calib/code_EBR/cnt_val.vhd @@ -6,7 +6,6 @@ entity cnt_val is Port ( CLK : in std_logic; RESET : in std_logic; - read : in std_logic; write : in std_logic; FPGA_read : in std_logic_vector( 3 downto 0); chnl_read : in std_logic_vector( 6 downto 0); @@ -19,9 +18,9 @@ entity cnt_val is cal_cnt_out : out unsigned(19 downto 0); DOUT : out std_logic_vector(31 downto 0); DOUT_ready : out std_logic; - DOUT_type : out std_logic_vector( 3 downto 0); - FPGA_out : out std_logic_vector( 3 downto 0); - CHNL_out : out std_logic_vector( 6 downto 0) + DOUT_type : out std_logic_vector( 3 downto 0)--; +-- FPGA_out : out std_logic_vector( 3 downto 0); +-- CHNL_out : out std_logic_vector( 6 downto 0) ); end cnt_val; @@ -29,8 +28,8 @@ architecture Behavioral of cnt_val is signal cal_cnt_i : std_logic_vector(19 downto 0) :=x"00000"; signal Q_col, Q_col_r : std_logic_vector(20 downto 0) :='0' & x"00000"; - signal chnl_r, chnl_2r : std_logic_vector( 6 downto 0); - signal fpga_r, fpga_2r : std_logic_vector( 3 downto 0); +-- signal chnl_r, chnl_2r : std_logic_vector( 6 downto 0); +-- signal fpga_r, fpga_2r : std_logic_vector( 3 downto 0); signal Q_i1 : std_logic_vector(15 downto 0); component RAM_pseudo_DP_wReg_36x1k is @@ -64,7 +63,7 @@ begin Reset => RESET, WrClock => CLK, WrClockEn => '1', - Q(35 downto 20) => Q_i1, + Q(35 downto 20) => Q_i1, --F**king modelsim wants it like this Q(19 downto 0) => cal_cnt_i ); @@ -91,12 +90,12 @@ begin DOUT <= DIN; DOUT_ready <= DIN_ready; DOUT_type <= DIN_type; - fpga_r <= FPGA_read; - fpga_2r <= fpga_r; - FPGA_out <= fpga_2r; - chnl_r <= chnl_read; - chnl_2r <= chnl_r; - CHNL_out <= chnl_2r; +-- fpga_r <= FPGA_read; +-- fpga_2r <= fpga_r; +-- FPGA_out <= fpga_2r; +-- chnl_r <= chnl_read; +-- chnl_2r <= chnl_r; +-- CHNL_out <= chnl_2r; end if; end process; end Behavioral; diff --git a/combiner_calib/code_EBR/read_cnt.vhd b/combiner_calib/code_EBR/read_cnt.vhd index edf911e..721bc23 100644 --- a/combiner_calib/code_EBR/read_cnt.vhd +++ b/combiner_calib/code_EBR/read_cnt.vhd @@ -17,22 +17,23 @@ entity read_cnt is DOUT : out std_logic_vector(31 downto 0); DOUT_ready : out std_logic; DOUT_type : out std_logic_vector( 3 downto 0); - Do_Cal : out std_logic + Do_Cal : out std_logic; + FPGA_cnt_mntr : out std_logic_vector( 3 downto 0); + FPGA_mntr : out std_logic_vector(15 downto 0) ); end read_cnt; architecture Behavioral of read_cnt is - type t_Fpga is array (0 to 11) of std_logic_vector(15 downto 0); - signal FPGA_num : t_Fpga; - signal cnt : integer range 0 to 11 := 0; - signal FPGA_i : integer range 0 to 11 := 0; - signal save : std_logic_vector(11 downto 0); + type t_Fpga is array (0 to 11) of std_logic_vector(15 downto 0); + signal FPGA_num : t_Fpga; + signal cnt : integer range 0 to 11 := 0; + signal FPGA_i : integer range 0 to 11 := 0; + signal save : std_logic_vector(11 downto 0); begin rd_cnt : process(CLK) - begin if rising_edge(CLK) then if (DIN(31) = '1') and (DIN_type = x"4") and (DIN_ready = '1') then @@ -54,96 +55,53 @@ begin end process; - -THE_FPGA_num : process(CLK) - -variable position : std_logic_vector(3 downto 0); -begin + THE_FPGA_num : process(CLK) + variable position : std_logic_vector(3 downto 0); + begin position := x"f"; if rising_edge(CLK) then if RESET = '1' then cnt <= 0; else - if DIN_ready = '1' then - C1 : case FPGA_in is - when x"156d" => FPGA_i <= 0; - when x"1691" => FPGA_i <= 1; - when x"13f9" => FPGA_i <= 2; - when x"12ee" => FPGA_i <= 3; - when x"12f8" => FPGA_i <= 4; - when x"1403" => FPGA_i <= 5; - when x"1663" => FPGA_i <= 6; - when others => FPGA_i <= 7; - end case C1; - end if; --- for i in 0 to 11 loop --- if FPGA_in = FPGA_num(i) then --- save(i) <= '1'; --- else --- save(i) <= '0'; --- end if; --- end loop; --- --- for i in 0 to 11 loop --- if save(i) = '1' then --- position := position and std_logic_vector(to_unsigned(i,4)); --- end if; --- end loop; --- --- if position = x"f" then --- FPGA_i <= cnt; --- FPGA_num(cnt) <= FPGA_in; --- cnt <= cnt + 1; --- else --- FPGA_i <= to_integer(unsigned(position)); --- end if; +-- if DIN_ready = '1' then +-- C1 : case FPGA_in is +-- when x"156d" => FPGA_i <= 0; +-- when x"1691" => FPGA_i <= 1; +-- when x"13f9" => FPGA_i <= 2; +-- when x"12ee" => FPGA_i <= 3; +-- when x"12f8" => FPGA_i <= 4; +-- when x"1403" => FPGA_i <= 5; +-- when x"1663" => FPGA_i <= 6; +-- when others => FPGA_i <= 7; +-- end case C1; +-- end if; + for i in 0 to 11 loop + if FPGA_in = FPGA_num(i) then + save(i) <= '1'; + else + save(i) <= '0'; + end if; + end loop; + + for i in 0 to 11 loop + if save(i) = '1' then + position := position and std_logic_vector(to_unsigned(i,4)); + end if; + end loop; + + if position = x"f" then + FPGA_i <= cnt; + FPGA_num(cnt) <= FPGA_in; + cnt <= cnt + 1; + else + FPGA_i <= to_integer(unsigned(position)); + end if; end if; end if; -end process; + end process; -end Behavioral; - --- architecture i of i is --- --- signal cnt : integer range 0 to 11 := 0; --- signal FPGA_i : integer range 0 to 11 := 0; --- signal save : std_logic_vector(11 downto 0); --- begin --- --- THE_FPGA_num : process(CLK) --- --- variable position : std_logic_vector(3 downto 0); --- --- begin --- position := x"f"; --- --- if rising_edge(CLK) then --- if RESET = '1' then --- cnt <= 0; --- else --- for i in 0 to 11 loop --- if FPGA_in = FPGA_num(i) then --- save(i) <= '1'; --- else --- save(i) <= '0'; --- end if; --- end loop; --- --- for i in 0 to 11 loop --- if save(i) = '1' then --- position := position and std_logic_vector(to_unsigned(i,4)); --- end if; --- end loop; --- --- if position = x"f" then --- FPGA_i <= cnt; --- FPGA_num(cnt) <= FPGA_in; --- cnt <= cnt + 1; --- else --- FPGA_i <= position; --- end if; --- end if; --- end if; --- end process; - + FPGA_mntr <= FPGA_num(cnt); + FPGA_cnt_mntr <= std_logic_vector(to_unsigned(cnt,4)); + +end Behavioral; \ No newline at end of file