From: Jan Michel Date: Fri, 11 Apr 2014 14:20:28 +0000 (+0200) Subject: Padiwa Usb slow-control running X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2ba7cc9ca263db2a52a9b5590490d8e6765142a6;p=padiwa.git Padiwa Usb slow-control running --- diff --git a/.gitignore b/.gitignore index 8d45df1..30702df 100644 --- a/.gitignore +++ b/.gitignore @@ -21,3 +21,4 @@ reportview.xml .kateproject.d */project/ */project2/ +design diff --git a/pulser/design/padiwa.ldf b/pulser/design/padiwa.ldf index 0621c38..d3880bd 100644 --- a/pulser/design/padiwa.ldf +++ b/pulser/design/padiwa.ldf @@ -2,9 +2,9 @@ - + - + @@ -33,7 +33,7 @@ - + diff --git a/pulser/padiwa_pulser.vhd b/pulser/padiwa_pulser.vhd index 4c4b8dd..5308020 100644 --- a/pulser/padiwa_pulser.vhd +++ b/pulser/padiwa_pulser.vhd @@ -52,6 +52,10 @@ signal bus_read : std_logic; signal bus_write : std_logic; signal bus_ready : std_logic; +signal register_1 : std_logic_vector(31 downto 0); +signal register_2 : std_logic_vector(15 downto 0); + + begin --------------------------------------------------------------------------- @@ -96,17 +100,36 @@ THE_UART : entity work.uart_sctrl ); -PROC_REGISTERS : process begin + +--------------------------------------------------------------------------- +-- Registers +--------------------------------------------------------------------------- +PROC_WRITE_REGISTERS : process begin wait until rising_edge(clk_osc); if bus_write= '1' then if uart_addr = x"01" then - lcd_data_i(31 downto 0) <= uart_rx_data; + register_1 <= uart_rx_data; + elsif uart_addr = x"02" then + register_2 <= uart_rx_data(15 downto 0); + end if; + end if; +end process; + + +PROC_READ_REGISTERS : process begin + wait until rising_edge(clk_osc); + bus_ready <= '0'; + if bus_read = '1' then + bus_ready <= '1'; + if uart_addr = x"01" then + uart_tx_data <= register_1; elsif uart_addr = x"02" then - lcd_data_i(79 downto 64) <= uart_rx_data(15 downto 0); + uart_tx_data <= x"0000" & register_2; end if; end if; end process; + --------------------------------------------------------------------------- -- LCD --------------------------------------------------------------------------- @@ -127,7 +150,13 @@ THE_LCD : entity work.lcd ); - + +lcd_data_i(31 downto 0) <= register_1; +lcd_data_i(63 downto 32) <= (others => '0'); +lcd_data_i(79 downto 64) <= register_2; +lcd_data_i(87 downto 80) <= uart_addr; +lcd_data_i(127 downto 96) <= uart_rx_data(31 downto 0); +lcd_data_i(255 downto 128) <= (others => '0'); diff --git a/pulser/padiwa_pulser_constraints.lpf b/pulser/padiwa_pulser_constraints.lpf new file mode 100644 index 0000000..e699a3f --- /dev/null +++ b/pulser/padiwa_pulser_constraints.lpf @@ -0,0 +1,2 @@ +FREQUENCY NET clk_i_c 133 MHz; + diff --git a/source/lcd.vhd b/source/lcd.vhd index 71f2c39..2ddd348 100644 --- a/source/lcd.vhd +++ b/source/lcd.vhd @@ -154,6 +154,11 @@ constant fontram : fontram_t := ( x"80", x"01", x"00", x"00", x"00", x"03", x"80", x"03", x"80", x"01", x"80", x"01", x"80", x"03", x"80", x"03", x"00", x"03", x"00", x"03", x"80", x"03", x"80", x"01", others => x"00"); + attribute syn_romstyle : string; + attribute syn_romstyle of fontram : constant is "block_rom"; + + + type initdc_t is array (0 to 15) of std_logic; constant initdc : initdc_t := ('0','1','0','1','0','0','1','1','1','1','0','1','1','1','1','0'); diff --git a/source/uart_sctrl.vhd b/source/uart_sctrl.vhd index 380b758..d4ef19b 100644 --- a/source/uart_sctrl.vhd +++ b/source/uart_sctrl.vhd @@ -39,7 +39,7 @@ signal rx_ready : std_logic; signal tx_send : std_logic; signal tx_ready : std_logic; -type rx_state_t is (IDLE,GET_ADDR,GET_BYTE0,GET_BYTE1,GET_BYTE2,GET_BYTE3,DO_WRITE,DO_READ,SEND_BYTE0,SEND_BYTE1,SEND_BYTE2); +type rx_state_t is (IDLE,GET_ADDR,GET_BYTE0,GET_BYTE1,GET_BYTE2,GET_BYTE3,DO_WRITE,DO_READ,SEND_BYTE0,SEND_BYTE1,SEND_BYTE2,SEND_BYTE3,SEND_TERM); signal state : rx_state_t; signal addr : std_logic_vector(7 downto 0) := (others => '0'); signal word : std_logic_vector(31 downto 0) := (others => '0'); @@ -77,10 +77,12 @@ PROC_RX : process begin READ_OUT <= '0'; WRITE_OUT <= '0'; tx_send <= '0'; + timer <= timer + 1; case state is when IDLE => cmd_rd <= '0'; cmd_wr <= '0'; + timer <= (others => '0'); if rx_ready = '1' then state <= GET_ADDR; if rx_data = x"52" then @@ -131,7 +133,13 @@ PROC_RX : process begin if READY_IN = '1' then word <= DATA_IN; tx_send <= '1'; - tx_data <= DATA_IN(31 downto 24); + tx_data <= x"52"; + state <= SEND_BYTE3; + end if; + when SEND_BYTE3=> + if tx_ready = '1' then + tx_send <= '1'; + tx_data <= word(31 downto 24); state <= SEND_BYTE2; end if; when SEND_BYTE2=> @@ -150,9 +158,15 @@ PROC_RX : process begin if tx_ready = '1' then tx_send <= '1'; tx_data <= word(7 downto 0); + state <= SEND_TERM; + end if; + when SEND_TERM=> + if tx_ready = '1' then + tx_send <= '1'; + tx_data <= x"0a"; state <= IDLE; end if; - + end case; if RESET = '1' or timeout = '1' then diff --git a/source/uart_trans.vhd b/source/uart_trans.vhd index 8b5afbb..c062f81 100644 --- a/source/uart_trans.vhd +++ b/source/uart_trans.vhd @@ -68,9 +68,10 @@ DEBUG(3) <= '0'; sync_output : process begin wait until rising_edge(CLK); TX <= symbol; - READY <= ready_sig; end process; + READY <= ready_sig and not SEND; + ---------------------------- -- Generate Serial Clock ----------------------------