From: Cahit <c.ugur@gsi.de>
Date: Tue, 15 Apr 2014 11:57:19 +0000 (+0200)
Subject: individual serdes placement for each project
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2be4e9bf8f2f236eda0de12b20e0943eaab40ff1;p=trb3.git

individual serdes placement for each project
---

diff --git a/base/cbmtof.lpf b/base/cbmtof.lpf
index ce8f9c7..106afc9 100644
--- a/base/cbmtof.lpf
+++ b/base/cbmtof.lpf
@@ -13,8 +13,13 @@ FREQUENCY PORT CLK_OSC 200 MHz;
 FREQUENCY PORT CLK_EXT 200 MHz;
 #FREQUENCY PORT CLK_CM_* 125 MHz;
 
-MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_OSC_c" 2 X ;
-#MULTICYCLE FROM CLKNET "CLK_OSC_c" TO CLKNET "clk_100_i_c" 1 X ;
+#MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_OSC_c" 2 X ;
+##MULTICYCLE FROM CLKNET "CLK_OSC_c" TO CLKNET "clk_100_i_c" 1 X ;
+
+MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_EXT" 2 X ;
+#MULTICYCLE FROM CLKNET "CLK_EXT" TO CLKNET "clk_100_i_c" 1 X ;
+
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc.THE_SERDES/PCSD_INST" SITE "PCSA" ;
 
 #################################################################
 # Clock I/O
diff --git a/base/trb3_periph_32PinAddOn.lpf b/base/trb3_periph_32PinAddOn.lpf
index 9a94475..0432b4e 100644
--- a/base/trb3_periph_32PinAddOn.lpf
+++ b/base/trb3_periph_32PinAddOn.lpf
@@ -17,6 +17,8 @@ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
 MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
 
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+
 #################################################################
 # Clock I/O
 #################################################################
diff --git a/base/trb3_periph_ADA.lpf b/base/trb3_periph_ADA.lpf
index caeaf6c..746468f 100644
--- a/base/trb3_periph_ADA.lpf
+++ b/base/trb3_periph_ADA.lpf
@@ -17,6 +17,8 @@ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
 MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
 
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+
 #################################################################
 # Clock I/O
 #################################################################
diff --git a/base/trb3_periph_gpin.lpf b/base/trb3_periph_gpin.lpf
index 96e89d1..5dc1beb 100644
--- a/base/trb3_periph_gpin.lpf
+++ b/base/trb3_periph_gpin.lpf
@@ -15,6 +15,8 @@ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
 MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
 
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+
 #################################################################
 # Clock I/O
 #################################################################
diff --git a/base/trb3_periph_padiwa.lpf b/base/trb3_periph_padiwa.lpf
index d6144d4..7979fab 100644
--- a/base/trb3_periph_padiwa.lpf
+++ b/base/trb3_periph_padiwa.lpf
@@ -15,6 +15,8 @@ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
 MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
 
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+
 #################################################################
 # Clock I/O
 #################################################################