From: hadeshyp Date: Mon, 12 Apr 2010 17:15:58 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~301 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2cb3813389985eabf0aaf436e2b99e53e95921f5;p=trbnet.git *** empty log message *** --- diff --git a/gbe_ecp2m/feeder.vhd b/gbe_ecp2m/feeder.vhd new file mode 100755 index 0000000..57fb2c2 --- /dev/null +++ b/gbe_ecp2m/feeder.vhd @@ -0,0 +1,620 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +use IEEE.std_logic_arith.all; + +library work; + +entity feeder is +port( CLK : in std_logic; + RESET : in std_logic; + -- IPU interface directed toward the CTS + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_READ_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data from Frontends + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_BUSY_IN : in std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + -- PacketConstructor interface + PC_WR_EN_OUT : out std_logic; + PC_DATA_OUT : out std_logic_vector (7 downto 0); + PC_READY_IN : in std_logic; + PC_SOS_OUT : out std_logic; + PC_EOD_OUT : out std_logic; + PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); + PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); + PC_PADDING_OUT : out std_logic; + -- Debug + BSM_SAVE_OUT : out std_logic_vector(3 downto 0); + BSM_LOAD_OUT : out std_logic_vector(3 downto 0); + DBG_REM_CTR_OUT : out std_logic_vector(3 downto 0); + DBG_CTS_CTR_OUT : out std_logic_vector(2 downto 0); + DBG_SF_WCNT_OUT : out std_logic_vector(15 downto 0); + DBG_SF_RCNT_OUT : out std_logic_vector(16 downto 0); + DBG_SF_DATA_OUT : out std_logic_vector(15 downto 0); + DBG_SF_RD_EN_OUT : out std_logic; + DBG_SF_WR_EN_OUT : out std_logic; + DBG_SF_EMPTY_OUT : out std_logic; + DBG_SF_FULL_OUT : out std_logic; + DBG_SF_AFULL_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end entity; + +architecture feeder of feeder is + +component fifo_32kx16x8_mb +port( Data : in std_logic_vector(15 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + AmFullThresh : in std_logic_vector(14 downto 0); + Q : out std_logic_vector(7 downto 0); + WCNT : out std_logic_vector(15 downto 0); + RCNT : out std_logic_vector(16 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); +end component; + +type saveStates is (SIDLE, WAIT_FOR_DATA, SAVE_DATA, TERMINATE, SCLOSE); +signal saveCurrentState, saveNextState : saveStates; +signal state : std_logic_vector(3 downto 0); +signal data_req_comb : std_logic; +signal data_req : std_logic; -- request data signal, will be used for fee_read generation +signal rst_saved_ctr_comb : std_logic; +signal rst_saved_ctr : std_logic; + +signal fee_read_comb : std_logic; +signal fee_read : std_logic; -- fee_read signal +signal saved_ctr : std_logic_vector(16 downto 0); +signal ce_saved_ctr : std_logic; + +-- header data +signal cts_rnd : std_logic_vector(15 downto 0); +signal cts_rnd_saved : std_logic; +signal cts_trg : std_logic_vector(15 downto 0); +signal cts_trg_saved : std_logic; +signal cts_len : std_logic_vector(16 downto 0); +signal cts_len_saved : std_logic; + +-- CTS interface +signal cts_error_pattern : std_logic_vector(31 downto 0); +signal cts_length : std_logic_vector(15 downto 0); +signal cts_readout_finished : std_logic; +signal cts_dataready : std_logic; +signal cts_data : std_logic_vector(31 downto 0); + +-- Split FIFO signals +signal sf_data : std_logic_vector(15 downto 0); +signal sf_wr_en_comb : std_logic; +signal sf_wr_en : std_logic; -- write signal for FIFO +signal sf_rd_en : std_logic; +signal sf_wcnt : std_logic_vector(15 downto 0); +signal sf_rcnt : std_logic_vector(16 downto 0); +signal sf_empty : std_logic; +signal sf_full : std_logic; +signal sf_afull : std_logic; + +------------------------------------------------------------------- +type loadStates is (LIDLE, INIT, REMOVE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, WAIT_PC, CLOSE); +signal loadCurrentState, loadNextState : loadStates; +signal state2 : std_logic_vector(3 downto 0); + +signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data +signal rst_rem_ctr_comb : std_logic; +signal rst_rem_ctr : std_logic; +signal rst_regs_comb : std_logic; +signal rst_regs : std_logic; +signal ce_rem_ctr_comb : std_logic; +signal ce_rem_ctr : std_logic; +signal remove_done_comb : std_logic; +signal remove_done : std_logic; -- end of header stripping process +signal load_done_comb : std_logic; +signal load_done : std_logic; -- end of data transfer into PC +signal calc_pad_comb : std_logic; +signal calc_pad : std_logic; -- add padding bytes, if needed +signal read_data_comb : std_logic; +signal read_data : std_logic; -- fetch data from split fifo +signal data_phase_comb : std_logic; +signal data_phase : std_logic; -- data transport phase from split fifo to PC +signal pc_sos_comb : std_logic; +signal pc_sos : std_logic; -- start of data signal +signal pc_eod_comb : std_logic; +signal pc_eod : std_logic; -- end of data signal +signal pad_data_comb : std_logic; +signal pad_data : std_logic; -- insert padding bytes + +signal pc_data : std_logic_vector(7 downto 0); +signal pc_data_q : std_logic_vector(7 downto 0); +signal pc_trig_nr : std_logic_vector(15 downto 0); +signal pc_sub_size : std_logic_vector(17 downto 0); +signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo +signal padding_needed : std_logic; +signal pc_wr_en_q : std_logic; +signal pc_wr_en_qq : std_logic; +signal pc_eod_q : std_logic; + +signal debug : std_logic_vector(31 downto 0); + +begin + +-- CTS interface signals +cts_error_pattern <= (others => '0'); -- FAKE +cts_dataready <= '1'; -- FAKE + +cts_length <= x"0000"; -- length of data payload is always 0 +cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1' + +cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0'; + + +-- Sync all critical pathes +THE_SYNC_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + sf_data <= FEE_DATA_IN; + sf_wr_en <= sf_wr_en_comb; + fee_read <= fee_read_comb; + load_done <= load_done_comb; + pc_eod_q <= pc_eod; + pc_wr_en_qq <= pc_wr_en_q; + pc_wr_en_q <= data_phase; + end if; +end process THE_SYNC_PROC; + +-- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY +fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) + else '0'; + +-- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY +sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) + else '0'; + +-- Counter for header word storage +THE_CTS_SAVED_CTR: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_saved_ctr = '1') ) then + saved_ctr <= (others => '0'); + elsif( ce_saved_ctr = '1' ) then + saved_ctr <= saved_ctr + 1; + end if; + end if; +end process THE_CTS_SAVED_CTR; + +ce_saved_ctr <= sf_wr_en; + +-- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO +saveMachineProc: process( CLK ) +begin + if rising_edge(CLK) then + if RESET = '1' then + saveCurrentState <= SIDLE; + data_req <= '0'; + rst_saved_ctr <= '0'; + else + saveCurrentState <= saveNextState; + data_req <= data_req_comb; + rst_saved_ctr <= rst_saved_ctr_comb; + end if; + end if; +end process saveMachineProc; + +saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN ) +begin + saveNextState <= SIDLE; + data_req_comb <= '0'; + rst_saved_ctr_comb <= '0'; + case saveCurrentState is + when SIDLE => + state <= x"0"; + if (CTS_START_READOUT_IN = '1') then + saveNextState <= WAIT_FOR_DATA; + data_req_comb <= '1'; + rst_saved_ctr_comb <= '1'; + else + saveNextState <= SIDLE; + end if; + when WAIT_FOR_DATA => + state <= x"1"; + if (FEE_BUSY_IN = '1') then + saveNextState <= SAVE_DATA; + data_req_comb <= '1'; + else + saveNextState <= WAIT_FOR_DATA; + data_req_comb <= '1'; + end if; + when SAVE_DATA => + state <= x"2"; + if (FEE_BUSY_IN = '0') then + saveNextState <= TERMINATE; + else + saveNextState <= SAVE_DATA; + data_req_comb <= '1'; + end if; + when TERMINATE => + state <= x"3"; + if (CTS_READ_IN = '1') then + saveNextState <= SCLOSE; + else + saveNextState <= TERMINATE; + end if; + when SCLOSE => + state <= x"4"; + if (CTS_START_READOUT_IN = '0') then + saveNextState <= SIDLE; + else + saveNextState <= SCLOSE; + end if; + when others => + state <= x"f"; + saveNextState <= SIDLE; + end case; +end process saveMachine; + +-- save triggerRnd from incoming data for cts response +CTS_RND_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_saved_ctr = '1') ) then + cts_rnd <= (others => '0'); + cts_rnd_saved <= '0'; + elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then + cts_rnd <= sf_data; + cts_rnd_saved <= '1'; + end if; + end if; +end process CTS_RND_PROC; + +-- save triggerNr from incoming data for cts response +CTS_TRG_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_saved_ctr = '1') ) then + cts_trg <= (others => '0'); + cts_trg_saved <= '0'; + elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then + cts_trg <= sf_data; + cts_trg_saved <= '1'; + end if; + end if; +end process CTS_TRG_PROC; + +-- save size from incoming data for cts response (future) and to get rid of padding +CTS_SIZE_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_saved_ctr = '1') ) then + cts_len <= (others => '0'); + cts_len_saved <= '0'; + elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then + cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words + elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then + cts_len <= cts_len + x"4"; + cts_len_saved <= '1'; + end if; + end if; +end process CTS_SIZE_PROC; + +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + +-- Split FIFO +THE_SPLIT_FIFO: fifo_32kx16x8_mb +port map( Data => sf_data, + WrClock => CLK, + RdClock => CLK, + WrEn => sf_wr_en, + RdEn => sf_rd_en, + Reset => RESET, + RPReset => RESET, + AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751 + Q => pc_data, --open, + WCNT => sf_wcnt, + RCNT => sf_rcnt, + Empty => sf_empty, + Full => sf_full, + AlmostFull => sf_afull + ); + +sf_rd_en <= read_data; +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + +-- FIFO data delay process (also forces padding bytes to known value) +THE_DATA_DELAY_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if( pad_data = '1' ) then + pc_data_q <= x"ee"; + else + pc_data_q <= pc_data; + end if; + end if; +end process THE_DATA_DELAY_PROC; + +-- Statemachine for reading the data payload from the SPLIT_FIFO and feeding +-- it into the packet constructor +loadMachineProc : process(CLK) +begin + if rising_edge(CLK) then + if RESET = '1' then + loadCurrentState <= LIDLE; + rst_regs <= '0'; + rst_rem_ctr <= '0'; + ce_rem_ctr <= '0'; + calc_pad <= '0'; + read_data <= '0'; + data_phase <= '0'; + pc_sos <= '0'; + pc_eod <= '0'; + pad_data <= '0'; + else + loadCurrentState <= loadNextState; + rst_regs <= rst_regs_comb; + rst_rem_ctr <= rst_rem_ctr_comb; + ce_rem_ctr <= ce_rem_ctr_comb; + calc_pad <= calc_pad_comb; + read_data <= read_data_comb; + data_phase <= data_phase_comb; + pc_sos <= pc_sos_comb; + pc_eod <= pc_eod_comb; + pad_data <= pad_data_comb; + end if; + end if; +end process loadMachineProc; + +loadMachine : process( loadCurrentState, sf_empty, remove_done, load_done, padding_needed, PC_READY_IN ) +begin + loadNextState <= LIDLE; + rst_regs_comb <= '0'; + rst_rem_ctr_comb <= '0'; + ce_rem_ctr_comb <= '0'; + calc_pad_comb <= '0'; + read_data_comb <= '0'; + data_phase_comb <= '0'; + pc_sos_comb <= '0'; + pc_eod_comb <= '0'; + pad_data_comb <= '0'; + case loadCurrentState is + when LIDLE => + state2 <= x"0"; + if( (sf_empty = '0') and (PC_READY_IN = '1') ) then + loadNextState <= INIT; + rst_regs_comb <= '1'; + rst_rem_ctr_comb <= '1'; + else + loadNextState <= LIDLE; + end if; + when INIT => + state2 <= x"1"; + loadNextState <= REMOVE; + ce_rem_ctr_comb <= '1'; + read_data_comb <= '1'; + when REMOVE => + state2 <= x"2"; + if( remove_done = '1' ) then + loadNextState <= CALCA; + calc_pad_comb <= '1'; + else + loadNextState <= REMOVE; + ce_rem_ctr_comb <= '1'; + read_data_comb <= '1'; + end if; + when CALCA => + state2 <= x"3"; + loadNextState <= CALCB; + when CALCB => + -- we need a branch in case of length "0"!!!! + state2 <= x"4"; + loadNextState <= LOAD; + read_data_comb <= '1'; + data_phase_comb <= '1'; + pc_sos_comb <= '1'; + when LOAD => + state2 <= x"5"; + if ( (load_done = '1') and (padding_needed = '0') ) then + loadNextState <= CLOSE; + elsif( (load_done = '1') and (padding_needed = '1') ) then + loadNextState <= PAD0; + data_phase_comb <= '1'; + else + loadNextState <= LOAD; + read_data_comb <= '1'; + data_phase_comb <= '1'; + end if; + when PAD0 => + state2 <= x"5"; + loadNextState <= PAD1; + data_phase_comb <= '1'; + pad_data_comb <= '1'; + when PAD1 => + state2 <= x"6"; + loadNextState <= PAD2; + data_phase_comb <= '1'; + pad_data_comb <= '1'; + when PAD2 => + state2 <= x"7"; + loadNextState <= PAD3; + data_phase_comb <= '1'; + pad_data_comb <= '1'; + when PAD3 => + state2 <= x"8"; + loadNextState <= CLOSE; + pad_data_comb <= '1'; + when CLOSE => + state2 <= x"9"; + loadNextState <= WAIT_PC; + pc_eod_comb <= '1'; + when WAIT_PC => + state2 <= x"a"; + if( PC_READY_IN = '1' ) then + loadNextState <= LIDLE; + rst_rem_ctr_comb <= '1'; + rst_regs_comb <= '1'; + else + loadNextState <= WAIT_PC; + end if; + when others => + state2 <= x"f"; + loadNextState <= LIDLE; + end case; +end process loadMachine; + +-- Counter for stripping the unneeded parts of the data stream, and saving the important parts +THE_REMOVE_CTR: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_rem_ctr = '1') ) then + rem_ctr <= (others => '0'); + elsif( ce_rem_ctr = '1' ) then + rem_ctr <= rem_ctr + 1; + end if; + end if; +end process THE_REMOVE_CTR; + +remove_done_comb <= '1' when ( rem_ctr = x"6" ) else '0'; + +THE_REM_DONE_SYNC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_rem_ctr = '1') ) then + remove_done <= '0'; + else + remove_done <= remove_done_comb; + end if; + end if; +end process THE_REM_DONE_SYNC; + +-- extract the trigger number from splitfifo data +THE_TRG_NR_PROC: process( CLK ) +begin + if rising_edge(CLK) then + if ( (RESET = '1') or (rst_regs = '1') ) then + pc_trig_nr <= (others => '0'); + elsif( (ce_rem_ctr = '1') and (rem_ctr = x"3") ) then + pc_trig_nr(7 downto 0) <= pc_data; + elsif( (ce_rem_ctr = '1') and (rem_ctr = x"4") ) then + pc_trig_nr(15 downto 8) <= pc_data; + end if; + end if; +end process THE_TRG_NR_PROC; + +-- check for padding +THE_PADDING_NEEDED_PROC: process( CLK ) +begin + if rising_edge(CLK) then + if ( (RESET = '1') or (rst_regs = '1') ) then + padding_needed <= '0'; + elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then + padding_needed <= '1'; + elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then + padding_needed <= '0'; + end if; + end if; +end process THE_PADDING_NEEDED_PROC; + +-- extract the subevent size from the splitfifo data, convert it from 32b to 8b units, +-- and in case of padding needed increase it accordingly +THE_SUB_SIZE_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_regs = '1') ) then + pc_sub_size <= (others => '0'); + elsif( (ce_rem_ctr = '1') and (rem_ctr = x"5") ) then + pc_sub_size(9 downto 2) <= pc_data; + elsif( (ce_rem_ctr = '1') and (rem_ctr = x"6") ) then + pc_sub_size(17 downto 10) <= pc_data; + elsif( (calc_pad = '1') and (padding_needed = '1') ) then + pc_sub_size <= pc_sub_size + 4; + end if; + end if; +end process THE_SUB_SIZE_PROC; + +-- number of bytes to read from split fifo +THE_READ_SIZE_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_rem_ctr = '1') ) then + read_size <= (others => '0'); + elsif( (ce_rem_ctr = '1') and (rem_ctr = x"5") ) then + read_size(9 downto 2) <= pc_data; + elsif( (ce_rem_ctr = '1') and (rem_ctr = x"6") ) then + read_size(17 downto 10) <= pc_data; + elsif( ((calc_pad = '1') and (load_done = '0')) ) then + read_size <= read_size - 2; + elsif( ((read_data = '1') and (data_phase = '1')) ) then + read_size <= read_size - 1; + end if; + end if; +end process THE_READ_SIZE_PROC; + +load_done_comb <= '1' when (read_size = 0) else '0'; + +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + +-- Debug signals +debug(31) <= remove_done; +debug(30) <= load_done; +debug(29) <= ce_rem_ctr; +debug(28) <= rst_rem_ctr; +debug(27) <= rst_regs; +debug(26) <= data_phase; +debug(25) <= read_data; +debug(24) <= pad_data; +debug(23 downto 18) <= (others => '0'); +debug(17 downto 0) <= read_size; + +-- Outputs +FEE_READ_OUT <= fee_read; +CTS_ERROR_PATTERN_OUT <= cts_error_pattern; +CTS_DATA_OUT <= cts_data; +CTS_DATAREADY_OUT <= cts_dataready; +CTS_READOUT_FINISHED_OUT <= cts_readout_finished; +CTS_LENGTH_OUT <= cts_length; + +PC_SOS_OUT <= pc_sos; +PC_EOD_OUT <= pc_eod_q; +PC_DATA_OUT <= pc_data_q; +PC_WR_EN_OUT <= pc_wr_en_qq; +PC_TRIG_NR_OUT <= x"0000" & pc_trig_nr; +PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size; +PC_PADDING_OUT <= padding_needed; + +BSM_SAVE_OUT <= state; +BSM_LOAD_OUT <= state2; +DBG_CTS_CTR_OUT <= saved_ctr(2 downto 0); +DBG_REM_CTR_OUT <= rem_ctr; +DBG_SF_DATA_OUT <= sf_data; +DBG_SF_WCNT_OUT <= sf_wcnt; +DBG_SF_RCNT_OUT <= sf_rcnt; +DBG_SF_RD_EN_OUT <= sf_rd_en; +DBG_SF_WR_EN_OUT <= sf_wr_en; +DBG_SF_EMPTY_OUT <= sf_empty; +DBG_SF_FULL_OUT <= sf_full; +DBG_SF_AFULL_OUT <= sf_afull; + +DEBUG_OUT <= debug; + +end architecture; \ No newline at end of file diff --git a/gbe_ecp2m/ip_configurator.vhd b/gbe_ecp2m/ip_configurator.vhd new file mode 100755 index 0000000..887f562 --- /dev/null +++ b/gbe_ecp2m/ip_configurator.vhd @@ -0,0 +1,337 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +use IEEE.std_logic_arith.all; + +library work; + +entity ip_configurator is +port( + CLK : in std_logic; + RESET : in std_logic; + -- configuration interface + START_CONFIG_IN : in std_logic; -- start configuration run + BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank + CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used + MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for + MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory + MEM_CLK_OUT : out std_logic; -- clock for BlockRAM + -- information for IP cores + DEST_MAC_OUT : out std_logic_vector(47 downto 0); -- destination MAC address + DEST_IP_OUT : out std_logic_vector(31 downto 0); -- destination IP address + DEST_UDP_OUT : out std_logic_vector(15 downto 0); -- destination port + SRC_MAC_OUT : out std_logic_vector(47 downto 0); -- source MAC address + SRC_IP_OUT : out std_logic_vector(31 downto 0); -- source IP address + SRC_UDP_OUT : out std_logic_vector(15 downto 0); -- source port + MTU_OUT : out std_logic_vector(15 downto 0); -- MTU size (max frame size) + -- Debug + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end entity; + +architecture ip_configurator of ip_configurator is + +type STATES is (IDLE, LOAD_REG, DELAY0, DELAY1, DELAY2, LOAD_DONE); +signal CURRENT_STATE, NEXT_STATE : STATES; +signal bsm : std_logic_vector(3 downto 0); +signal ce_ctr_comb : std_logic; +signal ce_ctr : std_logic; +signal rst_ctr_comb : std_logic; +signal rst_ctr : std_logic; +signal cfg_done_comb : std_logic; +signal cfg_done : std_logic; + +signal ctr_done_comb : std_logic; +signal ctr_done : std_logic; + +signal wr_select_comb : std_logic_vector(15 downto 0); +signal wr_select : std_logic_vector(15 downto 0); +signal wr_select_q : std_logic_vector(15 downto 0); + +signal addr_ctr : std_logic_vector(3 downto 0); +signal dest_mac : std_logic_vector(47 downto 0); +signal dest_ip : std_logic_vector(31 downto 0); +signal dest_udp : std_logic_vector(15 downto 0); +signal src_mac : std_logic_vector(47 downto 0); +signal src_ip : std_logic_vector(31 downto 0); +signal src_udp : std_logic_vector(15 downto 0); +signal mtu : std_logic_vector(15 downto 0); + +signal debug : std_logic_vector(31 downto 0); + +begin + + +-- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO +STATE_MACHINE_PROC: process( CLK ) +begin + if rising_edge(CLK) then + if RESET = '1' then + CURRENT_STATE <= IDLE; + ce_ctr <= '0'; + rst_ctr <= '0'; + cfg_done <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + ce_ctr <= ce_ctr_comb; + rst_ctr <= rst_ctr_comb; + cfg_done <= cfg_done_comb; + end if; + end if; +end process STATE_MACHINE_PROC; + +STATE_MACHINE_TRANS: process( CURRENT_STATE, START_CONFIG_IN, ctr_done ) +begin + NEXT_STATE <= IDLE; + ce_ctr_comb <= '0'; + rst_ctr_comb <= '0'; + cfg_done_comb <= '0'; + case CURRENT_STATE is + when IDLE => + bsm <= x"0"; + if( START_CONFIG_IN = '1' ) then + NEXT_STATE <= LOAD_REG; + ce_ctr_comb <= '1'; + else + NEXT_STATE <= IDLE; + end if; + when LOAD_REG => + bsm <= x"1"; + if( ctr_done = '1' ) then + NEXT_STATE <= DELAY0; + rst_ctr_comb <= '1'; + else + NEXT_STATE <= LOAD_REG; + ce_ctr_comb <= '1'; + end if; + when DELAY0 => + bsm <= x"2"; + NEXT_STATE <= DELAY1; + when DELAY1 => + bsm <= x"3"; + NEXT_STATE <= DELAY2; + when DELAY2 => + bsm <= x"4"; + NEXT_STATE <= LOAD_DONE; + cfg_done_comb <= '1'; + when LOAD_DONE => + bsm <= x"2"; + if( START_CONFIG_IN = '0' ) then + NEXT_STATE <= IDLE; + else + NEXT_STATE <= LOAD_DONE; + cfg_done_comb <= '1'; + end if; + when others => + bsm <= x"f"; + NEXT_STATE <= IDLE; + end case; +end process STATE_MACHINE_TRANS; + +-- address counter +THE_ADDR_CTR_PROC: process( CLK ) +begin + if ( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_ctr = '1') ) then + addr_ctr <= (others => '0'); + elsif( ce_ctr = '1' ) then + addr_ctr <= addr_ctr + 1; + end if; + end if; +end process THE_ADDR_CTR_PROC; + +ctr_done_comb <= '1' when (addr_ctr = x"e") else '0'; + +THE_SYNC_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + ctr_done <= ctr_done_comb; + wr_select_q <= wr_select; + wr_select <= wr_select_comb; + end if; +end process THE_SYNC_PROC; + +-- generate combinatorial write select signals, register and delay the (output registers in EBR!) +wr_select_comb(0) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"0") ) else '0'; -- dest MAC low +wr_select_comb(1) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"1") ) else '0'; -- dest MAC high +wr_select_comb(2) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"2") ) else '0'; -- dest IP +wr_select_comb(3) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"3") ) else '0'; -- dest port +wr_select_comb(4) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"4") ) else '0'; -- src MAC low +wr_select_comb(5) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"5") ) else '0'; -- src MAC high +wr_select_comb(6) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"6") ) else '0'; -- src IP +wr_select_comb(7) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"7") ) else '0'; -- src port +wr_select_comb(8) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"8") ) else '0'; -- MTU +wr_select_comb(9) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"9") ) else '0'; +wr_select_comb(10) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"a") ) else '0'; +wr_select_comb(11) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"b") ) else '0'; +wr_select_comb(12) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"c") ) else '0'; +wr_select_comb(13) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"d") ) else '0'; +wr_select_comb(14) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"e") ) else '0'; +wr_select_comb(15) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"f") ) else '0'; + +-- destination MAC low register +THE_D_MAC_LOW_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + dest_mac(31 downto 0) <= (others => '0'); + elsif( wr_select_q(0) = '1') then + dest_mac(31 downto 0) <= mem_data_in; + end if; + end if; +end process THE_D_MAC_LOW_PROC; + +-- destination MAC high register +THE_D_MAC_HIGH_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + dest_mac(47 downto 32) <= (others => '0'); + elsif( wr_select_q(1) = '1') then + dest_mac(47 downto 32) <= mem_data_in(15 downto 0); + end if; + end if; +end process THE_D_MAC_HIGH_PROC; + +-- destination IP register +THE_D_IP_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + dest_ip <= (others => '0'); + elsif( wr_select_q(2) = '1') then + dest_ip <= mem_data_in; + end if; + end if; +end process THE_D_IP_PROC; + +-- destination PORT register +THE_D_PORT_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + dest_udp <= (others => '0'); + elsif( wr_select_q(3) = '1') then + dest_udp <= mem_data_in(15 downto 0); + end if; + end if; +end process THE_D_PORT_PROC; + +-- source MAC low register +THE_S_MAC_LOW_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + src_mac(31 downto 0) <= (others => '0'); + elsif( wr_select_q(4) = '1') then + src_mac(31 downto 0) <= mem_data_in; + end if; + end if; +end process THE_S_MAC_LOW_PROC; + +-- source MAC high register +THE_S_MAC_HIGH_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + src_mac(47 downto 32) <= (others => '0'); + elsif( wr_select_q(5) = '1') then + src_mac(47 downto 32) <= mem_data_in(15 downto 0); + end if; + end if; +end process THE_S_MAC_HIGH_PROC; + +-- source IP register +THE_S_IP_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + src_ip <= (others => '0'); + elsif( wr_select_q(6) = '1') then + src_ip <= mem_data_in; + end if; + end if; +end process THE_S_IP_PROC; + +-- source PORT register +THE_S_PORT_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + src_udp <= (others => '0'); + elsif( wr_select_q(7) = '1') then + src_udp <= mem_data_in(15 downto 0); + end if; + end if; +end process THE_S_PORT_PROC; + +-- MTU size register +THE_MTU_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + mtu <= (others => '0'); + elsif( wr_select_q(8) = '1') then + mtu <= mem_data_in(15 downto 0); + end if; + end if; +end process THE_MTU_PROC; + + +-- Debug signals +debug(31 downto 12) <= (others => '0'); +debug(11 downto 8) <= addr_ctr; +debug(7) <= '0'; +debug(6) <= ctr_done; +debug(5) <= ce_ctr; +debug(4) <= rst_ctr; +debug(3 downto 0) <= bsm; +-- Outputs +MEM_ADDR_OUT(7 downto 4) <= BANK_SELECT_IN; +MEM_ADDR_OUT(3 downto 0) <= addr_ctr; +MEM_CLK_OUT <= CLK; +CONFIG_DONE_OUT <= cfg_done; + +-- destination MAC address - swap for user convinience +DEST_MAC_OUT(47 downto 40) <= dest_mac(7 downto 0); +DEST_MAC_OUT(39 downto 32) <= dest_mac(15 downto 8); +DEST_MAC_OUT(31 downto 24) <= dest_mac(23 downto 16); +DEST_MAC_OUT(23 downto 16) <= dest_mac(31 downto 24); +DEST_MAC_OUT(15 downto 8) <= dest_mac(39 downto 32); +DEST_MAC_OUT(7 downto 0) <= dest_mac(47 downto 40); + +-- destination IP address - swap for user convinience +DEST_IP_OUT(31 downto 24) <= dest_ip(7 downto 0); +DEST_IP_OUT(23 downto 16) <= dest_ip(15 downto 8); +DEST_IP_OUT(15 downto 8) <= dest_ip(23 downto 16); +DEST_IP_OUT(7 downto 0) <= dest_ip(31 downto 24); + +-- destination port address - swap for user convinience +DEST_UDP_OUT(15 downto 8) <= dest_udp(7 downto 0); +DEST_UDP_OUT(7 downto 0) <= dest_udp(15 downto 8); + +-- source MAC address - swap for user convinience +SRC_MAC_OUT(47 downto 40) <= src_mac(7 downto 0); +SRC_MAC_OUT(39 downto 32) <= src_mac(15 downto 8); +SRC_MAC_OUT(31 downto 24) <= src_mac(23 downto 16); +SRC_MAC_OUT(23 downto 16) <= src_mac(31 downto 24); +SRC_MAC_OUT(15 downto 8) <= src_mac(39 downto 32); +SRC_MAC_OUT(7 downto 0) <= src_mac(47 downto 40); + +-- source IP address - swap for user convinience +SRC_IP_OUT(31 downto 24) <= src_ip(7 downto 0); +SRC_IP_OUT(23 downto 16) <= src_ip(15 downto 8); +SRC_IP_OUT(15 downto 8) <= src_ip(23 downto 16); +SRC_IP_OUT(7 downto 0) <= src_ip(31 downto 24); + +-- source port address - swap for user convinience +SRC_UDP_OUT(15 downto 8) <= src_udp(7 downto 0); +SRC_UDP_OUT(7 downto 0) <= src_udp(15 downto 8); + +-- DO NOT SWAP! +MTU_OUT <= mtu; + +DEBUG_OUT <= debug; + +end architecture; \ No newline at end of file diff --git a/gbe_ecp2m/ipcores/.cvsignore b/gbe_ecp2m/ipcores/.cvsignore new file mode 100644 index 0000000..25a5568 --- /dev/null +++ b/gbe_ecp2m/ipcores/.cvsignore @@ -0,0 +1,6 @@ +*.jhd +*.naf +*.srp +*.sym +*.log +*tmpl.vhd diff --git a/gbe_ecp2m/ipcores/fifo_2048x8.lpc b/gbe_ecp2m/ipcores/fifo_2048x8.lpc new file mode 100755 index 0000000..542bbe2 --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_2048x8.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-5F900C +SpeedGrade=-5 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.2 +ModuleName=fifo_2048x8 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=12/26/2009 +Time=00:12:59 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=2048 +Width=8 +RDepth=2048 +RWidth=8 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_2048x8.vhd b/gbe_ecp2m/ipcores/fifo_2048x8.vhd new file mode 100755 index 0000000..2b75855 --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_2048x8.vhd @@ -0,0 +1,1913 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.2 +--/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e + +-- Sat Dec 26 00:12:59 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity fifo_2048x8 is + port ( + Data: in std_logic_vector(7 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_2048x8; + +architecture Structure of fifo_2048x8 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co5: std_logic; + signal wcount_11: std_logic; + signal co4: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co5_1: std_logic; + signal rcount_11: std_logic; + signal co4_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_10: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_10: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute GSR : string; + attribute initval of LUT4_31 : label is "0x6996"; + attribute initval of LUT4_30 : label is "0x6996"; + attribute initval of LUT4_29 : label is "0x6996"; + attribute initval of LUT4_28 : label is "0x6996"; + attribute initval of LUT4_27 : label is "0x6996"; + attribute initval of LUT4_26 : label is "0x6996"; + attribute initval of LUT4_25 : label is "0x6996"; + attribute initval of LUT4_24 : label is "0x6996"; + attribute initval of LUT4_23 : label is "0x6996"; + attribute initval of LUT4_22 : label is "0x6996"; + attribute initval of LUT4_21 : label is "0x6996"; + attribute initval of LUT4_20 : label is "0x6996"; + attribute initval of LUT4_19 : label is "0x6996"; + attribute initval of LUT4_18 : label is "0x6996"; + attribute initval of LUT4_17 : label is "0x6996"; + attribute initval of LUT4_16 : label is "0x6996"; + attribute initval of LUT4_15 : label is "0x6996"; + attribute initval of LUT4_14 : label is "0x6996"; + attribute initval of LUT4_13 : label is "0x6996"; + attribute initval of LUT4_12 : label is "0x6996"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x6996"; + attribute initval of LUT4_4 : label is "0x6996"; + attribute initval of LUT4_3 : label is "0x0410"; + attribute initval of LUT4_2 : label is "0x1004"; + attribute initval of LUT4_1 : label is "0x0140"; + attribute initval of LUT4_0 : label is "0x4001"; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL"; + attribute GSR of pdp_ram_0_0_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_0_0 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_0_0 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "9"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t24: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t23: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t22: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t21: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t20: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t19: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t18: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t17: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t16: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t15: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t14: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t13: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t12: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t11: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t10: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t9: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t8: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t7: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t6: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t5: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t4: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t3: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t2: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t1: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t0: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + LUT4_31: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_0); + + LUT4_30: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_1); + + LUT4_29: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_2); + + LUT4_28: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_27: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_26: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_25: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); + + LUT4_24: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); + + LUT4_23: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_22: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_21: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); + + LUT4_20: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_19: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_18: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_17: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, + DO0=>r_g2b_xor_cluster_0); + + LUT4_16: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, + DO0=>r_g2b_xor_cluster_1); + + LUT4_15: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, + DO0=>r_g2b_xor_cluster_2); + + LUT4_14: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), + DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), + DOB6=>Q(6), DOB7=>Q(7), DOB8=>open, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + FF_121: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_120: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_119: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_118: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_117: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_116: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_115: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_114: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_113: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_112: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_111: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_110: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_109: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_108: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_107: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_106: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_105: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_104: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_103: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_102: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_101: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_100: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_99: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_98: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_97: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_96: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_95: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_94: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_93: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_92: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_91: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_90: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_89: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_88: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_87: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_86: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_85: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_84: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_83: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_82: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_81: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_80: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_79: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_78: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_77: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_76: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_75: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_74: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_73: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_68: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_64: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_61: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_60: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_59: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_58: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_57: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_56: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_55: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_54: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_53: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_52: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_51: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_50: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_49: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_48: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_47: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_46: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_45: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_44: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_43: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_42: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_41: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_40: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_39: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_38: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_37: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_36: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_35: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_34: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_33: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_32: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_31: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_30: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_29: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_28: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_1: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10, + B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10, + B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of fifo_2048x8 is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_2048x8_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_2048x8_tmpl.vhd new file mode 100755 index 0000000..c365fcc --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_2048x8_tmpl.vhd @@ -0,0 +1,18 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.2 +-- Sat Dec 26 00:12:59 2009 + +-- parameterized module component declaration +component fifo_2048x8 + port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; + RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; + Reset: in std_logic; RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_2048x8 + port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.lpc b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.lpc new file mode 100755 index 0000000..8c82306 --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-5F900C +SpeedGrade=-5 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.3 +ModuleName=fifo_32kx16x8_mb +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=02/05/2010 +Time=16:48:12 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32768 +Width=16 +RDepth=65536 +RWidth=8 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Dynamic - Single Threshold +PeAssert=16 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=32752 +PfDeassert=506 +RDataCount=1 +WDataCount=1 +EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd new file mode 100755 index 0000000..d40ad50 --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd @@ -0,0 +1,5245 @@ +-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 5.3 +--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 32768 -width 16 -depth 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e + +-- Fri Feb 05 16:48:13 2010 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity fifo_32kx16x8_mb is + port ( + Data: in std_logic_vector(15 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + AmEmptyThresh: in std_logic_vector(15 downto 0); + AmFullThresh: in std_logic_vector(14 downto 0); + Q: out std_logic_vector(7 downto 0); + WCNT: out std_logic_vector(15 downto 0); + RCNT: out std_logic_vector(16 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end fifo_32kx16x8_mb; + +architecture Structure of fifo_32kx16x8_mb is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_3: std_logic; + signal func_xor_inet_2: std_logic; + signal func_xor_inet_1: std_logic; + signal func_xor_inet: std_logic; + signal rcount_w0: std_logic; + signal func_xor_inet_4: std_logic; + signal func_xor_inet_5: std_logic; + signal rcnt_reg_15_inv: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal wptr_15: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal r_gdata_15: std_logic; + signal rptr_16: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal r_gcount_16: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal r_gcount_w216: std_logic; + signal r_gcount_w16: std_logic; + signal rcnt_reg_16: std_logic; + signal empty_i: std_logic; + signal full_i: std_logic; + signal rRst: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co7: std_logic; + signal wcount_15: std_logic; + signal co6: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_1: std_logic; + signal ircount_16: std_logic; + signal co8: std_logic; + signal rcount_16: std_logic; + signal co7_1: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal rptr_15_ff: std_logic; + signal rptr_14_ff: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal wcnt_sub_0: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; + signal co0_2: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; + signal co1_2: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_6: std_logic; + signal co2_2: std_logic; + signal wcnt_sub_7: std_logic; + signal wcnt_sub_8: std_logic; + signal co3_2: std_logic; + signal wcnt_sub_9: std_logic; + signal wcnt_sub_10: std_logic; + signal co4_2: std_logic; + signal wcnt_sub_11: std_logic; + signal wcnt_sub_12: std_logic; + signal co5_2: std_logic; + signal wcnt_sub_13: std_logic; + signal wcnt_sub_14: std_logic; + signal co6_2: std_logic; + signal wcnt_sub_15: std_logic; + signal co7_2: std_logic; + signal wcnt_sub_msb: std_logic; + signal rcnt_sub_0: std_logic; + signal rcnt_sub_1: std_logic; + signal rcnt_sub_2: std_logic; + signal co0_3: std_logic; + signal rcnt_sub_3: std_logic; + signal rcnt_sub_4: std_logic; + signal co1_3: std_logic; + signal rcnt_sub_5: std_logic; + signal rcnt_sub_6: std_logic; + signal co2_3: std_logic; + signal rcnt_sub_7: std_logic; + signal rcnt_sub_8: std_logic; + signal co3_3: std_logic; + signal rcnt_sub_9: std_logic; + signal rcnt_sub_10: std_logic; + signal co4_3: std_logic; + signal rcnt_sub_11: std_logic; + signal rcnt_sub_12: std_logic; + signal co5_3: std_logic; + signal rcnt_sub_13: std_logic; + signal rcnt_sub_14: std_logic; + signal co6_3: std_logic; + signal rcnt_sub_15: std_logic; + signal rcnt_sub_16: std_logic; + signal co7_3: std_logic; + signal rcnt_sub_msb: std_logic; + signal co8_1d: std_logic; + signal co8_1: std_logic; + signal wfill_sub_0: std_logic; + signal wptr_0: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal co0_4: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal co1_4: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wfill_sub_5: std_logic; + signal wfill_sub_6: std_logic; + signal co2_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wfill_sub_7: std_logic; + signal wfill_sub_8: std_logic; + signal co3_4: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wfill_sub_9: std_logic; + signal wfill_sub_10: std_logic; + signal co4_4: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wfill_sub_11: std_logic; + signal wfill_sub_12: std_logic; + signal co5_4: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wfill_sub_13: std_logic; + signal wfill_sub_14: std_logic; + signal co6_4: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wfill_sub_15: std_logic; + signal co7_4: std_logic; + signal wfill_sub_msb: std_logic; + signal rfill_sub_0: std_logic; + signal rptr_0: std_logic; + signal scuba_vhi: std_logic; + signal rfill_sub_1: std_logic; + signal rfill_sub_2: std_logic; + signal co0_5: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rfill_sub_3: std_logic; + signal rfill_sub_4: std_logic; + signal co1_5: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rfill_sub_5: std_logic; + signal rfill_sub_6: std_logic; + signal co2_5: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rfill_sub_7: std_logic; + signal rfill_sub_8: std_logic; + signal co3_5: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rfill_sub_9: std_logic; + signal rfill_sub_10: std_logic; + signal co4_5: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rfill_sub_11: std_logic; + signal rfill_sub_12: std_logic; + signal co5_5: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rfill_sub_13: std_logic; + signal rfill_sub_14: std_logic; + signal co6_5: std_logic; + signal rptr_13: std_logic; + signal rptr_14: std_logic; + signal rfill_sub_15: std_logic; + signal rfill_sub_16: std_logic; + signal co7_5: std_logic; + signal rptr_15: std_logic; + signal rfill_sub_msb: std_logic; + signal co8_2d: std_logic; + signal co8_2: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_6: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_6: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_6: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_6: std_logic; + signal wcount_r7: std_logic; + signal wcount_r8: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_6: std_logic; + signal wcount_r9: std_logic; + signal wcount_r10: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_6: std_logic; + signal wcount_r11: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_6: std_logic; + signal wcount_r13: std_logic; + signal wcount_r14: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal co7_6: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_7: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_7: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_7: std_logic; + signal rcount_w7: std_logic; + signal rcount_w8: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_7: std_logic; + signal rcount_w9: std_logic; + signal rcount_w10: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_7: std_logic; + signal rcount_w11: std_logic; + signal rcount_w12: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_7: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w14: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_7: std_logic; + signal rcount_w15: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_14: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal rden_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcnt_reg_0: std_logic; + signal rcnt_reg_1: std_logic; + signal co0_8: std_logic; + signal rcnt_reg_2: std_logic; + signal rcnt_reg_3: std_logic; + signal co1_8: std_logic; + signal rcnt_reg_4: std_logic; + signal rcnt_reg_5: std_logic; + signal co2_8: std_logic; + signal rcnt_reg_6: std_logic; + signal rcnt_reg_7: std_logic; + signal co3_8: std_logic; + signal rcnt_reg_8: std_logic; + signal rcnt_reg_9: std_logic; + signal co4_8: std_logic; + signal rcnt_reg_10: std_logic; + signal rcnt_reg_11: std_logic; + signal co5_8: std_logic; + signal rcnt_reg_12: std_logic; + signal rcnt_reg_13: std_logic; + signal co6_8: std_logic; + signal rcnt_reg_14: std_logic; + signal rcnt_reg_15: std_logic; + signal co7_7: std_logic; + signal ae_clrsig: std_logic; + signal ae_setsig: std_logic; + signal ae_d: std_logic; + signal ae_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_3: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_9: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_9: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; + signal co2_9: std_logic; + signal wcnt_reg_6: std_logic; + signal wcnt_reg_7: std_logic; + signal co3_9: std_logic; + signal wcnt_reg_8: std_logic; + signal wcnt_reg_9: std_logic; + signal co4_9: std_logic; + signal wcnt_reg_10: std_logic; + signal wcnt_reg_11: std_logic; + signal co5_9: std_logic; + signal wcnt_reg_12: std_logic; + signal wcnt_reg_13: std_logic; + signal co6_9: std_logic; + signal wcnt_reg_14: std_logic; + signal wcnt_reg_15: std_logic; + signal af_d: std_logic; + signal af_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX41 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; SD1: in std_logic; SD2: in std_logic; + Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute GSR : string; + attribute initval of LUT4_52 : label is "0x6996"; + attribute initval of LUT4_51 : label is "0x6996"; + attribute initval of LUT4_50 : label is "0x6996"; + attribute initval of LUT4_49 : label is "0x6996"; + attribute initval of LUT4_48 : label is "0x6996"; + attribute initval of LUT4_47 : label is "0x6996"; + attribute initval of LUT4_46 : label is "0x6996"; + attribute initval of LUT4_45 : label is "0x6996"; + attribute initval of LUT4_44 : label is "0x6996"; + attribute initval of LUT4_43 : label is "0x6996"; + attribute initval of LUT4_42 : label is "0x6996"; + attribute initval of LUT4_41 : label is "0x6996"; + attribute initval of LUT4_40 : label is "0x6996"; + attribute initval of LUT4_39 : label is "0x6996"; + attribute initval of LUT4_38 : label is "0x6996"; + attribute initval of LUT4_37 : label is "0x6996"; + attribute initval of LUT4_36 : label is "0x6996"; + attribute initval of LUT4_35 : label is "0x6996"; + attribute initval of LUT4_34 : label is "0x6996"; + attribute initval of LUT4_33 : label is "0x6996"; + attribute initval of LUT4_32 : label is "0x6996"; + attribute initval of LUT4_31 : label is "0x6996"; + attribute initval of LUT4_30 : label is "0x6996"; + attribute initval of LUT4_29 : label is "0x6996"; + attribute initval of LUT4_28 : label is "0x6996"; + attribute initval of LUT4_27 : label is "0x6996"; + attribute initval of LUT4_26 : label is "0x6996"; + attribute initval of LUT4_25 : label is "0x6996"; + attribute initval of LUT4_24 : label is "0x6996"; + attribute initval of LUT4_23 : label is "0x6996"; + attribute initval of LUT4_22 : label is "0x6996"; + attribute initval of LUT4_21 : label is "0x6996"; + attribute initval of LUT4_20 : label is "0x6996"; + attribute initval of LUT4_19 : label is "0x6996"; + attribute initval of LUT4_18 : label is "0x6996"; + attribute initval of LUT4_17 : label is "0x6996"; + attribute initval of LUT4_16 : label is "0x6996"; + attribute initval of LUT4_15 : label is "0x6996"; + attribute initval of LUT4_14 : label is "0x6996"; + attribute initval of LUT4_13 : label is "0x6996"; + attribute initval of LUT4_12 : label is "0x6996"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x6996"; + attribute initval of LUT4_4 : label is "0x6996"; + attribute initval of LUT4_3 : label is "0x0410"; + attribute initval of LUT4_2 : label is "0x1004"; + attribute initval of LUT4_1 : label is "0x0140"; + attribute initval of LUT4_0 : label is "0x4001"; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL"; + attribute GSR of pdp_ram_0_0_31 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is ""; + attribute CSDECODE_B of pdp_ram_0_1_30 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_1_30 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_1_30 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_1_30 : label is "NORMAL"; + attribute GSR of pdp_ram_0_1_30 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_1_30 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_1_30 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_1_30 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_1_30 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_1_30 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is ""; + attribute CSDECODE_B of pdp_ram_0_2_29 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_2_29 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_2_29 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_2_29 : label is "NORMAL"; + attribute GSR of pdp_ram_0_2_29 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_2_29 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_2_29 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_2_29 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_2_29 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_2_29 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is ""; + attribute CSDECODE_B of pdp_ram_0_3_28 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_3_28 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_3_28 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_3_28 : label is "NORMAL"; + attribute GSR of pdp_ram_0_3_28 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_3_28 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_3_28 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_3_28 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_3_28 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_3_28 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is ""; + attribute CSDECODE_B of pdp_ram_0_4_27 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_4_27 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_4_27 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_4_27 : label is "NORMAL"; + attribute GSR of pdp_ram_0_4_27 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_4_27 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_4_27 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_4_27 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_4_27 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_4_27 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is ""; + attribute CSDECODE_B of pdp_ram_0_5_26 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_5_26 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_5_26 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_5_26 : label is "NORMAL"; + attribute GSR of pdp_ram_0_5_26 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_5_26 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_5_26 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_5_26 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_5_26 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_5_26 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is ""; + attribute CSDECODE_B of pdp_ram_0_6_25 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_6_25 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_6_25 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_6_25 : label is "NORMAL"; + attribute GSR of pdp_ram_0_6_25 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_6_25 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_6_25 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_6_25 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_6_25 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_6_25 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is ""; + attribute CSDECODE_B of pdp_ram_0_7_24 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_7_24 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_7_24 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_7_24 : label is "NORMAL"; + attribute GSR of pdp_ram_0_7_24 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_7_24 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_7_24 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_7_24 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_7_24 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_7_24 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is ""; + attribute CSDECODE_B of pdp_ram_1_0_23 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_0_23 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_0_23 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_0_23 : label is "NORMAL"; + attribute GSR of pdp_ram_1_0_23 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_0_23 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_0_23 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_0_23 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_0_23 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_0_23 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is ""; + attribute CSDECODE_B of pdp_ram_1_1_22 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_1_22 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_1_22 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_1_22 : label is "NORMAL"; + attribute GSR of pdp_ram_1_1_22 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_1_22 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_1_22 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_1_22 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_1_22 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_1_22 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is ""; + attribute CSDECODE_B of pdp_ram_1_2_21 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_2_21 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_2_21 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_2_21 : label is "NORMAL"; + attribute GSR of pdp_ram_1_2_21 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_2_21 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_2_21 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_2_21 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_2_21 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_2_21 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is ""; + attribute CSDECODE_B of pdp_ram_1_3_20 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_3_20 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_3_20 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_3_20 : label is "NORMAL"; + attribute GSR of pdp_ram_1_3_20 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_3_20 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_3_20 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_3_20 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_3_20 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_3_20 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is ""; + attribute CSDECODE_B of pdp_ram_1_4_19 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_4_19 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_4_19 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_4_19 : label is "NORMAL"; + attribute GSR of pdp_ram_1_4_19 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_4_19 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_4_19 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_4_19 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_4_19 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_4_19 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is ""; + attribute CSDECODE_B of pdp_ram_1_5_18 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_5_18 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_5_18 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_5_18 : label is "NORMAL"; + attribute GSR of pdp_ram_1_5_18 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_5_18 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_5_18 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_5_18 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_5_18 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_5_18 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is ""; + attribute CSDECODE_B of pdp_ram_1_6_17 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_6_17 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_6_17 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_6_17 : label is "NORMAL"; + attribute GSR of pdp_ram_1_6_17 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_6_17 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_6_17 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_6_17 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_6_17 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_6_17 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is ""; + attribute CSDECODE_B of pdp_ram_1_7_16 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_7_16 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_7_16 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_7_16 : label is "NORMAL"; + attribute GSR of pdp_ram_1_7_16 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_7_16 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_7_16 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_7_16 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_7_16 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_7_16 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is ""; + attribute CSDECODE_B of pdp_ram_2_0_15 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_0_15 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_0_15 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_0_15 : label is "NORMAL"; + attribute GSR of pdp_ram_2_0_15 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_0_15 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_0_15 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_0_15 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_0_15 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_0_15 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is ""; + attribute CSDECODE_B of pdp_ram_2_1_14 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_1_14 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_1_14 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_1_14 : label is "NORMAL"; + attribute GSR of pdp_ram_2_1_14 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_1_14 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_1_14 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_1_14 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_1_14 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_1_14 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is ""; + attribute CSDECODE_B of pdp_ram_2_2_13 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_2_13 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_2_13 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_2_13 : label is "NORMAL"; + attribute GSR of pdp_ram_2_2_13 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_2_13 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_2_13 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_2_13 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_2_13 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_2_13 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is ""; + attribute CSDECODE_B of pdp_ram_2_3_12 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_3_12 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_3_12 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_3_12 : label is "NORMAL"; + attribute GSR of pdp_ram_2_3_12 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_3_12 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_3_12 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_3_12 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_3_12 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_3_12 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is ""; + attribute CSDECODE_B of pdp_ram_2_4_11 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_4_11 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_4_11 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_4_11 : label is "NORMAL"; + attribute GSR of pdp_ram_2_4_11 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_4_11 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_4_11 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_4_11 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_4_11 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_4_11 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is ""; + attribute CSDECODE_B of pdp_ram_2_5_10 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_5_10 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_5_10 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_5_10 : label is "NORMAL"; + attribute GSR of pdp_ram_2_5_10 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_5_10 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_5_10 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_5_10 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_5_10 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_5_10 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is ""; + attribute CSDECODE_B of pdp_ram_2_6_9 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_6_9 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_6_9 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_6_9 : label is "NORMAL"; + attribute GSR of pdp_ram_2_6_9 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_6_9 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_6_9 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_6_9 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_6_9 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_6_9 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is ""; + attribute CSDECODE_B of pdp_ram_2_7_8 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_7_8 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_7_8 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_7_8 : label is "NORMAL"; + attribute GSR of pdp_ram_2_7_8 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_7_8 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_7_8 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_7_8 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_7_8 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_7_8 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is ""; + attribute CSDECODE_B of pdp_ram_3_0_7 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_0_7 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_0_7 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_0_7 : label is "NORMAL"; + attribute GSR of pdp_ram_3_0_7 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_0_7 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_0_7 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_0_7 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_0_7 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_0_7 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is ""; + attribute CSDECODE_B of pdp_ram_3_1_6 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_1_6 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_1_6 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_1_6 : label is "NORMAL"; + attribute GSR of pdp_ram_3_1_6 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_1_6 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_1_6 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_1_6 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_1_6 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_1_6 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is ""; + attribute CSDECODE_B of pdp_ram_3_2_5 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_2_5 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_2_5 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_2_5 : label is "NORMAL"; + attribute GSR of pdp_ram_3_2_5 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_2_5 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_2_5 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_2_5 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_2_5 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_2_5 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is ""; + attribute CSDECODE_B of pdp_ram_3_3_4 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_3_4 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_3_4 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_3_4 : label is "NORMAL"; + attribute GSR of pdp_ram_3_3_4 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_3_4 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_3_4 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_3_4 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_3_4 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_3_4 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is ""; + attribute CSDECODE_B of pdp_ram_3_4_3 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_4_3 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_4_3 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_4_3 : label is "NORMAL"; + attribute GSR of pdp_ram_3_4_3 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_4_3 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_4_3 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_4_3 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_4_3 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_4_3 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is ""; + attribute CSDECODE_B of pdp_ram_3_5_2 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_5_2 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_5_2 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_5_2 : label is "NORMAL"; + attribute GSR of pdp_ram_3_5_2 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_5_2 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_5_2 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_5_2 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_5_2 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_5_2 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is ""; + attribute CSDECODE_B of pdp_ram_3_6_1 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_6_1 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_6_1 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_6_1 : label is "NORMAL"; + attribute GSR of pdp_ram_3_6_1 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_6_1 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_6_1 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_6_1 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_6_1 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_6_1 : label is "2"; + attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is ""; + attribute CSDECODE_B of pdp_ram_3_7_0 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_7_0 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_7_0 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_7_0 : label is "NORMAL"; + attribute GSR of pdp_ram_3_7_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_7_0 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_7_0 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_7_0 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_7_0 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_7_0 : label is "2"; + attribute GSR of FF_236 : label is "ENABLED"; + attribute GSR of FF_235 : label is "ENABLED"; + attribute GSR of FF_234 : label is "ENABLED"; + attribute GSR of FF_233 : label is "ENABLED"; + attribute GSR of FF_232 : label is "ENABLED"; + attribute GSR of FF_231 : label is "ENABLED"; + attribute GSR of FF_230 : label is "ENABLED"; + attribute GSR of FF_229 : label is "ENABLED"; + attribute GSR of FF_228 : label is "ENABLED"; + attribute GSR of FF_227 : label is "ENABLED"; + attribute GSR of FF_226 : label is "ENABLED"; + attribute GSR of FF_225 : label is "ENABLED"; + attribute GSR of FF_224 : label is "ENABLED"; + attribute GSR of FF_223 : label is "ENABLED"; + attribute GSR of FF_222 : label is "ENABLED"; + attribute GSR of FF_221 : label is "ENABLED"; + attribute GSR of FF_220 : label is "ENABLED"; + attribute GSR of FF_219 : label is "ENABLED"; + attribute GSR of FF_218 : label is "ENABLED"; + attribute GSR of FF_217 : label is "ENABLED"; + attribute GSR of FF_216 : label is "ENABLED"; + attribute GSR of FF_215 : label is "ENABLED"; + attribute GSR of FF_214 : label is "ENABLED"; + attribute GSR of FF_213 : label is "ENABLED"; + attribute GSR of FF_212 : label is "ENABLED"; + attribute GSR of FF_211 : label is "ENABLED"; + attribute GSR of FF_210 : label is "ENABLED"; + attribute GSR of FF_209 : label is "ENABLED"; + attribute GSR of FF_208 : label is "ENABLED"; + attribute GSR of FF_207 : label is "ENABLED"; + attribute GSR of FF_206 : label is "ENABLED"; + attribute GSR of FF_205 : label is "ENABLED"; + attribute GSR of FF_204 : label is "ENABLED"; + attribute GSR of FF_203 : label is "ENABLED"; + attribute GSR of FF_202 : label is "ENABLED"; + attribute GSR of FF_201 : label is "ENABLED"; + attribute GSR of FF_200 : label is "ENABLED"; + attribute GSR of FF_199 : label is "ENABLED"; + attribute GSR of FF_198 : label is "ENABLED"; + attribute GSR of FF_197 : label is "ENABLED"; + attribute GSR of FF_196 : label is "ENABLED"; + attribute GSR of FF_195 : label is "ENABLED"; + attribute GSR of FF_194 : label is "ENABLED"; + attribute GSR of FF_193 : label is "ENABLED"; + attribute GSR of FF_192 : label is "ENABLED"; + attribute GSR of FF_191 : label is "ENABLED"; + attribute GSR of FF_190 : label is "ENABLED"; + attribute GSR of FF_189 : label is "ENABLED"; + attribute GSR of FF_188 : label is "ENABLED"; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t39: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_2: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t38: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_1: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t37: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t36: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t35: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t34: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t33: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t32: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t31: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t30: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t29: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t28: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t27: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t26: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t25: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t24: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t23: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t22: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t21: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t20: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t19: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t18: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t17: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t16: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t15: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t14: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t13: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t12: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t11: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t10: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t9: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t8: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t7: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + XOR2_t6: XOR2 + port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); + + LUT4_52: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, + DO0=>w_g2b_xor_cluster_0); + + LUT4_51: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_1); + + LUT4_50: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_2); + + LUT4_49: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_3); + + LUT4_48: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_47: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); + + LUT4_46: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_45: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); + + LUT4_44: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); + + LUT4_43: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_42: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_41: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); + + LUT4_40: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_39: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_38: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_37: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); + + LUT4_36: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_35: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r2); + + LUT4_34: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_33: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r1); + + LUT4_32: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r0); + + LUT4_31: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>r_gcount_w216, + DO0=>r_g2b_xor_cluster_0); + + LUT4_30: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_1); + + LUT4_29: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_2); + + LUT4_28: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_3); + + LUT4_27: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w15); + + LUT4_26: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, + AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_25: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); + + LUT4_24: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_23: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, + DO0=>rcount_w10); + + LUT4_22: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_21: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_20: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); + + LUT4_19: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_18: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_17: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_16: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); + + LUT4_15: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_14: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w3); + + LUT4_13: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w2); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_4); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, + AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, + DO0=>func_xor_inet_5); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + XOR2_t5: XOR2 + port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb); + + XOR2_t4: XOR2 + port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb); + + XOR2_t3: XOR2 + port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb); + + XOR2_t2: XOR2 + port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + INV_0: INV + port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv); + + AND2_t1: AND2 + port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig); + + AND2_t0: AND2 + port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig); + + pdp_ram_0_0_31: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_0, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_1_30: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_1, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_2_29: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_2, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_3_28: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_3, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_4_27: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_4, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_5_26: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_5, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_6_25: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_6, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_7_24: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_7, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_0_23: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_0, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_1_22: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_1, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_2_21: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_2, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_3_20: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_3, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_4_19: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_4, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_5_18: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_5, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_6_17: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_6, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_7_16: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_7, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_0_15: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_0, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_1_14: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_1, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_2_13: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_2, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_3_12: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_3, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_4_11: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_4, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_5_10: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_5, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_6_9: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_6, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_7_8: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_7, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_0_7: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_0, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_1_6: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_1, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_2_5: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_2, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_3_4: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_3, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_4_3: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_4, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_5_2: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_5, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_6_1: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_6, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_7_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_7, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + FF_236: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_235: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_234: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_233: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_232: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_231: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_230: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_229: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_228: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_227: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_226: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_225: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_224: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_223: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_222: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_221: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_220: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_219: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_218: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_217: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_216: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_215: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_214: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_213: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_212: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_211: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_210: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_209: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_208: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_207: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_206: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_205: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_204: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_203: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_202: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_201: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_200: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_199: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_198: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_197: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_196: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_195: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_194: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_193: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_192: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_191: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_190: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_189: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_188: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_187: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_186: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_185: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_184: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_183: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_182: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_181: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_180: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_179: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_178: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_177: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_176: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_175: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_174: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_173: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_172: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_16); + + FF_171: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_170: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_169: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_168: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_167: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_166: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_165: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_164: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_163: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_162: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_161: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_160: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_159: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_158: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_157: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_156: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_155: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_16); + + FF_154: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_153: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_152: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_151: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_150: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_149: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_148: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_147: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_146: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_145: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_144: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_143: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_142: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_141: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_140: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_139: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_138: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_16); + + FF_137: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_136: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_15_ff); + + FF_135: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_134: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_133: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_132: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_131: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_130: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_129: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_128: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_127: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_126: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_125: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_124: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_123: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_122: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_121: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_120: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_119: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_118: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_117: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_116: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_115: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_114: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_113: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_112: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_111: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_110: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_109: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_108: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_107: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_106: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_105: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_104: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_103: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); + + FF_102: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_101: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_100: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_99: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_98: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_97: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_96: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_95: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_94: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_93: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_92: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_91: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_90: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_89: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_88: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_87: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_86: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_85: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_84: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_83: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_82: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_81: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_80: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_79: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_78: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_77: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_76: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_75: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_74: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_73: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_72: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_71: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_70: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w216); + + FF_69: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); + + FF_68: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); + + FF_67: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); + + FF_66: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); + + FF_65: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); + + FF_64: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); + + FF_63: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); + + FF_62: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); + + FF_61: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8); + + FF_60: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9); + + FF_59: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10); + + FF_58: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11); + + FF_57: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12); + + FF_56: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13); + + FF_55: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14); + + FF_54: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15); + + FF_53: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); + + FF_52: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); + + FF_51: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); + + FF_50: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); + + FF_49: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); + + FF_48: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); + + FF_47: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); + + FF_46: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); + + FF_45: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8); + + FF_44: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9); + + FF_43: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10); + + FF_42: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11); + + FF_41: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12); + + FF_40: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13); + + FF_39: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14); + + FF_38: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15); + + FF_37: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16); + + FF_36: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_35: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_34: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_33: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_32: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_31: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); + + FF_30: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); + + FF_29: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); + + FF_28: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10)); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11)); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12)); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13)); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14)); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15)); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16)); + + FF_3: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_1: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + r_gctr_8: CU2 + port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8, + NC0=>ircount_16, NC1=>open); + + mux_7: MUX41 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0)); + + mux_6: MUX41 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1)); + + mux_5: MUX41 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2)); + + mux_4: MUX41 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3)); + + mux_3: MUX41 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4)); + + mux_2: MUX41 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5)); + + mux_1: MUX41 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6)); + + mux_0: MUX41 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7)); + + wcnt_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo, + B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, + S1=>wcnt_sub_0); + + wcnt_1: FSUB2B + port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2, + B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1, + S1=>wcnt_sub_2); + + wcnt_2: FSUB2B + port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4, + B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3, + S1=>wcnt_sub_4); + + wcnt_3: FSUB2B + port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6, + B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5, + S1=>wcnt_sub_6); + + wcnt_4: FSUB2B + port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8, + B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7, + S1=>wcnt_sub_8); + + wcnt_5: FSUB2B + port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10, + B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9, + S1=>wcnt_sub_10); + + wcnt_6: FSUB2B + port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2, + S0=>wcnt_sub_11, S1=>wcnt_sub_12); + + wcnt_7: FSUB2B + port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14, + B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13, + S1=>wcnt_sub_14); + + wcnt_8: FSUB2B + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15, + S1=>open); + + rcnt_0: FSUB2B + port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open, + S1=>rcnt_sub_0); + + rcnt_1: FSUB2B + port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1, + B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1, + S1=>rcnt_sub_2); + + rcnt_2: FSUB2B + port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3, + B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3, + S1=>rcnt_sub_4); + + rcnt_3: FSUB2B + port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5, + B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5, + S1=>rcnt_sub_6); + + rcnt_4: FSUB2B + port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7, + B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7, + S1=>rcnt_sub_8); + + rcnt_5: FSUB2B + port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9, + B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9, + S1=>rcnt_sub_10); + + rcnt_6: FSUB2B + port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11, + B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11, + S1=>rcnt_sub_12); + + rcnt_7: FSUB2B + port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13, + B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13, + S1=>rcnt_sub_14); + + rcnt_8: FSUB2B + port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15, + B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15, + S1=>rcnt_sub_16); + + rcntd: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open); + + wfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, + B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open, + S1=>wfill_sub_0); + + wfill_1: FSUB2B + port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, + BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2); + + wfill_2: FSUB2B + port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, + BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4); + + wfill_3: FSUB2B + port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, + BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6); + + wfill_4: FSUB2B + port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9, + BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8); + + wfill_5: FSUB2B + port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, + B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9, + S1=>wfill_sub_10); + + wfill_6: FSUB2B + port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4, + S0=>wfill_sub_11, S1=>wfill_sub_12); + + wfill_7: FSUB2B + port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14, + B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13, + S1=>wfill_sub_14); + + wfill_8: FSUB2B + port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + rfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, + S1=>rfill_sub_0); + + rfill_1: FSUB2B + port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2, + BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2); + + rfill_2: FSUB2B + port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4, + BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4); + + rfill_3: FSUB2B + port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6, + BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6); + + rfill_4: FSUB2B + port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8, + BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8); + + rfill_5: FSUB2B + port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10, + BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10); + + rfill_6: FSUB2B + port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11, + B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11, + S1=>rfill_sub_12); + + rfill_7: FSUB2B + port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13, + B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13, + S1=>rfill_sub_14); + + rfill_8: FSUB2B + port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15, + B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15, + S1=>rfill_sub_16); + + rfilld: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, + B1=>wcount_r2, CI=>co0_6, GE=>co1_6); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, + B1=>wcount_r4, CI=>co1_6, GE=>co2_6); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, + B1=>wcount_r6, CI=>co2_6, GE=>co3_6); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, + B1=>wcount_r8, CI=>co3_6, GE=>co4_6); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, + B1=>wcount_r10, CI=>co4_6, GE=>co5_6); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, + B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, + B1=>wcount_r14, CI=>co6_6, GE=>co7_6); + + empty_cmp_8: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, + B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, + B1=>rcount_w4, CI=>co0_7, GE=>co1_7); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, + B1=>rcount_w6, CI=>co1_7, GE=>co2_7); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, + B1=>rcount_w8, CI=>co2_7, GE=>co3_7); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, + B1=>rcount_w10, CI=>co3_7, GE=>co4_7); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, + B1=>rcount_w12, CI=>co4_7, GE=>co5_7); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w14, CI=>co5_7, GE=>co6_7); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, + B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + ae_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + ae_cmp_0: AGEB2 + port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), + B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8); + + ae_cmp_1: AGEB2 + port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), + B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8); + + ae_cmp_2: AGEB2 + port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), + B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8); + + ae_cmp_3: AGEB2 + port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), + B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8); + + ae_cmp_4: AGEB2 + port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9), + B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8); + + ae_cmp_5: AGEB2 + port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11), + B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8); + + ae_cmp_6: AGEB2 + port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13), + B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8); + + ae_cmp_7: AGEB2 + port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15), + B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7); + + ae_cmp_8: AGEB2 + port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, + B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); + + af_d_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); + + af_d_cmp_0: AGEB2 + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9); + + af_d_cmp_1: AGEB2 + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9); + + af_d_cmp_2: AGEB2 + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9); + + af_d_cmp_3: AGEB2 + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9); + + af_d_cmp_4: AGEB2 + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9); + + af_d_cmp_5: AGEB2 + port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), + B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9); + + af_d_cmp_6: AGEB2 + port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), + B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9); + + af_d_cmp_7: AGEB2 + port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14), + B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a3: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of fifo_32kx16x8_mb is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FSUB2B use entity ecp2m.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:MUX41 use entity ecp2m.MUX41(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb_tmpl.vhd new file mode 100755 index 0000000..bc2e00d --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb_tmpl.vhd @@ -0,0 +1,26 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 5.3 +-- Fri Feb 05 16:48:13 2010 + +-- parameterized module component declaration +component fifo_32kx16x8_mb + port (Data: in std_logic_vector(15 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; + AmEmptyThresh: in std_logic_vector(15 downto 0); + AmFullThresh: in std_logic_vector(14 downto 0); + Q: out std_logic_vector(7 downto 0); + WCNT: out std_logic_vector(15 downto 0); + RCNT: out std_logic_vector(16 downto 0); Empty: out std_logic; + Full: out std_logic; AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_32kx16x8_mb + port map (Data(15 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(15 downto 0)=>__, + AmFullThresh(14 downto 0)=>__, Q(7 downto 0)=>__, WCNT(15 downto 0)=>__, + RCNT(16 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__, + AlmostFull=>__); diff --git a/gbe_ecp2m/ipcores/fifo_4096x32.lpc b/gbe_ecp2m/ipcores/fifo_4096x32.lpc new file mode 100755 index 0000000..3f5196b --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_4096x32.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-5F900C +SpeedGrade=-5 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.3 +ModuleName=fifo_4096x32 +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=12/18/2009 +Time=03:02:30 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4096 +Width=32 +RDepth=4096 +RWidth=32 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_4096x32.vhd b/gbe_ecp2m/ipcores/fifo_4096x32.vhd new file mode 100755 index 0000000..51a2cd4 --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_4096x32.vhd @@ -0,0 +1,2415 @@ +-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 5.3 +--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 4096 -width 32 -depth 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e + +-- Fri Dec 18 03:02:30 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity fifo_4096x32 is + port ( + Data: in std_logic_vector(31 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(31 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_4096x32; + +architecture Structure of fifo_4096x32 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal co6: std_logic; + signal wcount_12: std_logic; + signal co5: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal co6_1: std_logic; + signal rcount_12: std_logic; + signal co5_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute GSR : string; + attribute initval of LUT4_33 : label is "0x6996"; + attribute initval of LUT4_32 : label is "0x6996"; + attribute initval of LUT4_31 : label is "0x6996"; + attribute initval of LUT4_30 : label is "0x6996"; + attribute initval of LUT4_29 : label is "0x6996"; + attribute initval of LUT4_28 : label is "0x6996"; + attribute initval of LUT4_27 : label is "0x6996"; + attribute initval of LUT4_26 : label is "0x6996"; + attribute initval of LUT4_25 : label is "0x6996"; + attribute initval of LUT4_24 : label is "0x6996"; + attribute initval of LUT4_23 : label is "0x6996"; + attribute initval of LUT4_22 : label is "0x6996"; + attribute initval of LUT4_21 : label is "0x6996"; + attribute initval of LUT4_20 : label is "0x6996"; + attribute initval of LUT4_19 : label is "0x6996"; + attribute initval of LUT4_18 : label is "0x6996"; + attribute initval of LUT4_17 : label is "0x6996"; + attribute initval of LUT4_16 : label is "0x6996"; + attribute initval of LUT4_15 : label is "0x6996"; + attribute initval of LUT4_14 : label is "0x6996"; + attribute initval of LUT4_13 : label is "0x6996"; + attribute initval of LUT4_12 : label is "0x6996"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x6996"; + attribute initval of LUT4_4 : label is "0x6996"; + attribute initval of LUT4_3 : label is "0x0410"; + attribute initval of LUT4_2 : label is "0x1004"; + attribute initval of LUT4_1 : label is "0x0140"; + attribute initval of LUT4_0 : label is "0x4001"; + attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is ""; + attribute CSDECODE_B of pdp_ram_0_0_7 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_0_7 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_0_7 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_0_7 : label is "NORMAL"; + attribute GSR of pdp_ram_0_0_7 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_7 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_0_7 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_0_7 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_0_7 : label is "4"; + attribute DATA_WIDTH_A of pdp_ram_0_0_7 : label is "4"; + attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is ""; + attribute CSDECODE_B of pdp_ram_0_1_6 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_1_6 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_1_6 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_1_6 : label is "NORMAL"; + attribute GSR of pdp_ram_0_1_6 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_1_6 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_1_6 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_1_6 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_1_6 : label is "4"; + attribute DATA_WIDTH_A of pdp_ram_0_1_6 : label is "4"; + attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is ""; + attribute CSDECODE_B of pdp_ram_0_2_5 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_2_5 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_2_5 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_2_5 : label is "NORMAL"; + attribute GSR of pdp_ram_0_2_5 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_2_5 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_2_5 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_2_5 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_2_5 : label is "4"; + attribute DATA_WIDTH_A of pdp_ram_0_2_5 : label is "4"; + attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is ""; + attribute CSDECODE_B of pdp_ram_0_3_4 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_3_4 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_3_4 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_3_4 : label is "NORMAL"; + attribute GSR of pdp_ram_0_3_4 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_3_4 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_3_4 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_3_4 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_3_4 : label is "4"; + attribute DATA_WIDTH_A of pdp_ram_0_3_4 : label is "4"; + attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is ""; + attribute CSDECODE_B of pdp_ram_0_4_3 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_4_3 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_4_3 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_4_3 : label is "NORMAL"; + attribute GSR of pdp_ram_0_4_3 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_4_3 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_4_3 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_4_3 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_4_3 : label is "4"; + attribute DATA_WIDTH_A of pdp_ram_0_4_3 : label is "4"; + attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is ""; + attribute CSDECODE_B of pdp_ram_0_5_2 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_5_2 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_5_2 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_5_2 : label is "NORMAL"; + attribute GSR of pdp_ram_0_5_2 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_5_2 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_5_2 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_5_2 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_5_2 : label is "4"; + attribute DATA_WIDTH_A of pdp_ram_0_5_2 : label is "4"; + attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is ""; + attribute CSDECODE_B of pdp_ram_0_6_1 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_6_1 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_6_1 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_6_1 : label is "NORMAL"; + attribute GSR of pdp_ram_0_6_1 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_6_1 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_6_1 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_6_1 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_6_1 : label is "4"; + attribute DATA_WIDTH_A of pdp_ram_0_6_1 : label is "4"; + attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is ""; + attribute CSDECODE_B of pdp_ram_0_7_0 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_7_0 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_7_0 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_7_0 : label is "NORMAL"; + attribute GSR of pdp_ram_0_7_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_7_0 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_7_0 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_7_0 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_7_0 : label is "4"; + attribute DATA_WIDTH_A of pdp_ram_0_7_0 : label is "4"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t26: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t25: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t24: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t23: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t22: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t21: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t20: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t19: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t18: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t17: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t16: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t15: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t14: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t13: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t12: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t11: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t10: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t9: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t8: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t7: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t6: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t5: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t4: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t3: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t2: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t1: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t0: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + LUT4_33: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_gcount_r212, + DO0=>w_g2b_xor_cluster_0); + + LUT4_32: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_1); + + LUT4_31: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_2); + + LUT4_30: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r11); + + LUT4_29: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_28: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); + + LUT4_27: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_26: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); + + LUT4_25: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_24: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_23: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); + + LUT4_22: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_21: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_20: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_19: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); + + LUT4_18: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_0); + + LUT4_17: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_1); + + LUT4_16: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_2); + + LUT4_15: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w11); + + LUT4_14: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_7: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, + ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, + ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, + ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_1_6: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + -- synopsys translate_on + port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), + DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, + ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, + ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, + ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(4), DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_2_5: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + -- synopsys translate_on + port map (DIA0=>Data(8), DIA1=>Data(9), DIA2=>Data(10), + DIA3=>Data(11), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, + ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, + ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, + ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(8), DOB1=>Q(9), DOB2=>Q(10), + DOB3=>Q(11), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, + DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_3_4: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + -- synopsys translate_on + port map (DIA0=>Data(12), DIA1=>Data(13), DIA2=>Data(14), + DIA3=>Data(15), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, + ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, + ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, + ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(12), DOB1=>Q(13), DOB2=>Q(14), + DOB3=>Q(15), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, + DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_4_3: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + -- synopsys translate_on + port map (DIA0=>Data(16), DIA1=>Data(17), DIA2=>Data(18), + DIA3=>Data(19), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, + ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, + ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, + ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(16), DOB1=>Q(17), DOB2=>Q(18), + DOB3=>Q(19), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, + DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_5_2: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + -- synopsys translate_on + port map (DIA0=>Data(20), DIA1=>Data(21), DIA2=>Data(22), + DIA3=>Data(23), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, + ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, + ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, + ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(20), DOB1=>Q(21), DOB2=>Q(22), + DOB3=>Q(23), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, + DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_6_1: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + -- synopsys translate_on + port map (DIA0=>Data(24), DIA1=>Data(25), DIA2=>Data(26), + DIA3=>Data(27), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, + ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, + ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, + ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(24), DOB1=>Q(25), DOB2=>Q(26), + DOB3=>Q(27), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, + DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_7_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + -- synopsys translate_on + port map (DIA0=>Data(28), DIA1=>Data(29), DIA2=>Data(30), + DIA3=>Data(31), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, + ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, + ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, + ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(28), DOB1=>Q(29), DOB2=>Q(30), + DOB3=>Q(31), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, + DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_131: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_130: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_129: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_128: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_127: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_126: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_125: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_124: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_123: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_122: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_121: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_120: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_119: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_118: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_117: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_116: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_115: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_114: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_113: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_112: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_111: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_110: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_109: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_108: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_107: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_106: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_105: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_104: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_103: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_102: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_101: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_100: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_99: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_98: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_97: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_96: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_95: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_94: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_93: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_92: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_91: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_90: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_89: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_88: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_87: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_86: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_85: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_84: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_83: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_82: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_81: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_80: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_79: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_78: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_77: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_76: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_75: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_74: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_73: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_68: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_64: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_61: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_60: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_59: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_58: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_57: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_56: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_55: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_54: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_53: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_52: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_51: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_50: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_49: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_48: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_47: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_46: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_45: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_44: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_43: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_42: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_41: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_40: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_39: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_38: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_37: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_36: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_35: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_34: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_33: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_32: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_31: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_30: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_29: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_28: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_1: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, + NC0=>iwcount_12, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, + NC0=>ircount_12, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of fifo_4096x32 is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_4096x32_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_4096x32_tmpl.vhd new file mode 100755 index 0000000..745eb44 --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_4096x32_tmpl.vhd @@ -0,0 +1,18 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 5.3 +-- Fri Dec 18 03:02:30 2009 + +-- parameterized module component declaration +component fifo_4096x32 + port (Data: in std_logic_vector(31 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(31 downto 0); + Empty: out std_logic; Full: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_4096x32 + port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_4096x9.lpc b/gbe_ecp2m/ipcores/fifo_4096x9.lpc new file mode 100755 index 0000000..22cb7c6 --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_4096x9.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-5F900C +SpeedGrade=-5 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.2 +ModuleName=fifo_4096x9 +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=01/05/2010 +Time=23:44:15 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4096 +Width=9 +RDepth=4096 +RWidth=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_4096x9.vhd b/gbe_ecp2m/ipcores/fifo_4096x9.vhd new file mode 100755 index 0000000..ca644d2 --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_4096x9.vhd @@ -0,0 +1,2171 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.2 +--/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 4096 -width 9 -depth 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e + +-- Tue Jan 5 23:44:15 2010 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity fifo_4096x9 is + port ( + Data: in std_logic_vector(8 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_4096x9; + +architecture Structure of fifo_4096x9 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_12: std_logic; + signal rptr_11: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal co6: std_logic; + signal wcount_12: std_logic; + signal co5: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal co6_1: std_logic; + signal rcount_12: std_logic; + signal co5_1: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX21 + port (D0: in std_logic; D1: in std_logic; SD: in std_logic; + Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute GSR : string; + attribute initval of LUT4_33 : label is "0x6996"; + attribute initval of LUT4_32 : label is "0x6996"; + attribute initval of LUT4_31 : label is "0x6996"; + attribute initval of LUT4_30 : label is "0x6996"; + attribute initval of LUT4_29 : label is "0x6996"; + attribute initval of LUT4_28 : label is "0x6996"; + attribute initval of LUT4_27 : label is "0x6996"; + attribute initval of LUT4_26 : label is "0x6996"; + attribute initval of LUT4_25 : label is "0x6996"; + attribute initval of LUT4_24 : label is "0x6996"; + attribute initval of LUT4_23 : label is "0x6996"; + attribute initval of LUT4_22 : label is "0x6996"; + attribute initval of LUT4_21 : label is "0x6996"; + attribute initval of LUT4_20 : label is "0x6996"; + attribute initval of LUT4_19 : label is "0x6996"; + attribute initval of LUT4_18 : label is "0x6996"; + attribute initval of LUT4_17 : label is "0x6996"; + attribute initval of LUT4_16 : label is "0x6996"; + attribute initval of LUT4_15 : label is "0x6996"; + attribute initval of LUT4_14 : label is "0x6996"; + attribute initval of LUT4_13 : label is "0x6996"; + attribute initval of LUT4_12 : label is "0x6996"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x6996"; + attribute initval of LUT4_4 : label is "0x6996"; + attribute initval of LUT4_3 : label is "0x0410"; + attribute initval of LUT4_2 : label is "0x1004"; + attribute initval of LUT4_1 : label is "0x0140"; + attribute initval of LUT4_0 : label is "0x4001"; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4096x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute CSDECODE_B of pdp_ram_0_0_1 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_0_1 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_0_1 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_0_1 : label is "NORMAL"; + attribute GSR of pdp_ram_0_0_1 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_0_1 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_0_1 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_0_1 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_0_0_1 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4096x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is ""; + attribute CSDECODE_B of pdp_ram_1_0_0 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_0_0 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_0_0 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_0_0 : label is "NORMAL"; + attribute GSR of pdp_ram_1_0_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_0_0 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_0_0 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_0_0 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_0_0 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_1_0_0 : label is "9"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t26: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t25: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t24: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t23: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t22: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t21: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t20: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t19: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t18: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t17: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t16: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t15: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t14: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t13: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t12: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t11: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t10: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t9: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t8: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t7: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t6: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t5: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t4: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t3: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t2: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t1: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t0: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + LUT4_33: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_gcount_r212, + DO0=>w_g2b_xor_cluster_0); + + LUT4_32: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_1); + + LUT4_31: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_2); + + LUT4_30: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r11); + + LUT4_29: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_28: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); + + LUT4_27: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_26: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); + + LUT4_25: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_24: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_23: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); + + LUT4_22: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_21: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_20: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_19: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); + + LUT4_18: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_0); + + LUT4_17: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_1); + + LUT4_16: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_2); + + LUT4_15: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w11); + + LUT4_14: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA0=>wptr_11, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>rptr_11, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, + DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, + DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, + DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_1_0_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA0=>wptr_11, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>rptr_11, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, + DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, + DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, + DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + FF_132: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_131: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_130: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_129: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_128: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_127: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_126: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_125: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_124: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_123: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_122: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_121: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_120: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_119: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_118: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_117: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_116: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_115: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_114: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_113: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_112: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_111: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_110: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_109: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_108: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_107: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_106: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_105: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_104: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_103: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_102: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_101: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_100: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_99: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_98: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_97: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_96: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_95: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_94: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_93: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_92: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_91: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_90: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_89: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_88: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_87: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_86: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_85: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_84: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_83: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_82: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_81: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_80: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_79: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_78: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_77: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_76: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_75: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_74: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_73: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_68: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_64: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_61: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_60: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_59: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_58: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_57: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_56: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_55: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_54: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_53: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_52: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_51: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_50: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_49: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_48: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_47: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_46: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_45: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_44: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_43: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_42: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_41: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_40: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_39: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_38: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_37: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_36: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_35: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_34: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_33: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_32: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_31: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_30: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_29: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_28: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_1: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, + NC0=>iwcount_12, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, + NC0=>ircount_12, NC1=>open); + + mux_8: MUX21 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff, + Z=>Q(0)); + + mux_7: MUX21 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff, + Z=>Q(1)); + + mux_6: MUX21 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff, + Z=>Q(2)); + + mux_5: MUX21 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff, + Z=>Q(3)); + + mux_4: MUX21 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff, + Z=>Q(4)); + + mux_3: MUX21 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff, + Z=>Q(5)); + + mux_2: MUX21 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff, + Z=>Q(6)); + + mux_1: MUX21 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff, + Z=>Q(7)); + + mux_0: MUX21 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff, + Z=>Q(8)); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of fifo_4096x9 is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:MUX21 use entity ecp2m.MUX21(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_4096x9_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_4096x9_tmpl.vhd new file mode 100755 index 0000000..f754d74 --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_4096x9_tmpl.vhd @@ -0,0 +1,18 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.2 +-- Tue Jan 5 23:44:15 2010 + +-- parameterized module component declaration +component fifo_4096x9 + port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic; + RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; + Reset: in std_logic; RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_4096x9 + port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_64kx8.lpc b/gbe_ecp2m/ipcores/fifo_64kx8.lpc new file mode 100755 index 0000000..3d27821 --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_64kx8.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-5F900C +SpeedGrade=-5 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.2 +ModuleName=fifo_64kx8 +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=12/26/2009 +Time=00:12:05 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=65536 +Width=8 +RDepth=65536 +RWidth=8 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_64kx8.vhd b/gbe_ecp2m/ipcores/fifo_64kx8.vhd new file mode 100755 index 0000000..ba79880 --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_64kx8.vhd @@ -0,0 +1,4435 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.2 +--/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 65536 -width 8 -depth 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e + +-- Sat Dec 26 00:12:05 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity fifo_64kx8 is + port ( + Data: in std_logic_vector(7 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_64kx8; + +architecture Structure of fifo_64kx8 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_3: std_logic; + signal func_xor_inet_2: std_logic; + signal func_xor_inet_1: std_logic; + signal func_xor_inet: std_logic; + signal func_xor_inet_4: std_logic; + signal func_xor_inet_5: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_9: std_logic; + signal func_xor_inet_8: std_logic; + signal func_xor_inet_7: std_logic; + signal func_xor_inet_6: std_logic; + signal func_xor_inet_10: std_logic; + signal func_xor_inet_11: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal w_gdata_15: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wptr_15: std_logic; + signal wptr_16: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal r_gdata_15: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal rptr_16: std_logic; + signal rptr_14: std_logic; + signal rptr_15: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal w_gcount_16: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal r_gcount_16: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal w_gcount_r216: std_logic; + signal w_gcount_r16: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal r_gcount_w216: std_logic; + signal r_gcount_w16: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co6: std_logic; + signal iwcount_16: std_logic; + signal co8: std_logic; + signal wcount_16: std_logic; + signal co7: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_1: std_logic; + signal ircount_16: std_logic; + signal co8_1: std_logic; + signal rcount_16: std_logic; + signal co7_1: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal rptr_15_ff: std_logic; + signal rptr_14_ff: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal wcount_r12: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_2: std_logic; + signal wcount_r14: std_logic; + signal wcount_r15: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal co7_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal rcount_w9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal rcount_w12: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_3: std_logic; + signal rcount_w14: std_logic; + signal rcount_w15: std_logic; + signal wcount_14: std_logic; + signal wcount_15: std_logic; + signal co7_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX41 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; SD1: in std_logic; SD2: in std_logic; + Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute GSR : string; + attribute initval of LUT4_59 : label is "0x6996"; + attribute initval of LUT4_58 : label is "0x6996"; + attribute initval of LUT4_57 : label is "0x6996"; + attribute initval of LUT4_56 : label is "0x6996"; + attribute initval of LUT4_55 : label is "0x6996"; + attribute initval of LUT4_54 : label is "0x6996"; + attribute initval of LUT4_53 : label is "0x6996"; + attribute initval of LUT4_52 : label is "0x6996"; + attribute initval of LUT4_51 : label is "0x6996"; + attribute initval of LUT4_50 : label is "0x6996"; + attribute initval of LUT4_49 : label is "0x6996"; + attribute initval of LUT4_48 : label is "0x6996"; + attribute initval of LUT4_47 : label is "0x6996"; + attribute initval of LUT4_46 : label is "0x6996"; + attribute initval of LUT4_45 : label is "0x6996"; + attribute initval of LUT4_44 : label is "0x6996"; + attribute initval of LUT4_43 : label is "0x6996"; + attribute initval of LUT4_42 : label is "0x6996"; + attribute initval of LUT4_41 : label is "0x6996"; + attribute initval of LUT4_40 : label is "0x6996"; + attribute initval of LUT4_39 : label is "0x6996"; + attribute initval of LUT4_38 : label is "0x6996"; + attribute initval of LUT4_37 : label is "0x6996"; + attribute initval of LUT4_36 : label is "0x6996"; + attribute initval of LUT4_35 : label is "0x6996"; + attribute initval of LUT4_34 : label is "0x6996"; + attribute initval of LUT4_33 : label is "0x6996"; + attribute initval of LUT4_32 : label is "0x6996"; + attribute initval of LUT4_31 : label is "0x6996"; + attribute initval of LUT4_30 : label is "0x6996"; + attribute initval of LUT4_29 : label is "0x6996"; + attribute initval of LUT4_28 : label is "0x6996"; + attribute initval of LUT4_27 : label is "0x6996"; + attribute initval of LUT4_26 : label is "0x6996"; + attribute initval of LUT4_25 : label is "0x6996"; + attribute initval of LUT4_24 : label is "0x6996"; + attribute initval of LUT4_23 : label is "0x6996"; + attribute initval of LUT4_22 : label is "0x6996"; + attribute initval of LUT4_21 : label is "0x6996"; + attribute initval of LUT4_20 : label is "0x6996"; + attribute initval of LUT4_19 : label is "0x6996"; + attribute initval of LUT4_18 : label is "0x6996"; + attribute initval of LUT4_17 : label is "0x6996"; + attribute initval of LUT4_16 : label is "0x6996"; + attribute initval of LUT4_15 : label is "0x6996"; + attribute initval of LUT4_14 : label is "0x6996"; + attribute initval of LUT4_13 : label is "0x6996"; + attribute initval of LUT4_12 : label is "0x6996"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x6996"; + attribute initval of LUT4_4 : label is "0x6996"; + attribute initval of LUT4_3 : label is "0x0410"; + attribute initval of LUT4_2 : label is "0x1004"; + attribute initval of LUT4_1 : label is "0x0140"; + attribute initval of LUT4_0 : label is "0x4001"; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL"; + attribute GSR of pdp_ram_0_0_31 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is ""; + attribute CSDECODE_B of pdp_ram_0_1_30 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_1_30 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_1_30 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_1_30 : label is "NORMAL"; + attribute GSR of pdp_ram_0_1_30 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_1_30 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_1_30 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_1_30 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_1_30 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_1_30 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is ""; + attribute CSDECODE_B of pdp_ram_0_2_29 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_2_29 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_2_29 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_2_29 : label is "NORMAL"; + attribute GSR of pdp_ram_0_2_29 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_2_29 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_2_29 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_2_29 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_2_29 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_2_29 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is ""; + attribute CSDECODE_B of pdp_ram_0_3_28 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_3_28 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_3_28 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_3_28 : label is "NORMAL"; + attribute GSR of pdp_ram_0_3_28 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_3_28 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_3_28 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_3_28 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_3_28 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_3_28 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is ""; + attribute CSDECODE_B of pdp_ram_0_4_27 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_4_27 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_4_27 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_4_27 : label is "NORMAL"; + attribute GSR of pdp_ram_0_4_27 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_4_27 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_4_27 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_4_27 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_4_27 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_4_27 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is ""; + attribute CSDECODE_B of pdp_ram_0_5_26 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_5_26 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_5_26 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_5_26 : label is "NORMAL"; + attribute GSR of pdp_ram_0_5_26 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_5_26 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_5_26 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_5_26 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_5_26 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_5_26 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is ""; + attribute CSDECODE_B of pdp_ram_0_6_25 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_6_25 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_6_25 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_6_25 : label is "NORMAL"; + attribute GSR of pdp_ram_0_6_25 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_6_25 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_6_25 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_6_25 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_6_25 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_6_25 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is ""; + attribute CSDECODE_B of pdp_ram_0_7_24 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_7_24 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_7_24 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_7_24 : label is "NORMAL"; + attribute GSR of pdp_ram_0_7_24 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_7_24 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_7_24 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_7_24 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_7_24 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_7_24 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is ""; + attribute CSDECODE_B of pdp_ram_1_0_23 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_0_23 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_0_23 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_0_23 : label is "NORMAL"; + attribute GSR of pdp_ram_1_0_23 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_0_23 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_0_23 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_0_23 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_0_23 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_0_23 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is ""; + attribute CSDECODE_B of pdp_ram_1_1_22 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_1_22 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_1_22 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_1_22 : label is "NORMAL"; + attribute GSR of pdp_ram_1_1_22 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_1_22 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_1_22 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_1_22 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_1_22 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_1_22 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is ""; + attribute CSDECODE_B of pdp_ram_1_2_21 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_2_21 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_2_21 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_2_21 : label is "NORMAL"; + attribute GSR of pdp_ram_1_2_21 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_2_21 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_2_21 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_2_21 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_2_21 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_2_21 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is ""; + attribute CSDECODE_B of pdp_ram_1_3_20 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_3_20 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_3_20 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_3_20 : label is "NORMAL"; + attribute GSR of pdp_ram_1_3_20 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_3_20 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_3_20 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_3_20 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_3_20 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_3_20 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is ""; + attribute CSDECODE_B of pdp_ram_1_4_19 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_4_19 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_4_19 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_4_19 : label is "NORMAL"; + attribute GSR of pdp_ram_1_4_19 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_4_19 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_4_19 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_4_19 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_4_19 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_4_19 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is ""; + attribute CSDECODE_B of pdp_ram_1_5_18 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_5_18 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_5_18 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_5_18 : label is "NORMAL"; + attribute GSR of pdp_ram_1_5_18 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_5_18 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_5_18 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_5_18 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_5_18 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_5_18 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is ""; + attribute CSDECODE_B of pdp_ram_1_6_17 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_6_17 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_6_17 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_6_17 : label is "NORMAL"; + attribute GSR of pdp_ram_1_6_17 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_6_17 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_6_17 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_6_17 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_6_17 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_6_17 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is ""; + attribute CSDECODE_B of pdp_ram_1_7_16 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_7_16 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_7_16 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_7_16 : label is "NORMAL"; + attribute GSR of pdp_ram_1_7_16 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_7_16 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_7_16 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_7_16 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_7_16 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_1_7_16 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is ""; + attribute CSDECODE_B of pdp_ram_2_0_15 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_0_15 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_0_15 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_0_15 : label is "NORMAL"; + attribute GSR of pdp_ram_2_0_15 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_0_15 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_0_15 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_0_15 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_0_15 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_0_15 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is ""; + attribute CSDECODE_B of pdp_ram_2_1_14 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_1_14 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_1_14 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_1_14 : label is "NORMAL"; + attribute GSR of pdp_ram_2_1_14 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_1_14 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_1_14 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_1_14 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_1_14 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_1_14 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is ""; + attribute CSDECODE_B of pdp_ram_2_2_13 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_2_13 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_2_13 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_2_13 : label is "NORMAL"; + attribute GSR of pdp_ram_2_2_13 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_2_13 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_2_13 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_2_13 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_2_13 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_2_13 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is ""; + attribute CSDECODE_B of pdp_ram_2_3_12 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_3_12 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_3_12 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_3_12 : label is "NORMAL"; + attribute GSR of pdp_ram_2_3_12 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_3_12 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_3_12 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_3_12 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_3_12 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_3_12 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is ""; + attribute CSDECODE_B of pdp_ram_2_4_11 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_4_11 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_4_11 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_4_11 : label is "NORMAL"; + attribute GSR of pdp_ram_2_4_11 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_4_11 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_4_11 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_4_11 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_4_11 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_4_11 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is ""; + attribute CSDECODE_B of pdp_ram_2_5_10 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_5_10 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_5_10 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_5_10 : label is "NORMAL"; + attribute GSR of pdp_ram_2_5_10 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_5_10 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_5_10 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_5_10 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_5_10 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_5_10 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is ""; + attribute CSDECODE_B of pdp_ram_2_6_9 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_6_9 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_6_9 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_6_9 : label is "NORMAL"; + attribute GSR of pdp_ram_2_6_9 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_6_9 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_6_9 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_6_9 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_6_9 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_6_9 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is ""; + attribute CSDECODE_B of pdp_ram_2_7_8 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_7_8 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_7_8 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_7_8 : label is "NORMAL"; + attribute GSR of pdp_ram_2_7_8 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_7_8 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_7_8 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_7_8 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_7_8 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_2_7_8 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is ""; + attribute CSDECODE_B of pdp_ram_3_0_7 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_0_7 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_0_7 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_0_7 : label is "NORMAL"; + attribute GSR of pdp_ram_3_0_7 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_0_7 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_0_7 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_0_7 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_0_7 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_0_7 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is ""; + attribute CSDECODE_B of pdp_ram_3_1_6 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_1_6 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_1_6 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_1_6 : label is "NORMAL"; + attribute GSR of pdp_ram_3_1_6 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_1_6 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_1_6 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_1_6 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_1_6 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_1_6 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is ""; + attribute CSDECODE_B of pdp_ram_3_2_5 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_2_5 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_2_5 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_2_5 : label is "NORMAL"; + attribute GSR of pdp_ram_3_2_5 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_2_5 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_2_5 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_2_5 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_2_5 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_2_5 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is ""; + attribute CSDECODE_B of pdp_ram_3_3_4 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_3_4 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_3_4 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_3_4 : label is "NORMAL"; + attribute GSR of pdp_ram_3_3_4 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_3_4 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_3_4 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_3_4 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_3_4 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_3_4 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is ""; + attribute CSDECODE_B of pdp_ram_3_4_3 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_4_3 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_4_3 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_4_3 : label is "NORMAL"; + attribute GSR of pdp_ram_3_4_3 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_4_3 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_4_3 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_4_3 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_4_3 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_4_3 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is ""; + attribute CSDECODE_B of pdp_ram_3_5_2 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_5_2 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_5_2 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_5_2 : label is "NORMAL"; + attribute GSR of pdp_ram_3_5_2 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_5_2 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_5_2 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_5_2 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_5_2 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_5_2 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is ""; + attribute CSDECODE_B of pdp_ram_3_6_1 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_6_1 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_6_1 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_6_1 : label is "NORMAL"; + attribute GSR of pdp_ram_3_6_1 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_6_1 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_6_1 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_6_1 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_6_1 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_6_1 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is ""; + attribute CSDECODE_B of pdp_ram_3_7_0 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_7_0 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_7_0 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_7_0 : label is "NORMAL"; + attribute GSR of pdp_ram_3_7_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_7_0 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_7_0 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_7_0 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_7_0 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_3_7_0 : label is "1"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t34: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t33: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t32: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t31: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t30: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t29: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t28: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t27: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t26: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t25: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t24: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t23: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t22: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t21: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t20: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t19: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t18: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t17: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t16: XOR2 + port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15); + + XOR2_t15: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t14: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t13: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t12: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t11: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t10: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t9: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t8: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t7: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t6: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t5: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t4: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t3: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t2: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t1: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + XOR2_t0: XOR2 + port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); + + LUT4_59: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>w_gcount_r216, + DO0=>w_g2b_xor_cluster_0); + + LUT4_58: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_gcount_r212, + DO0=>w_g2b_xor_cluster_1); + + LUT4_57: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_2); + + LUT4_56: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_3); + + LUT4_55: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r15); + + LUT4_54: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, + AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_53: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); + + LUT4_52: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_51: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, + DO0=>wcount_r10); + + LUT4_50: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_49: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_48: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); + + LUT4_47: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_46: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); + + LUT4_45: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_44: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); + + LUT4_43: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_42: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r3); + + LUT4_41: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_40: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r2); + + LUT4_39: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r1); + + LUT4_38: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); + + LUT4_37: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); + + LUT4_36: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); + + LUT4_35: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); + + LUT4_34: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_4); + + LUT4_33: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, + AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, + DO0=>func_xor_inet_5); + + LUT4_32: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_31: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>r_gcount_w216, + DO0=>r_g2b_xor_cluster_0); + + LUT4_30: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_1); + + LUT4_29: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_2); + + LUT4_28: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_3); + + LUT4_27: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w15); + + LUT4_26: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, + AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_25: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); + + LUT4_24: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_23: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, + DO0=>rcount_w10); + + LUT4_22: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_21: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_20: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); + + LUT4_19: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_18: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_17: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_16: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); + + LUT4_15: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_14: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w3); + + LUT4_13: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w2); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_10); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, + AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, + DO0=>func_xor_inet_11); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_31: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_0, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_1_30: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_1, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_2_29: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_2, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_3_28: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_3, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_4_27: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_4, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_5_26: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_5, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_6_25: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_6, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_7_24: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_7, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_0_23: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_0, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_1_22: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_1, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_2_21: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_2, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_3_20: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_3, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_4_19: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_4, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_5_18: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_5, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_6_17: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_6, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_7_16: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_7, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_0_15: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_0, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_1_14: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_1, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_2_13: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_2, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_3_12: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_3, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_4_11: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_4, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_5_10: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_5, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_6_9: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_6, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_7_8: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_7, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_0_7: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_0, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_1_6: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_1, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_2_5: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_2, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_3_4: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_3, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_4_3: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_4, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_5_2: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_5, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_6_1: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_6, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_7_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_7, DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + FF_173: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_172: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_171: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_170: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_169: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_168: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_167: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_166: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_165: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_164: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_163: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_162: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_161: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_160: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_159: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_158: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_157: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_16); + + FF_156: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_155: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_154: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_153: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_152: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_151: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_150: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_149: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_148: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_147: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_146: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_145: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_144: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_143: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_142: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_141: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_140: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_16); + + FF_139: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_138: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_137: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_136: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_135: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_134: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_133: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_132: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_131: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_130: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_129: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_128: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_127: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_126: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_125: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_124: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_123: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_16); + + FF_122: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_121: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_120: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_119: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_118: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_117: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_116: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_115: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_114: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_113: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_112: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_111: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_110: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_109: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_108: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_107: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_106: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_16); + + FF_105: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_104: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_103: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_102: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_101: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_100: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_99: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_98: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_97: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_96: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_95: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_94: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_93: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_92: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_91: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_90: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_89: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_16); + + FF_88: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_87: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_86: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_85: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_84: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_83: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_82: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_81: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_80: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_79: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_78: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_77: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_76: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_75: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_74: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_73: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_16); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_15_ff); + + FF_69: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_68: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_67: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_66: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_65: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_64: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_63: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_62: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_61: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_60: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_59: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_58: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_57: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_56: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_55: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_54: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_53: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r16); + + FF_52: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_51: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_50: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_49: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_48: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_47: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_46: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_45: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_44: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_43: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_42: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_41: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_40: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_39: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_38: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_37: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_36: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); + + FF_35: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_34: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_33: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_32: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_31: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_30: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_29: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_28: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r216); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w216); + + FF_1: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + w_gctr_8: CU2 + port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, + NC0=>iwcount_16, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + r_gctr_8: CU2 + port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, + NC0=>ircount_16, NC1=>open); + + mux_7: MUX41 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0)); + + mux_6: MUX41 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1)); + + mux_5: MUX41 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2)); + + mux_4: MUX41 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3)); + + mux_3: MUX41 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4)); + + mux_2: MUX41 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5)); + + mux_1: MUX41 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6)); + + mux_0: MUX41 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7)); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, + B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, + B1=>wcount_r15, CI=>co6_2, GE=>co7_2); + + empty_cmp_8: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, + B1=>rcount_w15, CI=>co6_3, GE=>co7_3); + + full_cmp_8: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of fifo_64kx8 is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:MUX41 use entity ecp2m.MUX41(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_64kx8_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_64kx8_tmpl.vhd new file mode 100755 index 0000000..c0c7959 --- /dev/null +++ b/gbe_ecp2m/ipcores/fifo_64kx8_tmpl.vhd @@ -0,0 +1,18 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.2 +-- Sat Dec 26 00:12:05 2009 + +-- parameterized module component declaration +component fifo_64kx8 + port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; + RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; + Reset: in std_logic; RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_64kx8 + port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/gbe_ecp2m/ipcores/ip_mem.lpc b/gbe_ecp2m/ipcores/ip_mem.lpc new file mode 100755 index 0000000..8383be6 --- /dev/null +++ b/gbe_ecp2m/ipcores/ip_mem.lpc @@ -0,0 +1,57 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-5F900C +SpeedGrade=-5 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_DP_TRUE +CoreRevision=7.1 +ModuleName=ip_mem +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=03/29/2010 +Time=21:52:48 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +AAddress=256 +BAddress=256 +AData=32 +BData=32 +enByte=0 +ByteSize=9 +AadPipeline=0 +BadPipeline=0 +AinPipeline=0 +BinPipeline=0 +AoutPipeline=0 +BoutPipeline=1 +AMOR=0 +BMOR=0 +AInData=Registered +BInData=Registered +AAdControl=Registered +BAdControl=Registered +MemFile=/home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem +MemFormat=orca +Reset=Sync +GSR=Enabled +WriteA=Normal +WriteB=Normal +Pad=0 +EnECC=0 +Optimization=Speed +Pipeline=0 diff --git a/gbe_ecp2m/ipcores/ip_mem.mem b/gbe_ecp2m/ipcores/ip_mem.mem new file mode 100755 index 0000000..836ca91 --- /dev/null +++ b/gbe_ecp2m/ipcores/ip_mem.mem @@ -0,0 +1,277 @@ +#Format=Address-Hex +#Depth=256 +#DataWidth=32 +#AddrRadix=3 +#DataRadix=3 + +00: 214397e9 +01: 0000001b +02: c0a80002 +03: 0000c350 +04: 023bdc00 +05: 00000013 +06: c0a80005 +07: 0000c350 +08: 00000578 +09: 00000000 +0a: 00000000 +0b: 00000000 +0c: 00000000 +0d: 00000000 +0e: 00000000 +0f: 00000000 + +10: 214397e9 +11: 0000001b +12: c0a80002 +13: 0000c351 +14: 023bdc01 +15: 00000013 +16: c0a80006 +17: 0000c350 +18: 00000578 +19: 00000000 +1a: 00000000 +1b: 00000000 +1c: 00000000 +1d: 00000000 +1e: 00000000 +1f: 00000000 + +20: 214397e9 +21: 0000001b +22: c0a80002 +23: 0000c352 +24: 023bdc02 +25: 00000013 +26: c0a80007 +27: 0000c350 +28: 00000578 +29: 00000000 +2a: 00000000 +2b: 00000000 +2c: 00000000 +2d: 00000000 +2e: 00000000 +2f: 00000000 + +30: 214397e9 +31: 0000001b +32: c0a80002 +33: 0000c353 +34: 023bdc03 +35: 00000013 +36: c0a80008 +37: 0000c350 +38: 00000578 +39: 00000000 +3a: 00000000 +3b: 00000000 +3c: 00000000 +3d: 00000000 +3e: 00000000 +3f: 00000000 + +40: 00000000 +41: 00000000 +42: 00000000 +43: 00000000 +44: 00000000 +45: 00000000 +46: 00000000 +47: 00000000 +48: 00000578 +49: 00000000 +4a: 00000000 +4b: 00000000 +4c: 00000000 +4d: 00000000 +4e: 00000000 +4f: 00000000 + +50: 00000000 +51: 00000000 +52: 00000000 +53: 00000000 +54: 00000000 +55: 00000000 +56: 00000000 +57: 00000000 +58: 00000578 +59: 00000000 +5a: 00000000 +5b: 00000000 +5c: 00000000 +5d: 00000000 +5e: 00000000 +5f: 00000000 + +60: 00000000 +61: 00000000 +62: 00000000 +63: 00000000 +64: 00000000 +65: 00000000 +66: 00000000 +67: 00000000 +68: 00000578 +69: 00000000 +6a: 00000000 +6b: 00000000 +6c: 00000000 +6d: 00000000 +6e: 00000000 +6f: 00000000 + +70: 00000000 +71: 00000000 +72: 00000000 +73: 00000000 +74: 00000000 +75: 00000000 +76: 00000000 +77: 00000000 +78: 00000578 +79: 00000000 +7a: 00000000 +7b: 00000000 +7c: 00000000 +7d: 00000000 +7e: 00000000 +7f: 00000000 + +80: 00000000 +81: 00000000 +82: 00000000 +83: 00000000 +84: 00000000 +85: 00000000 +86: 00000000 +87: 00000000 +88: 00000578 +89: 00000000 +8a: 00000000 +8b: 00000000 +8c: 00000000 +8d: 00000000 +8e: 00000000 +8f: 00000000 + +90: 00000000 +91: 00000000 +92: 00000000 +93: 00000000 +94: 00000000 +95: 00000000 +96: 00000000 +97: 00000000 +98: 00000578 +99: 00000000 +9a: 00000000 +9b: 00000000 +9c: 00000000 +9d: 00000000 +9e: 00000000 +9f: 00000000 + +a0: 00000000 +a1: 00000000 +a2: 00000000 +a3: 00000000 +a4: 00000000 +a5: 00000000 +a6: 00000000 +a7: 00000000 +a8: 00000578 +a9: 00000000 +aa: 00000000 +ab: 00000000 +ac: 00000000 +ad: 00000000 +ae: 00000000 +af: 00000000 + +b0: 00000000 +b1: 00000000 +b2: 00000000 +b3: 00000000 +b4: 00000000 +b5: 00000000 +b6: 00000000 +b7: 00000000 +b8: 00000578 +b9: 00000000 +ba: 00000000 +bb: 00000000 +bc: 00000000 +bd: 00000000 +be: 00000000 +bf: 00000000 + +c0: 00000000 +c1: 00000000 +c2: 00000000 +c3: 00000000 +c4: 00000000 +c5: 00000000 +c6: 00000000 +c7: 00000000 +c8: 00000578 +c9: 00000000 +ca: 00000000 +cb: 00000000 +cc: 00000000 +cd: 00000000 +ce: 00000000 +cf: 00000000 + +d0: 00000000 +d1: 00000000 +d2: 00000000 +d3: 00000000 +d4: 00000000 +d5: 00000000 +d6: 00000000 +d7: 00000000 +d8: 00000578 +d9: 00000000 +da: 00000000 +db: 00000000 +dc: 00000000 +dd: 00000000 +de: 00000000 +df: 00000000 + +e0: 00000000 +e1: 00000000 +e2: 00000000 +e3: 00000000 +e4: 00000000 +e5: 00000000 +e6: 00000000 +e7: 00000000 +e8: 00000578 +e9: 00000000 +ea: 00000000 +eb: 00000000 +ec: 00000000 +ed: 00000000 +ee: 00000000 +ef: 00000000 + +f0: 00000000 +f1: 00000000 +f2: 00000000 +f3: 00000000 +f4: 00000000 +f5: 00000000 +f6: 00000000 +f7: 00000000 +f8: 00000578 +f9: 00000000 +fa: 00000000 +fb: 00000000 +fc: 00000000 +fd: 00000000 +fe: 00000000 +ff: 00000000 diff --git a/gbe_ecp2m/ipcores/ip_mem.vhd b/gbe_ecp2m/ipcores/ip_mem.vhd new file mode 100755 index 0000000..cfa2c6e --- /dev/null +++ b/gbe_ecp2m/ipcores/ip_mem.vhd @@ -0,0 +1,606 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 7.1 +--/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 32 -num_rows 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -memfile /home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem -memformat orca -cascade -1 -e + +-- Mon Mar 29 21:52:49 2010 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity ip_mem is + port ( + DataInA: in std_logic_vector(31 downto 0); + DataInB: in std_logic_vector(31 downto 0); + AddressA: in std_logic_vector(7 downto 0); + AddressB: in std_logic_vector(7 downto 0); + ClockA: in std_logic; + ClockB: in std_logic; + ClockEnA: in std_logic; + ClockEnB: in std_logic; + WrA: in std_logic; + WrB: in std_logic; + ResetA: in std_logic; + ResetB: in std_logic; + QA: out std_logic_vector(31 downto 0); + QB: out std_logic_vector(31 downto 0)); +end ip_mem; + +architecture Structure of ip_mem is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (INITVAL_3F : in String; INITVAL_3E : in String; + INITVAL_3D : in String; INITVAL_3C : in String; + INITVAL_3B : in String; INITVAL_3A : in String; + INITVAL_39 : in String; INITVAL_38 : in String; + INITVAL_37 : in String; INITVAL_36 : in String; + INITVAL_35 : in String; INITVAL_34 : in String; + INITVAL_33 : in String; INITVAL_32 : in String; + INITVAL_31 : in String; INITVAL_30 : in String; + INITVAL_2F : in String; INITVAL_2E : in String; + INITVAL_2D : in String; INITVAL_2C : in String; + INITVAL_2B : in String; INITVAL_2A : in String; + INITVAL_29 : in String; INITVAL_28 : in String; + INITVAL_27 : in String; INITVAL_26 : in String; + INITVAL_25 : in String; INITVAL_24 : in String; + INITVAL_23 : in String; INITVAL_22 : in String; + INITVAL_21 : in String; INITVAL_20 : in String; + INITVAL_1F : in String; INITVAL_1E : in String; + INITVAL_1D : in String; INITVAL_1C : in String; + INITVAL_1B : in String; INITVAL_1A : in String; + INITVAL_19 : in String; INITVAL_18 : in String; + INITVAL_17 : in String; INITVAL_16 : in String; + INITVAL_15 : in String; INITVAL_14 : in String; + INITVAL_13 : in String; INITVAL_12 : in String; + INITVAL_11 : in String; INITVAL_10 : in String; + INITVAL_0F : in String; INITVAL_0E : in String; + INITVAL_0D : in String; INITVAL_0C : in String; + INITVAL_0B : in String; INITVAL_0A : in String; + INITVAL_09 : in String; INITVAL_08 : in String; + INITVAL_07 : in String; INITVAL_06 : in String; + INITVAL_05 : in String; INITVAL_04 : in String; + INITVAL_03 : in String; INITVAL_02 : in String; + INITVAL_01 : in String; INITVAL_00 : in String; + GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute INITVAL_3F : string; + attribute INITVAL_3E : string; + attribute INITVAL_3D : string; + attribute INITVAL_3C : string; + attribute INITVAL_3B : string; + attribute INITVAL_3A : string; + attribute INITVAL_39 : string; + attribute INITVAL_38 : string; + attribute INITVAL_37 : string; + attribute INITVAL_36 : string; + attribute INITVAL_35 : string; + attribute INITVAL_34 : string; + attribute INITVAL_33 : string; + attribute INITVAL_32 : string; + attribute INITVAL_31 : string; + attribute INITVAL_30 : string; + attribute INITVAL_2F : string; + attribute INITVAL_2E : string; + attribute INITVAL_2D : string; + attribute INITVAL_2C : string; + attribute INITVAL_2B : string; + attribute INITVAL_2A : string; + attribute INITVAL_29 : string; + attribute INITVAL_28 : string; + attribute INITVAL_27 : string; + attribute INITVAL_26 : string; + attribute INITVAL_25 : string; + attribute INITVAL_24 : string; + attribute INITVAL_23 : string; + attribute INITVAL_22 : string; + attribute INITVAL_21 : string; + attribute INITVAL_20 : string; + attribute INITVAL_1F : string; + attribute INITVAL_1E : string; + attribute INITVAL_1D : string; + attribute INITVAL_1C : string; + attribute INITVAL_1B : string; + attribute INITVAL_1A : string; + attribute INITVAL_19 : string; + attribute INITVAL_18 : string; + attribute INITVAL_17 : string; + attribute INITVAL_16 : string; + attribute INITVAL_15 : string; + attribute INITVAL_14 : string; + attribute INITVAL_13 : string; + attribute INITVAL_12 : string; + attribute INITVAL_11 : string; + attribute INITVAL_10 : string; + attribute INITVAL_0F : string; + attribute INITVAL_0E : string; + attribute INITVAL_0D : string; + attribute INITVAL_0C : string; + attribute INITVAL_0B : string; + attribute INITVAL_0A : string; + attribute INITVAL_09 : string; + attribute INITVAL_08 : string; + attribute INITVAL_07 : string; + attribute INITVAL_06 : string; + attribute INITVAL_05 : string; + attribute INITVAL_04 : string; + attribute INITVAL_03 : string; + attribute INITVAL_02 : string; + attribute INITVAL_01 : string; + attribute INITVAL_00 : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute GSR : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute MEM_LPC_FILE of ip_mem_0_0_1 : label is "ip_mem.lpc"; + attribute MEM_INIT_FILE of ip_mem_0_0_1 : label is "ip_mem.mem"; + attribute INITVAL_3F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_39 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_38 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_37 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_36 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_35 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_34 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_33 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_32 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_31 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_30 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_29 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_28 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_27 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_26 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_25 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_24 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_23 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_22 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_21 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_20 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_19 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_18 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_17 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_16 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_15 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_14 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_13 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_12 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_11 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_10 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_0F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; + attribute INITVAL_0E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; + attribute INITVAL_0D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; + attribute INITVAL_0C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; + attribute INITVAL_0B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; + attribute INITVAL_0A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; + attribute INITVAL_09 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; + attribute INITVAL_08 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; + attribute INITVAL_07 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; + attribute INITVAL_06 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; + attribute INITVAL_05 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; + attribute INITVAL_04 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; + attribute INITVAL_03 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9"; + attribute INITVAL_02 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9"; + attribute INITVAL_01 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9"; + attribute INITVAL_00 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9"; + attribute CSDECODE_B of ip_mem_0_0_1 : label is "0b000"; + attribute CSDECODE_A of ip_mem_0_0_1 : label is "0b000"; + attribute WRITEMODE_B of ip_mem_0_0_1 : label is "NORMAL"; + attribute WRITEMODE_A of ip_mem_0_0_1 : label is "NORMAL"; + attribute GSR of ip_mem_0_0_1 : label is "DISABLED"; + attribute RESETMODE of ip_mem_0_0_1 : label is "SYNC"; + attribute REGMODE_B of ip_mem_0_0_1 : label is "OUTREG"; + attribute REGMODE_A of ip_mem_0_0_1 : label is "NOREG"; + attribute DATA_WIDTH_B of ip_mem_0_0_1 : label is "18"; + attribute DATA_WIDTH_A of ip_mem_0_0_1 : label is "18"; + attribute MEM_LPC_FILE of ip_mem_0_1_0 : label is "ip_mem.lpc"; + attribute MEM_INIT_FILE of ip_mem_0_1_0 : label is "ip_mem.mem"; + attribute INITVAL_3F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_39 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_38 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_37 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_36 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_35 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_34 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_33 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_32 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_31 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_30 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_29 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_28 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_27 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_26 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_25 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_24 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_23 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_22 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_21 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_20 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_19 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_18 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_17 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_16 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_15 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_14 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_13 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_12 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_11 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_10 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_0F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_0E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_0D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_0C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_0B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_0A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_09 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_08 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_07 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_06 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_05 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_04 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_03 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850"; + attribute INITVAL_02 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850"; + attribute INITVAL_01 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850"; + attribute INITVAL_00 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850"; + attribute CSDECODE_B of ip_mem_0_1_0 : label is "0b000"; + attribute CSDECODE_A of ip_mem_0_1_0 : label is "0b000"; + attribute WRITEMODE_B of ip_mem_0_1_0 : label is "NORMAL"; + attribute WRITEMODE_A of ip_mem_0_1_0 : label is "NORMAL"; + attribute GSR of ip_mem_0_1_0 : label is "DISABLED"; + attribute RESETMODE of ip_mem_0_1_0 : label is "SYNC"; + attribute REGMODE_B of ip_mem_0_1_0 : label is "OUTREG"; + attribute REGMODE_A of ip_mem_0_1_0 : label is "NOREG"; + attribute DATA_WIDTH_B of ip_mem_0_1_0 : label is "18"; + attribute DATA_WIDTH_A of ip_mem_0_1_0 : label is "18"; + +begin + -- component instantiation statements + ip_mem_0_0_1: DP16KB + -- synopsys translate_off + generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_03=> "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9", + INITVAL_02=> "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9", + INITVAL_01=> "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9", + INITVAL_00=> "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9", + CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + -- synopsys translate_on + port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2), + DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5), + DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8), + DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11), + DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14), + DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17), + ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, + ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1), + ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4), + ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7), + ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA, + CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(0), + DIB1=>DataInB(1), DIB2=>DataInB(2), DIB3=>DataInB(3), + DIB4=>DataInB(4), DIB5=>DataInB(5), DIB6=>DataInB(6), + DIB7=>DataInB(7), DIB8=>DataInB(8), DIB9=>DataInB(9), + DIB10=>DataInB(10), DIB11=>DataInB(11), DIB12=>DataInB(12), + DIB13=>DataInB(13), DIB14=>DataInB(14), DIB15=>DataInB(15), + DIB16=>DataInB(16), DIB17=>DataInB(17), ADB0=>scuba_vhi, + ADB1=>scuba_vhi, ADB2=>scuba_vlo, ADB3=>scuba_vlo, + ADB4=>AddressB(0), ADB5=>AddressB(1), ADB6=>AddressB(2), + ADB7=>AddressB(3), ADB8=>AddressB(4), ADB9=>AddressB(5), + ADB10=>AddressB(6), ADB11=>AddressB(7), ADB12=>scuba_vlo, + ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>ResetB, DOA0=>QA(0), DOA1=>QA(1), DOA2=>QA(2), + DOA3=>QA(3), DOA4=>QA(4), DOA5=>QA(5), DOA6=>QA(6), + DOA7=>QA(7), DOA8=>QA(8), DOA9=>QA(9), DOA10=>QA(10), + DOA11=>QA(11), DOA12=>QA(12), DOA13=>QA(13), DOA14=>QA(14), + DOA15=>QA(15), DOA16=>QA(16), DOA17=>QA(17), DOB0=>QB(0), + DOB1=>QB(1), DOB2=>QB(2), DOB3=>QB(3), DOB4=>QB(4), + DOB5=>QB(5), DOB6=>QB(6), DOB7=>QB(7), DOB8=>QB(8), + DOB9=>QB(9), DOB10=>QB(10), DOB11=>QB(11), DOB12=>QB(12), + DOB13=>QB(13), DOB14=>QB(14), DOB15=>QB(15), DOB16=>QB(16), + DOB17=>QB(17)); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + ip_mem_0_1_0: DP16KB + -- synopsys translate_off + generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_03=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + INITVAL_02=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + INITVAL_01=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + INITVAL_00=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + -- synopsys translate_on + port map (DIA0=>DataInA(18), DIA1=>DataInA(19), + DIA2=>DataInA(20), DIA3=>DataInA(21), DIA4=>DataInA(22), + DIA5=>DataInA(23), DIA6=>DataInA(24), DIA7=>DataInA(25), + DIA8=>DataInA(26), DIA9=>DataInA(27), DIA10=>DataInA(28), + DIA11=>DataInA(29), DIA12=>DataInA(30), DIA13=>DataInA(31), + DIA14=>scuba_vlo, DIA15=>scuba_vlo, DIA16=>scuba_vlo, + DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>AddressA(0), + ADA5=>AddressA(1), ADA6=>AddressA(2), ADA7=>AddressA(3), + ADA8=>AddressA(4), ADA9=>AddressA(5), ADA10=>AddressA(6), + ADA11=>AddressA(7), ADA12=>scuba_vlo, ADA13=>scuba_vlo, + CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>ResetA, + DIB0=>DataInB(18), DIB1=>DataInB(19), DIB2=>DataInB(20), + DIB3=>DataInB(21), DIB4=>DataInB(22), DIB5=>DataInB(23), + DIB6=>DataInB(24), DIB7=>DataInB(25), DIB8=>DataInB(26), + DIB9=>DataInB(27), DIB10=>DataInB(28), DIB11=>DataInB(29), + DIB12=>DataInB(30), DIB13=>DataInB(31), DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vhi, ADB1=>scuba_vhi, ADB2=>scuba_vlo, + ADB3=>scuba_vlo, ADB4=>AddressB(0), ADB5=>AddressB(1), + ADB6=>AddressB(2), ADB7=>AddressB(3), ADB8=>AddressB(4), + ADB9=>AddressB(5), ADB10=>AddressB(6), ADB11=>AddressB(7), + ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>ClockEnB, + CLKB=>ClockB, WEB=>WrB, CSB0=>scuba_vlo, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>ResetB, DOA0=>QA(18), DOA1=>QA(19), + DOA2=>QA(20), DOA3=>QA(21), DOA4=>QA(22), DOA5=>QA(23), + DOA6=>QA(24), DOA7=>QA(25), DOA8=>QA(26), DOA9=>QA(27), + DOA10=>QA(28), DOA11=>QA(29), DOA12=>QA(30), DOA13=>QA(31), + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>QB(18), DOB1=>QB(19), DOB2=>QB(20), DOB3=>QB(21), + DOB4=>QB(22), DOB5=>QB(23), DOB6=>QB(24), DOB7=>QB(25), + DOB8=>QB(26), DOB9=>QB(27), DOB10=>QB(28), DOB11=>QB(29), + DOB12=>QB(30), DOB13=>QB(31), DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of ip_mem is + for Structure + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/ip_mem_tmpl.vhd b/gbe_ecp2m/ipcores/ip_mem_tmpl.vhd new file mode 100755 index 0000000..7d1cea6 --- /dev/null +++ b/gbe_ecp2m/ipcores/ip_mem_tmpl.vhd @@ -0,0 +1,23 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 7.1 +-- Mon Mar 29 21:52:49 2010 + +-- parameterized module component declaration +component ip_mem + port (DataInA: in std_logic_vector(31 downto 0); + DataInB: in std_logic_vector(31 downto 0); + AddressA: in std_logic_vector(7 downto 0); + AddressB: in std_logic_vector(7 downto 0); + ClockA: in std_logic; ClockB: in std_logic; + ClockEnA: in std_logic; ClockEnB: in std_logic; + WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic; + ResetB: in std_logic; QA: out std_logic_vector(31 downto 0); + QB: out std_logic_vector(31 downto 0)); +end component; + +-- parameterized module component instance +__ : ip_mem + port map (DataInA(31 downto 0)=>__, DataInB(31 downto 0)=>__, + AddressA(7 downto 0)=>__, AddressB(7 downto 0)=>__, ClockA=>__, + ClockB=>__, ClockEnA=>__, ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__, + ResetB=>__, QA(31 downto 0)=>__, QB(31 downto 0)=>__); diff --git a/gbe_ecp2m/ipcores/macInitDataInvWithMac.mem b/gbe_ecp2m/ipcores/macInitDataInvWithMac.mem new file mode 100755 index 0000000..c93b822 --- /dev/null +++ b/gbe_ecp2m/ipcores/macInitDataInvWithMac.mem @@ -0,0 +1,59 @@ +#Format=Bin +#Depth=54 +#Width=8 +#AddrRadix=3 +#DataRadix=3 +#Data +00001111 +00001111 +10011001 +00000001 +11101110 +00000101 +00000000 +00000000 +00001100 +00000000 +00110100 +00010010 +01111000 +01010110 +10111100 +10011010 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +10000000 diff --git a/gbe_ecp2m/ipcores/mac_init_mem.lpc b/gbe_ecp2m/ipcores/mac_init_mem.lpc new file mode 100755 index 0000000..02c8376 --- /dev/null +++ b/gbe_ecp2m/ipcores/mac_init_mem.lpc @@ -0,0 +1,45 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=ROM +CoreRevision=5.0 +ModuleName=mac_init_mem +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/20/2009 +Time=16:00:49 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Address=54 +Data=8 +adPipeline=0 +inPipeline=0 +outPipeline=1 +MOR=0 +InData=Registered +AdControl=Registered +MemFile=/home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem +MemFormat=bin +Reset=Sync +Pad=0 +GSR=Enabled +EnECC=0 +Optimization=Speed +Pipeline=0 diff --git a/gbe_ecp2m/ipcores/mac_init_mem.vhd b/gbe_ecp2m/ipcores/mac_init_mem.vhd new file mode 100755 index 0000000..c2c95e4 --- /dev/null +++ b/gbe_ecp2m/ipcores/mac_init_mem.vhd @@ -0,0 +1,413 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.0 +--/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 00 -rp 1100 -addr_width 6 -data_width 8 -num_rows 54 -outdata REGISTERED -resetmode SYNC -memfile /home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem -memformat bin -cascade -1 -e + +-- Thu Aug 20 16:00:49 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity mac_init_mem is + port ( + Address: in std_logic_vector(5 downto 0); + OutClock: in std_logic; + OutClockEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(7 downto 0)); +end mac_init_mem; + +architecture Structure of mac_init_mem is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (INITVAL_3F : in String; INITVAL_3E : in String; + INITVAL_3D : in String; INITVAL_3C : in String; + INITVAL_3B : in String; INITVAL_3A : in String; + INITVAL_39 : in String; INITVAL_38 : in String; + INITVAL_37 : in String; INITVAL_36 : in String; + INITVAL_35 : in String; INITVAL_34 : in String; + INITVAL_33 : in String; INITVAL_32 : in String; + INITVAL_31 : in String; INITVAL_30 : in String; + INITVAL_2F : in String; INITVAL_2E : in String; + INITVAL_2D : in String; INITVAL_2C : in String; + INITVAL_2B : in String; INITVAL_2A : in String; + INITVAL_29 : in String; INITVAL_28 : in String; + INITVAL_27 : in String; INITVAL_26 : in String; + INITVAL_25 : in String; INITVAL_24 : in String; + INITVAL_23 : in String; INITVAL_22 : in String; + INITVAL_21 : in String; INITVAL_20 : in String; + INITVAL_1F : in String; INITVAL_1E : in String; + INITVAL_1D : in String; INITVAL_1C : in String; + INITVAL_1B : in String; INITVAL_1A : in String; + INITVAL_19 : in String; INITVAL_18 : in String; + INITVAL_17 : in String; INITVAL_16 : in String; + INITVAL_15 : in String; INITVAL_14 : in String; + INITVAL_13 : in String; INITVAL_12 : in String; + INITVAL_11 : in String; INITVAL_10 : in String; + INITVAL_0F : in String; INITVAL_0E : in String; + INITVAL_0D : in String; INITVAL_0C : in String; + INITVAL_0B : in String; INITVAL_0A : in String; + INITVAL_09 : in String; INITVAL_08 : in String; + INITVAL_07 : in String; INITVAL_06 : in String; + INITVAL_05 : in String; INITVAL_04 : in String; + INITVAL_03 : in String; INITVAL_02 : in String; + INITVAL_01 : in String; INITVAL_00 : in String; + GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute INITVAL_3F : string; + attribute INITVAL_3E : string; + attribute INITVAL_3D : string; + attribute INITVAL_3C : string; + attribute INITVAL_3B : string; + attribute INITVAL_3A : string; + attribute INITVAL_39 : string; + attribute INITVAL_38 : string; + attribute INITVAL_37 : string; + attribute INITVAL_36 : string; + attribute INITVAL_35 : string; + attribute INITVAL_34 : string; + attribute INITVAL_33 : string; + attribute INITVAL_32 : string; + attribute INITVAL_31 : string; + attribute INITVAL_30 : string; + attribute INITVAL_2F : string; + attribute INITVAL_2E : string; + attribute INITVAL_2D : string; + attribute INITVAL_2C : string; + attribute INITVAL_2B : string; + attribute INITVAL_2A : string; + attribute INITVAL_29 : string; + attribute INITVAL_28 : string; + attribute INITVAL_27 : string; + attribute INITVAL_26 : string; + attribute INITVAL_25 : string; + attribute INITVAL_24 : string; + attribute INITVAL_23 : string; + attribute INITVAL_22 : string; + attribute INITVAL_21 : string; + attribute INITVAL_20 : string; + attribute INITVAL_1F : string; + attribute INITVAL_1E : string; + attribute INITVAL_1D : string; + attribute INITVAL_1C : string; + attribute INITVAL_1B : string; + attribute INITVAL_1A : string; + attribute INITVAL_19 : string; + attribute INITVAL_18 : string; + attribute INITVAL_17 : string; + attribute INITVAL_16 : string; + attribute INITVAL_15 : string; + attribute INITVAL_14 : string; + attribute INITVAL_13 : string; + attribute INITVAL_12 : string; + attribute INITVAL_11 : string; + attribute INITVAL_10 : string; + attribute INITVAL_0F : string; + attribute INITVAL_0E : string; + attribute INITVAL_0D : string; + attribute INITVAL_0C : string; + attribute INITVAL_0B : string; + attribute INITVAL_0A : string; + attribute INITVAL_09 : string; + attribute INITVAL_08 : string; + attribute INITVAL_07 : string; + attribute INITVAL_06 : string; + attribute INITVAL_05 : string; + attribute INITVAL_04 : string; + attribute INITVAL_03 : string; + attribute INITVAL_02 : string; + attribute INITVAL_01 : string; + attribute INITVAL_00 : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute GSR : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute MEM_LPC_FILE of mac_init_mem_0_0_0 : label is "mac_init_mem.lpc"; + attribute MEM_INIT_FILE of mac_init_mem_0_0_0 : label is "macInitDataInvWithMac.mem"; + attribute INITVAL_3F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_39 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_38 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_37 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_36 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_35 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_34 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_33 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_32 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_31 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_30 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_29 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_28 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_27 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_26 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_25 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_24 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_23 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_22 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_21 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_20 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_19 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_18 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_17 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_16 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_15 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_14 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_13 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_12 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_11 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_10 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_0F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_0E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_0D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_0C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_0B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_0A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_09 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_08 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_07 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_06 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_05 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_04 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_03 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_02 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_01 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000"; + attribute INITVAL_00 of mac_init_mem_0_0_0 : label is "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F"; + attribute CSDECODE_B of mac_init_mem_0_0_0 : label is "0b111"; + attribute CSDECODE_A of mac_init_mem_0_0_0 : label is "0b000"; + attribute WRITEMODE_B of mac_init_mem_0_0_0 : label is "NORMAL"; + attribute WRITEMODE_A of mac_init_mem_0_0_0 : label is "NORMAL"; + attribute GSR of mac_init_mem_0_0_0 : label is "DISABLED"; + attribute RESETMODE of mac_init_mem_0_0_0 : label is "SYNC"; + attribute REGMODE_B of mac_init_mem_0_0_0 : label is "NOREG"; + attribute REGMODE_A of mac_init_mem_0_0_0 : label is "OUTREG"; + attribute DATA_WIDTH_B of mac_init_mem_0_0_0 : label is "9"; + attribute DATA_WIDTH_A of mac_init_mem_0_0_0 : label is "9"; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + mac_init_mem_0_0_0: DP16KB + -- synopsys translate_off + generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_01=> "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000", + INITVAL_00=> "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F", + CSDECODE_B=> "111", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>Address(0), ADA4=>Address(1), ADA5=>Address(2), + ADA6=>Address(3), ADA7=>Address(4), ADA8=>Address(5), + ADA9=>scuba_vlo, ADA10=>scuba_vlo, ADA11=>scuba_vlo, + ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>OutClockEn, + CLKA=>OutClock, WEA=>scuba_vlo, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>scuba_vlo, ADB4=>scuba_vlo, ADB5=>scuba_vlo, + ADB6=>scuba_vlo, ADB7=>scuba_vlo, ADB8=>scuba_vlo, + ADB9=>scuba_vlo, ADB10=>scuba_vlo, ADB11=>scuba_vlo, + ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>scuba_vhi, + CLKB=>scuba_vlo, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>scuba_vlo, + DOA0=>Q(0), DOA1=>Q(1), DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), + DOA5=>Q(5), DOA6=>Q(6), DOA7=>Q(7), DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>open, DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of mac_init_mem is + for Structure + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/mac_init_mem_tmpl.vhd b/gbe_ecp2m/ipcores/mac_init_mem_tmpl.vhd new file mode 100755 index 0000000..1aee5c2 --- /dev/null +++ b/gbe_ecp2m/ipcores/mac_init_mem_tmpl.vhd @@ -0,0 +1,15 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.0 +-- Thu Aug 20 16:00:49 2009 + +-- parameterized module component declaration +component mac_init_mem + port (Address: in std_logic_vector(5 downto 0); + OutClock: in std_logic; OutClockEn: in std_logic; + Reset: in std_logic; Q: out std_logic_vector(7 downto 0)); +end component; + +-- parameterized module component instance +__ : mac_init_mem + port map (Address(5 downto 0)=>__, OutClock=>__, OutClockEn=>__, + Reset=>__, Q(7 downto 0)=>__); diff --git a/gbe_ecp2m/ipcores/serdes/.cvsignore b/gbe_ecp2m/ipcores/serdes/.cvsignore new file mode 100644 index 0000000..85eef7b --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes/.cvsignore @@ -0,0 +1,9 @@ +*.jhd +*.naf +*.srp +*.sym +*.log +*.pp +*.tft +*.readme +*tmpl.vhd diff --git a/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.lpc b/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.lpc new file mode 100755 index 0000000..4efe9cf --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.lpc @@ -0,0 +1,140 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PCS +CoreRevision=7.0 +ModuleName=serdes_gbe_0_extclock_8b +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=08/20/2009 +Time=11:50:53 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Protocol=Quad +mode=Gigabit Ethernet +Channel0=SINGLE +Channel1=DISABLE +Channel2=DISABLE +Channel3=DISABLE +Rate0=None +Rate1=None +Rate2=None +Rate3=None +TxRefClk=REFCLK +RxRefClk=REFCLK +ClkRate=1.25 +ClkMult=10X +CalClkRate=125.0 +DataWidth=8 +FPGAClkRate=125.0 +TxRefClkCM=REFCLK +RxRefClk0CM=REFCLK +RxRefClk1CM=REFCLK +RxRefClk2CM=REFCLK +RxRefClk3CM=REFCLK +ClkRateH=0.625 +ClkMultH=10XH +CalClkRateH=125.0 +DataWidthH=8 +FPGAClkRateH=62.5 +VCh0=0 +VCh1=0 +VCh2=0 +VCh3=0 +PreCh0=DISABLE +PreCh1=DISABLE +PreCh2=DISABLE +PreCh3=DISABLE +TxCh0=50 +TxCh1=50 +TxCh2=50 +TxCh3=50 +EqCh0=DISABLE +EqCh1=DISABLE +EqCh2=DISABLE +EqCh3=DISABLE +RxTermCh0=50 +RxTermCh1=50 +RxTermCh2=50 +RxTermCh3=50 +RxCoupCh0=AC +RxCoupCh1=AC +RxCoupCh2=AC +RxCoupCh3=AC +Loss=0 +CDRLoss=0 +TxTerm=50 +TxCoup=AC +TxPllLoss=0 +TxInvCh0=NORMAL +TxInvCh1=NORMAL +TxInvCh2=NORMAL +TxInvCh3=NORMAL +RxInvCh0=NORMAL +RxInvCh1=NORMAL +RxInvCh2=NORMAL +RxInvCh3=NORMAL +RxModeCh0=NORMAL +RxModeCh1=NORMAL +RxModeCh2=NORMAL +RxModeCh3=NORMAL +Plus=1100000101 +Minus=0011111010 +Mask=1111111111 +Align=AUTO +CTCCh0=NORMAL +CTCCh1=NORMAL +CTCCh2=NORMAL +CTCCh3=NORMAL +CC_MATCH1=0000000000 +CC_MATCH2=0000000000 +CC_MATCH3=0110111100 +CC_MATCH4=0001010000 +MinIPG=3 +High=9 +Low=7 +CC_MATCH_MODE=MATCH_3_4 +RxDataCh0=FALSE +RxDataCh1=FALSE +RxDataCh2=FALSE +RxDataCh3=FALSE +AlignerCh0=FALSE +AlignerCh1=FALSE +AlignerCh2=FALSE +AlignerCh3=FALSE +DetectCh0=FALSE +DetectCh1=FALSE +DetectCh2=FALSE +DetectCh3=FALSE +ELSMCh0=FALSE +ELSMCh1=FALSE +ELSMCh2=FALSE +ELSMCh3=FALSE +_teidleCh0=FALSE +_teidleCh1=FALSE +_teidleCh2=FALSE +_teidleCh3=FALSE +Ports0=FALSE +rdoPorts0=Serial Loopback +Ports1=FALSE +Ports2=TRUE +Ports3=FALSE +Ports3_1=FALSE +Ports4=FALSE diff --git a/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.txt b/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.txt new file mode 100755 index 0000000..6aad9a9 --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.txt @@ -0,0 +1,49 @@ + +# This file is used by the simulation model as well as the ispLEVER bitstream +# generation process to automatically initialize the PCSC quad to the mode +# selected in the IPexpress. This file is expected to be modified by the +# end user to adjust the PCSC quad to the final design requirements. + +DEVICE_NAME "LFE2M100E" +PROTOCOL "GIGE" +CH0_MODE "SINGLE" +CH1_MODE "DISABLE" +CH2_MODE "DISABLE" +CH3_MODE "DISABLE" +PLL_SRC "REFCLK" +DATARANGE "MED" +CH0_CDR_SRC "REFCLK" +CH0_DATA_WIDTH "8" +CH0_REFCK_MULT "10X" +#REFCLK_RATE 125.0 +#FPGAINTCLK_RATE 125.0 +CH0_TDRV_AMP "0" +CH0_TX_PRE "DISABLE" +CH0_RTERM_TX "50" +CH0_RX_EQ "DISABLE" +CH0_RTERM_RX "50" +CH0_RX_DCC "AC" +LOS_THRESHOLD "0" +PLL_TERM "50" +PLL_DCC "AC" +PLL_LOL_SET "0" +CH0_TX_SB "NORMAL" +CH0_RX_SB "NORMAL" +CH0_8B10B "NORMAL" +COMMA_A "1100000101" +COMMA_B "0011111010" +COMMA_M "1111111111" +CH0_COMMA_ALIGN "AUTO" +CH0_CTC_BYP "NORMAL" +CC_MATCH1 "0000000000" +CC_MATCH2 "0000000000" +CC_MATCH3 "0110111100" +CC_MATCH4 "0001010000" +CC_MATCH_MODE "MATCH_3_4" +CC_MIN_IPG "3" +CCHMARK "9" +CCLMARK "7" +OS_REFCK2CORE "1" +OS_PLLQCLKPORTS "0" +OS_INT_ALL "0" + diff --git a/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.vhd b/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.vhd new file mode 100755 index 0000000..c3d0eda --- /dev/null +++ b/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.vhd @@ -0,0 +1,2182 @@ + + +--synopsys translate_off + +library pcsc_work; +use pcsc_work.all; +library IEEE; +use IEEE.std_logic_1164.all; + +entity PCSC is +GENERIC( + CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt" + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); + +end PCSC; + +architecture PCSC_arch of PCSC is + +component PCSC_sim +GENERIC( + CONFIG_FILE : String + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); +end component; + +begin + +PCSC_sim_inst : PCSC_sim +generic map ( + CONFIG_FILE => CONFIG_FILE) +port map ( + HDINN0 => HDINN0, + HDINN1 => HDINN1, + HDINN2 => HDINN2, + HDINN3 => HDINN3, + HDINP0 => HDINP0, + HDINP1 => HDINP1, + HDINP2 => HDINP2, + HDINP3 => HDINP3, + REFCLKN => REFCLKN, + REFCLKP => REFCLKP, + CIN11 => CIN11, + CIN10 => CIN10, + CIN9 => CIN9, + CIN8 => CIN8, + CIN7 => CIN7, + CIN6 => CIN6, + CIN5 => CIN5, + CIN4 => CIN4, + CIN3 => CIN3, + CIN2 => CIN2, + CIN1 => CIN1, + CIN0 => CIN0, + CYAWSTN => CYAWSTN, + FF_EBRD_CLK_3 => FF_EBRD_CLK_3, + FF_EBRD_CLK_2 => FF_EBRD_CLK_2, + FF_EBRD_CLK_1 => FF_EBRD_CLK_1, + FF_EBRD_CLK_0 => FF_EBRD_CLK_0, + FF_RXI_CLK_3 => FF_RXI_CLK_3, + FF_RXI_CLK_2 => FF_RXI_CLK_2, + FF_RXI_CLK_1 => FF_RXI_CLK_1, + FF_RXI_CLK_0 => FF_RXI_CLK_0, + + FF_TX_D_0_0 => FF_TX_D_0_0, + FF_TX_D_0_1 => FF_TX_D_0_1, + FF_TX_D_0_2 => FF_TX_D_0_2, + FF_TX_D_0_3 => FF_TX_D_0_3, + FF_TX_D_0_4 => FF_TX_D_0_4, + FF_TX_D_0_5 => FF_TX_D_0_5, + FF_TX_D_0_6 => FF_TX_D_0_6, + FF_TX_D_0_7 => FF_TX_D_0_7, + FF_TX_D_0_8 => FF_TX_D_0_8, + FF_TX_D_0_9 => FF_TX_D_0_9, + FF_TX_D_0_10 => FF_TX_D_0_10, + FF_TX_D_0_11 => FF_TX_D_0_11, + FF_TX_D_0_12 => FF_TX_D_0_12, + FF_TX_D_0_13 => FF_TX_D_0_13, + FF_TX_D_0_14 => FF_TX_D_0_14, + FF_TX_D_0_15 => FF_TX_D_0_15, + FF_TX_D_0_16 => FF_TX_D_0_16, + FF_TX_D_0_17 => FF_TX_D_0_17, + FF_TX_D_0_18 => FF_TX_D_0_18, + FF_TX_D_0_19 => FF_TX_D_0_19, + FF_TX_D_0_20 => FF_TX_D_0_20, + FF_TX_D_0_21 => FF_TX_D_0_21, + FF_TX_D_0_22 => FF_TX_D_0_22, + FF_TX_D_0_23 => FF_TX_D_0_23, + FF_TX_D_1_0 => FF_TX_D_1_0, + FF_TX_D_1_1 => FF_TX_D_1_1, + FF_TX_D_1_2 => FF_TX_D_1_2, + FF_TX_D_1_3 => FF_TX_D_1_3, + FF_TX_D_1_4 => FF_TX_D_1_4, + FF_TX_D_1_5 => FF_TX_D_1_5, + FF_TX_D_1_6 => FF_TX_D_1_6, + FF_TX_D_1_7 => FF_TX_D_1_7, + FF_TX_D_1_8 => FF_TX_D_1_8, + FF_TX_D_1_9 => FF_TX_D_1_9, + FF_TX_D_1_10 => FF_TX_D_1_10, + FF_TX_D_1_11 => FF_TX_D_1_11, + FF_TX_D_1_12 => FF_TX_D_1_12, + FF_TX_D_1_13 => FF_TX_D_1_13, + FF_TX_D_1_14 => FF_TX_D_1_14, + FF_TX_D_1_15 => FF_TX_D_1_15, + FF_TX_D_1_16 => FF_TX_D_1_16, + FF_TX_D_1_17 => FF_TX_D_1_17, + FF_TX_D_1_18 => FF_TX_D_1_18, + FF_TX_D_1_19 => FF_TX_D_1_19, + FF_TX_D_1_20 => FF_TX_D_1_20, + FF_TX_D_1_21 => FF_TX_D_1_21, + FF_TX_D_1_22 => FF_TX_D_1_22, + FF_TX_D_1_23 => FF_TX_D_1_23, + FF_TX_D_2_0 => FF_TX_D_2_0, + FF_TX_D_2_1 => FF_TX_D_2_1, + FF_TX_D_2_2 => FF_TX_D_2_2, + FF_TX_D_2_3 => FF_TX_D_2_3, + FF_TX_D_2_4 => FF_TX_D_2_4, + FF_TX_D_2_5 => FF_TX_D_2_5, + FF_TX_D_2_6 => FF_TX_D_2_6, + FF_TX_D_2_7 => FF_TX_D_2_7, + FF_TX_D_2_8 => FF_TX_D_2_8, + FF_TX_D_2_9 => FF_TX_D_2_9, + FF_TX_D_2_10 => FF_TX_D_2_10, + FF_TX_D_2_11 => FF_TX_D_2_11, + FF_TX_D_2_12 => FF_TX_D_2_12, + FF_TX_D_2_13 => FF_TX_D_2_13, + FF_TX_D_2_14 => FF_TX_D_2_14, + FF_TX_D_2_15 => FF_TX_D_2_15, + FF_TX_D_2_16 => FF_TX_D_2_16, + FF_TX_D_2_17 => FF_TX_D_2_17, + FF_TX_D_2_18 => FF_TX_D_2_18, + FF_TX_D_2_19 => FF_TX_D_2_19, + FF_TX_D_2_20 => FF_TX_D_2_20, + FF_TX_D_2_21 => FF_TX_D_2_21, + FF_TX_D_2_22 => FF_TX_D_2_22, + FF_TX_D_2_23 => FF_TX_D_2_23, + FF_TX_D_3_0 => FF_TX_D_3_0, + FF_TX_D_3_1 => FF_TX_D_3_1, + FF_TX_D_3_2 => FF_TX_D_3_2, + FF_TX_D_3_3 => FF_TX_D_3_3, + FF_TX_D_3_4 => FF_TX_D_3_4, + FF_TX_D_3_5 => FF_TX_D_3_5, + FF_TX_D_3_6 => FF_TX_D_3_6, + FF_TX_D_3_7 => FF_TX_D_3_7, + FF_TX_D_3_8 => FF_TX_D_3_8, + FF_TX_D_3_9 => FF_TX_D_3_9, + FF_TX_D_3_10 => FF_TX_D_3_10, + FF_TX_D_3_11 => FF_TX_D_3_11, + FF_TX_D_3_12 => FF_TX_D_3_12, + FF_TX_D_3_13 => FF_TX_D_3_13, + FF_TX_D_3_14 => FF_TX_D_3_14, + FF_TX_D_3_15 => FF_TX_D_3_15, + FF_TX_D_3_16 => FF_TX_D_3_16, + FF_TX_D_3_17 => FF_TX_D_3_17, + FF_TX_D_3_18 => FF_TX_D_3_18, + FF_TX_D_3_19 => FF_TX_D_3_19, + FF_TX_D_3_20 => FF_TX_D_3_20, + FF_TX_D_3_21 => FF_TX_D_3_21, + FF_TX_D_3_22 => FF_TX_D_3_22, + FF_TX_D_3_23 => FF_TX_D_3_23, + FF_TXI_CLK_0 => FF_TXI_CLK_0, + FF_TXI_CLK_1 => FF_TXI_CLK_1, + FF_TXI_CLK_2 => FF_TXI_CLK_2, + FF_TXI_CLK_3 => FF_TXI_CLK_3, + FFC_CK_CORE_RX => FFC_CK_CORE_RX, + FFC_CK_CORE_TX => FFC_CK_CORE_TX, + FFC_EI_EN_0 => FFC_EI_EN_0, + FFC_EI_EN_1 => FFC_EI_EN_1, + FFC_EI_EN_2 => FFC_EI_EN_2, + FFC_EI_EN_3 => FFC_EI_EN_3, + FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, + FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, + FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, + FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, + FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, + FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, + FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, + FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, + FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, + FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, + FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, + FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, + FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, + FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, + FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, + FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, + FFC_MACRO_RST => FFC_MACRO_RST, + FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, + FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, + FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, + FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, + FFC_PCIE_CT_0 => FFC_PCIE_CT_0, + FFC_PCIE_CT_1 => FFC_PCIE_CT_1, + FFC_PCIE_CT_2 => FFC_PCIE_CT_2, + FFC_PCIE_CT_3 => FFC_PCIE_CT_3, + FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, + FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, + FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, + FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, + FFC_QUAD_RST => FFC_QUAD_RST, + FFC_RRST_0 => FFC_RRST_0, + FFC_RRST_1 => FFC_RRST_1, + FFC_RRST_2 => FFC_RRST_2, + FFC_RRST_3 => FFC_RRST_3, + FFC_RXPWDNB_0 => FFC_RXPWDNB_0, + FFC_RXPWDNB_1 => FFC_RXPWDNB_1, + FFC_RXPWDNB_2 => FFC_RXPWDNB_2, + FFC_RXPWDNB_3 => FFC_RXPWDNB_3, + FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, + FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, + FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, + FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, + FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, + FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, + FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, + FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, + FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, + FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, + FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, + FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, + FFC_TRST => FFC_TRST, + FFC_TXPWDNB_0 => FFC_TXPWDNB_0, + FFC_TXPWDNB_1 => FFC_TXPWDNB_1, + FFC_TXPWDNB_2 => FFC_TXPWDNB_2, + FFC_TXPWDNB_3 => FFC_TXPWDNB_3, + SCIADDR0 => SCIADDR0, + SCIADDR1 => SCIADDR1, + SCIADDR2 => SCIADDR2, + SCIADDR3 => SCIADDR3, + SCIADDR4 => SCIADDR4, + SCIADDR5 => SCIADDR5, + SCIENAUX => SCIENAUX, + SCIENCH0 => SCIENCH0, + SCIENCH1 => SCIENCH1, + SCIENCH2 => SCIENCH2, + SCIENCH3 => SCIENCH3, + SCIRD => SCIRD, + SCISELAUX => SCISELAUX, + SCISELCH0 => SCISELCH0, + SCISELCH1 => SCISELCH1, + SCISELCH2 => SCISELCH2, + SCISELCH3 => SCISELCH3, + SCIWDATA0 => SCIWDATA0, + SCIWDATA1 => SCIWDATA1, + SCIWDATA2 => SCIWDATA2, + SCIWDATA3 => SCIWDATA3, + SCIWDATA4 => SCIWDATA4, + SCIWDATA5 => SCIWDATA5, + SCIWDATA6 => SCIWDATA6, + SCIWDATA7 => SCIWDATA7, + SCIWSTN => SCIWSTN, + HDOUTN0 => HDOUTN0, + HDOUTN1 => HDOUTN1, + HDOUTN2 => HDOUTN2, + HDOUTN3 => HDOUTN3, + HDOUTP0 => HDOUTP0, + HDOUTP1 => HDOUTP1, + HDOUTP2 => HDOUTP2, + HDOUTP3 => HDOUTP3, + COUT19 => COUT19, + COUT18 => COUT18, + COUT17 => COUT17, + COUT16 => COUT16, + COUT15 => COUT15, + COUT14 => COUT14, + COUT13 => COUT13, + COUT12 => COUT12, + COUT11 => COUT11, + COUT10 => COUT10, + COUT9 => COUT9, + COUT8 => COUT8, + COUT7 => COUT7, + COUT6 => COUT6, + COUT5 => COUT5, + COUT4 => COUT4, + COUT3 => COUT3, + COUT2 => COUT2, + COUT1 => COUT1, + COUT0 => COUT0, + FF_RX_D_0_0 => FF_RX_D_0_0, + FF_RX_D_0_1 => FF_RX_D_0_1, + FF_RX_D_0_2 => FF_RX_D_0_2, + FF_RX_D_0_3 => FF_RX_D_0_3, + FF_RX_D_0_4 => FF_RX_D_0_4, + FF_RX_D_0_5 => FF_RX_D_0_5, + FF_RX_D_0_6 => FF_RX_D_0_6, + FF_RX_D_0_7 => FF_RX_D_0_7, + FF_RX_D_0_8 => FF_RX_D_0_8, + FF_RX_D_0_9 => FF_RX_D_0_9, + FF_RX_D_0_10 => FF_RX_D_0_10, + FF_RX_D_0_11 => FF_RX_D_0_11, + FF_RX_D_0_12 => FF_RX_D_0_12, + FF_RX_D_0_13 => FF_RX_D_0_13, + FF_RX_D_0_14 => FF_RX_D_0_14, + FF_RX_D_0_15 => FF_RX_D_0_15, + FF_RX_D_0_16 => FF_RX_D_0_16, + FF_RX_D_0_17 => FF_RX_D_0_17, + FF_RX_D_0_18 => FF_RX_D_0_18, + FF_RX_D_0_19 => FF_RX_D_0_19, + FF_RX_D_0_20 => FF_RX_D_0_20, + FF_RX_D_0_21 => FF_RX_D_0_21, + FF_RX_D_0_22 => FF_RX_D_0_22, + FF_RX_D_0_23 => FF_RX_D_0_23, + FF_RX_D_1_0 => FF_RX_D_1_0, + FF_RX_D_1_1 => FF_RX_D_1_1, + FF_RX_D_1_2 => FF_RX_D_1_2, + FF_RX_D_1_3 => FF_RX_D_1_3, + FF_RX_D_1_4 => FF_RX_D_1_4, + FF_RX_D_1_5 => FF_RX_D_1_5, + FF_RX_D_1_6 => FF_RX_D_1_6, + FF_RX_D_1_7 => FF_RX_D_1_7, + FF_RX_D_1_8 => FF_RX_D_1_8, + FF_RX_D_1_9 => FF_RX_D_1_9, + FF_RX_D_1_10 => FF_RX_D_1_10, + FF_RX_D_1_11 => FF_RX_D_1_11, + FF_RX_D_1_12 => FF_RX_D_1_12, + FF_RX_D_1_13 => FF_RX_D_1_13, + FF_RX_D_1_14 => FF_RX_D_1_14, + FF_RX_D_1_15 => FF_RX_D_1_15, + FF_RX_D_1_16 => FF_RX_D_1_16, + FF_RX_D_1_17 => FF_RX_D_1_17, + FF_RX_D_1_18 => FF_RX_D_1_18, + FF_RX_D_1_19 => FF_RX_D_1_19, + FF_RX_D_1_20 => FF_RX_D_1_20, + FF_RX_D_1_21 => FF_RX_D_1_21, + FF_RX_D_1_22 => FF_RX_D_1_22, + FF_RX_D_1_23 => FF_RX_D_1_23, + FF_RX_D_2_0 => FF_RX_D_2_0, + FF_RX_D_2_1 => FF_RX_D_2_1, + FF_RX_D_2_2 => FF_RX_D_2_2, + FF_RX_D_2_3 => FF_RX_D_2_3, + FF_RX_D_2_4 => FF_RX_D_2_4, + FF_RX_D_2_5 => FF_RX_D_2_5, + FF_RX_D_2_6 => FF_RX_D_2_6, + FF_RX_D_2_7 => FF_RX_D_2_7, + FF_RX_D_2_8 => FF_RX_D_2_8, + FF_RX_D_2_9 => FF_RX_D_2_9, + FF_RX_D_2_10 => FF_RX_D_2_10, + FF_RX_D_2_11 => FF_RX_D_2_11, + FF_RX_D_2_12 => FF_RX_D_2_12, + FF_RX_D_2_13 => FF_RX_D_2_13, + FF_RX_D_2_14 => FF_RX_D_2_14, + FF_RX_D_2_15 => FF_RX_D_2_15, + FF_RX_D_2_16 => FF_RX_D_2_16, + FF_RX_D_2_17 => FF_RX_D_2_17, + FF_RX_D_2_18 => FF_RX_D_2_18, + FF_RX_D_2_19 => FF_RX_D_2_19, + FF_RX_D_2_20 => FF_RX_D_2_20, + FF_RX_D_2_21 => FF_RX_D_2_21, + FF_RX_D_2_22 => FF_RX_D_2_22, + FF_RX_D_2_23 => FF_RX_D_2_23, + FF_RX_D_3_0 => FF_RX_D_3_0, + FF_RX_D_3_1 => FF_RX_D_3_1, + FF_RX_D_3_2 => FF_RX_D_3_2, + FF_RX_D_3_3 => FF_RX_D_3_3, + FF_RX_D_3_4 => FF_RX_D_3_4, + FF_RX_D_3_5 => FF_RX_D_3_5, + FF_RX_D_3_6 => FF_RX_D_3_6, + FF_RX_D_3_7 => FF_RX_D_3_7, + FF_RX_D_3_8 => FF_RX_D_3_8, + FF_RX_D_3_9 => FF_RX_D_3_9, + FF_RX_D_3_10 => FF_RX_D_3_10, + FF_RX_D_3_11 => FF_RX_D_3_11, + FF_RX_D_3_12 => FF_RX_D_3_12, + FF_RX_D_3_13 => FF_RX_D_3_13, + FF_RX_D_3_14 => FF_RX_D_3_14, + FF_RX_D_3_15 => FF_RX_D_3_15, + FF_RX_D_3_16 => FF_RX_D_3_16, + FF_RX_D_3_17 => FF_RX_D_3_17, + FF_RX_D_3_18 => FF_RX_D_3_18, + FF_RX_D_3_19 => FF_RX_D_3_19, + FF_RX_D_3_20 => FF_RX_D_3_20, + FF_RX_D_3_21 => FF_RX_D_3_21, + FF_RX_D_3_22 => FF_RX_D_3_22, + FF_RX_D_3_23 => FF_RX_D_3_23, + FF_RX_F_CLK_0 => FF_RX_F_CLK_0, + FF_RX_F_CLK_1 => FF_RX_F_CLK_1, + FF_RX_F_CLK_2 => FF_RX_F_CLK_2, + FF_RX_F_CLK_3 => FF_RX_F_CLK_3, + FF_RX_H_CLK_0 => FF_RX_H_CLK_0, + FF_RX_H_CLK_1 => FF_RX_H_CLK_1, + FF_RX_H_CLK_2 => FF_RX_H_CLK_2, + FF_RX_H_CLK_3 => FF_RX_H_CLK_3, + FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0, + FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1, + FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2, + FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3, + FF_TX_F_CLK => FF_TX_F_CLK, + FF_TX_H_CLK => FF_TX_H_CLK, + FF_TX_Q_CLK => FF_TX_Q_CLK, + FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, + FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, + FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, + FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, + FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, + FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, + FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, + FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, + FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, + FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, + FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, + FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, + FFS_PCIE_CON_0 => FFS_PCIE_CON_0, + FFS_PCIE_CON_1 => FFS_PCIE_CON_1, + FFS_PCIE_CON_2 => FFS_PCIE_CON_2, + FFS_PCIE_CON_3 => FFS_PCIE_CON_3, + FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, + FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, + FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, + FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, + FFS_RLOS_LO_0 => FFS_RLOS_LO_0, + FFS_RLOS_LO_1 => FFS_RLOS_LO_1, + FFS_RLOS_LO_2 => FFS_RLOS_LO_2, + FFS_RLOS_LO_3 => FFS_RLOS_LO_3, + FFS_PLOL => FFS_PLOL, + FFS_RLOL_0 => FFS_RLOL_0, + FFS_RLOL_1 => FFS_RLOL_1, + FFS_RLOL_2 => FFS_RLOL_2, + FFS_RLOL_3 => FFS_RLOL_3, + FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, + FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, + FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, + FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, + FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, + FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, + FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, + FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, + OOB_OUT_0 => OOB_OUT_0, + OOB_OUT_1 => OOB_OUT_1, + OOB_OUT_2 => OOB_OUT_2, + OOB_OUT_3 => OOB_OUT_3, + REFCK2CORE => REFCK2CORE, + SCIINT => SCIINT, + SCIRDATA0 => SCIRDATA0, + SCIRDATA1 => SCIRDATA1, + SCIRDATA2 => SCIRDATA2, + SCIRDATA3 => SCIRDATA3, + SCIRDATA4 => SCIRDATA4, + SCIRDATA5 => SCIRDATA5, + SCIRDATA6 => SCIRDATA6, + SCIRDATA7 => SCIRDATA7 + ); + +end PCSC_arch; + +--synopsys translate_on + +--synopsys translate_off +library ECP2; +use ECP2.components.all; +--synopsys translate_on + +library IEEE, STD; +use IEEE.std_logic_1164.all; +use STD.TEXTIO.all; + +entity serdes_gbe_0_extclock_8b is + GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt"); + port ( + refclkp, refclkn : in std_logic; + hdinp0, hdinn0 : in std_logic; + hdoutp0, hdoutn0 : out std_logic; + ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic; + ff_txdata_ch0 : in std_logic_vector (7 downto 0); + ff_rxdata_ch0 : out std_logic_vector (7 downto 0); + ff_tx_k_cntrl_ch0 : in std_logic; + ff_rx_k_cntrl_ch0 : out std_logic; + ff_rxfullclk_ch0 : out std_logic; + ff_xmit_ch0 : in std_logic; + ff_correct_disp_ch0 : in std_logic; + ff_disp_err_ch0, ff_cv_ch0 : out std_logic; + ff_rx_even_ch0 : out std_logic; + ffc_rrst_ch0 : in std_logic; + ffc_lane_tx_rst_ch0 : in std_logic; + ffc_lane_rx_rst_ch0 : in std_logic; + ffc_txpwdnb_ch0 : in std_logic; + ffc_rxpwdnb_ch0 : in std_logic; + ffs_rlos_lo_ch0 : out std_logic; + ffs_ls_sync_status_ch0 : out std_logic; + ffs_rlol_ch0 : out std_logic; + oob_out_ch0 : out std_logic; + ffc_macro_rst : in std_logic; + ffc_quad_rst : in std_logic; + ffc_trst : in std_logic; + ff_txfullclk : out std_logic; + ff_txhalfclk : out std_logic; + refck2core : out std_logic; + ffs_plol : out std_logic); + +end serdes_gbe_0_extclock_8b; + +architecture serdes_gbe_0_extclock_8b_arch of serdes_gbe_0_extclock_8b is + +component VLO +port ( + Z : out std_logic); +end component; + +component VHI +port ( + Z : out std_logic); +end component; +component PCSC +--synopsys translate_off +GENERIC( + CONFIG_FILE : String + ); +--synopsys translate_on +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); +end component; + attribute IS_ASB: string; + attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd"; + attribute CONFIG_FILE: string; + attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE; + attribute black_box_pad_pin: string; + attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; + +signal fpsc_vlo : std_logic := '0'; +signal cin : std_logic_vector (11 downto 0) := "000000000000"; +signal cout : std_logic_vector (19 downto 0); + +begin + +vlo_inst : VLO port map(Z => fpsc_vlo); + +-- pcs_quad instance +PCSC_INST : PCSC +--synopsys translate_off + generic map (CONFIG_FILE => USER_CONFIG_FILE) +--synopsys translate_on +port map ( + FFC_CK_CORE_TX => fpsc_vlo, + FFC_CK_CORE_RX => fpsc_vlo, + REFCLKP => refclkp, + REFCLKN => refclkn, + HDINP0 => hdinp0, + HDINN0 => hdinn0, + HDOUTP0 => hdoutp0, + HDOUTN0 => hdoutn0, + SCISELCH0 => fpsc_vlo, + SCIENCH0 => fpsc_vlo, + FF_RXI_CLK_0 => ff_rxiclk_ch0, + FF_TXI_CLK_0 => ff_txiclk_ch0, + FF_EBRD_CLK_0 => ff_ebrd_clk_0, + FF_RX_F_CLK_0 => ff_rxfullclk_ch0, + FF_RX_H_CLK_0 => open, + FF_RX_Q_CLK_0 => open, + FF_TX_D_0_0 => ff_txdata_ch0(0), + FF_TX_D_0_1 => ff_txdata_ch0(1), + FF_TX_D_0_2 => ff_txdata_ch0(2), + FF_TX_D_0_3 => ff_txdata_ch0(3), + FF_TX_D_0_4 => ff_txdata_ch0(4), + FF_TX_D_0_5 => ff_txdata_ch0(5), + FF_TX_D_0_6 => ff_txdata_ch0(6), + FF_TX_D_0_7 => ff_txdata_ch0(7), + FF_TX_D_0_8 => ff_tx_k_cntrl_ch0, + FF_TX_D_0_9 => fpsc_vlo, + FF_TX_D_0_10 => ff_xmit_ch0, + FF_TX_D_0_11 => ff_correct_disp_ch0, + FF_TX_D_0_12 => fpsc_vlo, + FF_TX_D_0_13 => fpsc_vlo, + FF_TX_D_0_14 => fpsc_vlo, + FF_TX_D_0_15 => fpsc_vlo, + FF_TX_D_0_16 => fpsc_vlo, + FF_TX_D_0_17 => fpsc_vlo, + FF_TX_D_0_18 => fpsc_vlo, + FF_TX_D_0_19 => fpsc_vlo, + FF_TX_D_0_20 => fpsc_vlo, + FF_TX_D_0_21 => fpsc_vlo, + FF_TX_D_0_22 => fpsc_vlo, + FF_TX_D_0_23 => fpsc_vlo, + FF_RX_D_0_0 => ff_rxdata_ch0(0), + FF_RX_D_0_1 => ff_rxdata_ch0(1), + FF_RX_D_0_2 => ff_rxdata_ch0(2), + FF_RX_D_0_3 => ff_rxdata_ch0(3), + FF_RX_D_0_4 => ff_rxdata_ch0(4), + FF_RX_D_0_5 => ff_rxdata_ch0(5), + FF_RX_D_0_6 => ff_rxdata_ch0(6), + FF_RX_D_0_7 => ff_rxdata_ch0(7), + FF_RX_D_0_8 => ff_rx_k_cntrl_ch0, + FF_RX_D_0_9 => ff_disp_err_ch0, + FF_RX_D_0_10 => ff_cv_ch0, + FF_RX_D_0_11 => ff_rx_even_ch0, + FF_RX_D_0_12 => open, + FF_RX_D_0_13 => open, + FF_RX_D_0_14 => open, + FF_RX_D_0_15 => open, + FF_RX_D_0_16 => open, + FF_RX_D_0_17 => open, + FF_RX_D_0_18 => open, + FF_RX_D_0_19 => open, + FF_RX_D_0_20 => open, + FF_RX_D_0_21 => open, + FF_RX_D_0_22 => open, + FF_RX_D_0_23 => open, + FFC_RRST_0 => ffc_rrst_ch0, + FFC_SIGNAL_DETECT_0 => fpsc_vlo, + FFC_ENABLE_CGALIGN_0 => fpsc_vlo, + FFC_SB_PFIFO_LP_0 => fpsc_vlo, + FFC_PFIFO_CLR_0 => fpsc_vlo, + FFC_FB_LOOPBACK_0 => fpsc_vlo, + FFC_SB_INV_RX_0 => fpsc_vlo, + FFC_PCIE_CT_0 => fpsc_vlo, + FFC_PCI_DET_EN_0 => fpsc_vlo, + FFS_PCIE_DONE_0 => open, + FFS_PCIE_CON_0 => open, + FFC_EI_EN_0 => fpsc_vlo, + FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0, + FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0, + FFC_TXPWDNB_0 => ffc_txpwdnb_ch0, + FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0, + FFS_RLOS_LO_0 => ffs_rlos_lo_ch0, + FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0, + FFS_CC_UNDERRUN_0 => open, + FFS_CC_OVERRUN_0 => open, + FFS_RXFBFIFO_ERROR_0 => open, + FFS_TXFBFIFO_ERROR_0 => open, + FFS_RLOL_0 => ffs_rlol_ch0, + OOB_OUT_0 => oob_out_ch0, + HDINP1 => fpsc_vlo, + HDINN1 => fpsc_vlo, + HDOUTP1 => open, + HDOUTN1 => open, + SCISELCH1 => fpsc_vlo, + SCIENCH1 => fpsc_vlo, + FF_RXI_CLK_1 => fpsc_vlo, + FF_TXI_CLK_1 => fpsc_vlo, + FF_EBRD_CLK_1 => fpsc_vlo, + FF_RX_F_CLK_1 => open, + FF_RX_H_CLK_1 => open, + FF_RX_Q_CLK_1 => open, + FF_TX_D_1_0 => fpsc_vlo, + FF_TX_D_1_1 => fpsc_vlo, + FF_TX_D_1_2 => fpsc_vlo, + FF_TX_D_1_3 => fpsc_vlo, + FF_TX_D_1_4 => fpsc_vlo, + FF_TX_D_1_5 => fpsc_vlo, + FF_TX_D_1_6 => fpsc_vlo, + FF_TX_D_1_7 => fpsc_vlo, + FF_TX_D_1_8 => fpsc_vlo, + FF_TX_D_1_9 => fpsc_vlo, + FF_TX_D_1_10 => fpsc_vlo, + FF_TX_D_1_11 => fpsc_vlo, + FF_TX_D_1_12 => fpsc_vlo, + FF_TX_D_1_13 => fpsc_vlo, + FF_TX_D_1_14 => fpsc_vlo, + FF_TX_D_1_15 => fpsc_vlo, + FF_TX_D_1_16 => fpsc_vlo, + FF_TX_D_1_17 => fpsc_vlo, + FF_TX_D_1_18 => fpsc_vlo, + FF_TX_D_1_19 => fpsc_vlo, + FF_TX_D_1_20 => fpsc_vlo, + FF_TX_D_1_21 => fpsc_vlo, + FF_TX_D_1_22 => fpsc_vlo, + FF_TX_D_1_23 => fpsc_vlo, + FF_RX_D_1_0 => open, + FF_RX_D_1_1 => open, + FF_RX_D_1_2 => open, + FF_RX_D_1_3 => open, + FF_RX_D_1_4 => open, + FF_RX_D_1_5 => open, + FF_RX_D_1_6 => open, + FF_RX_D_1_7 => open, + FF_RX_D_1_8 => open, + FF_RX_D_1_9 => open, + FF_RX_D_1_10 => open, + FF_RX_D_1_11 => open, + FF_RX_D_1_12 => open, + FF_RX_D_1_13 => open, + FF_RX_D_1_14 => open, + FF_RX_D_1_15 => open, + FF_RX_D_1_16 => open, + FF_RX_D_1_17 => open, + FF_RX_D_1_18 => open, + FF_RX_D_1_19 => open, + FF_RX_D_1_20 => open, + FF_RX_D_1_21 => open, + FF_RX_D_1_22 => open, + FF_RX_D_1_23 => open, + FFC_RRST_1 => fpsc_vlo, + FFC_SIGNAL_DETECT_1 => fpsc_vlo, + FFC_SB_PFIFO_LP_1 => fpsc_vlo, + FFC_SB_INV_RX_1 => fpsc_vlo, + FFC_PFIFO_CLR_1 => fpsc_vlo, + FFC_PCIE_CT_1 => fpsc_vlo, + FFC_PCI_DET_EN_1 => fpsc_vlo, + FFC_FB_LOOPBACK_1 => fpsc_vlo, + FFC_ENABLE_CGALIGN_1 => fpsc_vlo, + FFC_EI_EN_1 => fpsc_vlo, + FFC_LANE_TX_RST_1 => fpsc_vlo, + FFC_LANE_RX_RST_1 => fpsc_vlo, + FFC_TXPWDNB_1 => fpsc_vlo, + FFC_RXPWDNB_1 => fpsc_vlo, + FFS_RLOS_LO_1 => open, + FFS_PCIE_DONE_1 => open, + FFS_PCIE_CON_1 => open, + FFS_LS_SYNC_STATUS_1 => open, + FFS_CC_UNDERRUN_1 => open, + FFS_CC_OVERRUN_1 => open, + FFS_RLOL_1 => open, + FFS_RXFBFIFO_ERROR_1 => open, + FFS_TXFBFIFO_ERROR_1 => open, + OOB_OUT_1 => open, + HDINP2 => fpsc_vlo, + HDINN2 => fpsc_vlo, + HDOUTP2 => open, + HDOUTN2 => open, + SCISELCH2 => fpsc_vlo, + SCIENCH2 => fpsc_vlo, + FF_RXI_CLK_2 => fpsc_vlo, + FF_TXI_CLK_2 => fpsc_vlo, + FF_EBRD_CLK_2 => fpsc_vlo, + FF_RX_F_CLK_2 => open, + FF_RX_H_CLK_2 => open, + FF_RX_Q_CLK_2 => open, + FF_TX_D_2_0 => fpsc_vlo, + FF_TX_D_2_1 => fpsc_vlo, + FF_TX_D_2_2 => fpsc_vlo, + FF_TX_D_2_3 => fpsc_vlo, + FF_TX_D_2_4 => fpsc_vlo, + FF_TX_D_2_5 => fpsc_vlo, + FF_TX_D_2_6 => fpsc_vlo, + FF_TX_D_2_7 => fpsc_vlo, + FF_TX_D_2_8 => fpsc_vlo, + FF_TX_D_2_9 => fpsc_vlo, + FF_TX_D_2_10 => fpsc_vlo, + FF_TX_D_2_11 => fpsc_vlo, + FF_TX_D_2_12 => fpsc_vlo, + FF_TX_D_2_13 => fpsc_vlo, + FF_TX_D_2_14 => fpsc_vlo, + FF_TX_D_2_15 => fpsc_vlo, + FF_TX_D_2_16 => fpsc_vlo, + FF_TX_D_2_17 => fpsc_vlo, + FF_TX_D_2_18 => fpsc_vlo, + FF_TX_D_2_19 => fpsc_vlo, + FF_TX_D_2_20 => fpsc_vlo, + FF_TX_D_2_21 => fpsc_vlo, + FF_TX_D_2_22 => fpsc_vlo, + FF_TX_D_2_23 => fpsc_vlo, + FF_RX_D_2_0 => open, + FF_RX_D_2_1 => open, + FF_RX_D_2_2 => open, + FF_RX_D_2_3 => open, + FF_RX_D_2_4 => open, + FF_RX_D_2_5 => open, + FF_RX_D_2_6 => open, + FF_RX_D_2_7 => open, + FF_RX_D_2_8 => open, + FF_RX_D_2_9 => open, + FF_RX_D_2_10 => open, + FF_RX_D_2_11 => open, + FF_RX_D_2_12 => open, + FF_RX_D_2_13 => open, + FF_RX_D_2_14 => open, + FF_RX_D_2_15 => open, + FF_RX_D_2_16 => open, + FF_RX_D_2_17 => open, + FF_RX_D_2_18 => open, + FF_RX_D_2_19 => open, + FF_RX_D_2_20 => open, + FF_RX_D_2_21 => open, + FF_RX_D_2_22 => open, + FF_RX_D_2_23 => open, + FFC_RRST_2 => fpsc_vlo, + FFC_SIGNAL_DETECT_2 => fpsc_vlo, + FFC_SB_PFIFO_LP_2 => fpsc_vlo, + FFC_SB_INV_RX_2 => fpsc_vlo, + FFC_PFIFO_CLR_2 => fpsc_vlo, + FFC_PCIE_CT_2 => fpsc_vlo, + FFC_PCI_DET_EN_2 => fpsc_vlo, + FFC_FB_LOOPBACK_2 => fpsc_vlo, + FFC_ENABLE_CGALIGN_2 => fpsc_vlo, + FFC_EI_EN_2 => fpsc_vlo, + FFC_LANE_TX_RST_2 => fpsc_vlo, + FFC_LANE_RX_RST_2 => fpsc_vlo, + FFC_TXPWDNB_2 => fpsc_vlo, + FFC_RXPWDNB_2 => fpsc_vlo, + FFS_RLOS_LO_2 => open, + FFS_PCIE_DONE_2 => open, + FFS_PCIE_CON_2 => open, + FFS_LS_SYNC_STATUS_2 => open, + FFS_CC_UNDERRUN_2 => open, + FFS_CC_OVERRUN_2 => open, + FFS_RLOL_2 => open, + FFS_RXFBFIFO_ERROR_2 => open, + FFS_TXFBFIFO_ERROR_2 => open, + OOB_OUT_2 => open, + HDINP3 => fpsc_vlo, + HDINN3 => fpsc_vlo, + HDOUTP3 => open, + HDOUTN3 => open, + SCISELCH3 => fpsc_vlo, + SCIENCH3 => fpsc_vlo, + FF_RXI_CLK_3 => fpsc_vlo, + FF_TXI_CLK_3 => fpsc_vlo, + FF_EBRD_CLK_3 => fpsc_vlo, + FF_RX_F_CLK_3 => open, + FF_RX_H_CLK_3 => open, + FF_RX_Q_CLK_3 => open, + FF_TX_D_3_0 => fpsc_vlo, + FF_TX_D_3_1 => fpsc_vlo, + FF_TX_D_3_2 => fpsc_vlo, + FF_TX_D_3_3 => fpsc_vlo, + FF_TX_D_3_4 => fpsc_vlo, + FF_TX_D_3_5 => fpsc_vlo, + FF_TX_D_3_6 => fpsc_vlo, + FF_TX_D_3_7 => fpsc_vlo, + FF_TX_D_3_8 => fpsc_vlo, + FF_TX_D_3_9 => fpsc_vlo, + FF_TX_D_3_10 => fpsc_vlo, + FF_TX_D_3_11 => fpsc_vlo, + FF_TX_D_3_12 => fpsc_vlo, + FF_TX_D_3_13 => fpsc_vlo, + FF_TX_D_3_14 => fpsc_vlo, + FF_TX_D_3_15 => fpsc_vlo, + FF_TX_D_3_16 => fpsc_vlo, + FF_TX_D_3_17 => fpsc_vlo, + FF_TX_D_3_18 => fpsc_vlo, + FF_TX_D_3_19 => fpsc_vlo, + FF_TX_D_3_20 => fpsc_vlo, + FF_TX_D_3_21 => fpsc_vlo, + FF_TX_D_3_22 => fpsc_vlo, + FF_TX_D_3_23 => fpsc_vlo, + FF_RX_D_3_0 => open, + FF_RX_D_3_1 => open, + FF_RX_D_3_2 => open, + FF_RX_D_3_3 => open, + FF_RX_D_3_4 => open, + FF_RX_D_3_5 => open, + FF_RX_D_3_6 => open, + FF_RX_D_3_7 => open, + FF_RX_D_3_8 => open, + FF_RX_D_3_9 => open, + FF_RX_D_3_10 => open, + FF_RX_D_3_11 => open, + FF_RX_D_3_12 => open, + FF_RX_D_3_13 => open, + FF_RX_D_3_14 => open, + FF_RX_D_3_15 => open, + FF_RX_D_3_16 => open, + FF_RX_D_3_17 => open, + FF_RX_D_3_18 => open, + FF_RX_D_3_19 => open, + FF_RX_D_3_20 => open, + FF_RX_D_3_21 => open, + FF_RX_D_3_22 => open, + FF_RX_D_3_23 => open, + FFC_RRST_3 => fpsc_vlo, + FFC_SIGNAL_DETECT_3 => fpsc_vlo, + FFC_SB_PFIFO_LP_3 => fpsc_vlo, + FFC_SB_INV_RX_3 => fpsc_vlo, + FFC_PFIFO_CLR_3 => fpsc_vlo, + FFC_PCIE_CT_3 => fpsc_vlo, + FFC_PCI_DET_EN_3 => fpsc_vlo, + FFC_FB_LOOPBACK_3 => fpsc_vlo, + FFC_ENABLE_CGALIGN_3 => fpsc_vlo, + FFC_EI_EN_3 => fpsc_vlo, + FFC_LANE_TX_RST_3 => fpsc_vlo, + FFC_LANE_RX_RST_3 => fpsc_vlo, + FFC_TXPWDNB_3 => fpsc_vlo, + FFC_RXPWDNB_3 => fpsc_vlo, + FFS_RLOS_LO_3 => open, + FFS_PCIE_DONE_3 => open, + FFS_PCIE_CON_3 => open, + FFS_LS_SYNC_STATUS_3 => open, + FFS_CC_UNDERRUN_3 => open, + FFS_CC_OVERRUN_3 => open, + FFS_RLOL_3 => open, + FFS_RXFBFIFO_ERROR_3 => open, + FFS_TXFBFIFO_ERROR_3 => open, + OOB_OUT_3 => open, + SCIWDATA0 => fpsc_vlo, + SCIWDATA1 => fpsc_vlo, + SCIWDATA2 => fpsc_vlo, + SCIWDATA3 => fpsc_vlo, + SCIWDATA4 => fpsc_vlo, + SCIWDATA5 => fpsc_vlo, + SCIWDATA6 => fpsc_vlo, + SCIWDATA7 => fpsc_vlo, + SCIADDR0 => fpsc_vlo, + SCIADDR1 => fpsc_vlo, + SCIADDR2 => fpsc_vlo, + SCIADDR3 => fpsc_vlo, + SCIADDR4 => fpsc_vlo, + SCIADDR5 => fpsc_vlo, + SCIRDATA0 => open, + SCIRDATA1 => open, + SCIRDATA2 => open, + SCIRDATA3 => open, + SCIRDATA4 => open, + SCIRDATA5 => open, + SCIRDATA6 => open, + SCIRDATA7 => open, + SCIENAUX => fpsc_vlo, + SCISELAUX => fpsc_vlo, + SCIRD => fpsc_vlo, + SCIWSTN => fpsc_vlo, + CYAWSTN => fpsc_vlo, + SCIINT => open, + FFC_MACRO_RST => ffc_macro_rst, + FFC_QUAD_RST => ffc_quad_rst, + FFC_TRST => ffc_trst, + FF_TX_F_CLK => ff_txfullclk, + FF_TX_H_CLK => ff_txhalfclk, + FF_TX_Q_CLK => open, + REFCK2CORE => refck2core, + CIN0 => cin(0), + CIN1 => cin(1), + CIN2 => cin(2), + CIN3 => cin(3), + CIN4 => cin(4), + CIN5 => cin(5), + CIN6 => cin(6), + CIN7 => cin(7), + CIN8 => cin(8), + CIN9 => cin(9), + CIN10 => cin(10), + CIN11 => cin(11), + COUT0 => cout(0), + COUT1 => cout(1), + COUT2 => cout(2), + COUT3 => cout(3), + COUT4 => cout(4), + COUT5 => cout(5), + COUT6 => cout(6), + COUT7 => cout(7), + COUT8 => cout(8), + COUT9 => cout(9), + COUT10 => cout(10), + COUT11 => cout(11), + COUT12 => cout(12), + COUT13 => cout(13), + COUT14 => cout(14), + COUT15 => cout(15), + COUT16 => cout(16), + COUT17 => cout(17), + COUT18 => cout(18), + COUT19 => cout(19), + FFS_PLOL => ffs_plol); + +--synopsys translate_off +file_read : PROCESS +VARIABLE open_status : file_open_status; +FILE config : text; +BEGIN + file_open (open_status, config, USER_CONFIG_FILE, read_mode); + IF (open_status = name_error) THEN + report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" + severity ERROR; + END IF; + wait; +END PROCESS; +--synopsys translate_on + +end serdes_gbe_0_extclock_8b_arch ; diff --git a/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/.cvsignore b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/.cvsignore new file mode 100644 index 0000000..67edf82 --- /dev/null +++ b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/.cvsignore @@ -0,0 +1,11 @@ +*.jhd +*.naf +*.srp +*.sym +*.log +*.v +*.htm +*.tcl +*tmpl.vhd +sgmii_pcs_eval + diff --git a/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/pmi_fifo_dcLEan71301616161010.ngo b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/pmi_fifo_dcLEan71301616161010.ngo new file mode 100755 index 0000000..d3c4b97 Binary files /dev/null and b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/pmi_fifo_dcLEan71301616161010.ngo differ diff --git a/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_gbe_pcs32.lpc b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_gbe_pcs32.lpc new file mode 100755 index 0000000..6f17c6f --- /dev/null +++ b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_gbe_pcs32.lpc @@ -0,0 +1,26 @@ +[Device] +Family=ep5m00 +PartType=LFE2M100E +PartName=LFE2M100E-5F900C +SpeedGrade=-5 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=IPCFG +CoreStatus=Demo +CoreName=SGMII/Gb Ethernet PCS +CoreRevision=3.2 +ModuleName=sgmii_gbe_pcs32 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=12/10/2009 +Time=15:57:40 + +[Parameters] +RX_CTC=2 +RX_CTC_LOW=16 +RX_CTC_HIGH=32 +EasyConnect=1 diff --git a/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_gbe_pcs32.ngo b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_gbe_pcs32.ngo new file mode 100755 index 0000000..c6f8129 Binary files /dev/null and b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_gbe_pcs32.ngo differ diff --git a/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_pcs_eval.tar b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_pcs_eval.tar new file mode 100644 index 0000000..afc70d6 Binary files /dev/null and b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_pcs_eval.tar differ diff --git a/gbe_ecp2m/ipcores/tb_fifo_2048x8_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_2048x8_tmpl.vhd new file mode 100755 index 0000000..31ea3c3 --- /dev/null +++ b/gbe_ecp2m/ipcores/tb_fifo_2048x8_tmpl.vhd @@ -0,0 +1,102 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component fifo_2048x8 + port (Data : in std_logic_vector(7 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(7 downto 0); Empty: out std_logic; + Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(7 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(7 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : fifo_2048x8 + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 2051 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 2051 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 2051 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd new file mode 100755 index 0000000..faff46a --- /dev/null +++ b/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd @@ -0,0 +1,115 @@ +-- VHDL testbench template generated by SCUBA ispLever_v8.0_PROD_Build (41) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component fifo_32kx16x8_mb + port (Data : in std_logic_vector(15 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + AmEmptyThresh : in std_logic_vector(15 downto 0); + AmFullThresh : in std_logic_vector(14 downto 0); + Q : out std_logic_vector(7 downto 0); + WCNT : out std_logic_vector(15 downto 0); + RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic; + Full: out std_logic; AlmostEmpty: out std_logic; + AlmostFull: out std_logic + ); + end component; + + signal Data : std_logic_vector(15 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal AmEmptyThresh : std_logic_vector(15 downto 0) := (others => '0'); + signal AmFullThresh : std_logic_vector(14 downto 0) := (others => '0'); + signal Q : std_logic_vector(7 downto 0); + signal WCNT : std_logic_vector(15 downto 0); + signal RCNT : std_logic_vector(16 downto 0); + signal Empty: std_logic; + signal Full: std_logic; + signal AlmostEmpty: std_logic; + signal AlmostFull: std_logic; +begin + u1 : fifo_32kx16x8_mb + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + AmEmptyThresh => AmEmptyThresh, AmFullThresh => AmFullThresh, + Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full, + AlmostEmpty => AlmostEmpty, AlmostFull => AlmostFull + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 32771 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 32771 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 32771 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_tmpl.vhd new file mode 100755 index 0000000..3bbafb6 --- /dev/null +++ b/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_tmpl.vhd @@ -0,0 +1,106 @@ +-- VHDL testbench template generated by SCUBA ispLever_v8.0_PROD_Build (41) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component fifo_32kx16x8 + port (Data : in std_logic_vector(15 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(7 downto 0); + WCNT : out std_logic_vector(15 downto 0); + RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic; + Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(15 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(7 downto 0); + signal WCNT : std_logic_vector(15 downto 0); + signal RCNT : std_logic_vector(16 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : fifo_32kx16x8 + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 32771 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 32771 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 32771 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_4096x32_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_4096x32_tmpl.vhd new file mode 100755 index 0000000..69b93a2 --- /dev/null +++ b/gbe_ecp2m/ipcores/tb_fifo_4096x32_tmpl.vhd @@ -0,0 +1,102 @@ +-- VHDL testbench template generated by SCUBA ispLever_v8.0_PROD_Build (41) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component fifo_4096x32 + port (Data : in std_logic_vector(31 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(31 downto 0); Empty: out std_logic; + Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(31 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(31 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : fifo_4096x32 + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 4099 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 4099 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 4099 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_4096x9_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_4096x9_tmpl.vhd new file mode 100755 index 0000000..a300fbe --- /dev/null +++ b/gbe_ecp2m/ipcores/tb_fifo_4096x9_tmpl.vhd @@ -0,0 +1,102 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component fifo_4096x9 + port (Data : in std_logic_vector(8 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(8 downto 0); Empty: out std_logic; + Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(8 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(8 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : fifo_4096x9 + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 4099 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 4099 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 4099 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_64kx8_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_64kx8_tmpl.vhd new file mode 100755 index 0000000..b60730e --- /dev/null +++ b/gbe_ecp2m/ipcores/tb_fifo_64kx8_tmpl.vhd @@ -0,0 +1,102 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component fifo_64kx8 + port (Data : in std_logic_vector(7 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(7 downto 0); Empty: out std_logic; + Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(7 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(7 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : fifo_64kx8 + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 65539 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 65539 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 65539 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_ip_mem_tmpl.vhd b/gbe_ecp2m/ipcores/tb_ip_mem_tmpl.vhd new file mode 100755 index 0000000..3b2d37f --- /dev/null +++ b/gbe_ecp2m/ipcores/tb_ip_mem_tmpl.vhd @@ -0,0 +1,174 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component ip_mem + port (DataInA : in std_logic_vector(31 downto 0); + DataInB : in std_logic_vector(31 downto 0); + AddressA : in std_logic_vector(7 downto 0); + AddressB : in std_logic_vector(7 downto 0); ClockA: in std_logic; + ClockB: in std_logic; ClockEnA: in std_logic; + ClockEnB: in std_logic; WrA: in std_logic; WrB: in std_logic; + ResetA: in std_logic; ResetB: in std_logic; + QA : out std_logic_vector(31 downto 0); + QB : out std_logic_vector(31 downto 0) + ); + end component; + + signal DataInA : std_logic_vector(31 downto 0) := (others => '0'); + signal DataInB : std_logic_vector(31 downto 0) := (others => '0'); + signal AddressA : std_logic_vector(7 downto 0) := (others => '0'); + signal AddressB : std_logic_vector(7 downto 0) := (others => '0'); + signal ClockA: std_logic := '0'; + signal ClockB: std_logic := '0'; + signal ClockEnA: std_logic := '0'; + signal ClockEnB: std_logic := '0'; + signal WrA: std_logic := '0'; + signal WrB: std_logic := '0'; + signal ResetA: std_logic := '0'; + signal ResetB: std_logic := '0'; + signal QA : std_logic_vector(31 downto 0); + signal QB : std_logic_vector(31 downto 0); +begin + u1 : ip_mem + port map (DataInA => DataInA, DataInB => DataInB, AddressA => AddressA, + AddressB => AddressB, ClockA => ClockA, ClockB => ClockB, + ClockEnA => ClockEnA, ClockEnB => ClockEnB, WrA => WrA, WrB => WrB, + ResetA => ResetA, ResetB => ResetB, QA => QA, QB => QB + ); + + process + + begin + DataInA <= (others => '0') ; + wait for 100 ns; + wait until ResetA = '0'; + for i in 0 to 259 loop + wait until ClockA'event and ClockA = '1'; + DataInA <= DataInA + '1' after 1 ns; + end loop; + wait; + end process; + + process + + begin + DataInB <= (others => '0') ; + wait for 100 ns; + wait until ResetB = '0'; + wait until WrB = '1'; + for i in 0 to 259 loop + wait until ClockB'event and ClockB = '1'; + DataInB <= DataInB + '1' after 1 ns; + end loop; + wait; + end process; + + process + + begin + AddressA <= (others => '0') ; + wait for 100 ns; + wait until ResetA = '0'; + for i in 0 to 518 loop + wait until ClockA'event and ClockA = '1'; + AddressA <= AddressA + '1' after 1 ns; + end loop; + wait; + end process; + + process + + begin + AddressB <= (others => '0') ; + wait for 100 ns; + wait until ResetB = '0'; + wait until WrB = '1'; + for i in 0 to 518 loop + wait until ClockB'event and ClockB = '1'; + AddressB <= AddressB + '1' after 1 ns; + end loop; + wait; + end process; + + ClockA <= not ClockA after 5.00 ns; + + ClockB <= not ClockB after 5.00 ns; + + process + + begin + ClockEnA <= '0' ; + wait for 100 ns; + wait until ResetA = '0'; + ClockEnA <= '1' ; + wait; + end process; + + process + + begin + ClockEnB <= '0' ; + wait for 100 ns; + wait until ResetB = '0'; + ClockEnB <= '1' ; + wait; + end process; + + process + + begin + WrA <= '0' ; + wait until ResetA = '0'; + for i in 0 to 259 loop + wait until ClockA'event and ClockA = '1'; + WrA <= '1' after 1 ns; + end loop; + WrA <= '0' ; + wait; + end process; + + process + + begin + WrB <= '0' ; + wait until ResetB = '0'; + wait until WrA = '1'; + wait until WrA = '0'; + for i in 0 to 259 loop + wait until ClockA'event and ClockA = '1'; + end loop; + for i in 0 to 259 loop + wait until ClockB'event and ClockB = '1'; + WrB <= '1' after 1 ns; + end loop; + WrB <= '0' ; + wait; + end process; + + process + + begin + ResetA <= '1' ; + wait for 100 ns; + ResetA <= '0' ; + wait; + end process; + + process + + begin + ResetB <= '1' ; + wait for 100 ns; + ResetB <= '0' ; + wait; + end process; + +end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_mac_init_mem_tmpl.vhd b/gbe_ecp2m/ipcores/tb_mac_init_mem_tmpl.vhd new file mode 100755 index 0000000..fd983a6 --- /dev/null +++ b/gbe_ecp2m/ipcores/tb_mac_init_mem_tmpl.vhd @@ -0,0 +1,64 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component mac_init_mem + port (Address : in std_logic_vector(5 downto 0); + OutClock: in std_logic; OutClockEn: in std_logic; + Reset: in std_logic; Q : out std_logic_vector(7 downto 0) + ); + end component; + + signal Address : std_logic_vector(5 downto 0) := (others => '0'); + signal OutClock: std_logic := '0'; + signal OutClockEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal Q : std_logic_vector(7 downto 0); +begin + u1 : mac_init_mem + port map (Address => Address, OutClock => OutClock, OutClockEn => OutClockEn, + Reset => Reset, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 57 loop + wait until OutClock'event and OutClock = '1'; + Address <= Address + '1' after 1 ns; + end loop; + wait; + end process; + + OutClock <= not OutClock after 5.00 ns; + + process + + begin + OutClockEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + OutClockEn <= '1' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/gbe_ecp2m/ipcores/tsmac3/.cvsignore b/gbe_ecp2m/ipcores/tsmac3/.cvsignore new file mode 100644 index 0000000..1fb5c68 --- /dev/null +++ b/gbe_ecp2m/ipcores/tsmac3/.cvsignore @@ -0,0 +1,9 @@ +*.jhd +*.naf +*.srp +*.sym +*.log +*.tcl +*.v +*tmpl.vhd +ts_mac_eval diff --git a/gbe_ecp2m/ipcores/tsmac3/pmi_ram_dpEbnonessdn208256208256.ngo b/gbe_ecp2m/ipcores/tsmac3/pmi_ram_dpEbnonessdn208256208256.ngo new file mode 100755 index 0000000..e40fc8f Binary files /dev/null and b/gbe_ecp2m/ipcores/tsmac3/pmi_ram_dpEbnonessdn208256208256.ngo differ diff --git a/gbe_ecp2m/ipcores/tsmac3/pmi_ram_dpEbnonessdn96649664.ngo b/gbe_ecp2m/ipcores/tsmac3/pmi_ram_dpEbnonessdn96649664.ngo new file mode 100755 index 0000000..7e4f604 Binary files /dev/null and b/gbe_ecp2m/ipcores/tsmac3/pmi_ram_dpEbnonessdn96649664.ngo differ diff --git a/gbe_ecp2m/ipcores/tsmac3/ts_mac_eval.tar b/gbe_ecp2m/ipcores/tsmac3/ts_mac_eval.tar new file mode 100644 index 0000000..bd092f2 Binary files /dev/null and b/gbe_ecp2m/ipcores/tsmac3/ts_mac_eval.tar differ diff --git a/gbe_ecp2m/ipcores/tsmac3/tsmac3.lpc b/gbe_ecp2m/ipcores/tsmac3/tsmac3.lpc new file mode 100755 index 0000000..011a767 --- /dev/null +++ b/gbe_ecp2m/ipcores/tsmac3/tsmac3.lpc @@ -0,0 +1,28 @@ +[Device] +Family=ep5m00 +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=IPCFG +CoreStatus=Demo +CoreName=Tri-Speed Ethernet MAC +CoreRevision=3.0 +ModuleName=tsmac3 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/24/2009 +Time=21:02:34 + +[Parameters] +MIIM=No +MODE=SGMII easy connect +SYNP_TOOL=1 +PREC_TOOL=0 +MODS_TOOL=1 +ALDC_TOOL=0 diff --git a/gbe_ecp2m/ipcores/tsmac3/tsmac3.ngo b/gbe_ecp2m/ipcores/tsmac3/tsmac3.ngo new file mode 100755 index 0000000..5c0e54f Binary files /dev/null and b/gbe_ecp2m/ipcores/tsmac3/tsmac3.ngo differ diff --git a/gbe_ecp2m/mb_mac_sim.vhd b/gbe_ecp2m/mb_mac_sim.vhd new file mode 100755 index 0000000..1b1f57e --- /dev/null +++ b/gbe_ecp2m/mb_mac_sim.vhd @@ -0,0 +1,331 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +use IEEE.std_logic_arith.all; + +library work; +--use work.trb_net_std.all; +--use work.trb_net_components.all; +--use work.trb_net16_hub_func.all; + +entity mb_mac_sim is +port ( + -------------------------------------------------------------------------- + --------------- clock, reset, clock enable ------------------------------- + HCLK : in std_logic; + TX_MAC_CLK : in std_logic; + RX_MAC_CLK : in std_logic; + RESET_N : in std_logic; + TXMAC_CLK_EN : in std_logic; + RXMAC_CLK_EN : in std_logic; + -------------------------------------------------------------------------- + --------------- SGMII receive interface ---------------------------------- + RXD : in std_logic_vector(7 downto 0); + RX_DV : in std_logic; + RX_ER : in std_logic; + COL : in std_logic; + CRS : in std_logic; + -------------------------------------------------------------------------- + --------------- SGMII transmit interface --------------------------------- + TXD : out std_logic_vector(7 downto 0); + TX_EN : out std_logic; + TX_ER : out std_logic; + -------------------------------------------------------------------------- + --------------- CPU configuration interface ------------------------------ + HADDR : in std_logic_vector(7 downto 0); + HDATAIN : in std_logic_vector(7 downto 0); + HCS_N : in std_logic; + HWRITE_N : in std_logic; + HREAD_N : in std_logic; + HDATAOUT : out std_logic_vector(7 downto 0); + HDATAOUT_EN_N : out std_logic; + HREADY_N : out std_logic; + CPU_IF_GBIT_EN : out std_logic; + -------------------------------------------------------------------------- + --------------- Transmit FIFO interface ---------------------------------- + TX_FIFODATA : in std_logic_vector(7 downto 0); + TX_FIFOAVAIL : in std_logic; + TX_FIFOEOF : in std_logic; + TX_FIFOEMPTY : in std_logic; + TX_MACREAD : out std_logic; + TX_DONE : out std_logic; + TX_SNDPAUSTIM : in std_logic_vector(15 downto 0); + TX_SNDPAUSREQ : in std_logic; + TX_FIFOCTRL : in std_logic; + TX_DISCFRM : out std_logic; + TX_STATEN : out std_logic; + TX_STATVEC : out std_logic_vector(30 downto 0); + -------------------------------------------------------------------------- + --------------- Receive FIFO interface ----------------------------------- + RX_DBOUT : out std_logic_vector(7 downto 0); + RX_FIFO_FULL : in std_logic; + IGNORE_PKT : in std_logic; + RX_FIFO_ERROR : out std_logic; + RX_STAT_VECTOR : out std_logic_vector(31 downto 0); + RX_STAT_EN : out std_logic; + RX_WRITE : out std_logic; + RX_EOF : out std_logic; + RX_ERROR : out std_logic +); +end mb_mac_sim; + +architecture mb_mac_sim of mb_mac_sim is + + +-- CPU interface stuff +type HC_STATES is (HC_SLEEP, HC_READ, HC_WRITE, HC_RACK, HC_WACK); +signal HC_CURRENT_STATE, HC_NEXT_STATE: HC_STATES; + +signal hready_n_comb : std_logic; +signal hready_n_buf : std_logic; +signal hdataout_en_n_comb : std_logic; +signal hdataout_en_n_buf : std_logic; + +-- TX stuff +type TX_STATES is (TX_SLEEP, TX_READ, TX_DELAY, TX_TRANS, TX_CHECK); +signal TX_CURRENT_STATE, TX_NEXT_STATE: TX_STATES; + +signal tx_bsm : std_logic_vector(3 downto 0); +signal tx_macread_comb : std_logic; +signal tx_done_comb : std_logic; +signal tx_done_buf : std_logic; + +signal preread_ctr : std_logic_vector(3 downto 0); -- preread counter for TX +signal preread_ce_comb : std_logic; +signal preread_rst_comb : std_logic; +signal preread_done_comb : std_logic; +signal read_on_comb : std_logic; + + +begin + +------------------------------------------------------------------------------ +-- state machine for configuration interface +------------------------------------------------------------------------------ +-- BUG: no register simulated here! + +-- state registers +HC_STATE_MEM: process( HCLK ) +begin + if ( RESET_N = '0' ) then + HC_CURRENT_STATE <= HC_SLEEP; + hready_n_buf <= '1'; + hdataout_en_n_buf <= '1'; + elsif( rising_edge(HCLK) ) then + HC_CURRENT_STATE <= HC_NEXT_STATE; + hready_n_buf <= hready_n_comb; + hdataout_en_n_buf <= hdataout_en_n_comb; + end if; +end process HC_STATE_MEM; + +-- state transitions +HC_STATE_TRANSFORM: process( HC_CURRENT_STATE, HCS_N, HREAD_N, HWRITE_N ) +begin + HC_NEXT_STATE <= HC_SLEEP; -- avoid latches + hready_n_comb <= '1'; + hdataout_en_n_comb <= '1'; + case HC_CURRENT_STATE is + when HC_SLEEP => if ( (HCS_N = '0') and (HREAD_N = '0') ) then + HC_NEXT_STATE <= HC_READ; + elsif( (HCS_N = '0') and (HWRITE_N = '0') ) then + HC_NEXT_STATE <= HC_WRITE; + else + HC_NEXT_STATE <= HC_SLEEP; + end if; + when HC_READ => HC_NEXT_STATE <= HC_RACK; + hdataout_en_n_comb <= '0'; + hready_n_comb <= '0'; + when HC_RACK => HC_NEXT_STATE <= HC_SLEEP; + when HC_WRITE => HC_NEXT_STATE <= HC_WACK; + hready_n_comb <= '0'; + when HC_WACK => HC_NEXT_STATE <= HC_SLEEP; + when others => HC_NEXT_STATE <= HC_SLEEP; + end case; +end process HC_STATE_TRANSFORM; + +HREADY_N <= hready_n_buf; +HDATAOUT_EN_N <= hdataout_en_n_buf; + +------------------------------------------------------------------------------ +-- state machine for "transmission" +------------------------------------------------------------------------------ + +-- preread counter +THE_PREREAD_CTR: process( TX_MAC_CLK ) +begin + if ( RESET_N = '0' ) then + preread_ctr <= (others => '0'); + elsif( rising_edge(TX_MAC_CLK) ) then + if ( preread_rst_comb = '1' ) then + preread_ctr <= (others => '0'); + elsif( preread_ce_comb = '1' ) then + preread_ctr <= preread_ctr + 1; + end if; + end if; +end process THE_PREREAD_CTR; +preread_done_comb <= '1' when (preread_ctr = x"6") + else '0'; + +-- state registers +TX_STATE_MEM: process( TX_MAC_CLK, RESET_N ) +begin + if ( RESET_N = '0' ) then + TX_CURRENT_STATE <= TX_SLEEP; + tx_done_buf <= '0'; + elsif( rising_edge(TX_MAC_CLK) ) then + TX_CURRENT_STATE <= TX_NEXT_STATE; + tx_done_buf <= tx_done_comb; + end if; +end process TX_STATE_MEM; + +tx_macread_comb <= preread_ce_comb or read_on_comb; + +-- state transitions +TX_STATE_TRANSFORM: process( TX_CURRENT_STATE, TX_FIFOEMPTY, TX_FIFOAVAIL, TX_FIFOEOF, preread_done_comb ) +begin + TX_NEXT_STATE <= TX_SLEEP; -- avoid latches + preread_ce_comb <= '0'; + preread_rst_comb <= '0'; + read_on_comb <= '0'; + tx_done_comb <= '0'; + case TX_CURRENT_STATE is + when TX_SLEEP => tx_bsm <= x"0"; + if( TX_FIFOEMPTY = '0' ) then + TX_NEXT_STATE <= TX_READ; + preread_ce_comb <= '1'; + else + TX_NEXT_STATE <= TX_SLEEP; + end if; + when TX_READ => tx_bsm <= x"1"; + if ( TX_FIFOEMPTY = '1' ) then + TX_NEXT_STATE <= TX_DELAY; + preread_rst_comb <= '1'; + elsif( (preread_done_comb = '1') and (TX_FIFOAVAIL = '0') ) then + TX_NEXT_STATE <= TX_DELAY; + preread_rst_comb <= '1'; + elsif( (preread_done_comb = '1') and (TX_FIFOAVAIL = '1') ) then + TX_NEXT_STATE <= TX_TRANS; + preread_rst_comb <= '1'; + read_on_comb <= '1'; + else + TX_NEXT_STATE <= TX_READ; + preread_ce_comb <= '1'; + end if; + when TX_DELAY => tx_bsm <= x"2"; + if( TX_FIFOAVAIL = '1' ) then + TX_NEXT_STATE <= TX_TRANS; + read_on_comb <= '1'; + else + TX_NEXT_STATE <= TX_DELAY; + end if; + when TX_TRANS => tx_bsm <= x"3"; + if( TX_FIFOEOF = '1' ) then + TX_NEXT_STATE <= TX_CHECK; + tx_done_comb <= '1'; -- don't know if this is realistic + else + TX_NEXT_STATE <= TX_TRANS; + read_on_comb <= '1'; + end if; + when TX_CHECK => tx_bsm <= x"4"; + if( (TX_FIFOEMPTY = '0') and (TX_FIFOAVAIL = '1') ) then + TX_NEXT_STATE <= TX_READ; + preread_ce_comb <= '1'; + else + TX_NEXT_STATE <= TX_SLEEP; + end if; + when others => tx_bsm <= x"f"; + TX_NEXT_STATE <= TX_SLEEP; + end case; +end process TX_STATE_TRANSFORM; + + + + +------------------------------------------------------------------------------ +-- Fake signals +------------------------------------------------------------------------------ +RX_DBOUT <= preread_ctr & tx_bsm; -- x"00"; +RX_FIFO_ERROR <= '0'; +RX_STAT_VECTOR <= x"0000_0000"; +RX_STAT_EN <= '0'; +RX_WRITE <= '0'; +RX_EOF <= '0'; +RX_ERROR <= '0'; + +TX_DISCFRM <= '0'; +TX_EN <= '0'; +TX_ER <= '0'; +TX_STATVEC <= (others => '0'); +TX_STATEN <= '0'; +TXD <= x"00"; + +CPU_IF_GBIT_EN <= '0'; + +TX_DONE <= tx_done_buf; +TX_MACREAD <= tx_macread_comb; + +HDATAOUT <= x"00"; + + +end mb_mac_sim; + + +--port map( +-- -------------------------------------------------------------------------- +-- --------------- clock, reset, clock enable ------------------------------- +-- hclk => CLK, -- (in) host clock (100MHz) +-- txmac_clk => TX_MAC_CLK, -- (in) GbE clock (125MHz) +-- rxmac_clk => '0', -- (in) not used (no receiving on GbE) +-- reset_n => GSR_N, -- (in) global set/reset +-- txmac_clk_en => TSM_TX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation +-- rxmac_clk_en => TSM_RX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation +-- -------------------------------------------------------------------------- +-- --------------- SGMII receive interface ---------------------------------- +-- rxd => x"00", -- (in) receive data from SGMII core +-- rx_dv => '0', -- (in) data valid from SGMII core +-- rx_er => '0', -- (in) receive data error +-- col => TSM_COL_IN, -- (in) collision from SGMII core +-- crs => TSM_CRS_IN, -- (in) carrier sense from SGMII core +-- -------------------------------------------------------------------------- +-- --------------- SGMII transmit interface --------------------------------- +-- txd => CH_TXD_OUT, -- (out) transmit data to SGMII core +-- tx_en => CH_TX_EN_OUT, -- (out) transmit enable +-- tx_er => CH_TX_ER_OUT, -- (out) transmit error +-- -------------------------------------------------------------------------- +-- --------------- CPU configuration interface ------------------------------ +-- haddr => haddr, -- (in) host address bus for configuration +-- hdatain => hdataout, -- (in) host data bus for write accesses +-- hcs_n => hcs, -- (in) host chip select signal +-- hwrite_n => hwrite, -- (in) host write strobe signal +-- hread_n => hread, -- (in) host read strobe signal +-- hdataout => hdatain, -- (out) host data bus for read accesses +-- hdataout_en_n => hdataout_en, -- (out) read data valid signal +-- hready_n => hready, -- (out) data acknowledge signal +-- cpu_if_gbit_en => open, -- (out) status bit +-- -------------------------------------------------------------------------- +-- --------------- Transmit FIFO interface ---------------------------------- +-- tx_fifodata => ft_data(7 downto 0), -- (in) transmit FIFO data bus +-- tx_fifoavail => mac_fifoavail, -- (in) transmit FIFO data available +-- tx_fifoeof => mac_fifoeof, -- (in) transmit FIFO end of frame +-- tx_fifoempty => mac_fifoempty, -- (in) transmit FIFO empty +-- tx_macread => mac_tx_rd_en, -- (out) transmit FIFO read +-- tx_done => mac_tx_done, -- (out) transmit done (without errors) +-- tx_sndpaustim => x"0000", -- (in) PAUSE frame timer +-- tx_sndpausreq => '0', -- (in) PAUSE frame request +-- tx_fifoctrl => '0', -- (in) FIFO control frame ('0' = data, '1' = control) +-- tx_discfrm => open, -- (out) discard frame +-- tx_staten => open, -- (out) transmit statistics vector enable +-- tx_statvec => open, -- (out) transmit statistics vector +-- -------------------------------------------------------------------------- +-- --------------- Receive FIFO interface ----------------------------------- +-- rx_dbout => open, -- (out) receive FIFO data output +-- rx_fifo_full => '0', -- (in) receive FIFO full +-- ignore_pkt => '0', -- (in) ignore next packet +-- rx_fifo_error => open, -- (out) receive FIFO error +-- rx_stat_vector => open, -- (out) receive statistics vector +-- rx_stat_en => open, -- (out) receive statistics vector enable +-- rx_write => open, -- (out) receive FIFO write +-- rx_eof => open, -- (out) end of frame +-- rx_error => open -- (out) receive packet error +--); diff --git a/gbe_ecp2m/tb_feeder.vhd b/gbe_ecp2m/tb_feeder.vhd new file mode 100755 index 0000000..d526404 --- /dev/null +++ b/gbe_ecp2m/tb_feeder.vhd @@ -0,0 +1,300 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT feeder + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + CTS_NUMBER_IN : IN std_logic_vector(15 downto 0); + CTS_CODE_IN : IN std_logic_vector(7 downto 0); + CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0); + CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0); + CTS_START_READOUT_IN : IN std_logic; + CTS_READ_IN : IN std_logic; + FEE_DATA_IN : IN std_logic_vector(15 downto 0); + FEE_DATAREADY_IN : IN std_logic; + FEE_BUSY_IN : IN std_logic; + FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0); + PC_READY_IN : IN std_logic; + CTS_DATA_OUT : OUT std_logic_vector(31 downto 0); + CTS_DATAREADY_OUT : OUT std_logic; + CTS_READOUT_FINISHED_OUT : OUT std_logic; + CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0); + CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0); + FEE_READ_OUT : OUT std_logic; + PC_WR_EN_OUT : OUT std_logic; + PC_DATA_OUT : OUT std_logic_vector(7 downto 0); + PC_SOS_OUT : OUT std_logic; + PC_EOD_OUT : OUT std_logic; + PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0); + PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0); + PC_PADDING_OUT : OUT std_logic; + BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0); + BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0); + DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0); + DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0); + DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0); + DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0); + DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0); + DBG_SF_RD_EN_OUT : OUT std_logic; + DBG_SF_WR_EN_OUT : OUT std_logic; + DBG_SF_EMPTY_OUT : OUT std_logic; + DBG_SF_FULL_OUT : OUT std_logic; + DBG_SF_AFULL_OUT : OUT std_logic; + DEBUG_OUT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK : std_logic; + SIGNAL RESET : std_logic; + SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0); + SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0); + SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0); + SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0); + SIGNAL CTS_START_READOUT_IN : std_logic; + SIGNAL CTS_READ_IN : std_logic; + SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL CTS_DATAREADY_OUT : std_logic; + SIGNAL CTS_READOUT_FINISHED_OUT : std_logic; + SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0); + SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); + SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0); + SIGNAL FEE_DATAREADY_IN : std_logic; + SIGNAL FEE_READ_OUT : std_logic; + SIGNAL FEE_BUSY_IN : std_logic; + SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0); + SIGNAL PC_WR_EN_OUT : std_logic; + SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0); + SIGNAL PC_READY_IN : std_logic; + SIGNAL PC_SOS_OUT : std_logic; + SIGNAL PC_EOD_OUT : std_logic; + SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0); + SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0); + SIGNAL PC_PADDING_OUT : std_logic; + SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0); + SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0); + SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0); + SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0); + SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0); + SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0); + SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0); + SIGNAL DBG_SF_RD_EN_OUT : std_logic; + SIGNAL DBG_SF_WR_EN_OUT : std_logic; + SIGNAL DBG_SF_EMPTY_OUT : std_logic; + SIGNAL DBG_SF_FULL_OUT : std_logic; + SIGNAL DBG_SF_AFULL_OUT : std_logic; + SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: feeder PORT MAP( + CLK => CLK, + RESET => RESET, + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_READ_IN => CTS_READ_IN, + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_BUSY_IN => FEE_BUSY_IN, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + PC_WR_EN_OUT => PC_WR_EN_OUT, + PC_DATA_OUT => PC_DATA_OUT, + PC_READY_IN => PC_READY_IN, + PC_SOS_OUT => PC_SOS_OUT, + PC_EOD_OUT => PC_EOD_OUT, + PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT, + PC_TRIG_NR_OUT => PC_TRIG_NR_OUT, + PC_PADDING_OUT => PC_PADDING_OUT, + BSM_SAVE_OUT => BSM_SAVE_OUT, + BSM_LOAD_OUT => BSM_LOAD_OUT, + DBG_REM_CTR_OUT => DBG_REM_CTR_OUT, + DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT, + DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT, + DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT, + DBG_SF_DATA_OUT => DBG_SF_DATA_OUT, + DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT, + DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT, + DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT, + DBG_SF_FULL_OUT => DBG_SF_FULL_OUT, + DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +CLOCK_GEN: process +begin + clk <= '1'; wait for 5.0 ns; + clk <= '0'; wait for 5.0 ns; +end process CLOCK_GEN; + +-- Testbench +TESTBENCH_PROC: process +variable test_data_len : integer range 0 to 65535 := 49; +variable test_loop_len : integer range 0 to 65535 := 0; +variable test_hdr_len : unsigned(15 downto 0) := x"0000"; +variable test_evt_len : unsigned(15 downto 0) := x"0000"; +variable test_data : unsigned(15 downto 0) := x"ffff"; + +variable trigger_counter : unsigned(15 downto 0) := x"4710"; +variable trigger_loop : integer range 0 to 65535 := 15; +begin + -- Setup signals + reset <= '0'; + cts_number_in <= x"0000"; + cts_code_in <= x"00"; + cts_information_in <= x"00"; + cts_readout_type_in <= x"0"; + cts_start_readout_in <= '0'; + cts_read_in <= '0'; + fee_data_in <= x"0000"; + fee_dataready_in <= '0'; + fee_status_bits_in <= x"0000_0000"; + fee_busy_in <= '0'; + pc_ready_in <= '0'; + + wait for 22 ns; + + -- Reset the whole stuff + wait until rising_edge(clk); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait until rising_edge(clk); + wait for 200 ns; + + +------------------------------------------------------------------------------- +-- Loop the transmissions +------------------------------------------------------------------------------- + trigger_counter := x"4710"; + trigger_loop := 9; + test_data_len := 14; + + MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop + -- IPU transmission starts + wait until rising_edge(clk); + cts_number_in <= std_logic_vector( trigger_counter ); + cts_code_in <= x"aa"; + cts_information_in <= x"de"; + cts_readout_type_in <= x"1"; + cts_start_readout_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + fee_busy_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + -- ONE DATA TRANSMISSION + -- calculate the needed variables +-- test_data_len := 4096; + test_loop_len := 2*(test_data_len - 1) + 1; + test_hdr_len := to_unsigned( test_data_len + 1, 16 ); + test_evt_len := to_unsigned( test_data_len, 16 ); + + -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21) + fee_dataready_in <= '1'; + fee_data_in <= x"10aa"; + wait until rising_edge(clk); + fee_data_in <= std_logic_vector( trigger_counter ); + wait until rising_edge(clk); + fee_data_in <= std_logic_vector( test_hdr_len ); + wait until rising_edge(clk); + fee_data_in <= x"ff21"; + wait until rising_edge(clk); + fee_data_in <= std_logic_vector( test_evt_len ); + wait until rising_edge(clk); + fee_data_in <= x"ff22"; + + test_data := x"ffff"; + MY_DATA_LOOP: for J in 0 to test_loop_len loop + test_data := test_data + 1; + wait until rising_edge(clk); + fee_data_in <= std_logic_vector(test_data); + end loop MY_DATA_LOOP; + + fee_busy_in <= '0'; -- correct? + wait until rising_edge(clk); + fee_dataready_in <= '0'; + fee_data_in <= x"0000"; + + trigger_loop := trigger_loop + 1; + trigger_counter := trigger_counter + 1; + + wait until rising_edge(clk); + wait until rising_edge(clk); + cts_read_in <= '1'; + wait until rising_edge(clk); + cts_read_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + cts_start_readout_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + end loop MY_TRIGGER_LOOP; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + + wait for 300 ns; + + -- Start packet_constructor + wait until rising_edge(clk); + wait until rising_edge(clk); + pc_ready_in <= '1'; + wait until rising_edge(clk); + + wait; + + wait until rising_edge(clk); + wait until pc_eod_out = '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + pc_ready_in <= '0'; + + -- Stay a while... stay forever!!! + wait; + +end process TESTBENCH_PROC; + + +END; diff --git a/gbe_ecp2m/tb_gbe_buf.vhd b/gbe_ecp2m/tb_gbe_buf.vhd new file mode 100755 index 0000000..a472efa --- /dev/null +++ b/gbe_ecp2m/tb_gbe_buf.vhd @@ -0,0 +1,688 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.math_real.all; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT trb_net16_gbe_buf + GENERIC( DO_SIMULATION : integer range 0 to 1 := 1 ); + PORT( + CLK : IN std_logic; + TEST_CLK : IN std_logic; + RESET : IN std_logic; + GSR_N : IN std_logic; + STAGE_CTRL_REGS_IN : IN std_logic_vector(31 downto 0); + ------------------------ + IP_CFG_START_IN : IN std_logic; + IP_CFG_BANK_SEL_IN : IN std_logic_vector(3 downto 0); + IP_CFG_MEM_DATA_IN : IN std_logic_vector(31 downto 0); + MR_RESET_IN : IN std_logic; + MR_MODE_IN : IN std_logic; + MR_RESTART_IN : IN std_logic; + IP_CFG_MEM_CLK_OUT : OUT std_logic; + IP_CFG_DONE_OUT : OUT std_logic; + IP_CFG_MEM_ADDR_OUT : OUT std_logic_vector(7 downto 0); + -- gk 29.03.10 + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + ------------------------ + CTS_NUMBER_IN : IN std_logic_vector(15 downto 0); + CTS_CODE_IN : IN std_logic_vector(7 downto 0); + CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0); + CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0); + CTS_START_READOUT_IN : IN std_logic; + CTS_READ_IN : IN std_logic; + FEE_DATA_IN : IN std_logic_vector(15 downto 0); + FEE_DATAREADY_IN : IN std_logic; + FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0); + FEE_BUSY_IN : IN std_logic; + SFP_RXD_P_IN : IN std_logic; + SFP_RXD_N_IN : IN std_logic; + SFP_REFCLK_P_IN : IN std_logic; + SFP_REFCLK_N_IN : IN std_logic; + SFP_PRSNT_N_IN : IN std_logic; + SFP_LOS_IN : IN std_logic; + STAGE_STAT_REGS_OUT : OUT std_logic_vector(31 downto 0); + CTS_DATA_OUT : OUT std_logic_vector(31 downto 0); + CTS_DATAREADY_OUT : OUT std_logic; + CTS_READOUT_FINISHED_OUT : OUT std_logic; + CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0); + CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0); + FEE_READ_OUT : OUT std_logic; + SFP_TXD_P_OUT : OUT std_logic; + SFP_TXD_N_OUT : OUT std_logic; + SFP_TXDIS_OUT : OUT std_logic; + IG_CTS_CTR_TST : OUT std_logic_vector(2 downto 0); + IG_REM_CTR_TST : OUT std_logic_vector(3 downto 0); + IG_BSM_LOAD_TST : OUT std_logic_vector(3 downto 0); + IG_BSM_SAVE_TST : OUT std_logic_vector(3 downto 0); + IG_DATA_TST : OUT std_logic_vector(15 downto 0); + IG_WCNT_TST : OUT std_logic_vector(15 downto 0); + IG_RCNT_TST : OUT std_logic_vector(16 downto 0); + IG_RD_EN_TST : OUT std_logic; + IG_WR_EN_TST : OUT std_logic; + IG_EMPTY_TST : OUT std_logic; + IG_AEMPTY_TST : OUT std_logic; + IG_FULL_TST : OUT std_logic; + IG_AFULL_TST : OUT std_logic; + PC_WR_EN_TST : OUT std_logic; + PC_DATA_TST : OUT std_logic_vector(7 downto 0); + PC_READY_TST : OUT std_logic; + PC_START_OF_SUB_TST : OUT std_logic; + PC_END_OF_DATA_TST : OUT std_logic; + PC_ALL_CTR_TST : OUT std_logic_vector(4 downto 0); + PC_SUB_CTR_TST : OUT std_logic_vector(4 downto 0); + PC_SUB_SIZE_TST : OUT std_logic_vector(31 downto 0); + PC_TRIG_NR_TST : OUT std_logic_vector(31 downto 0); + PC_PADDING_TST : OUT std_logic; + PC_DECODING_TST : OUT std_logic_vector(31 downto 0); + PC_EVENT_ID_TST : OUT std_logic_vector(31 downto 0); + PC_QUEUE_DEC_TST : OUT std_logic_vector(31 downto 0); + PC_BSM_CONSTR_TST : OUT std_logic_vector(3 downto 0); + PC_BSM_LOAD_TST : OUT std_logic_vector(3 downto 0); + PC_BSM_SAVE_TST : OUT std_logic_vector(3 downto 0); + PC_SHF_EMPTY_TST : OUT std_logic; + PC_SHF_FULL_TST : OUT std_logic; + PC_SHF_WR_EN_TST : OUT std_logic; + PC_SHF_RD_EN_TST : OUT std_logic; + PC_SHF_Q_TST : OUT std_logic_vector(7 downto 0); + PC_DF_EMPTY_TST : OUT std_logic; + PC_DF_FULL_TST : OUT std_logic; + PC_DF_WR_EN_TST : OUT std_logic; + PC_DF_RD_EN_TST : OUT std_logic; + PC_DF_Q_TST : OUT std_logic_vector(7 downto 0); + PC_BYTES_LOADED_TST : OUT std_logic_vector(15 downto 0); + PC_SIZE_LEFT_TST : OUT std_logic_vector(31 downto 0); + PC_SUB_SIZE_TO_SAVE_TST : OUT std_logic_vector(31 downto 0); + PC_SUB_SIZE_LOADED_TST : OUT std_logic_vector(31 downto 0); + PC_SUB_BYTES_LOADED_TST : OUT std_logic_vector(31 downto 0); + PC_QUEUE_SIZE_TST : OUT std_logic_vector(31 downto 0); + PC_ACT_QUEUE_SIZE_TST : OUT std_logic_vector(31 downto 0); + FC_WR_EN_TST : OUT std_logic; + FC_DATA_TST : OUT std_logic_vector(7 downto 0); + FC_H_READY_TST : OUT std_logic; + FC_READY_TST : OUT std_logic; + FC_IP_SIZE_TST : OUT std_logic_vector(15 downto 0); + FC_UDP_SIZE_TST : OUT std_logic_vector(15 downto 0); + FC_IDENT_TST : OUT std_logic_vector(15 downto 0); + FC_FLAGS_OFFSET_TST : OUT std_logic_vector(15 downto 0); + FC_SOD_TST : OUT std_logic; + FC_EOD_TST : OUT std_logic; + FC_BSM_CONSTR_TST : OUT std_logic_vector(7 downto 0); + FC_BSM_TRANS_TST : OUT std_logic_vector(3 downto 0); + FT_DATA_TST : OUT std_logic_vector(8 downto 0); + FT_TX_EMPTY_TST : OUT std_logic; + FT_START_OF_PACKET_TST : OUT std_logic; + FT_BSM_INIT_TST : OUT std_logic_vector(3 downto 0); + FT_BSM_MAC_TST : OUT std_logic_vector(3 downto 0); + FT_BSM_TRANS_TST : OUT std_logic_vector(3 downto 0); + MAC_HADDR_TST : OUT std_logic_vector(7 downto 0); + MAC_HDATA_TST : OUT std_logic_vector(7 downto 0); + MAC_HCS_TST : OUT std_logic; + MAC_HWRITE_TST : OUT std_logic; + MAC_HREAD_TST : OUT std_logic; + MAC_HREADY_TST : OUT std_logic; + MAC_HDATA_EN_TST : OUT std_logic; + MAC_FIFOAVAIL_TST : OUT std_logic; + MAC_FIFOEOF_TST : OUT std_logic; + MAC_FIFOEMPTY_TST : OUT std_logic; + MAC_TX_READ_TST : OUT std_logic; + MAC_TX_DONE_TST : OUT std_logic; + PCS_AN_LP_ABILITY_TST : OUT std_logic_vector(15 downto 0); + PCS_AN_COMPLETE_TST : OUT std_logic; + PCS_AN_PAGE_RX_TST : OUT std_logic; + ANALYZER_DEBUG_OUT : OUT std_logic_vector(63 downto 0) + ); + END COMPONENT; + + SIGNAL CLK : std_logic; + SIGNAL TEST_CLK : std_logic; + SIGNAL RESET : std_logic; + SIGNAL GSR_N : std_logic; + SIGNAL STAGE_STAT_REGS_OUT : std_logic_vector(31 downto 0); + SIGNAL STAGE_CTRL_REGS_IN : std_logic_vector(31 downto 0); + SIGNAL IP_CFG_START_IN : std_logic; + SIGNAL IP_CFG_BANK_SEL_IN : std_logic_vector(3 downto 0); + SIGNAL IP_CFG_MEM_DATA_IN : std_logic_vector(31 downto 0); + SIGNAL MR_RESET_IN : std_logic; + SIGNAL MR_MODE_IN : std_logic; + SIGNAL MR_RESTART_IN : std_logic; + SIGNAL IP_CFG_MEM_CLK_OUT : std_logic; + SIGNAL IP_CFG_DONE_OUT : std_logic; + SIGNAL IP_CFG_MEM_ADDR_OUT : std_logic_vector(7 downto 0); + SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0); + SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0); + SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0); + SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0); + SIGNAL CTS_START_READOUT_IN : std_logic; + SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL CTS_DATAREADY_OUT : std_logic; + SIGNAL CTS_READOUT_FINISHED_OUT : std_logic; + SIGNAL CTS_READ_IN : std_logic; + SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0); + SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); + SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0); + SIGNAL FEE_DATAREADY_IN : std_logic; + SIGNAL FEE_READ_OUT : std_logic; + SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0); + SIGNAL FEE_BUSY_IN : std_logic; + SIGNAL SFP_RXD_P_IN : std_logic; + SIGNAL SFP_RXD_N_IN : std_logic; + SIGNAL SFP_TXD_P_OUT : std_logic; + SIGNAL SFP_TXD_N_OUT : std_logic; + SIGNAL SFP_REFCLK_P_IN : std_logic; + SIGNAL SFP_REFCLK_N_IN : std_logic; + SIGNAL SFP_PRSNT_N_IN : std_logic; + SIGNAL SFP_LOS_IN : std_logic; + SIGNAL SFP_TXDIS_OUT : std_logic; + SIGNAL IG_CTS_CTR_TST : std_logic_vector(2 downto 0); + SIGNAL IG_REM_CTR_TST : std_logic_vector(3 downto 0); + SIGNAL IG_BSM_LOAD_TST : std_logic_vector(3 downto 0); + SIGNAL IG_BSM_SAVE_TST : std_logic_vector(3 downto 0); + SIGNAL IG_DATA_TST : std_logic_vector(15 downto 0); + SIGNAL IG_WCNT_TST : std_logic_vector(15 downto 0); + SIGNAL IG_RCNT_TST : std_logic_vector(16 downto 0); + SIGNAL IG_RD_EN_TST : std_logic; + SIGNAL IG_WR_EN_TST : std_logic; + SIGNAL IG_EMPTY_TST : std_logic; + SIGNAL IG_AEMPTY_TST : std_logic; + SIGNAL IG_FULL_TST : std_logic; + SIGNAL IG_AFULL_TST : std_logic; + SIGNAL PC_WR_EN_TST : std_logic; + SIGNAL PC_DATA_TST : std_logic_vector(7 downto 0); + SIGNAL PC_READY_TST : std_logic; + SIGNAL PC_START_OF_SUB_TST : std_logic; + SIGNAL PC_END_OF_DATA_TST : std_logic; + SIGNAL PC_SUB_SIZE_TST : std_logic_vector(31 downto 0); + SIGNAL PC_TRIG_NR_TST : std_logic_vector(31 downto 0); + SIGNAL PC_PADDING_TST : std_logic; + SIGNAL PC_DECODING_TST : std_logic_vector(31 downto 0); + SIGNAL PC_EVENT_ID_TST : std_logic_vector(31 downto 0); + SIGNAL PC_QUEUE_DEC_TST : std_logic_vector(31 downto 0); + SIGNAL PC_BSM_CONSTR_TST : std_logic_vector(3 downto 0); + SIGNAL PC_BSM_LOAD_TST : std_logic_vector(3 downto 0); + SIGNAL PC_BSM_SAVE_TST : std_logic_vector(3 downto 0); + SIGNAL PC_SHF_EMPTY_TST : std_logic; + SIGNAL PC_SHF_FULL_TST : std_logic; + SIGNAL PC_SHF_WR_EN_TST : std_logic; + SIGNAL PC_SHF_RD_EN_TST : std_logic; + SIGNAL PC_SHF_Q_TST : std_logic_vector(7 downto 0); + SIGNAL PC_DF_EMPTY_TST : std_logic; + SIGNAL PC_DF_FULL_TST : std_logic; + SIGNAL PC_DF_WR_EN_TST : std_logic; + SIGNAL PC_DF_RD_EN_TST : std_logic; + SIGNAL PC_DF_Q_TST : std_logic_vector(7 downto 0); + SIGNAL PC_ALL_CTR_TST : std_logic_vector(4 downto 0); + SIGNAL PC_SUB_CTR_TST : std_logic_vector(4 downto 0); + SIGNAL PC_BYTES_LOADED_TST : std_logic_vector(15 downto 0); + SIGNAL PC_SIZE_LEFT_TST : std_logic_vector(31 downto 0); + SIGNAL PC_SUB_SIZE_TO_SAVE_TST : std_logic_vector(31 downto 0); + SIGNAL PC_SUB_SIZE_LOADED_TST : std_logic_vector(31 downto 0); + SIGNAL PC_SUB_BYTES_LOADED_TST : std_logic_vector(31 downto 0); + SIGNAL PC_QUEUE_SIZE_TST : std_logic_vector(31 downto 0); + SIGNAL PC_ACT_QUEUE_SIZE_TST : std_logic_vector(31 downto 0); + SIGNAL FC_WR_EN_TST : std_logic; + SIGNAL FC_DATA_TST : std_logic_vector(7 downto 0); + SIGNAL FC_H_READY_TST : std_logic; + SIGNAL FC_READY_TST : std_logic; + SIGNAL FC_IP_SIZE_TST : std_logic_vector(15 downto 0); + SIGNAL FC_UDP_SIZE_TST : std_logic_vector(15 downto 0); + SIGNAL FC_IDENT_TST : std_logic_vector(15 downto 0); + SIGNAL FC_FLAGS_OFFSET_TST : std_logic_vector(15 downto 0); + SIGNAL FC_SOD_TST : std_logic; + SIGNAL FC_EOD_TST : std_logic; + SIGNAL FC_BSM_CONSTR_TST : std_logic_vector(7 downto 0); + SIGNAL FC_BSM_TRANS_TST : std_logic_vector(3 downto 0); + SIGNAL FT_DATA_TST : std_logic_vector(8 downto 0); + SIGNAL FT_TX_EMPTY_TST : std_logic; + SIGNAL FT_START_OF_PACKET_TST : std_logic; + SIGNAL FT_BSM_INIT_TST : std_logic_vector(3 downto 0); + SIGNAL FT_BSM_MAC_TST : std_logic_vector(3 downto 0); + SIGNAL FT_BSM_TRANS_TST : std_logic_vector(3 downto 0); + SIGNAL MAC_HADDR_TST : std_logic_vector(7 downto 0); + SIGNAL MAC_HDATA_TST : std_logic_vector(7 downto 0); + SIGNAL MAC_HCS_TST : std_logic; + SIGNAL MAC_HWRITE_TST : std_logic; + SIGNAL MAC_HREAD_TST : std_logic; + SIGNAL MAC_HREADY_TST : std_logic; + SIGNAL MAC_HDATA_EN_TST : std_logic; + SIGNAL MAC_FIFOAVAIL_TST : std_logic; + SIGNAL MAC_FIFOEOF_TST : std_logic; + SIGNAL MAC_FIFOEMPTY_TST : std_logic; + SIGNAL MAC_TX_READ_TST : std_logic; + SIGNAL MAC_TX_DONE_TST : std_logic; + SIGNAL PCS_AN_LP_ABILITY_TST : std_logic_vector(15 downto 0); + SIGNAL PCS_AN_COMPLETE_TST : std_logic; + SIGNAL PCS_AN_PAGE_RX_TST : std_logic; + SIGNAL ANALYZER_DEBUG_OUT : std_logic_vector(63 downto 0); + --gk 29.03.10 + signal SLV_ADDR_IN : std_logic_vector(7 downto 0); + signal SLV_READ_IN : std_logic; + signal SLV_WRITE_IN : std_logic; + signal SLV_BUSY_OUT : std_logic; + signal SLV_ACK_OUT : std_logic; + signal SLV_DATA_IN : std_logic_vector(31 downto 0); + signal SLV_DATA_OUT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: trb_net16_gbe_buf + GENERIC MAP( DO_SIMULATION => 1 ) + PORT MAP( + CLK => CLK, + TEST_CLK => TEST_CLK, + RESET => RESET, + GSR_N => GSR_N, + STAGE_STAT_REGS_OUT => STAGE_STAT_REGS_OUT, + STAGE_CTRL_REGS_IN => STAGE_CTRL_REGS_IN, + IP_CFG_START_IN => IP_CFG_START_IN, + IP_CFG_BANK_SEL_IN => IP_CFG_BANK_SEL_IN, + IP_CFG_MEM_DATA_IN => IP_CFG_MEM_DATA_IN, + MR_RESET_IN => MR_RESET_IN, + MR_MODE_IN => MR_MODE_IN, + MR_RESTART_IN => MR_RESTART_IN, + IP_CFG_MEM_CLK_OUT => IP_CFG_MEM_CLK_OUT, + IP_CFG_DONE_OUT => IP_CFG_DONE_OUT, + IP_CFG_MEM_ADDR_OUT => IP_CFG_MEM_ADDR_OUT, + -- gk 29.03.10 + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => SLV_BUSY_OUT, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_READ_IN => CTS_READ_IN, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + FEE_BUSY_IN => FEE_BUSY_IN, + SFP_RXD_P_IN => SFP_RXD_P_IN, + SFP_RXD_N_IN => SFP_RXD_N_IN, + SFP_TXD_P_OUT => SFP_TXD_P_OUT, + SFP_TXD_N_OUT => SFP_TXD_N_OUT, + SFP_REFCLK_P_IN => SFP_REFCLK_P_IN, + SFP_REFCLK_N_IN => SFP_REFCLK_N_IN, + SFP_PRSNT_N_IN => SFP_PRSNT_N_IN, + SFP_LOS_IN => SFP_LOS_IN, + SFP_TXDIS_OUT => SFP_TXDIS_OUT, + IG_CTS_CTR_TST => IG_CTS_CTR_TST, + IG_REM_CTR_TST => IG_REM_CTR_TST, + IG_BSM_LOAD_TST => IG_BSM_LOAD_TST, + IG_BSM_SAVE_TST => IG_BSM_SAVE_TST, + IG_DATA_TST => IG_DATA_TST, + IG_WCNT_TST => IG_WCNT_TST, + IG_RCNT_TST => IG_RCNT_TST, + IG_RD_EN_TST => IG_RD_EN_TST, + IG_WR_EN_TST => IG_WR_EN_TST, + IG_EMPTY_TST => IG_EMPTY_TST, + IG_AEMPTY_TST => IG_AEMPTY_TST, + IG_FULL_TST => IG_FULL_TST, + IG_AFULL_TST => IG_AFULL_TST, + PC_WR_EN_TST => PC_WR_EN_TST, + PC_DATA_TST => PC_DATA_TST, + PC_READY_TST => PC_READY_TST, + PC_START_OF_SUB_TST => PC_START_OF_SUB_TST, + PC_END_OF_DATA_TST => PC_END_OF_DATA_TST, + PC_SUB_SIZE_TST => PC_SUB_SIZE_TST, + PC_TRIG_NR_TST => PC_TRIG_NR_TST, + PC_PADDING_TST => PC_PADDING_TST, + PC_DECODING_TST => PC_DECODING_TST, + PC_EVENT_ID_TST => PC_EVENT_ID_TST, + PC_QUEUE_DEC_TST => PC_QUEUE_DEC_TST, + PC_BSM_CONSTR_TST => PC_BSM_CONSTR_TST, + PC_BSM_LOAD_TST => PC_BSM_LOAD_TST, + PC_BSM_SAVE_TST => PC_BSM_SAVE_TST, + PC_SHF_EMPTY_TST => PC_SHF_EMPTY_TST, + PC_SHF_FULL_TST => PC_SHF_FULL_TST, + PC_SHF_WR_EN_TST => PC_SHF_WR_EN_TST, + PC_SHF_RD_EN_TST => PC_SHF_RD_EN_TST, + PC_SHF_Q_TST => PC_SHF_Q_TST, + PC_DF_EMPTY_TST => PC_DF_EMPTY_TST, + PC_DF_FULL_TST => PC_DF_FULL_TST, + PC_DF_WR_EN_TST => PC_DF_WR_EN_TST, + PC_DF_RD_EN_TST => PC_DF_RD_EN_TST, + PC_DF_Q_TST => PC_DF_Q_TST, + PC_ALL_CTR_TST => PC_ALL_CTR_TST, + PC_SUB_CTR_TST => PC_SUB_CTR_TST, + PC_BYTES_LOADED_TST => PC_BYTES_LOADED_TST, + PC_SIZE_LEFT_TST => PC_SIZE_LEFT_TST, + PC_SUB_SIZE_TO_SAVE_TST => PC_SUB_SIZE_TO_SAVE_TST, + PC_SUB_SIZE_LOADED_TST => PC_SUB_SIZE_LOADED_TST, + PC_SUB_BYTES_LOADED_TST => PC_SUB_BYTES_LOADED_TST, + PC_QUEUE_SIZE_TST => PC_QUEUE_SIZE_TST, + PC_ACT_QUEUE_SIZE_TST => PC_ACT_QUEUE_SIZE_TST, + FC_WR_EN_TST => FC_WR_EN_TST, + FC_DATA_TST => FC_DATA_TST, + FC_H_READY_TST => FC_H_READY_TST, + FC_READY_TST => FC_READY_TST, + FC_IP_SIZE_TST => FC_IP_SIZE_TST, + FC_UDP_SIZE_TST => FC_UDP_SIZE_TST, + FC_IDENT_TST => FC_IDENT_TST, + FC_FLAGS_OFFSET_TST => FC_FLAGS_OFFSET_TST, + FC_SOD_TST => FC_SOD_TST, + FC_EOD_TST => FC_EOD_TST, + FC_BSM_CONSTR_TST => FC_BSM_CONSTR_TST, + FC_BSM_TRANS_TST => FC_BSM_TRANS_TST, + FT_DATA_TST => FT_DATA_TST, + FT_TX_EMPTY_TST => FT_TX_EMPTY_TST, + FT_START_OF_PACKET_TST => FT_START_OF_PACKET_TST, + FT_BSM_INIT_TST => FT_BSM_INIT_TST, + FT_BSM_MAC_TST => FT_BSM_MAC_TST, + FT_BSM_TRANS_TST => FT_BSM_TRANS_TST, + MAC_HADDR_TST => MAC_HADDR_TST, + MAC_HDATA_TST => MAC_HDATA_TST, + MAC_HCS_TST => MAC_HCS_TST, + MAC_HWRITE_TST => MAC_HWRITE_TST, + MAC_HREAD_TST => MAC_HREAD_TST, + MAC_HREADY_TST => MAC_HREADY_TST, + MAC_HDATA_EN_TST => MAC_HDATA_EN_TST, + MAC_FIFOAVAIL_TST => MAC_FIFOAVAIL_TST, + MAC_FIFOEOF_TST => MAC_FIFOEOF_TST, + MAC_FIFOEMPTY_TST => MAC_FIFOEMPTY_TST, + MAC_TX_READ_TST => MAC_TX_READ_TST, + MAC_TX_DONE_TST => MAC_TX_DONE_TST, + PCS_AN_LP_ABILITY_TST => PCS_AN_LP_ABILITY_TST, + PCS_AN_COMPLETE_TST => PCS_AN_COMPLETE_TST, + PCS_AN_PAGE_RX_TST => PCS_AN_PAGE_RX_TST, + ANALYZER_DEBUG_OUT => ANALYZER_DEBUG_OUT + ); + + + +-- 100 MHz system clock +CLOCK_GEN_PROC: process +begin + clk <= '1'; wait for 5.0 ns; + clk <= '0'; wait for 5.0 ns; +end process CLOCK_GEN_PROC; + +-- 125 MHz MAC clock +CLOCK2_GEN_PROC: process +begin + test_clk <= '1'; wait for 4.0 ns; + test_clk <= '0'; wait for 3.0 ns; +end process CLOCK2_GEN_PROC; + +-- Testbench +TESTBENCH_PROC: process +-- test data from TRBnet +variable test_data_len : integer range 0 to 65535 := 1; +variable test_loop_len : integer range 0 to 65535 := 0; +variable test_hdr_len : unsigned(15 downto 0) := x"0000"; +variable test_evt_len : unsigned(15 downto 0) := x"0000"; +variable test_data : unsigned(15 downto 0) := x"ffff"; + +variable trigger_counter : unsigned(15 downto 0) := x"4710"; +variable trigger_loop : integer range 0 to 65535 := 15; + +-- 1400 bytes MTU => 350 as limit for fragmentation +variable max_event_size : real := 512.0; + +variable seed1 : positive; -- seed for random generator +variable seed2 : positive; -- seed for random generator +variable rand : real; -- random value (0.0 ... 1.0) +variable int_rand : integer; -- random value, scaled to your needs +variable cts_random_number : std_logic_vector(7 downto 0); + +variable stim : std_logic_vector(15 downto 0); + +-- RND test +--UNIFORM(seed1, seed2, rand); +--int_rand := INTEGER(TRUNC(rand*65536.0)); +--stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH)); + +begin + -- Setup signals + reset <= '0'; + gsr_n <= '1'; + + stage_ctrl_regs_in <= x"0000_0000"; + + --ip_cfg_start_in <= '0'; + --ip_cfg_bank_sel_in <= x"0"; + --ip_cfg_mem_data_in <= x"0000_0000"; + mr_reset_in <= '0'; + mr_mode_in <= '0'; + mr_restart_in <= '0'; + SLV_ADDR_IN <= x"00"; + SLV_READ_IN <= '0'; + SLV_WRITE_IN <= '0'; + SLV_DATA_IN <= x"0000_0000"; + + sfp_los_in <= '0'; -- signal from SFP is present + sfp_prsnt_n_in <= '0'; -- SFP itself is present + sfp_refclk_n_in <= '0'; + sfp_refclk_p_in <= '1'; + + cts_number_in <= x"0000"; + cts_code_in <= x"00"; + cts_information_in <= x"00"; + cts_readout_type_in <= x"0"; + cts_start_readout_in <= '0'; + cts_read_in <= '0'; + + fee_data_in <= x"0000"; + fee_dataready_in <= '0'; + fee_status_bits_in <= x"1234_5678"; + fee_busy_in <= '0'; + + wait for 22 ns; + + -- Reset the whole stuff + wait until rising_edge(clk); + reset <= '1'; + gsr_n <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + gsr_n <= '1'; + wait until rising_edge(clk); + --wait for 100 ns; + + -- Tests may start here + wait until ft_bsm_init_tst = x"7"; + + --ip_cfg_start_in <= '1'; + + wait for 500 ns; + +------------------------------------------------------------------------------- +-- Loop the transmissions +------------------------------------------------------------------------------- + trigger_counter := x"4710"; + trigger_loop := 10; + + MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop + -- generate a real random byte for CTS + UNIFORM(seed1, seed2, rand); + int_rand := INTEGER(TRUNC(rand*256.0)); + cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH)); + + -- IPU transmission starts + wait until rising_edge(clk); + cts_number_in <= std_logic_vector( trigger_counter ); + cts_code_in <= cts_random_number; + cts_information_in <= x"d1"; -- cts_information_in <= x"de"; -- gk 29.03.10 + cts_readout_type_in <= x"1"; + cts_start_readout_in <= '1'; + wait until rising_edge(clk); + wait for 400 ns; + + wait until rising_edge(clk); + fee_busy_in <= '1'; + wait for 300 ns; + wait until rising_edge(clk); + + -- ONE DATA TRANSMISSION + -- dice a length + UNIFORM(seed1, seed2, rand); + test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1; + + --test_data_len := 9685; + test_data_len := 200; + + -- calculate the needed variables + test_loop_len := 2*(test_data_len - 1) + 1; + test_hdr_len := to_unsigned( test_data_len + 1, 16 ); + test_evt_len := to_unsigned( test_data_len, 16 ); + + -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21) + fee_dataready_in <= '1'; + fee_data_in <= x"10" & cts_random_number; + wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word + fee_dataready_in <= '0'; + wait until rising_edge(clk); -- BLA + wait until rising_edge(clk); -- BLA + wait until rising_edge(clk); + wait until rising_edge(clk); + fee_dataready_in <= '1'; + fee_data_in <= std_logic_vector( trigger_counter ); + wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word + fee_dataready_in <= '0'; + wait until rising_edge(clk); -- BLA + wait until rising_edge(clk); -- BLA + wait until rising_edge(clk); -- BLA + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + fee_dataready_in <= '1'; + fee_data_in <= std_logic_vector( test_hdr_len ); + wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word + fee_data_in <= x"ff21"; + wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word + fee_dataready_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + fee_dataready_in <= '1'; + fee_data_in <= std_logic_vector( test_evt_len ); + wait until rising_edge(clk) and (fee_read_out = '1'); + fee_data_in <= x"ff22"; + wait until rising_edge(clk) and (fee_read_out = '1'); + fee_dataready_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + test_data := x"ffff"; + MY_DATA_LOOP: for J in 0 to test_loop_len loop + test_data := test_data + 1; + wait until rising_edge(clk); + fee_data_in <= std_logic_vector(test_data); + if( (test_data MOD 5) = 0 ) then + fee_dataready_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + fee_dataready_in <= '1'; + else + fee_dataready_in <= '1'; + end if; + end loop MY_DATA_LOOP; + -- there must be padding words to get multiple of four LWs + + wait until rising_edge(clk); + fee_dataready_in <= '0'; + fee_data_in <= x"0000"; + + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + fee_busy_in <= '0'; + + + trigger_loop := trigger_loop + 1; + trigger_counter := trigger_counter + 1; + + wait until rising_edge(clk); + wait until rising_edge(clk); + cts_read_in <= '1'; + wait until rising_edge(clk); + cts_read_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + cts_start_readout_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + --wait for 8 us; + + end loop MY_TRIGGER_LOOP; + +-- wait for 8 us; +------------------------------------------------------------------------------- +-- end of loop +------------------------------------------------------------------------------- + -- Stay a while... stay forever!!! + wait; + +end process TESTBENCH_PROC; + +END; + diff --git a/gbe_ecp2m/tb_ip_configurator.vhd b/gbe_ecp2m/tb_ip_configurator.vhd new file mode 100755 index 0000000..6188d42 --- /dev/null +++ b/gbe_ecp2m/tb_ip_configurator.vhd @@ -0,0 +1,145 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT ip_configurator + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + START_CONFIG_IN : IN std_logic; + BANK_SELECT_IN : IN std_logic_vector(3 downto 0); + MEM_DATA_IN : IN std_logic_vector(31 downto 0); + CONFIG_DONE_OUT : OUT std_logic; + MEM_ADDR_OUT : OUT std_logic_vector(7 downto 0); + MEM_CLK_OUT : OUT std_logic; + DEST_MAC_OUT : OUT std_logic_vector(47 downto 0); + DEST_IP_OUT : OUT std_logic_vector(31 downto 0); + DEST_UDP_OUT : OUT std_logic_vector(15 downto 0); + SRC_MAC_OUT : OUT std_logic_vector(47 downto 0); + SRC_IP_OUT : OUT std_logic_vector(31 downto 0); + SRC_UDP_OUT : OUT std_logic_vector(15 downto 0); + MTU_OUT : OUT std_logic_vector(15 downto 0); + DEBUG_OUT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK : std_logic; + SIGNAL RESET : std_logic; + SIGNAL START_CONFIG_IN : std_logic; + SIGNAL BANK_SELECT_IN : std_logic_vector(3 downto 0); + SIGNAL CONFIG_DONE_OUT : std_logic; + SIGNAL MEM_ADDR_OUT : std_logic_vector(7 downto 0); + SIGNAL MEM_DATA_IN : std_logic_vector(31 downto 0); + SIGNAL MEM_CLK_OUT : std_logic; + SIGNAL DEST_MAC_OUT : std_logic_vector(47 downto 0); + SIGNAL DEST_IP_OUT : std_logic_vector(31 downto 0); + SIGNAL DEST_UDP_OUT : std_logic_vector(15 downto 0); + SIGNAL SRC_MAC_OUT : std_logic_vector(47 downto 0); + SIGNAL SRC_IP_OUT : std_logic_vector(31 downto 0); + SIGNAL SRC_UDP_OUT : std_logic_vector(15 downto 0); + SIGNAL MTU_OUT : std_logic_vector(15 downto 0); + SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: ip_configurator PORT MAP( + CLK => CLK, + RESET => RESET, + START_CONFIG_IN => START_CONFIG_IN, + BANK_SELECT_IN => BANK_SELECT_IN, + CONFIG_DONE_OUT => CONFIG_DONE_OUT, + MEM_ADDR_OUT => MEM_ADDR_OUT, + MEM_DATA_IN => MEM_DATA_IN, + MEM_CLK_OUT => MEM_CLK_OUT, + DEST_MAC_OUT => DEST_MAC_OUT, + DEST_IP_OUT => DEST_IP_OUT, + DEST_UDP_OUT => DEST_UDP_OUT, + SRC_MAC_OUT => SRC_MAC_OUT, + SRC_IP_OUT => SRC_IP_OUT, + SRC_UDP_OUT => SRC_UDP_OUT, + MTU_OUT => MTU_OUT, + DEBUG_OUT => DEBUG_OUT + ); + + +CLK_GEN_PROC: process +begin + clk <= '0'; wait for 5.0 ns; + clk <= '1'; wait for 5.0 ns; +end process CLK_GEN_PROC; + +THE_TESTBENCH: process +begin + -- Setup signals + reset <= '0'; + start_config_in <= '0'; + bank_select_in <= x"0"; + mem_data_in <= x"0000_0000"; + + -- Reset the whole stuff + wait until rising_edge(clk); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait for 100 ns; + wait until rising_edge(clk); + + -- Tests may start now + wait until rising_edge(clk); + start_config_in <= '1'; + wait until mem_addr_out(3 downto 0) = x"1"; + wait until rising_edge(clk); + mem_data_in <= x"4902d745"; -- dest MAC low + wait until rising_edge(clk); + mem_data_in <= x"00006cf0"; -- dest MAC high + wait until rising_edge(clk); + mem_data_in <= x"c0a80002"; -- dest IP + wait until rising_edge(clk); + mem_data_in <= x"0000c350"; -- dest port + wait until rising_edge(clk); + mem_data_in <= x"eeeeeeee"; -- src MAC low + wait until rising_edge(clk); + mem_data_in <= x"0000eeee"; -- src MAC high + wait until rising_edge(clk); + mem_data_in <= x"c0a80005"; -- src IP + wait until rising_edge(clk); + mem_data_in <= x"0000c350"; -- src port + wait until rising_edge(clk); + mem_data_in <= x"00000578"; -- MTU + wait until rising_edge(clk); + mem_data_in <= x"99999999"; + wait until rising_edge(clk); + mem_data_in <= x"aaaaaaaa"; + wait until rising_edge(clk); + mem_data_in <= x"bbbbbbbb"; + wait until rising_edge(clk); + mem_data_in <= x"cccccccc"; + wait until rising_edge(clk); + mem_data_in <= x"dddddddd"; + wait until rising_edge(clk); + mem_data_in <= x"eeeeeeee"; + wait until rising_edge(clk); + mem_data_in <= x"ffffffff"; + wait until rising_edge(clk); + mem_data_in <= x"00000000"; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + start_config_in <= '0'; + + -- Stay a while... stay forever!!! Muahahaha!!!!! + wait; +end process THE_TESTBENCH; + + +END; diff --git a/gbe_ecp2m/tb_ipu2gbe.vhd b/gbe_ecp2m/tb_ipu2gbe.vhd new file mode 100755 index 0000000..065e674 --- /dev/null +++ b/gbe_ecp2m/tb_ipu2gbe.vhd @@ -0,0 +1,428 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.math_real.all; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT trb_net16_ipu2gbe + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + START_CONFIG_OUT : OUT std_logic; + BANK_SELECT_OUT : OUT std_logic_vector(3 downto 0); + CONFIG_DONE_IN : IN std_logic; + DATA_GBE_ENABLE_IN : IN std_logic; + DATA_IPU_ENABLE_IN : IN std_logic; + MULTI_EVT_ENABLE_IN : IN std_logic; + CTS_NUMBER_IN : IN std_logic_vector(15 downto 0); + CTS_CODE_IN : IN std_logic_vector(7 downto 0); + CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0); + CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0); + CTS_START_READOUT_IN : IN std_logic; + CTS_READ_IN : IN std_logic; + FEE_DATA_IN : IN std_logic_vector(15 downto 0); + FEE_DATAREADY_IN : IN std_logic; + FEE_BUSY_IN : IN std_logic; + FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0); + PC_READY_IN : IN std_logic; + CTS_DATA_OUT : OUT std_logic_vector(31 downto 0); + CTS_DATAREADY_OUT : OUT std_logic; + CTS_READOUT_FINISHED_OUT : OUT std_logic; + CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0); + CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0); + FEE_READ_OUT : OUT std_logic; + PC_WR_EN_OUT : OUT std_logic; + PC_DATA_OUT : OUT std_logic_vector(7 downto 0); + PC_SOS_OUT : OUT std_logic; + PC_EOD_OUT : OUT std_logic; + PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0); + PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0); + PC_PADDING_OUT : OUT std_logic; + BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0); + BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0); + DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0); + DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0); + DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0); + DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0); + DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0); + DBG_SF_RD_EN_OUT : OUT std_logic; + DBG_SF_WR_EN_OUT : OUT std_logic; + DBG_SF_EMPTY_OUT : OUT std_logic; + DBG_SF_AEMPTY_OUT : OUT std_logic; + DBG_SF_FULL_OUT : OUT std_logic; + DBG_SF_AFULL_OUT : OUT std_logic; + DEBUG_OUT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK : std_logic; + SIGNAL RESET : std_logic; + SIGNAL START_CONFIG_OUT : std_logic; + SIGNAL BANK_SELECT_OUT : std_logic_vector(3 downto 0); + SIGNAL CONFIG_DONE_IN : std_logic; + SIGNAL DATA_GBE_ENABLE_IN : std_logic; + SIGNAL DATA_IPU_ENABLE_IN : std_logic; + SIGNAL MULTI_EVT_ENABLE_IN : std_logic; + SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0); + SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0); + SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0); + SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0); + SIGNAL CTS_START_READOUT_IN : std_logic; + SIGNAL CTS_READ_IN : std_logic; + SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL CTS_DATAREADY_OUT : std_logic; + SIGNAL CTS_READOUT_FINISHED_OUT : std_logic; + SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0); + SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); + SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0); + SIGNAL FEE_DATAREADY_IN : std_logic; + SIGNAL FEE_READ_OUT : std_logic; + SIGNAL FEE_BUSY_IN : std_logic; + SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0); + SIGNAL PC_WR_EN_OUT : std_logic; + SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0); + SIGNAL PC_READY_IN : std_logic; + SIGNAL PC_SOS_OUT : std_logic; + SIGNAL PC_EOD_OUT : std_logic; + SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0); + SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0); + SIGNAL PC_PADDING_OUT : std_logic; + SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0); + SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0); + SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0); + SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0); + SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0); + SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0); + SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0); + SIGNAL DBG_SF_RD_EN_OUT : std_logic; + SIGNAL DBG_SF_WR_EN_OUT : std_logic; + SIGNAL DBG_SF_EMPTY_OUT : std_logic; + SIGNAL DBG_SF_AEMPTY_OUT : std_logic; + SIGNAL DBG_SF_FULL_OUT : std_logic; + SIGNAL DBG_SF_AFULL_OUT : std_logic; + SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: trb_net16_ipu2gbe PORT MAP( + CLK => CLK, + RESET => RESET, + START_CONFIG_OUT => START_CONFIG_OUT, + BANK_SELECT_OUT => BANK_SELECT_OUT, + CONFIG_DONE_IN => CONFIG_DONE_IN, + DATA_GBE_ENABLE_IN => DATA_GBE_ENABLE_IN, + DATA_IPU_ENABLE_IN => DATA_IPU_ENABLE_IN, + MULTI_EVT_ENABLE_IN => MULTI_EVT_ENABLE_IN, + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_READ_IN => CTS_READ_IN, + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_BUSY_IN => FEE_BUSY_IN, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + PC_WR_EN_OUT => PC_WR_EN_OUT, + PC_DATA_OUT => PC_DATA_OUT, + PC_READY_IN => PC_READY_IN, + PC_SOS_OUT => PC_SOS_OUT, + PC_EOD_OUT => PC_EOD_OUT, + PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT, + PC_TRIG_NR_OUT => PC_TRIG_NR_OUT, + PC_PADDING_OUT => PC_PADDING_OUT, + BSM_SAVE_OUT => BSM_SAVE_OUT, + BSM_LOAD_OUT => BSM_LOAD_OUT, + DBG_REM_CTR_OUT => DBG_REM_CTR_OUT, + DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT, + DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT, + DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT, + DBG_SF_DATA_OUT => DBG_SF_DATA_OUT, + DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT, + DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT, + DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT, + DBG_SF_AEMPTY_OUT => DBG_SF_AEMPTY_OUT, + DBG_SF_FULL_OUT => DBG_SF_FULL_OUT, + DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +CLOCK_GEN: process +begin + clk <= '1'; wait for 5.0 ns; + clk <= '0'; wait for 5.0 ns; +end process CLOCK_GEN; + +PC_READY_PROC: process +begin + pc_ready_in <= '0'; + wait for 500 ns; + pc_ready_in <= '1'; + wait for 500 ns; + pc_ready_in <= '0'; + wait for 99 us; +end process PC_READY_PROC; + +-- Testbench +TESTBENCH_PROC: process +-- test data from TRBnet +variable test_data_len : integer range 0 to 65535 := 1; +variable test_loop_len : integer range 0 to 65535 := 0; +variable test_hdr_len : unsigned(15 downto 0) := x"0000"; +variable test_evt_len : unsigned(15 downto 0) := x"0000"; +variable test_data : unsigned(15 downto 0) := x"ffff"; + +variable trigger_counter : unsigned(15 downto 0) := x"4710"; +variable trigger_loop : integer range 0 to 65535 := 15; + +-- 1400 bytes MTU => 350 as limit for fragmentation +--variable max_event_size : real := 512.0; +variable max_event_size : real := 17.0; + +variable seed1 : positive; -- seed for random generator +variable seed2 : positive; -- seed for random generator +variable rand : real; -- random value (0.0 ... 1.0) +variable int_rand : integer; -- random value, scaled to your needs +variable cts_random_number : std_logic_vector(7 downto 0); + +variable stim : std_logic_vector(15 downto 0); + +begin + -- Setup signals + reset <= '0'; + cts_number_in <= x"0000"; + cts_code_in <= x"00"; + cts_information_in <= x"00"; + cts_readout_type_in <= x"0"; + cts_start_readout_in <= '0'; + cts_read_in <= '0'; + fee_data_in <= x"0000"; + fee_dataready_in <= '0'; + fee_status_bits_in <= x"0000_0000"; + fee_busy_in <= '0'; +-- pc_ready_in <= '0'; + + config_done_in <= '1'; + data_gbe_enable_in <= '1'; + data_ipu_enable_in <= '0'; + multi_evt_enable_in <= '0'; + + wait for 22 ns; + + -- Reset the whole stuff + wait until rising_edge(clk); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait until rising_edge(clk); + wait for 200 ns; + +--------------------------- + +------------------------------------------------------------------------------- +-- Loop the transmissions +------------------------------------------------------------------------------- + trigger_counter := x"4710"; + trigger_loop := 2; + + MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop + -- generate a real random byte for CTS + UNIFORM(seed1, seed2, rand); + int_rand := INTEGER(TRUNC(rand*256.0)); + cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH)); + + -- IPU transmission starts + wait until rising_edge(clk); + cts_number_in <= std_logic_vector( trigger_counter ); + cts_code_in <= cts_random_number; + cts_information_in <= x"de"; + cts_readout_type_in <= x"1"; + cts_start_readout_in <= '1'; + wait until rising_edge(clk); + wait for 400 ns; + + wait until rising_edge(clk); + fee_busy_in <= '1'; + wait for 300 ns; + wait until rising_edge(clk); + + -- ONE DATA TRANSMISSION + -- dice a length + UNIFORM(seed1, seed2, rand); + test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1; + +-- test_data_len := 9685; + + -- calculate the needed variables + test_loop_len := 2*(test_data_len - 1) + 1; + test_hdr_len := to_unsigned( test_data_len + 1, 16 ); + test_evt_len := to_unsigned( test_data_len, 16 ); + + -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21) + fee_dataready_in <= '1'; + fee_data_in <= x"10" & cts_random_number; + wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word + fee_dataready_in <= '0'; + wait until rising_edge(clk); -- BLA + wait until rising_edge(clk); -- BLA + wait until rising_edge(clk); + wait until rising_edge(clk); + fee_dataready_in <= '1'; + fee_data_in <= std_logic_vector( trigger_counter ); + wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word + fee_dataready_in <= '0'; + wait until rising_edge(clk); -- BLA + wait until rising_edge(clk); -- BLA + wait until rising_edge(clk); -- BLA + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + fee_dataready_in <= '1'; + fee_data_in <= std_logic_vector( test_hdr_len ); + wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word + fee_data_in <= x"ff21"; + wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word + fee_dataready_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + fee_dataready_in <= '1'; + fee_data_in <= std_logic_vector( test_evt_len ); + wait until rising_edge(clk) and (fee_read_out = '1'); + fee_data_in <= x"ff22"; + wait until rising_edge(clk) and (fee_read_out = '1'); + fee_dataready_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + test_data := x"ffff"; + MY_DATA_LOOP: for J in 0 to test_loop_len loop + test_data := test_data + 1; + wait until rising_edge(clk) and (fee_read_out = '1'); -- + fee_data_in <= std_logic_vector(test_data); + if( (test_data MOD 5) = 0 ) then + fee_dataready_in <= '0'; +-- wait until rising_edge(clk); +-- wait until rising_edge(clk); +-- wait until rising_edge(clk); +-- wait until rising_edge(clk); +-- wait until rising_edge(clk); +-- wait until rising_edge(clk); +-- wait until rising_edge(clk); +-- wait until rising_edge(clk); +-- wait until rising_edge(clk); +-- wait until rising_edge(clk); +-- wait until rising_edge(clk); +-- wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + fee_dataready_in <= '1'; + else + fee_dataready_in <= '1'; + end if; + end loop MY_DATA_LOOP; + -- there must be padding words to get multiple of four LWs + + wait until rising_edge(clk); + fee_dataready_in <= '0'; + fee_data_in <= x"0000"; + + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + fee_busy_in <= '0'; + + + trigger_loop := trigger_loop + 1; + trigger_counter := trigger_counter + 1; + + wait until rising_edge(clk); + wait until rising_edge(clk); + cts_read_in <= '1'; + wait until rising_edge(clk); + cts_read_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + cts_start_readout_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + --wait for 8 us; + + end loop MY_TRIGGER_LOOP; + + + +--------------------------- +--------------------------- + wait for 300 ns; + + wait; + + -- Start packet_constructor + wait until rising_edge(clk); + wait until rising_edge(clk); +-- pc_ready_in <= '1'; + wait until rising_edge(clk); + + wait until rising_edge(clk); + wait until pc_eod_out = '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); +-- pc_ready_in <= '0'; + + -- Stay a while... stay forever!!! + wait; + +end process TESTBENCH_PROC; + + +END; diff --git a/gbe_ecp2m/tb_lsm.vhd b/gbe_ecp2m/tb_lsm.vhd new file mode 100755 index 0000000..6e86029 --- /dev/null +++ b/gbe_ecp2m/tb_lsm.vhd @@ -0,0 +1,113 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT trb_net16_lsm_sfp_gbe + PORT( + SYSCLK : IN std_logic; + RESET : IN std_logic; + CLEAR : IN std_logic; + SFP_MISSING_IN : IN std_logic; + SFP_LOS_IN : IN std_logic; + SD_LINK_OK_IN : IN std_logic; + SD_LOS_IN : IN std_logic; + SD_TXCLK_BAD_IN : IN std_logic; + SD_RXCLK_BAD_IN : IN std_logic; + FULL_RESET_OUT : OUT std_logic; + LANE_RESET_OUT : OUT std_logic; + USER_RESET_OUT : OUT std_logic; + TIMING_CTR_OUT : OUT std_logic_vector(18 downto 0); + BSM_OUT : OUT std_logic_vector(3 downto 0); + DEBUG_OUT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL SYSCLK : std_logic; + SIGNAL RESET : std_logic; + SIGNAL CLEAR : std_logic; + SIGNAL SFP_MISSING_IN : std_logic; + SIGNAL SFP_LOS_IN : std_logic; + SIGNAL SD_LINK_OK_IN : std_logic; + SIGNAL SD_LOS_IN : std_logic; + SIGNAL SD_TXCLK_BAD_IN : std_logic; + SIGNAL SD_RXCLK_BAD_IN : std_logic; + SIGNAL FULL_RESET_OUT : std_logic; + SIGNAL LANE_RESET_OUT : std_logic; + SIGNAL USER_RESET_OUT : std_logic; + SIGNAL TIMING_CTR_OUT : std_logic_vector(18 downto 0); + SIGNAL BSM_OUT : std_logic_vector(3 downto 0); + SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: trb_net16_lsm_sfp_gbe PORT MAP( + SYSCLK => SYSCLK, + RESET => RESET, + CLEAR => CLEAR, + SFP_MISSING_IN => SFP_MISSING_IN, + SFP_LOS_IN => SFP_LOS_IN, + SD_LINK_OK_IN => SD_LINK_OK_IN, + SD_LOS_IN => SD_LOS_IN, + SD_TXCLK_BAD_IN => SD_TXCLK_BAD_IN, + SD_RXCLK_BAD_IN => SD_RXCLK_BAD_IN, + FULL_RESET_OUT => FULL_RESET_OUT, + LANE_RESET_OUT => LANE_RESET_OUT, + USER_RESET_OUT => USER_RESET_OUT, + TIMING_CTR_OUT => TIMING_CTR_OUT, + BSM_OUT => BSM_OUT, + DEBUG_OUT => DEBUG_OUT + ); + + +CLOCK_GEN: process +begin + sysclk <= '1'; wait for 4.0 ns; + sysclk <= '0'; wait for 4.0 ns; +end process CLOCK_GEN; + +THE_TESTBENCH: process +begin + -- Setup signals + reset <= '0'; + clear <= '0'; + sfp_missing_in <= '0'; + sfp_los_in <= '0'; + sd_link_ok_in <= '0'; + sd_los_in <= '0'; + sd_txclk_bad_in <= '1'; + sd_rxclk_bad_in <= '1'; + wait for 100 ns; + + -- Reset + clear <= '1'; + wait for 100 ns; + clear <= '0'; + wait for 10 ns; + + -- Tests may start now + wait until falling_edge(full_reset_out); + wait for 123 ns; + sd_txclk_bad_in <= '0'; + wait for 433 ns; + sd_rxclk_bad_in <= '0'; + + wait for 1.1 us; + sd_rxclk_bad_in <= '1'; + wait for 33 ns; + sd_rxclk_bad_in <= '0'; + + + wait until rising_edge(sysclk); + + -- Stay a while.... stay forever!!! Muahahaha!!!! + wait; + +end process THE_TESTBENCH; + +END; \ No newline at end of file diff --git a/gbe_ecp2m/tb_pc.vhd b/gbe_ecp2m/tb_pc.vhd new file mode 100755 index 0000000..ac85375 --- /dev/null +++ b/gbe_ecp2m/tb_pc.vhd @@ -0,0 +1,310 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT trb_net16_gbe_packet_constr + PORT( + RESET : IN std_logic; + CLK : IN std_logic; + PC_WR_EN_IN : IN std_logic; + PC_DATA_IN : IN std_logic_vector(7 downto 0); + PC_START_OF_SUB_IN : IN std_logic; + PC_END_OF_DATA_IN : IN std_logic; + PC_SUB_SIZE_IN : IN std_logic_vector(31 downto 0); + PC_DECODING_IN : IN std_logic_vector(31 downto 0); + PC_EVENT_ID_IN : IN std_logic_vector(31 downto 0); + PC_TRIG_NR_IN : IN std_logic_vector(31 downto 0); + PC_QUEUE_DEC_IN : IN std_logic_vector(31 downto 0); + PC_MAX_FRAME_SIZE_IN : IN std_logic_vector(15 downto 0); + FC_H_READY_IN : IN std_logic; + FC_READY_IN : IN std_logic; + PC_READY_OUT : OUT std_logic; + FC_WR_EN_OUT : OUT std_logic; + FC_DATA_OUT : OUT std_logic_vector(7 downto 0); + FC_IP_SIZE_OUT : OUT std_logic_vector(15 downto 0); + FC_UDP_SIZE_OUT : OUT std_logic_vector(15 downto 0); + FC_IDENT_OUT : OUT std_logic_vector(15 downto 0); + FC_FLAGS_OFFSET_OUT : OUT std_logic_vector(15 downto 0); + FC_SOD_OUT : OUT std_logic; + FC_EOD_OUT : OUT std_logic; + BSM_CONSTR_OUT : OUT std_logic_vector(3 downto 0); + BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0); + BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0); + DBG_SHF_EMPTY : OUT std_logic; + DBG_SHF_FULL : OUT std_logic; + DBG_SHF_WR_EN : OUT std_logic; + DBG_SHF_RD_EN : OUT std_logic; + DBG_DF_EMPTY : OUT std_logic; + DBG_DF_FULL : OUT std_logic; + DBG_DF_WR_EN : OUT std_logic; + DBG_DF_RD_EN : OUT std_logic; + DBG_ALL_CTR : OUT std_logic_vector(4 downto 0); + DBG_SUB_CTR : OUT std_logic_vector(4 downto 0); + DBG_MY_CTR : OUT std_logic_vector(1 downto 0); + DBG_BYTES_LOADED : OUT std_logic_vector(15 downto 0); + DBG_SIZE_LEFT : OUT std_logic_vector(31 downto 0); + DBG_SUB_SIZE_TO_SAVE : OUT std_logic_vector(31 downto 0); + DBG_SUB_SIZE_LOADED : OUT std_logic_vector(31 downto 0); + DBG_SUB_BYTES_LOADED : OUT std_logic_vector(31 downto 0); + DBG_QUEUE_SIZE : OUT std_logic_vector(31 downto 0); + DBG_ACT_QUEUE_SIZE : OUT std_logic_vector(31 downto 0); + DEBUG_OUT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL RESET : std_logic; + SIGNAL CLK : std_logic; + SIGNAL PC_WR_EN_IN : std_logic; + SIGNAL PC_DATA_IN : std_logic_vector(7 downto 0); + SIGNAL PC_READY_OUT : std_logic; + SIGNAL PC_START_OF_SUB_IN : std_logic; + SIGNAL PC_END_OF_DATA_IN : std_logic; + SIGNAL PC_SUB_SIZE_IN : std_logic_vector(31 downto 0); + SIGNAL PC_DECODING_IN : std_logic_vector(31 downto 0); + SIGNAL PC_EVENT_ID_IN : std_logic_vector(31 downto 0); + SIGNAL PC_TRIG_NR_IN : std_logic_vector(31 downto 0); + SIGNAL PC_QUEUE_DEC_IN : std_logic_vector(31 downto 0); + SIGNAL PC_MAX_FRAME_SIZE_IN : std_logic_vector(15 downto 0); + SIGNAL FC_WR_EN_OUT : std_logic; + SIGNAL FC_DATA_OUT : std_logic_vector(7 downto 0); + SIGNAL FC_H_READY_IN : std_logic; + SIGNAL FC_READY_IN : std_logic; + SIGNAL FC_IP_SIZE_OUT : std_logic_vector(15 downto 0); + SIGNAL FC_UDP_SIZE_OUT : std_logic_vector(15 downto 0); + SIGNAL FC_IDENT_OUT : std_logic_vector(15 downto 0); + SIGNAL FC_FLAGS_OFFSET_OUT : std_logic_vector(15 downto 0); + SIGNAL FC_SOD_OUT : std_logic; + SIGNAL FC_EOD_OUT : std_logic; + SIGNAL BSM_CONSTR_OUT : std_logic_vector(3 downto 0); + SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0); + SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0); + SIGNAL DBG_SHF_EMPTY : std_logic; + SIGNAL DBG_SHF_FULL : std_logic; + SIGNAL DBG_SHF_WR_EN : std_logic; + SIGNAL DBG_SHF_RD_EN : std_logic; + SIGNAL DBG_DF_EMPTY : std_logic; + SIGNAL DBG_DF_FULL : std_logic; + SIGNAL DBG_DF_WR_EN : std_logic; + SIGNAL DBG_DF_RD_EN : std_logic; + SIGNAL DBG_ALL_CTR : std_logic_vector(4 downto 0); + SIGNAL DBG_SUB_CTR : std_logic_vector(4 downto 0); + SIGNAL DBG_MY_CTR : std_logic_vector(1 downto 0); + SIGNAL DBG_BYTES_LOADED : std_logic_vector(15 downto 0); + SIGNAL DBG_SIZE_LEFT : std_logic_vector(31 downto 0); + SIGNAL DBG_SUB_SIZE_TO_SAVE : std_logic_vector(31 downto 0); + SIGNAL DBG_SUB_SIZE_LOADED : std_logic_vector(31 downto 0); + SIGNAL DBG_SUB_BYTES_LOADED : std_logic_vector(31 downto 0); + SIGNAL DBG_QUEUE_SIZE : std_logic_vector(31 downto 0); + SIGNAL DBG_ACT_QUEUE_SIZE : std_logic_vector(31 downto 0); + SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: trb_net16_gbe_packet_constr PORT MAP( + RESET => RESET, + CLK => CLK, + PC_WR_EN_IN => PC_WR_EN_IN, + PC_DATA_IN => PC_DATA_IN, + PC_READY_OUT => PC_READY_OUT, + PC_START_OF_SUB_IN => PC_START_OF_SUB_IN, + PC_END_OF_DATA_IN => PC_END_OF_DATA_IN, + PC_SUB_SIZE_IN => PC_SUB_SIZE_IN, + PC_DECODING_IN => PC_DECODING_IN, + PC_EVENT_ID_IN => PC_EVENT_ID_IN, + PC_TRIG_NR_IN => PC_TRIG_NR_IN, + PC_QUEUE_DEC_IN => PC_QUEUE_DEC_IN, + PC_MAX_FRAME_SIZE_IN => PC_MAX_FRAME_SIZE_IN, + FC_WR_EN_OUT => FC_WR_EN_OUT, + FC_DATA_OUT => FC_DATA_OUT, + FC_H_READY_IN => FC_H_READY_IN, + FC_READY_IN => FC_READY_IN, + FC_IP_SIZE_OUT => FC_IP_SIZE_OUT, + FC_UDP_SIZE_OUT => FC_UDP_SIZE_OUT, + FC_IDENT_OUT => FC_IDENT_OUT, + FC_FLAGS_OFFSET_OUT => FC_FLAGS_OFFSET_OUT, + FC_SOD_OUT => FC_SOD_OUT, + FC_EOD_OUT => FC_EOD_OUT, + BSM_CONSTR_OUT => BSM_CONSTR_OUT, + BSM_LOAD_OUT => BSM_LOAD_OUT, + BSM_SAVE_OUT => BSM_SAVE_OUT, + DBG_SHF_EMPTY => DBG_SHF_EMPTY, + DBG_SHF_FULL => DBG_SHF_FULL, + DBG_SHF_WR_EN => DBG_SHF_WR_EN, + DBG_SHF_RD_EN => DBG_SHF_RD_EN, + DBG_DF_EMPTY => DBG_DF_EMPTY, + DBG_DF_FULL => DBG_DF_FULL, + DBG_DF_WR_EN => DBG_DF_WR_EN, + DBG_DF_RD_EN => DBG_DF_RD_EN, + DBG_ALL_CTR => DBG_ALL_CTR, + DBG_SUB_CTR => DBG_SUB_CTR, + DBG_MY_CTR => DBG_MY_CTR, + DBG_BYTES_LOADED => DBG_BYTES_LOADED, + DBG_SIZE_LEFT => DBG_SIZE_LEFT, + DBG_SUB_SIZE_TO_SAVE => DBG_SUB_SIZE_TO_SAVE, + DBG_SUB_SIZE_LOADED => DBG_SUB_SIZE_LOADED, + DBG_SUB_BYTES_LOADED => DBG_SUB_BYTES_LOADED, + DBG_QUEUE_SIZE => DBG_QUEUE_SIZE, + DBG_ACT_QUEUE_SIZE => DBG_ACT_QUEUE_SIZE, + DEBUG_OUT => DEBUG_OUT + ); + +CLK_GEN: process +begin + clk <= '1'; wait for 5.0 ns; + clk <= '0'; wait for 5.0 ns; +end process CLK_GEN; + +THE_TESTBENCH: process +variable test_data_len : integer range 0 to 65535 := 1; +variable test_loop_len : integer range 0 to 65535 := 0; +variable test_evt_len : unsigned(15 downto 0) := x"0000"; +variable test_evt_len_vec : std_logic_vector(15 downto 0); +variable test_sub_len : unsigned(15 downto 0) := x"0000"; +variable test_sub_len_vec : std_logic_vector(15 downto 0); +variable test_data : unsigned(15 downto 0) := x"ffff"; +variable test_data_vec : std_logic_vector(15 downto 0); + +variable trigger_counter : unsigned(15 downto 0) := x"4710"; +variable trigger_loop : integer range 0 to 65535 := 15; +begin + -- Set up signals + reset <= '0'; + pc_wr_en_in <= '0'; + pc_data_in <= x"00"; + pc_start_of_sub_in <= '0'; + pc_end_of_data_in <= '0'; + pc_sub_size_in <= x"0000_0000"; + pc_trig_nr_in <= x"0000_0000"; + pc_decoding_in <= x"0002_0001"; -- static + pc_event_id_in <= x"0000_00ca"; -- static + pc_queue_dec_in <= x"0003_0062"; -- static + pc_max_frame_size_in <= x"0578"; -- static + fc_h_ready_in <= '0'; + fc_ready_in <= '0'; + wait until rising_edge(clk); + + -- Reset the whole stuff + wait until rising_edge(clk); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait until rising_edge(clk); + wait for 200 ns; + wait until rising_edge(clk); + + -- Tests may start now + +------------------------------------------------------------------------------- +-- Loop the transmissions +------------------------------------------------------------------------------- + trigger_counter := x"4710"; + trigger_loop := 0; + + test_data_len := 14; + + MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop + + -- calculate the needed variables + test_loop_len := 2*(test_data_len - 1) + 1; + test_evt_len := to_unsigned( test_data_len, 16 ); + test_evt_len_vec := std_logic_vector(test_evt_len); + test_sub_len := test_evt_len + 1; + test_sub_len_vec := std_logic_vector(test_sub_len); + + -- start of subevent marker + wait until rising_edge(clk); + wait until rising_edge(clk); + pc_trig_nr_in <= x"0000" & std_logic_vector(trigger_counter); + pc_sub_size_in <= b"0000_0000_0000_00" & test_sub_len_vec & b"00"; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + pc_start_of_sub_in <= '1'; + wait until rising_edge(clk); + pc_start_of_sub_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + pc_data_in <= test_evt_len_vec(15 downto 8); + pc_wr_en_in <= '1'; + wait until rising_edge(clk); + pc_data_in <= test_evt_len_vec(7 downto 0); + pc_wr_en_in <= '1'; + wait until rising_edge(clk); + pc_wr_en_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + pc_data_in <= x"ff"; -- source address high byte + pc_wr_en_in <= '1'; + wait until rising_edge(clk); + pc_data_in <= x"22"; -- source address low byte + pc_wr_en_in <= '1'; + wait until rising_edge(clk); + pc_wr_en_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + + test_data := x"ffff"; + MY_DATA_LOOP: for J in 0 to test_loop_len loop + test_data := test_data + 1; + test_data_vec := std_logic_vector(test_data); + wait until rising_edge(clk); + pc_data_in <= test_data_vec(15 downto 8); + pc_wr_en_in <= '1'; + wait until rising_edge(clk); + pc_data_in <= test_data_vec(7 downto 0); + pc_wr_en_in <= '1'; + wait until rising_edge(clk); + pc_wr_en_in <= '0'; +-- wait until rising_edge(clk); +-- wait until rising_edge(clk); + end loop MY_DATA_LOOP; + + -- end of subevent marker +-- wait until rising_edge(clk); + pc_end_of_data_in <= '1'; + wait until rising_edge(clk); + pc_end_of_data_in <= '0'; + pc_sub_size_in <= x"0000_0000"; + pc_trig_nr_in <= x"0000_0000"; + wait until rising_edge(clk); + wait until rising_edge(clk); + + trigger_loop := trigger_loop + 1; + trigger_counter := trigger_counter + 1; + + wait for 500 ns; + wait until rising_edge(clk); + end loop MY_TRIGGER_LOOP; + +-- wait for 8 us; +------------------------------------------------------------------------------- +-- end of loop +------------------------------------------------------------------------------- + + wait until rising_edge(clk); + fc_ready_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + fc_h_ready_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + -- Stay a while... stay forever!!!Muahahah!!! + wait; + +end process THE_TESTBENCH; + +END; \ No newline at end of file diff --git a/gbe_ecp2m/tb_slv_mac_memory.vhd b/gbe_ecp2m/tb_slv_mac_memory.vhd new file mode 100755 index 0000000..00293c3 --- /dev/null +++ b/gbe_ecp2m/tb_slv_mac_memory.vhd @@ -0,0 +1,114 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT slv_mac_memory + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + BUSY_IN : IN std_logic; + SLV_ADDR_IN : IN std_logic_vector(7 downto 0); + SLV_READ_IN : IN std_logic; + SLV_WRITE_IN : IN std_logic; + SLV_DATA_IN : IN std_logic_vector(31 downto 0); + MEM_CLK_IN : IN std_logic; + MEM_ADDR_IN : IN std_logic_vector(7 downto 0); + SLV_BUSY_OUT : OUT std_logic; + SLV_ACK_OUT : OUT std_logic; + SLV_DATA_OUT : OUT std_logic_vector(31 downto 0); + MEM_DATA_OUT : OUT std_logic_vector(31 downto 0); + STAT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK : std_logic; + SIGNAL RESET : std_logic; + SIGNAL BUSY_IN : std_logic; + SIGNAL SLV_ADDR_IN : std_logic_vector(7 downto 0); + SIGNAL SLV_READ_IN : std_logic; + SIGNAL SLV_WRITE_IN : std_logic; + SIGNAL SLV_BUSY_OUT : std_logic; + SIGNAL SLV_ACK_OUT : std_logic; + SIGNAL SLV_DATA_IN : std_logic_vector(31 downto 0); + SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL MEM_CLK_IN : std_logic; + SIGNAL MEM_ADDR_IN : std_logic_vector(7 downto 0); + SIGNAL MEM_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL STAT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: slv_mac_memory PORT MAP( + CLK => CLK, + RESET => RESET, + BUSY_IN => BUSY_IN, + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => SLV_BUSY_OUT, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + MEM_CLK_IN => MEM_CLK_IN, + MEM_ADDR_IN => MEM_ADDR_IN, + MEM_DATA_OUT => MEM_DATA_OUT, + STAT => STAT + ); + +CLK_GEN_PROC: process +begin + clk <= '0'; mem_clk_in <= '0'; wait for 5.0 ns; + clk <= '1'; mem_clk_in <= '1'; wait for 5.0 ns; +end process CLK_GEN_PROC; + +THE_TESTBENCH: process +begin + -- Setup signals + reset <= '0'; + busy_in <= '0'; + slv_addr_in <= x"00"; + slv_read_in <= '0'; + slv_write_in <= '0'; + slv_data_in <= x"dead_beef"; + mem_addr_in <= x"f0"; + wait until rising_edge(clk); + + -- Reset the whole stuff + wait until rising_edge(clk); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait until rising_edge(clk); + + -- Tests may start now + wait until rising_edge(clk); + mem_addr_in <= x"00"; + wait until rising_edge(clk); + mem_addr_in <= x"01"; + wait until rising_edge(clk); + mem_addr_in <= x"02"; + wait until rising_edge(clk); + mem_addr_in <= x"03"; + wait until rising_edge(clk); + mem_addr_in <= x"04"; + wait until rising_edge(clk); + mem_addr_in <= x"05"; + wait until rising_edge(clk); + mem_addr_in <= x"06"; + wait until rising_edge(clk); + mem_addr_in <= x"07"; + wait until rising_edge(clk); + mem_addr_in <= x"08"; + + -- Stay a while... stay forever!!! Muahahaha!!!!! + wait; +end process THE_TESTBENCH; + +END; diff --git a/gbe_ecp2m/trb_net16_gbe_buf.vhd b/gbe_ecp2m/trb_net16_gbe_buf.vhd new file mode 100755 index 0000000..5011959 --- /dev/null +++ b/gbe_ecp2m/trb_net16_gbe_buf.vhd @@ -0,0 +1,1268 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +use IEEE.std_logic_arith.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.version.all; + +entity trb_net16_gbe_buf is +generic( + DO_SIMULATION : integer range 0 to 1 := 1 +); +port( + CLK : in std_logic; + TEST_CLK : in std_logic; -- only for simulation! + RESET : in std_logic; + GSR_N : in std_logic; + -- Debug + STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); + STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); + -- configuration interface + IP_CFG_START_IN : in std_logic; + IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); + IP_CFG_DONE_OUT : out std_logic; + IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); + IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); + IP_CFG_MEM_CLK_OUT : out std_logic; + MR_RESET_IN : in std_logic; + MR_MODE_IN : in std_logic; + MR_RESTART_IN : in std_logic; + -- gk 29.03.10 + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + --SFP Connection + SFP_RXD_P_IN : in std_logic; + SFP_RXD_N_IN : in std_logic; + SFP_TXD_P_OUT : out std_logic; + SFP_TXD_N_OUT : out std_logic; + SFP_REFCLK_P_IN : in std_logic; + SFP_REFCLK_N_IN : in std_logic; + SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SFP_TXDIS_OUT : out std_logic; -- SFP disable + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- PacketConstructor interface + IG_CTS_CTR_TST : out std_logic_vector(2 downto 0); + IG_REM_CTR_TST : out std_logic_vector(3 downto 0); + IG_BSM_LOAD_TST : out std_logic_vector(3 downto 0); + IG_BSM_SAVE_TST : out std_logic_vector(3 downto 0); + IG_DATA_TST : out std_logic_vector(15 downto 0); + IG_WCNT_TST : out std_logic_vector(15 downto 0); + IG_RCNT_TST : out std_logic_vector(16 downto 0); + IG_RD_EN_TST : out std_logic; + IG_WR_EN_TST : out std_logic; + IG_EMPTY_TST : out std_logic; + IG_AEMPTY_TST : out std_logic; + IG_FULL_TST : out std_logic; + IG_AFULL_TST : out std_logic; + PC_WR_EN_TST : out std_logic; + PC_DATA_TST : out std_logic_vector (7 downto 0); + PC_READY_TST : out std_logic; + PC_START_OF_SUB_TST : out std_logic; + PC_END_OF_DATA_TST : out std_logic; + PC_SUB_SIZE_TST : out std_logic_vector(31 downto 0); + PC_TRIG_NR_TST : out std_logic_vector(31 downto 0); + PC_PADDING_TST : out std_logic; + PC_DECODING_TST : out std_logic_vector(31 downto 0); + PC_EVENT_ID_TST : out std_logic_vector(31 downto 0); + PC_QUEUE_DEC_TST : out std_logic_vector(31 downto 0); + PC_BSM_CONSTR_TST : out std_logic_vector(3 downto 0); + PC_BSM_LOAD_TST : out std_logic_vector(3 downto 0); + PC_BSM_SAVE_TST : out std_logic_vector(3 downto 0); + PC_SHF_EMPTY_TST : out std_logic; + PC_SHF_FULL_TST : out std_logic; + PC_SHF_WR_EN_TST : out std_logic; + PC_SHF_RD_EN_TST : out std_logic; + PC_SHF_Q_TST : out std_logic_vector(7 downto 0); + PC_DF_EMPTY_TST : out std_logic; + PC_DF_FULL_TST : out std_logic; + PC_DF_WR_EN_TST : out std_logic; + PC_DF_RD_EN_TST : out std_logic; + PC_DF_Q_TST : out std_logic_vector(7 downto 0); + PC_ALL_CTR_TST : out std_logic_vector(4 downto 0); + PC_SUB_CTR_TST : out std_logic_vector(4 downto 0); + PC_BYTES_LOADED_TST : out std_logic_vector(15 downto 0); + PC_SIZE_LEFT_TST : out std_logic_vector(31 downto 0); + PC_SUB_SIZE_TO_SAVE_TST : out std_logic_vector(31 downto 0); + PC_SUB_SIZE_LOADED_TST : out std_logic_vector(31 downto 0); + PC_SUB_BYTES_LOADED_TST : out std_logic_vector(31 downto 0); + PC_QUEUE_SIZE_TST : out std_logic_vector(31 downto 0); + PC_ACT_QUEUE_SIZE_TST : out std_logic_vector(31 downto 0); + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- FrameConstructor interface + FC_WR_EN_TST : out std_logic; + FC_DATA_TST : out std_logic_vector(7 downto 0); + FC_H_READY_TST : out std_logic; + FC_READY_TST : out std_logic; + FC_IP_SIZE_TST : out std_logic_vector(15 downto 0); + FC_UDP_SIZE_TST : out std_logic_vector(15 downto 0); + FC_IDENT_TST : out std_logic_vector(15 downto 0); + FC_FLAGS_OFFSET_TST : out std_logic_vector(15 downto 0); + FC_SOD_TST : out std_logic; + FC_EOD_TST : out std_logic; + FC_BSM_CONSTR_TST : out std_logic_vector(7 downto 0); + FC_BSM_TRANS_TST : out std_logic_vector(3 downto 0); + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- FrameTransmitter interface + FT_DATA_TST : out std_logic_vector(8 downto 0); + FT_TX_EMPTY_TST : out std_logic; + FT_START_OF_PACKET_TST : out std_logic; + FT_BSM_INIT_TST : out std_logic_vector(3 downto 0); + FT_BSM_MAC_TST : out std_logic_vector(3 downto 0); + FT_BSM_TRANS_TST : out std_logic_vector(3 downto 0); + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- MAC interface + MAC_HADDR_TST : out std_logic_vector(7 downto 0); + MAC_HDATA_TST : out std_logic_vector(7 downto 0); + MAC_HCS_TST : out std_logic; + MAC_HWRITE_TST : out std_logic; + MAC_HREAD_TST : out std_logic; + MAC_HREADY_TST : out std_logic; + MAC_HDATA_EN_TST : out std_logic; + MAC_FIFOAVAIL_TST : out std_logic; + MAC_FIFOEOF_TST : out std_logic; + MAC_FIFOEMPTY_TST : out std_logic; + MAC_TX_READ_TST : out std_logic; + MAC_TX_DONE_TST : out std_logic; + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- pcs and serdes + PCS_AN_LP_ABILITY_TST : out std_logic_vector(15 downto 0); + PCS_AN_COMPLETE_TST : out std_logic; + PCS_AN_PAGE_RX_TST : out std_logic; + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- debug ports + ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end entity trb_net16_gbe_buf; + +architecture trb_net16_gbe_buf of trb_net16_gbe_buf is + +-- Placer Directives +attribute HGROUP : string; +-- for whole architecture +attribute HGROUP of trb_net16_gbe_buf : architecture is "GBE_BUF_group"; + +-- Interface between IPU channel and packet constructor +component trb_net16_ipu2gbe is +port( + CLK : in std_logic; + RESET : in std_logic; + --Event information coming from CTS + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + --Information sent to CTS + --status data, equipped with DHDR + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data from Frontends + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; --must be high when idle, otherwise you will never get a dataready + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + -- slow control interface + START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size + BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address + CONFIG_DONE_IN : in std_logic; -- configuration finished + DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE + DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet + MULTI_EVT_ENABLE_IN : in std_logic; -- enable multi event packets + MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 + -- PacketConstructor interface + PC_WR_EN_OUT : out std_logic; + PC_DATA_OUT : out std_logic_vector (7 downto 0); + PC_READY_IN : in std_logic; + PC_SOS_OUT : out std_logic; + PC_EOD_OUT : out std_logic; + PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); + PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); + PC_PADDING_OUT : out std_logic; + -- Debug + BSM_SAVE_OUT : out std_logic_vector(3 downto 0); + BSM_LOAD_OUT : out std_logic_vector(3 downto 0); + DBG_CTS_CTR_OUT : out std_logic_vector(2 downto 0); + DBG_REM_CTR_OUT : out std_logic_vector(3 downto 0); + DBG_SF_WCNT_OUT : out std_logic_vector(15 downto 0); + DBG_SF_RCNT_OUT : out std_logic_vector(16 downto 0); + DBG_SF_DATA_OUT : out std_logic_vector(15 downto 0); + DBG_SF_RD_EN_OUT : out std_logic; + DBG_SF_WR_EN_OUT : out std_logic; + DBG_SF_EMPTY_OUT : out std_logic; + DBG_SF_AEMPTY_OUT : out std_logic; + DBG_SF_FULL_OUT : out std_logic; + DBG_SF_AFULL_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end component; + +component ip_configurator is +port( + CLK : in std_logic; + RESET : in std_logic; + -- configuration interface + START_CONFIG_IN : in std_logic; -- start configuration run + BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank + CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used + MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for + MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory + MEM_CLK_OUT : out std_logic; -- clock for BlockRAM + -- information for IP cores + DEST_MAC_OUT : out std_logic_vector(47 downto 0); -- destination MAC address + DEST_IP_OUT : out std_logic_vector(31 downto 0); -- destination IP address + DEST_UDP_OUT : out std_logic_vector(15 downto 0); -- destination port + SRC_MAC_OUT : out std_logic_vector(47 downto 0); -- source MAC address + SRC_IP_OUT : out std_logic_vector(31 downto 0); -- source IP address + SRC_UDP_OUT : out std_logic_vector(15 downto 0); -- source port + MTU_OUT : out std_logic_vector(15 downto 0); -- MTU size (max frame size) + -- Debug + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end component; + +-- PacketConstructor for UDP packet +component trb_net16_gbe_packet_constr is +port ( + -- ports for user logic + RESET : in std_logic; + CLK : in std_logic; + PC_WR_EN_IN : in std_logic; + PC_DATA_IN : in std_logic_vector(7 downto 0); + PC_READY_OUT : out std_logic; + PC_START_OF_SUB_IN : in std_logic; + PC_END_OF_DATA_IN : in std_logic; + -- queue and subevent layer headers + PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); + PC_PADDING_IN : in std_logic; -- gk 29.03.10 + PC_DECODING_IN : in std_logic_vector(31 downto 0); + PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); + PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); + PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); + PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + -- NEW PORTS + FC_WR_EN_OUT : out std_logic; + FC_DATA_OUT : out std_logic_vector(7 downto 0); + FC_H_READY_IN : in std_logic; + FC_READY_IN : in std_logic; + FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); + FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); + FC_IDENT_OUT : out std_logic_vector(15 downto 0); + FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); + FC_SOD_OUT : out std_logic; + FC_EOD_OUT : out std_logic; + -- debug ports + BSM_CONSTR_OUT : out std_logic_vector(3 downto 0); + BSM_LOAD_OUT : out std_logic_vector(3 downto 0); + BSM_SAVE_OUT : out std_logic_vector(3 downto 0); + DBG_SHF_EMPTY : out std_logic; + DBG_SHF_FULL : out std_logic; + DBG_SHF_WR_EN : out std_logic; + DBG_SHF_RD_EN : out std_logic; + DBG_SHF_Q : out std_logic_vector(7 downto 0); + DBG_DF_EMPTY : out std_logic; + DBG_DF_FULL : out std_logic; + DBG_DF_WR_EN : out std_logic; + DBG_DF_RD_EN : out std_logic; + DBG_DF_Q : out std_logic_vector(7 downto 0); + DBG_ALL_CTR : out std_logic_vector(4 downto 0); + DBG_SUB_CTR : out std_logic_vector(4 downto 0); + DBG_MY_CTR : out std_logic_vector(1 downto 0); + DBG_BYTES_LOADED : out std_logic_vector(15 downto 0); + DBG_SIZE_LEFT : out std_logic_vector(31 downto 0); + DBG_SUB_SIZE_TO_SAVE : out std_logic_vector(31 downto 0); + DBG_SUB_SIZE_LOADED : out std_logic_vector(31 downto 0); + DBG_SUB_BYTES_LOADED : out std_logic_vector(31 downto 0); + DBG_QUEUE_SIZE : out std_logic_vector(31 downto 0); + DBG_ACT_QUEUE_SIZE : out std_logic_vector(31 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end component; + +-- FrameConstructor for IP packets +component trb_net16_gbe_frame_constr is +port ( + -- ports for user logic + CLK : in std_logic; + RESET : in std_logic; + -- + WR_EN_IN : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + START_OF_DATA_IN : in std_logic; + END_OF_DATA_IN : in std_logic; + IP_F_SIZE_IN : in std_logic_vector(15 downto 0); + UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation + HEADERS_READY_OUT : out std_logic; + READY_OUT : out std_logic; + DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + FRAME_TYPE_IN : in std_logic_vector(15 downto 0); + IHL_VERSION_IN : in std_logic_vector(7 downto 0); + TOS_IN : in std_logic_vector(7 downto 0); + IDENTIFICATION_IN : in std_logic_vector(15 downto 0); + FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); + TTL_IN : in std_logic_vector(7 downto 0); + PROTOCOL_IN : in std_logic_vector(7 downto 0); + -- ports for packetTransmitter + RD_CLK : in std_logic; + FT_DATA_OUT : out std_logic_vector(8 downto 0); + FT_TX_EMPTY_OUT : out std_logic; + FT_TX_RD_EN_IN : in std_logic; + FT_START_OF_PACKET_OUT : out std_logic; + FT_TX_DONE_IN : in std_logic; + -- debug ports + BSM_CONSTR_OUT : out std_logic_vector(7 downto 0); + BSM_TRANS_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end component; + +component trb_net16_gbe_frame_trans is +port ( + CLK : in std_logic; + RESET : in std_logic; + TX_MAC_CLK : in std_logic; + TX_EMPTY_IN : in std_logic; + START_OF_PACKET_IN : in std_logic; + DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC + -- NEW PORTS + HADDR_OUT : out std_logic_vector(7 downto 0); + HDATA_OUT : out std_logic_vector(7 downto 0); + HCS_OUT : out std_logic; + HWRITE_OUT : out std_logic; + HREAD_OUT : out std_logic; + HREADY_IN : in std_logic; + HDATA_EN_IN : in std_logic; + TX_FIFOAVAIL_OUT : out std_logic; + TX_FIFOEOF_OUT : out std_logic; + TX_FIFOEMPTY_OUT : out std_logic; + TX_DONE_IN : in std_logic; + -- Debug + BSM_INIT_OUT : out std_logic_vector(3 downto 0); + BSM_MAC_OUT : out std_logic_vector(3 downto 0); + BSM_TRANS_OUT : out std_logic_vector(3 downto 0); + DBG_RD_DONE_OUT : out std_logic; + DBG_INIT_DONE_OUT : out std_logic; + DBG_ENABLED_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end component; + +component tsmac3 +port( + --------------- clock and reset port declarations ------------------ + hclk : in std_logic; + txmac_clk : in std_logic; + rxmac_clk : in std_logic; + reset_n : in std_logic; + txmac_clk_en : in std_logic; + rxmac_clk_en : in std_logic; + ------------------- Input signals to the GMII ---------------- + rxd : in std_logic_vector(7 downto 0); + rx_dv : in std_logic; + rx_er : in std_logic; + col : in std_logic; + crs : in std_logic; + -------------------- Input signals to the CPU I/F ------------------- + haddr : in std_logic_vector(7 downto 0); + hdatain : in std_logic_vector(7 downto 0); + hcs_n : in std_logic; + hwrite_n : in std_logic; + hread_n : in std_logic; + ---------------- Input signals to the Tx MAC FIFO I/F --------------- + tx_fifodata : in std_logic_vector(7 downto 0); + tx_fifoavail : in std_logic; + tx_fifoeof : in std_logic; + tx_fifoempty : in std_logic; + tx_sndpaustim : in std_logic_vector(15 downto 0); + tx_sndpausreq : in std_logic; + tx_fifoctrl : in std_logic; + ---------------- Input signals to the Rx MAC FIFO I/F --------------- + rx_fifo_full : in std_logic; + ignore_pkt : in std_logic; + -------------------- Output signals from the GMII ----------------------- + txd : out std_logic_vector(7 downto 0); + tx_en : out std_logic; + tx_er : out std_logic; + -------------------- Output signals from the CPU I/F ------------------- + hdataout : out std_logic_vector(7 downto 0); + hdataout_en_n : out std_logic; + hready_n : out std_logic; + cpu_if_gbit_en : out std_logic; + ---------------- Output signals from the Tx MAC FIFO I/F --------------- + tx_macread : out std_logic; + tx_discfrm : out std_logic; + tx_staten : out std_logic; + tx_done : out std_logic; + tx_statvec : out std_logic_vector(30 downto 0); + ---------------- Output signals from the Rx MAC FIFO I/F --------------- + rx_fifo_error : out std_logic; + rx_stat_vector : out std_logic_vector(31 downto 0); + rx_dbout : out std_logic_vector(7 downto 0); + rx_write : out std_logic; + rx_stat_en : out std_logic; + rx_eof : out std_logic; + rx_error : out std_logic +); +end component; + +component mb_mac_sim is +port ( + -------------------------------------------------------------------------- + --------------- clock, reset, clock enable ------------------------------- + HCLK : in std_logic; + TX_MAC_CLK : in std_logic; + RX_MAC_CLK : in std_logic; + RESET_N : in std_logic; + TXMAC_CLK_EN : in std_logic; + RXMAC_CLK_EN : in std_logic; + -------------------------------------------------------------------------- + --------------- SGMII receive interface ---------------------------------- + RXD : in std_logic_vector(7 downto 0); + RX_DV : in std_logic; + RX_ER : in std_logic; + COL : in std_logic; + CRS : in std_logic; + -------------------------------------------------------------------------- + --------------- SGMII transmit interface --------------------------------- + TXD : out std_logic_vector(7 downto 0); + TX_EN : out std_logic; + TX_ER : out std_logic; + -------------------------------------------------------------------------- + --------------- CPU configuration interface ------------------------------ + HADDR : in std_logic_vector(7 downto 0); + HDATAIN : in std_logic_vector(7 downto 0); + HCS_N : in std_logic; + HWRITE_N : in std_logic; + HREAD_N : in std_logic; + HDATAOUT : out std_logic_vector(7 downto 0); + HDATAOUT_EN_N : out std_logic; + HREADY_N : out std_logic; + CPU_IF_GBIT_EN : out std_logic; + -------------------------------------------------------------------------- + --------------- Transmit FIFO interface ---------------------------------- + TX_FIFODATA : in std_logic_vector(7 downto 0); + TX_FIFOAVAIL : in std_logic; + TX_FIFOEOF : in std_logic; + TX_FIFOEMPTY : in std_logic; + TX_MACREAD : out std_logic; + TX_DONE : out std_logic; + TX_SNDPAUSTIM : in std_logic_vector(15 downto 0); + TX_SNDPAUSREQ : in std_logic; + TX_FIFOCTRL : in std_logic; + TX_DISCFRM : out std_logic; + TX_STATEN : out std_logic; + TX_STATVEC : out std_logic_vector(30 downto 0); + -------------------------------------------------------------------------- + --------------- Receive FIFO interface ----------------------------------- + RX_DBOUT : out std_logic_vector(7 downto 0); + RX_FIFO_FULL : in std_logic; + IGNORE_PKT : in std_logic; + RX_FIFO_ERROR : out std_logic; + RX_STAT_VECTOR : out std_logic_vector(31 downto 0); + RX_STAT_EN : out std_logic; + RX_WRITE : out std_logic; + RX_EOF : out std_logic; + RX_ERROR : out std_logic +); +end component; + +component trb_net16_med_ecp_sfp_gbe_8b is +port( + RESET : in std_logic; + GSR_N : in std_logic; + CLK_125_OUT : out std_logic; + CLK_RX_OUT : out std_logic; + CLK_TX_OUT : out std_logic; + --SGMII connection to frame transmitter (tsmac) + FT_TX_CLK_EN_OUT : out std_logic; + FT_RX_CLK_EN_OUT : out std_logic; + FT_COL_OUT : out std_logic; + FT_CRS_OUT : out std_logic; + FT_TXD_IN : in std_logic_vector(7 downto 0); + FT_TX_EN_IN : in std_logic; + FT_TX_ER_IN : in std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic; -- SFP disable + -- Autonegotiation stuff + MR_RESET_IN : in std_logic; + MR_MODE_IN : in std_logic; + MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0); + MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0); + MR_AN_PAGE_RX_OUT : out std_logic; + MR_AN_COMPLETE_OUT : out std_logic; + MR_AN_ENABLE_IN : in std_logic; + MR_RESTART_AN_IN : in std_logic; + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) +); +end component; + +component slv_mac_memory is +port( + CLK : in std_logic; + RESET : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + MEM_CLK_IN : in std_logic; + MEM_ADDR_IN : in std_logic_vector(7 downto 0); + MEM_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component; + + +signal ig_bsm_save : std_logic_vector(3 downto 0); +signal ig_bsm_load : std_logic_vector(3 downto 0); +signal ig_cts_ctr : std_logic_vector(2 downto 0); +signal ig_rem_ctr : std_logic_vector(3 downto 0); +signal ig_debug : std_logic_vector(31 downto 0); +signal ig_data : std_logic_vector(15 downto 0); +signal ig_wcnt : std_logic_vector(15 downto 0); +signal ig_rcnt : std_logic_vector(16 downto 0); +signal ig_rd_en : std_logic; +signal ig_wr_en : std_logic; +signal ig_empty : std_logic; +signal ig_aempty : std_logic; +signal ig_full : std_logic; +signal ig_afull : std_logic; + +signal pc_wr_en : std_logic; +signal pc_data : std_logic_vector(7 downto 0); +signal pc_eod : std_logic; +signal pc_sos : std_logic; +signal pc_ready : std_logic; +signal pc_padding : std_logic; +signal pc_decoding : std_logic_vector(31 downto 0); +signal pc_event_id : std_logic_vector(31 downto 0); +signal pc_queue_dec : std_logic_vector(31 downto 0); +signal pc_max_frame_size : std_logic_vector(15 downto 0); +signal pc_bsm_constr : std_logic_vector(3 downto 0); +signal pc_bsm_load : std_logic_vector(3 downto 0); +signal pc_bsm_save : std_logic_vector(3 downto 0); +signal pc_shf_empty : std_logic; +signal pc_shf_full : std_logic; +signal pc_shf_wr_en : std_logic; +signal pc_shf_rd_en : std_logic; +signal pc_shf_q : std_logic_vector(7 downto 0); +signal pc_df_empty : std_logic; +signal pc_df_full : std_logic; +signal pc_df_wr_en : std_logic; +signal pc_df_rd_en : std_logic; +signal pc_df_q : std_logic_vector(7 downto 0); +signal pc_all_ctr : std_logic_vector(4 downto 0); +signal pc_sub_ctr : std_logic_vector(4 downto 0); +signal pc_bytes_loaded : std_logic_vector(15 downto 0); +signal pc_size_left : std_logic_vector(31 downto 0); +signal pc_sub_size_to_save : std_logic_vector(31 downto 0); +signal pc_sub_size_loaded : std_logic_vector(31 downto 0); +signal pc_sub_bytes_loaded : std_logic_vector(31 downto 0); +signal pc_queue_size : std_logic_vector(31 downto 0); +signal pc_act_queue_size : std_logic_vector(31 downto 0); + +signal fee_read : std_logic; +signal cts_readout_finished : std_logic; +signal cts_dataready : std_logic; +signal cts_length : std_logic_vector(15 downto 0); +signal cts_data : std_logic_vector(31 downto 0); -- DHDR of rest packet +signal cts_error_pattern : std_logic_vector(31 downto 0); + +signal pc_sub_size : std_logic_vector(31 downto 0); +signal pc_trig_nr : std_logic_vector(31 downto 0); + +signal fc_wr_en : std_logic; +signal fc_data : std_logic_vector(7 downto 0); +signal fc_ip_size : std_logic_vector(15 downto 0); +signal fc_udp_size : std_logic_vector(15 downto 0); +signal fc_ident : std_logic_vector(15 downto 0); +signal fc_flags_offset : std_logic_vector(15 downto 0); +signal fc_sod : std_logic; +signal fc_eod : std_logic; +signal fc_h_ready : std_logic; +signal fc_ready : std_logic; +signal fc_dest_mac : std_logic_vector(47 downto 0); +signal fc_dest_ip : std_logic_vector(31 downto 0); +signal fc_dest_udp : std_logic_vector(15 downto 0); +signal fc_src_mac : std_logic_vector(47 downto 0); +signal fc_src_ip : std_logic_vector(31 downto 0); +signal fc_src_udp : std_logic_vector(15 downto 0); +signal fc_type : std_logic_vector(15 downto 0); +signal fc_ihl_version : std_logic_vector(7 downto 0); +signal fc_tos : std_logic_vector(7 downto 0); +signal fc_ttl : std_logic_vector(7 downto 0); +signal fc_protocol : std_logic_vector(7 downto 0); +signal fc_bsm_constr : std_logic_vector(7 downto 0); +signal fc_bsm_trans : std_logic_vector(3 downto 0); + +signal ft_data : std_logic_vector(8 downto 0); +signal ft_tx_empty : std_logic; +signal ft_start_of_packet : std_logic; +signal ft_bsm_init : std_logic_vector(3 downto 0); +signal ft_bsm_mac : std_logic_vector(3 downto 0); +signal ft_bsm_trans : std_logic_vector(3 downto 0); + +signal mac_haddr : std_logic_vector(7 downto 0); +signal mac_hdataout : std_logic_vector(7 downto 0); +signal mac_hcs : std_logic; +signal mac_hwrite : std_logic; +signal mac_hread : std_logic; +signal mac_fifoavail : std_logic; +signal mac_fifoempty : std_logic; +signal mac_fifoeof : std_logic; +signal mac_hready : std_logic; +signal mac_hdata_en : std_logic; +signal mac_tx_done : std_logic; +signal mac_tx_read : std_logic; + +signal serdes_clk_125 : std_logic; +signal mac_tx_clk_en : std_logic; +signal mac_rx_clk_en : std_logic; +signal mac_col : std_logic; +signal mac_crs : std_logic; +signal pcs_txd : std_logic_vector(7 downto 0); +signal pcs_tx_en : std_logic; +signal pcs_tx_er : std_logic; +signal pcs_an_lp_ability : std_logic_vector(15 downto 0); +signal pcs_an_complete : std_logic; +signal pcs_an_page_rx : std_logic; + +signal pcs_stat_debug : std_logic_vector(63 downto 0); + +signal stage_stat_regs : std_logic_vector(31 downto 0); +signal stage_ctrl_regs : std_logic_vector(31 downto 0); + +signal analyzer_debug : std_logic_vector(63 downto 0); + +signal ip_cfg_start : std_logic; +signal ip_cfg_bank : std_logic_vector(3 downto 0); +signal ip_cfg_done : std_logic; + +signal ip_cfg_mem_addr : std_logic_vector(7 downto 0); +signal ip_cfg_mem_data : std_logic_vector(31 downto 0); +signal ip_cfg_mem_clk : std_logic; + +begin + +stage_ctrl_regs <= STAGE_CTRL_REGS_IN; + +-- PacketConstructor fixed magic values +pc_decoding <= x"00020001"; -- !!!! swap it!!!! +pc_event_id <= x"000000ca"; -- !!!! swap it!!!! +pc_queue_dec <= x"00030062"; -- !!!! swap it!!!! +-- FrameConstructor fixed magic values +fc_type <= x"0008"; +fc_ihl_version <= x"45"; +fc_tos <= x"10"; +fc_ttl <= x"ff"; +fc_protocol <= x"11"; + +-- IP configurator: allows IP config to change for each event builder +THE_IP_CONFIGURATOR: ip_configurator +port map( + CLK => CLK, + RESET => RESET, + -- configuration interface + START_CONFIG_IN => ip_cfg_start, --IP_CFG_START_IN, -- new -- gk 7.03.10 + BANK_SELECT_IN => ip_cfg_bank, --IP_CFG_BANK_SEL_IN, -- new -- gk 27.03.10 + CONFIG_DONE_OUT => ip_cfg_done, --IP_CFG_DONE_OUT, -- new -- gk 27.03.10 + MEM_ADDR_OUT => ip_cfg_mem_addr, --IP_CFG_MEM_ADDR_OUT, -- new -- gk 27.03.10 + MEM_DATA_IN => ip_cfg_mem_data, --IP_CFG_MEM_DATA_IN, -- new -- gk 27.03.10 + MEM_CLK_OUT => ip_cfg_mem_clk, --IP_CFG_MEM_CLK_OUT, -- new -- gk 27.03.10 + -- information for IP cores + DEST_MAC_OUT => fc_dest_mac, + DEST_IP_OUT => fc_dest_ip, + DEST_UDP_OUT => fc_dest_udp, + SRC_MAC_OUT => fc_src_mac, + SRC_IP_OUT => fc_src_ip, + SRC_UDP_OUT => fc_src_udp, + MTU_OUT => pc_max_frame_size, + -- Debug + DEBUG_OUT => open +); + +-- gk 27.03.01 +MB_IP_CONFIG: slv_mac_memory +port map( + CLK => CLK, -- clk_100, + RESET => RESET, --reset_i, + BUSY_IN => '0', + -- Slave bus + SLV_ADDR_IN => SLV_ADDR_IN, --x"00", --mb_ip_mem_addr(7 downto 0), + SLV_READ_IN => SLV_READ_IN, --'0', --mb_ip_mem_read, + SLV_WRITE_IN => SLV_WRITE_IN, --mb_ip_mem_write, + SLV_BUSY_OUT => SLV_BUSY_OUT, + SLV_ACK_OUT => SLV_ACK_OUT, --mb_ip_mem_ack, + SLV_DATA_IN => SLV_DATA_IN, --mb_ip_mem_data_wr, + SLV_DATA_OUT => SLV_DATA_OUT, --mb_ip_mem_data_rd, + -- I/O to the backend + MEM_CLK_IN => ip_cfg_mem_clk, + MEM_ADDR_IN => ip_cfg_mem_addr, + MEM_DATA_OUT => ip_cfg_mem_data, + -- Status lines + STAT => open +); + + +-- First stage: get data from IPU channel, buffer it and terminate the IPU transmission to CTS +THE_IPU_INTERFACE: trb_net16_ipu2gbe +port map( + CLK => CLK, + RESET => RESET, + --Event information coming from CTS + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + --Information sent to CTS + --status data, equipped with DHDR + CTS_DATA_OUT => cts_data, + CTS_DATAREADY_OUT => cts_dataready, + CTS_READOUT_FINISHED_OUT => cts_readout_finished, + CTS_READ_IN => CTS_READ_IN, + CTS_LENGTH_OUT => cts_length, + CTS_ERROR_PATTERN_OUT => cts_error_pattern, + -- Data from Frontends + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => fee_read, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + FEE_BUSY_IN => FEE_BUSY_IN, + -- slow control interface + START_CONFIG_OUT => ip_cfg_start, --open, --: out std_logic; -- reconfigure MACs/IPs/ports/packet size -- gk 27.03.10 + BANK_SELECT_OUT => ip_cfg_bank, --open, --: out std_logic_vector(3 downto 0); -- configuration page address -- gk 27.03.10 + CONFIG_DONE_IN => ip_cfg_done, --'1', --: in std_logic; -- configuration finished -- gk 27.03.10 + DATA_GBE_ENABLE_IN => '1', --: in std_logic; -- IPU data is forwarded to GbE + DATA_IPU_ENABLE_IN => '0', --: in std_logic; -- IPU data is forwarded to CTS / TRBnet + MULTI_EVT_ENABLE_IN => '0', --: in std_logic; -- enable multi event packets + MAX_MESSAGE_SIZE_IN => x"0000_1000", -- gk 08.04.10 -- temporarily fixed here, to be set by slow ctrl + -- PacketConstructor interface + PC_WR_EN_OUT => pc_wr_en, + PC_DATA_OUT => pc_data, + PC_READY_IN => pc_ready, + PC_SOS_OUT => pc_sos, + PC_EOD_OUT => pc_eod, + PC_SUB_SIZE_OUT => pc_sub_size, + PC_TRIG_NR_OUT => pc_trig_nr, + PC_PADDING_OUT => pc_padding, + -- Debug + BSM_SAVE_OUT => ig_bsm_save, + BSM_LOAD_OUT => ig_bsm_load, + DBG_CTS_CTR_OUT => ig_cts_ctr, + DBG_REM_CTR_OUT => ig_rem_ctr, + DBG_SF_WCNT_OUT => ig_wcnt, + DBG_SF_RCNT_OUT => ig_rcnt, + DBG_SF_DATA_OUT => ig_data, + DBG_SF_RD_EN_OUT => ig_rd_en, + DBG_SF_WR_EN_OUT => ig_wr_en, + DBG_SF_EMPTY_OUT => ig_empty, + DBG_SF_AEMPTY_OUT => ig_aempty, + DBG_SF_FULL_OUT => ig_full, + DBG_SF_AFULL_OUT => ig_afull, + DEBUG_OUT => ig_debug +); + +-- Second stage: Packet constructor +PACKET_CONSTRUCTOR : trb_net16_gbe_packet_constr +port map( + -- ports for user logic + RESET => RESET, + CLK => CLK, + PC_WR_EN_IN => pc_wr_en, + PC_DATA_IN => pc_data, + PC_READY_OUT => pc_ready, + PC_START_OF_SUB_IN => pc_sos, + PC_END_OF_DATA_IN => pc_eod, + -- queue and subevent layer headers + PC_SUB_SIZE_IN => pc_sub_size, + PC_PADDING_IN => pc_padding, -- gk 29.03.10 + PC_DECODING_IN => pc_decoding, + PC_EVENT_ID_IN => pc_event_id, + PC_TRIG_NR_IN => pc_trig_nr, + PC_QUEUE_DEC_IN => pc_queue_dec, + PC_MAX_FRAME_SIZE_IN => pc_max_frame_size, + -- NEW PORTS + FC_WR_EN_OUT => fc_wr_en, + FC_DATA_OUT => fc_data, + FC_H_READY_IN => fc_h_ready, + FC_READY_IN => fc_ready, + FC_IP_SIZE_OUT => fc_ip_size, + FC_UDP_SIZE_OUT => fc_udp_size, + FC_IDENT_OUT => fc_ident, + FC_FLAGS_OFFSET_OUT => fc_flags_offset, + FC_SOD_OUT => fc_sod, + FC_EOD_OUT => fc_eod, + -- debug ports + BSM_CONSTR_OUT => pc_bsm_constr, + BSM_LOAD_OUT => pc_bsm_load, + BSM_SAVE_OUT => pc_bsm_save, + DBG_SHF_EMPTY => pc_shf_empty, + DBG_SHF_FULL => pc_shf_full, + DBG_SHF_WR_EN => pc_shf_wr_en, + DBG_SHF_RD_EN => pc_shf_rd_en, + DBG_SHF_Q => pc_shf_q, + DBG_DF_EMPTY => pc_df_empty, + DBG_DF_FULL => pc_df_full, + DBG_DF_WR_EN => pc_df_wr_en, + DBG_DF_RD_EN => pc_df_rd_en, + DBG_DF_Q => pc_df_q, + DBG_ALL_CTR => pc_all_ctr, + DBG_SUB_CTR => pc_sub_ctr, + DBG_MY_CTR => open, + DBG_BYTES_LOADED => pc_bytes_loaded, + DBG_SIZE_LEFT => pc_size_left, + DBG_SUB_SIZE_TO_SAVE => pc_sub_size_to_save, + DBG_SUB_SIZE_LOADED => pc_sub_size_loaded, + DBG_SUB_BYTES_LOADED => pc_sub_bytes_loaded, + DBG_QUEUE_SIZE => pc_queue_size, + DBG_ACT_QUEUE_SIZE => pc_act_queue_size, + DEBUG_OUT => open +); + +-- Third stage: Frame Constructor +FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr +port map( + -- ports for user logic + RESET => RESET, + CLK => CLK, + -- + WR_EN_IN => fc_wr_en, + DATA_IN => fc_data, + START_OF_DATA_IN => fc_sod, + END_OF_DATA_IN => fc_eod, + IP_F_SIZE_IN => fc_ip_size, + UDP_P_SIZE_IN => fc_udp_size, + HEADERS_READY_OUT => fc_h_ready, + READY_OUT => fc_ready, + DEST_MAC_ADDRESS_IN => fc_dest_mac, + DEST_IP_ADDRESS_IN => fc_dest_ip, + DEST_UDP_PORT_IN => fc_dest_udp, + SRC_MAC_ADDRESS_IN => fc_src_mac, + SRC_IP_ADDRESS_IN => fc_src_ip, + SRC_UDP_PORT_IN => fc_src_udp, + FRAME_TYPE_IN => fc_type, + IHL_VERSION_IN => fc_ihl_version, + TOS_IN => fc_tos, + IDENTIFICATION_IN => fc_ident, + FLAGS_OFFSET_IN => fc_flags_offset, + TTL_IN => fc_ttl, + PROTOCOL_IN => fc_protocol, + -- ports for packetTransmitter + RD_CLK => serdes_clk_125, + FT_DATA_OUT => ft_data, + FT_TX_EMPTY_OUT => ft_tx_empty, + FT_TX_RD_EN_IN => mac_tx_read, + FT_START_OF_PACKET_OUT => ft_start_of_packet, + FT_TX_DONE_IN => mac_tx_done, + -- debug ports + BSM_CONSTR_OUT => fc_bsm_constr, + BSM_TRANS_OUT => fc_bsm_trans, + DEBUG_OUT => open +); + +FRAME_TRANSMITTER: trb_net16_gbe_frame_trans +port map( + CLK => CLK, + RESET => RESET, + TX_MAC_CLK => serdes_clk_125, + TX_EMPTY_IN => ft_tx_empty, + START_OF_PACKET_IN => ft_start_of_packet, + DATA_ENDFLAG_IN => ft_data(8), + -- MAC interface + HADDR_OUT => mac_haddr, + HDATA_OUT => mac_hdataout, + HCS_OUT => mac_hcs, + HWRITE_OUT => mac_hwrite, + HREAD_OUT => mac_hread, + HREADY_IN => mac_hready, + HDATA_EN_IN => mac_hdata_en, + TX_FIFOAVAIL_OUT => mac_fifoavail, + TX_FIFOEOF_OUT => mac_fifoeof, + TX_FIFOEMPTY_OUT => mac_fifoempty, + TX_DONE_IN => mac_tx_done, + -- Debug + BSM_INIT_OUT => ft_bsm_init, + BSM_MAC_OUT => ft_bsm_mac, + BSM_TRANS_OUT => ft_bsm_trans, + DBG_RD_DONE_OUT => open, + DBG_INIT_DONE_OUT => open, + DBG_ENABLED_OUT => open, + DEBUG_OUT => open +); + +-- in case of real hardware, we use the IP cores for MAC and PHY, and also put a SerDes in +imp_gen: if (DO_SIMULATION = 0) generate + -------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------- + -- Implementation + -------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------- + + -- MAC part + MAC: tsmac3 + port map( + ----------------- clock and reset port declarations ------------------ + hclk => CLK, + txmac_clk => serdes_clk_125, + rxmac_clk => serdes_clk_125, + reset_n => GSR_N, + txmac_clk_en => mac_tx_clk_en, + rxmac_clk_en => mac_rx_clk_en, + ------------------- Input signals to the GMII ---------------- NOT USED + rxd => x"00", + rx_dv => '0', + rx_er => '0', + col => mac_col, + crs => mac_crs, + -------------------- Input signals to the CPU I/F ------------------- + haddr => mac_haddr, + hdatain => mac_hdataout, + hcs_n => mac_hcs, + hwrite_n => mac_hwrite, + hread_n => mac_hread, + ---------------- Input signals to the Tx MAC FIFO I/F --------------- + tx_fifodata => ft_data(7 downto 0), + tx_fifoavail => mac_fifoavail, + tx_fifoeof => mac_fifoeof, + tx_fifoempty => mac_fifoempty, + tx_sndpaustim => x"0000", + tx_sndpausreq => '0', + tx_fifoctrl => '0', -- always data frame + ---------------- Input signals to the Rx MAC FIFO I/F --------------- + rx_fifo_full => '0', + ignore_pkt => '0', + ---------------- Output signals from the GMII ----------------------- + txd => pcs_txd, + tx_en => pcs_tx_en, + tx_er => pcs_tx_er, + ----------------- Output signals from the CPU I/F ------------------- + hdataout => open, + hdataout_en_n => mac_hdata_en, + hready_n => mac_hready, + cpu_if_gbit_en => open, + ------------- Output signals from the Tx MAC FIFO I/F --------------- + tx_macread => mac_tx_read, + tx_discfrm => open, + tx_staten => open, + tx_statvec => open, + tx_done => mac_tx_done, + ------------- Output signals from the Rx MAC FIFO I/F --------------- + rx_fifo_error => open, + rx_stat_vector => open, + rx_dbout => open, + rx_write => open, + rx_stat_en => open, + rx_eof => open, + rx_error => open + ); + + -- PHY part + PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b + port map( RESET => RESET, + GSR_N => GSR_N, + CLK_125_OUT => serdes_clk_125, + CLK_RX_OUT => open, + CLK_TX_OUT => open, + FT_TX_CLK_EN_OUT => mac_tx_clk_en, + FT_RX_CLK_EN_OUT => mac_rx_clk_en, + --connection to frame transmitter (tsmac) + FT_COL_OUT => mac_col, + FT_CRS_OUT => mac_crs, + FT_TXD_IN => pcs_txd, + FT_TX_EN_IN => pcs_tx_en, + FT_TX_ER_IN => pcs_tx_er, + --SFP Connection + SD_RXD_P_IN => SFP_RXD_P_IN, + SD_RXD_N_IN => SFP_RXD_N_IN, + SD_TXD_P_OUT => SFP_TXD_P_OUT, + SD_TXD_N_OUT => SFP_TXD_N_OUT, + SD_REFCLK_P_IN => SFP_REFCLK_P_IN, + SD_REFCLK_N_IN => SFP_REFCLK_N_IN, + SD_PRSNT_N_IN => SFP_PRSNT_N_IN, + SD_LOS_IN => SFP_LOS_IN, + SD_TXDIS_OUT => SFP_TXDIS_OUT, + -- Autonegotiation stuff + MR_ADV_ABILITY_IN => x"0020", -- full duplex only + MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability, + MR_AN_PAGE_RX_OUT => pcs_an_page_rx, + MR_AN_COMPLETE_OUT => pcs_an_complete, + MR_RESET_IN => MR_RESET_IN, + MR_MODE_IN => MR_MODE_IN, + MR_AN_ENABLE_IN => '1', -- do autonegotiation + MR_RESTART_AN_IN => MR_RESTART_IN, + -- Status and control port + STAT_OP => open, + CTRL_OP => x"0000", + STAT_DEBUG => pcs_stat_debug, --open, + CTRL_DEBUG => x"0000_0000_0000_0000" + ); + + stage_stat_regs(31 downto 28) <= x"d"; + stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link status + stage_stat_regs(23 downto 20) <= pcs_stat_debug(35 downto 32); -- reset bsm + stage_stat_regs(19 downto 18) <= (others => '0'); + stage_stat_regs(17) <= pcs_an_complete; + stage_stat_regs(16) <= pcs_an_page_rx; + stage_stat_regs(15 downto 0) <= pcs_an_lp_ability; + +end generate imp_gen; + +-- in case of simulation we include a fake MAC and no PHY/SerDes. +sim_gen: if (DO_SIMULATION = 1) generate + -------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------- + -- Simulation + -------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------- + MAC: mb_mac_sim + port map( -------------------------------------------------------------------------- + --------------- clock, reset, clock enable ------------------------------- + HCLK => CLK, + TX_MAC_CLK => serdes_clk_125, + RX_MAC_CLK => serdes_clk_125, + RESET_N => GSR_N, + TXMAC_CLK_EN => mac_tx_clk_en, + RXMAC_CLK_EN => mac_rx_clk_en, + -------------------------------------------------------------------------- + --------------- SGMII receive interface ---------------------------------- + RXD => x"00", + RX_DV => '0', + RX_ER => '0', + COL => mac_col, + CRS => mac_crs, + -------------------------------------------------------------------------- + --------------- SGMII transmit interface --------------------------------- + TXD => pcs_txd, + TX_EN => pcs_tx_en, + TX_ER => pcs_tx_er, + -------------------------------------------------------------------------- + --------------- CPU configuration interface ------------------------------ + HADDR => mac_haddr, + HDATAIN => mac_hdataout, + HCS_N => mac_hcs, + HWRITE_N => mac_hwrite, + HREAD_N => mac_hread, + HDATAOUT => open, + HDATAOUT_EN_N => mac_hdata_en, + HREADY_N => mac_hready, + CPU_IF_GBIT_EN => open, + -------------------------------------------------------------------------- + --------------- Transmit FIFO interface ---------------------------------- + TX_FIFODATA => ft_data(7 downto 0), + TX_FIFOAVAIL => mac_fifoavail, + TX_FIFOEOF => mac_fifoeof, + TX_FIFOEMPTY => mac_fifoempty, + TX_MACREAD => mac_tx_read, + TX_DONE => mac_tx_done, + TX_SNDPAUSTIM => x"0000", + TX_SNDPAUSREQ => '0', + TX_FIFOCTRL => '0', + TX_DISCFRM => open, + TX_STATEN => open, + TX_STATVEC => open, + -------------------------------------------------------------------------- + --------------- Receive FIFO interface ----------------------------------- + RX_DBOUT => open, + RX_FIFO_FULL => '0', + IGNORE_PKT => '0', + RX_FIFO_ERROR => open, + RX_STAT_VECTOR => open, + RX_STAT_EN => open, + RX_WRITE => open, + RX_EOF => open, + RX_ERROR => open + ); + + -- add external test clock for the MAC part + serdes_clk_125 <= TEST_CLK; + + -- fake signals + pcs_an_lp_ability <= x"4060"; + pcs_an_page_rx <= '0'; + pcs_an_complete <= '1'; + mac_tx_clk_en <= '1'; + mac_rx_clk_en <= '1'; + + stage_stat_regs(31 downto 0) <= (others => '0'); + + pcs_stat_debug(63 downto 0) <= (others => '0'); + + SFP_TXD_P_OUT <= '1'; + SFP_TXD_N_OUT <= '0'; + SFP_TXDIS_OUT <= '0'; + +end generate sim_gen; + + +------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------ + +--*************** +-- LOGIC ANALYZER SIGNALS +--*************** +analyzer_debug <= pcs_stat_debug; + +-- Interconnection signals +IG_CTS_CTR_TST <= ig_cts_ctr; +IG_REM_CTR_TST <= ig_rem_ctr; +IG_BSM_LOAD_TST <= ig_bsm_load; +IG_BSM_SAVE_TST <= ig_bsm_save; +IG_DATA_TST <= ig_data; +IG_WCNT_TST <= ig_wcnt; +IG_RCNT_TST <= ig_rcnt; +IG_RD_EN_TST <= ig_rd_en; +IG_WR_EN_TST <= ig_wr_en; +IG_EMPTY_TST <= ig_empty; +IG_AEMPTY_TST <= ig_aempty; +IG_FULL_TST <= ig_full; +IG_AFULL_TST <= ig_afull; +-- PacketConstructor signals +PC_WR_EN_TST <= pc_wr_en; +PC_DATA_TST <= pc_data; +PC_READY_TST <= pc_ready; +PC_START_OF_SUB_TST <= pc_sos; +PC_END_OF_DATA_TST <= pc_eod; +PC_SUB_SIZE_TST <= pc_sub_size; +PC_TRIG_NR_TST <= pc_trig_nr; +PC_PADDING_TST <= pc_padding; +PC_DECODING_TST <= pc_decoding; +PC_EVENT_ID_TST <= pc_event_id; +PC_QUEUE_DEC_TST <= pc_queue_dec; +PC_BSM_CONSTR_TST <= pc_bsm_constr; +PC_BSM_LOAD_TST <= pc_bsm_load; +PC_BSM_SAVE_TST <= pc_bsm_save; +PC_SHF_EMPTY_TST <= pc_shf_empty; +PC_SHF_FULL_TST <= pc_shf_full; +PC_SHF_WR_EN_TST <= pc_shf_wr_en; +PC_SHF_RD_EN_TST <= pc_shf_rd_en; +PC_SHF_Q_TST <= pc_shf_q; +PC_DF_EMPTY_TST <= pc_df_empty; +PC_DF_FULL_TST <= pc_df_full; +PC_DF_WR_EN_TST <= pc_df_wr_en; +PC_DF_RD_EN_TST <= pc_df_rd_en; +PC_DF_Q_TST <= pc_df_q; +PC_ALL_CTR_TST <= pc_all_ctr; +PC_SUB_CTR_TST <= pc_sub_ctr; +PC_BYTES_LOADED_TST <= pc_bytes_loaded; +PC_SIZE_LEFT_TST <= pc_size_left; +PC_SUB_SIZE_TO_SAVE_TST <= pc_sub_size_to_save; +PC_SUB_SIZE_LOADED_TST <= pc_sub_size_loaded; +PC_SUB_BYTES_LOADED_TST <= pc_sub_bytes_loaded; +PC_QUEUE_SIZE_TST <= pc_queue_size; +PC_ACT_QUEUE_SIZE_TST <= pc_act_queue_size; +-- FrameConstructor signals +FC_WR_EN_TST <= fc_wr_en; +FC_DATA_TST <= fc_data; +FC_SOD_TST <= fc_sod; +FC_EOD_TST <= fc_eod; +FC_IP_SIZE_TST <= fc_ip_size; +FC_UDP_SIZE_TST <= fc_udp_size; +FC_H_READY_TST <= fc_h_ready; +FC_READY_TST <= fc_ready; +FC_IDENT_TST <= fc_ident; +FC_FLAGS_OFFSET_TST <= fc_flags_offset; +FC_BSM_CONSTR_TST <= fc_bsm_constr; +FC_BSM_TRANS_TST <= fc_bsm_trans; +-- FrameTransmitter signals +FT_TX_EMPTY_TST <= ft_tx_empty; +FT_DATA_TST <= ft_data; +FT_START_OF_PACKET_TST <= ft_start_of_packet; +FT_BSM_INIT_TST <= ft_bsm_init; +FT_BSM_MAC_TST <= ft_bsm_mac; +FT_BSM_TRANS_TST <= ft_bsm_trans; +-- MAC +MAC_HADDR_TST <= mac_haddr; +MAC_HDATA_TST <= mac_hdataout; +MAC_HCS_TST <= mac_hcs; +MAC_HWRITE_TST <= mac_hwrite; +MAC_HREAD_TST <= mac_hread; +MAC_HREADY_TST <= mac_hready; +MAC_HDATA_EN_TST <= mac_hdata_en; +MAC_FIFOAVAIL_TST <= mac_fifoavail; +MAC_FIFOEOF_TST <= mac_fifoeof; +MAC_FIFOEMPTY_TST <= mac_fifoempty; +MAC_TX_DONE_TST <= mac_tx_done; +MAC_TX_READ_TST <= mac_tx_read; +PCS_AN_LP_ABILITY_TST <= pcs_an_lp_ability; +PCS_AN_COMPLETE_TST <= pcs_an_complete; +PCS_AN_PAGE_RX_TST <= pcs_an_page_rx; + +-- Outputs +FEE_READ_OUT <= fee_read; + +CTS_READOUT_FINISHED_OUT <= cts_readout_finished; +CTS_DATAREADY_OUT <= cts_dataready; +CTS_DATA_OUT <= cts_data; +CTS_LENGTH_OUT <= cts_length; +CTS_ERROR_PATTERN_OUT <= cts_error_pattern; + +STAGE_STAT_REGS_OUT <= stage_stat_regs; + +ANALYZER_DEBUG_OUT <= analyzer_debug; + +end architecture; diff --git a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd new file mode 100755 index 0000000..ce1ff3c --- /dev/null +++ b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd @@ -0,0 +1,500 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +entity trb_net16_gbe_frame_constr is +port( + -- ports for user logic + RESET : in std_logic; + CLK : in std_logic; + -- + WR_EN_IN : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + START_OF_DATA_IN : in std_logic; + END_OF_DATA_IN : in std_logic; + IP_F_SIZE_IN : in std_logic_vector(15 downto 0); + UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation + HEADERS_READY_OUT : out std_logic; + READY_OUT : out std_logic; + DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + FRAME_TYPE_IN : in std_logic_vector(15 downto 0); + IHL_VERSION_IN : in std_logic_vector(7 downto 0); + TOS_IN : in std_logic_vector(7 downto 0); + IDENTIFICATION_IN : in std_logic_vector(15 downto 0); + FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); + TTL_IN : in std_logic_vector(7 downto 0); + PROTOCOL_IN : in std_logic_vector(7 downto 0); + -- ports for packetTransmitter + RD_CLK : in std_logic; -- 125MHz clock!!! + FT_DATA_OUT : out std_logic_vector(8 downto 0); + FT_TX_EMPTY_OUT : out std_logic; + FT_TX_RD_EN_IN : in std_logic; + FT_START_OF_PACKET_OUT : out std_logic; + FT_TX_DONE_IN : in std_logic; + -- debug ports + BSM_CONSTR_OUT : out std_logic_vector(7 downto 0); + BSM_TRANS_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end trb_net16_gbe_frame_constr; + +architecture trb_net16_gbe_frame_constr of trb_net16_gbe_frame_constr is + +component fifo_4096x9 is +port( + Data : in std_logic_vector(8 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(8 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +attribute sys_encoding : string; + +type constructStates is (IDLE, DEST_MAC_ADDR, SRC_MAC_ADDR, FRAME_TYPE_S, VERSION, + TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS, + SRC_IP_ADDR, DEST_IP_ADDR, SRC_PORT, DEST_PORT, UDP_LENGTH, + UDP_CS, SAVE_DATA, CLEANUP); +signal constructCurrentState, constructNextState : constructStates; +signal bsm_constr : std_logic_vector(7 downto 0); +attribute sys_encoding of constructCurrentState: signal is "safe,gray"; + +type transmitStates is (T_IDLE, T_LOAD, T_TRANSMIT, T_CLEANUP); +signal transmitCurrentState, transmitNextState : transmitStates; +signal bsm_trans : std_logic_vector(3 downto 0); + +signal headers_int_counter : integer range 0 to 6; +signal fpf_data : std_logic_vector(7 downto 0); +signal fpf_empty : std_logic; +signal fpf_full : std_logic; +signal fpf_wr_en : std_logic; +signal fpf_q : std_logic_vector(8 downto 0); +signal ip_size : std_logic_vector(15 downto 0); +signal ip_checksum : std_logic_vector(31 downto 0); +signal udp_size : std_logic_vector(15 downto 0); +signal udp_checksum : std_logic_vector(15 downto 0); +signal ft_sop : std_logic; +signal put_udp_headers : std_logic; +signal ready_frames_ctr : std_logic_vector(15 downto 0); +signal sent_frames_ctr : std_logic_vector(15 downto 0); +signal debug : std_logic_vector(31 downto 0); +signal ready : std_logic; +signal headers_ready : std_logic; + +signal cur_max : integer range 0 to 10; + +signal ready_frames_ctr_q : std_logic_vector(15 downto 0); +signal ip_cs_temp_right : std_logic_vector(15 downto 0); -- gk 29.03.10 + +begin + +-- Fakes +udp_checksum <= x"0000"; -- no checksum test needed +debug <= (others => '0'); + +ready <= '1' when (constructCurrentState = IDLE) + else '0'; +headers_ready <= '1' when (constructCurrentState = SAVE_DATA) + else '0'; + +sizeProc: process( put_udp_headers, IP_F_SIZE_IN, UDP_P_SIZE_IN ) +begin + if( put_udp_headers = '1' ) then + ip_size <= IP_F_SIZE_IN + x"14" + x"8"; + udp_size <= UDP_P_SIZE_IN + x"8"; + else + ip_size <= IP_F_SIZE_IN + x"14"; + udp_size <= UDP_P_SIZE_IN; + end if; +end process sizeProc; + +ipCsProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (constructCurrentState = IDLE) then + ip_checksum <= x"00000000"; + else + case constructCurrentState is + when DEST_MAC_ADDR => + case headers_int_counter is + when 0 => + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + SRC_IP_ADDRESS_IN(7 downto 0); + when 1 => + ip_checksum <= ip_checksum + SRC_IP_ADDRESS_IN(15 downto 8); + when 2 => + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + SRC_IP_ADDRESS_IN(23 downto 16); + when 3 => + ip_checksum <= ip_checksum + SRC_IP_ADDRESS_IN(31 downto 24); + when 4 => + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + DEST_IP_ADDRESS_IN(7 downto 0); + when 5 => + ip_checksum <= ip_checksum + DEST_IP_ADDRESS_IN(15 downto 8); + when others => null; + end case; + when SRC_MAC_ADDR => + case headers_int_counter is + when 0 => + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + DEST_IP_ADDRESS_IN(23 downto 16); + when 1 => + ip_checksum <= ip_checksum + DEST_IP_ADDRESS_IN(31 downto 24); + when 2 => + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + IHL_VERSION_IN; + when 3 => + ip_checksum <= ip_checksum + TOS_IN; + when 4 => + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + ip_size(15 downto 8); + when 5 => + ip_checksum <= ip_checksum + ip_size(7 downto 0); + when others => null; + end case; + when VERSION => + if headers_int_counter = 0 then + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + IDENTIFICATION_IN(7 downto 0); + end if; + when TOS_S => + if headers_int_counter = 0 then + ip_checksum <= ip_checksum + IDENTIFICATION_IN(15 downto 8); + end if; + when IP_LENGTH => + if headers_int_counter = 0 then + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + FLAGS_OFFSET_IN(15 downto 8); + elsif headers_int_counter = 1 then + ip_checksum <= ip_checksum + FLAGS_OFFSET_IN(7 downto 0); + end if; + when IDENT => + if headers_int_counter = 0 then + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + TTL_IN; + elsif headers_int_counter = 1 then + ip_checksum <= ip_checksum + PROTOCOL_IN; + end if; + -- gk 29.03.10 corrected the bug with bad checksums when sum larger than 16b + when FLAGS => + if headers_int_counter = 0 then + ip_cs_temp_right <= ip_checksum(31 downto 16); + elsif headers_int_counter = 1 then + ip_checksum(31 downto 16) <= (others => '0'); + end if; + when TTL_S => + if headers_int_counter = 0 then + ip_checksum <= ip_checksum + ip_cs_temp_right; + end if; + when PROTO => + if headers_int_counter = 0 then + ip_checksum(15 downto 0) <= ip_checksum(15 downto 0) + ip_checksum(31 downto 16); + end if; + when others => null; + end case; + end if; + end if; +end process ipCsProc; + + +constructMachineProc: process( CLK ) +begin + if( rising_edge(CLK) ) then + if( RESET = '1' ) then + constructCurrentState <= IDLE; + else + constructCurrentState <= constructNextState; + end if; + end if; +end process constructMachineProc; + + +--find next state of construct machine +constructMachine: process( constructCurrentState, START_OF_DATA_IN, END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX ) +begin + constructNextState <= constructCurrentState; + if( headers_int_counter = cur_max ) then --can be checked everytime - if not in use, counter and cur_max are 0 + case constructCurrentState is + when IDLE => + if( START_OF_DATA_IN = '1' ) then + constructNextState <= DEST_MAC_ADDR; + end if; + when DEST_MAC_ADDR => + constructNextState <= SRC_MAC_ADDR; + when SRC_MAC_ADDR => + constructNextState <= FRAME_TYPE_S; + when FRAME_TYPE_S => + constructNextState <= VERSION; + when VERSION => + constructNextState <= TOS_S; + when TOS_S => + constructNextState <= IP_LENGTH; + when IP_LENGTH => + constructNextState <= IDENT; + when IDENT => + constructNextState <= FLAGS; + when FLAGS => + constructNextState <= TTL_S; + when TTL_S => + constructNextState <= PROTO; + when PROTO => + constructNextState <= HEADER_CS; + when HEADER_CS => + constructNextState <= SRC_IP_ADDR; + when SRC_IP_ADDR => + constructNextState <= DEST_IP_ADDR; + when DEST_IP_ADDR => + if (put_udp_headers = '1') then + constructNextState <= SRC_PORT; + else + constructNextState <= SAVE_DATA; + end if; + when SRC_PORT => + constructNextState <= DEST_PORT; + when DEST_PORT => + constructNextState <= UDP_LENGTH; + when UDP_LENGTH => + constructNextState <= UDP_CS; + when UDP_CS => + constructNextState <= SAVE_DATA; + when SAVE_DATA => + if (END_OF_DATA_IN = '1') then + constructNextState <= CLEANUP; + end if; + when CLEANUP => + constructNextState <= IDLE; + when others => + constructNextState <= IDLE; + end case; + end if; +end process constructMachine; + + +bsmConstrProc : process(constructCurrentState) +begin +--find maximum time in each state & set state bits + case constructCurrentState is + when IDLE => cur_max <= 0; bsm_constr <= x"01"; + when DEST_MAC_ADDR => cur_max <= 5; bsm_constr <= x"02"; + when SRC_MAC_ADDR => cur_max <= 5; bsm_constr <= x"03"; + when FRAME_TYPE_S => cur_max <= 1; bsm_constr <= x"04"; + when VERSION => cur_max <= 0; bsm_constr <= x"05"; + when TOS_S => cur_max <= 0; bsm_constr <= x"06"; + when IP_LENGTH => cur_max <= 1; bsm_constr <= x"07"; + when IDENT => cur_max <= 1; bsm_constr <= x"08"; + when FLAGS => cur_max <= 1; bsm_constr <= x"09"; + when TTL_S => cur_max <= 0; bsm_constr <= x"0a"; + when PROTO => cur_max <= 0; bsm_constr <= x"0b"; + when HEADER_CS => cur_max <= 1; bsm_constr <= x"0c"; + when SRC_IP_ADDR => cur_max <= 3; bsm_constr <= x"0d"; + when DEST_IP_ADDR => cur_max <= 3; bsm_constr <= x"0e"; + when SRC_PORT => cur_max <= 1; bsm_constr <= x"0f"; + when DEST_PORT => cur_max <= 1; bsm_constr <= x"10"; + when UDP_LENGTH => cur_max <= 1; bsm_constr <= x"11"; + when UDP_CS => cur_max <= 1; bsm_constr <= x"12"; + when SAVE_DATA => cur_max <= 0; bsm_constr <= x"13"; + when CLEANUP => cur_max <= 0; bsm_constr <= x"14"; + when others => cur_max <= 0; bsm_constr <= x"1f"; + end case; +end process; + + +headersIntProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (constructCurrentState = IDLE) then + headers_int_counter <= 0; + else + if headers_int_counter = cur_max then + headers_int_counter <= 0; + else + headers_int_counter <= headers_int_counter + 1; + end if; + end if; + end if; +end process headersIntProc; + + + +putUdpHeadersProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (FLAGS_OFFSET_IN(12 downto 0) = "0000000000000") then + put_udp_headers <= '1'; + else + put_udp_headers <= '0'; + end if; + end if; +end process putUdpHeadersProc; + + +fpfWrEnProc : process(constructCurrentState, WR_EN_IN) +begin + if (constructCurrentState /= IDLE) and (constructCurrentState /= CLEANUP) and (constructCurrentState /= SAVE_DATA) then + fpf_wr_en <= '1'; + elsif (constructCurrentState = SAVE_DATA) and (WR_EN_IN = '1') then + fpf_wr_en <= '1'; + else + fpf_wr_en <= '0'; + end if; +end process fpfWrEnProc; + +fpfDataProc : process(constructCurrentState, DEST_MAC_ADDRESS_IN, SRC_MAC_ADDRESS_IN, FRAME_TYPE_IN, IHL_VERSION_IN, + TOS_IN, ip_size, IDENTIFICATION_IN, FLAGS_OFFSET_IN, TTL_IN, PROTOCOL_IN, + ip_checksum, SRC_IP_ADDRESS_IN, DEST_IP_ADDRESS_IN, + SRC_UDP_PORT_IN, DEST_UDP_PORT_IN, udp_size, udp_checksum, headers_int_counter, DATA_IN) +begin + case constructCurrentState is + when IDLE => fpf_data <= DEST_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when DEST_MAC_ADDR => fpf_data <= DEST_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when SRC_MAC_ADDR => fpf_data <= SRC_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when FRAME_TYPE_S => fpf_data <= FRAME_TYPE_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when VERSION => fpf_data <= IHL_VERSION_IN; + when TOS_S => fpf_data <= TOS_IN; + when IP_LENGTH => fpf_data <= ip_size(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); + when IDENT => fpf_data <= IDENTIFICATION_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when FLAGS => fpf_data <= FLAGS_OFFSET_IN(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); + when TTL_S => fpf_data <= TTL_IN; + when PROTO => fpf_data <= PROTOCOL_IN; + when HEADER_CS => fpf_data <= x"ff" - ip_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); + when SRC_IP_ADDR => fpf_data <= SRC_IP_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when DEST_IP_ADDR => fpf_data <= DEST_IP_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when SRC_PORT => fpf_data <= SRC_UDP_PORT_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when DEST_PORT => fpf_data <= DEST_UDP_PORT_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when UDP_LENGTH => fpf_data <= udp_size(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); + when UDP_CS => fpf_data <= udp_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); + when SAVE_DATA => fpf_data <= DATA_IN; + when CLEANUP => fpf_data <= x"ab"; + when others => fpf_data <= x"00"; + end case; +end process fpfDataProc; + +readyFramesCtrProc: process( CLK ) +begin + if rising_edge(CLK) then + if (RESET = '1') then + ready_frames_ctr <= (others => '0'); + elsif (constructCurrentState = CLEANUP) then + ready_frames_ctr <= ready_frames_ctr + 1; + end if; + end if; +end process readyFramesCtrProc; + +FINAL_PACKET_FIFO: fifo_4096x9 +port map( + Data(7 downto 0) => fpf_data, + Data(8) => END_OF_DATA_IN, + WrClock => CLK, + RdClock => RD_CLK, + WrEn => fpf_wr_en, + RdEn => FT_TX_RD_EN_IN, + Reset => RESET, + RPReset => RESET, + Q => fpf_q, + Empty => fpf_empty, + Full => fpf_full +); + + +transferToRdClock : signal_sync + generic map( + DEPTH => 2, + WIDTH => 16 + ) + port map( + RESET => RESET, + D_IN => ready_frames_ctr, + CLK0 => RD_CLK, + CLK1 => RD_CLK, + D_OUT => ready_frames_ctr_q + ); + +transmitMachineProc: process( RD_CLK ) +begin + if( rising_edge(RD_CLK) ) then + if( RESET = '1' ) then + transmitCurrentState <= T_IDLE; + else + transmitCurrentState <= transmitNextState; + end if; + end if; +end process transmitMachineProc; + +transmitMachine: process( transmitCurrentState, fpf_q, FT_TX_DONE_IN, sent_frames_ctr, ready_frames_ctr_q ) +begin + case transmitCurrentState is + when T_IDLE => + bsm_trans <= x"0"; + if( sent_frames_ctr /= ready_frames_ctr_q ) then + transmitNextState <= T_LOAD; + else + transmitNextState <= T_IDLE; + end if; + when T_LOAD => + bsm_trans <= x"1"; + if( fpf_q(8) = '1' ) then + transmitNextState <= T_TRANSMIT; + else + transmitNextState <= T_LOAD; + end if; + when T_TRANSMIT => + bsm_trans <= x"2"; + if( ft_tx_done_in = '1' ) then + transmitNextState <= T_CLEANUP; + else + transmitNextState <= T_TRANSMIT; + end if; + when T_CLEANUP => + bsm_trans <= x"3"; + transmitNextState <= T_IDLE; + when others => + bsm_trans <= x"f"; + transmitNextState <= T_IDLE; + end case; +end process transmitMachine; + +sopProc: process( RD_CLK ) +begin + if rising_edge(RD_CLK) then + if ( RESET = '1' ) then + ft_sop <= '0'; + elsif( (transmitCurrentState = T_IDLE) and (sent_frames_ctr /= ready_frames_ctr_q) ) then + ft_sop <= '1'; + else + ft_sop <= '0'; + end if; + end if; +end process sopProc; + +sentFramesCtrProc: process( RD_CLK ) +begin + if rising_edge(RD_CLK) then + if ( RESET = '1' ) then + sent_frames_ctr <= (others => '0'); + elsif( ft_tx_done_in = '1' ) then + sent_frames_ctr <= sent_frames_ctr + 1; + end if; + end if; +end process sentFramesCtrProc; + +-- Outputs +FT_DATA_OUT <= fpf_q; +FT_TX_EMPTY_OUT <= fpf_empty; +FT_START_OF_PACKET_OUT <= ft_sop; +READY_OUT <= ready; +HEADERS_READY_OUT <= headers_ready; + +BSM_CONSTR_OUT <= bsm_constr; +BSM_TRANS_OUT <= bsm_trans; +DEBUG_OUT <= debug; + +end trb_net16_gbe_frame_constr; \ No newline at end of file diff --git a/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd b/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd new file mode 100755 index 0000000..3778f3e --- /dev/null +++ b/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd @@ -0,0 +1,579 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +entity trb_net16_gbe_frame_trans is +port ( + CLK : in std_logic; + RESET : in std_logic; + TX_MAC_CLK : in std_logic; + TX_EMPTY_IN : in std_logic; + START_OF_PACKET_IN : in std_logic; + DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC + -- NEW PORTS + HADDR_OUT : out std_logic_vector(7 downto 0); + HDATA_OUT : out std_logic_vector(7 downto 0); + HCS_OUT : out std_logic; + HWRITE_OUT : out std_logic; + HREAD_OUT : out std_logic; + HREADY_IN : in std_logic; + HDATA_EN_IN : in std_logic; + TX_FIFOAVAIL_OUT : out std_logic; + TX_FIFOEOF_OUT : out std_logic; + TX_FIFOEMPTY_OUT : out std_logic; + TX_DONE_IN : in std_logic; + -- Debug + BSM_INIT_OUT : out std_logic_vector(3 downto 0); + BSM_MAC_OUT : out std_logic_vector(3 downto 0); + BSM_TRANS_OUT : out std_logic_vector(3 downto 0); + DBG_RD_DONE_OUT : out std_logic; + DBG_INIT_DONE_OUT : out std_logic; + DBG_ENABLED_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end trb_net16_gbe_frame_trans; + +-- FifoRd ?!? + +architecture trb_net16_gbe_frame_trans of trb_net16_gbe_frame_trans is + +component mac_init_mem is +port ( + Address : in std_logic_vector(5 downto 0); + OutClock : in std_logic; + OutClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(7 downto 0) +); +end component; + +attribute syn_encoding : string; + +type macInitStates is (I_IDLE, I_INCRADDRESS, I_PAUSE, I_WRITE, I_PAUSE2, I_READ, I_PAUSE3, I_ENDED); +signal macInitState, macInitNextState : macInitStates; +attribute syn_encoding of macInitState: signal is "safe,gray"; +signal bsm_init : std_logic_vector(3 downto 0); + +type macStates is (M_RESETING, M_IDLE, M_INIT); +signal macCurrentState, macNextState : macStates; +signal bsm_mac : std_logic_vector(3 downto 0); + +type transmitStates is (T_IDLE, T_TRANSMIT, T_WAITFORFIFO); +signal transmitCurrentState, transmitNextState : transmitStates; +attribute syn_encoding of transmitCurrentState: signal is "safe,gray"; +signal bsm_trans : std_logic_vector(3 downto 0); + +signal tx_fifoavail_i : std_logic; +signal tx_fifoeof_i : std_logic; + +-- host interface signals +signal hcs_n_i : std_logic; +signal hwrite_n_i : std_logic; +signal hread_n_i : std_logic; + +-- MAC INITIALIZATION signals +signal macInitMemAddr : std_logic_vector(5 downto 0); +signal macInitMemQ : std_logic_vector(7 downto 0); +signal macInitMemEn : std_logic; +signal reading_done : std_logic; +signal init_done : std_logic; +signal enabled : std_logic; +signal addrSig : std_logic_vector(5 downto 0); +signal addr2 : std_logic_vector(5 downto 0); +signal resetAddr : std_logic; + +signal FifoEmpty : std_logic; +signal debug : std_logic_vector(31 downto 0); + +begin + +-- Fakes +debug <= (others => '0'); + + +TransmitStateMachineProc : process (TX_MAC_CLK) +begin + if rising_edge(TX_MAC_CLK) then + if RESET = '1' then + transmitCurrentState <= T_IDLE; + else + transmitCurrentState <= transmitNextState; + end if; + end if; +end process TransmitStatemachineProc; + +TransmitStateMachine : process (transmitCurrentState, macCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN) +begin + case transmitCurrentState is + when T_IDLE => + bsm_trans <= x"0"; + if ((START_OF_PACKET_IN = '1') and (macCurrentState = M_IDLE)) then + transmitNextState <= T_TRANSMIT; + else + transmitNextState <= T_IDLE; + end if; + when T_TRANSMIT => + bsm_trans <= x"1"; + if (DATA_ENDFLAG_IN = '1') then + transmitNextState <= T_WAITFORFIFO; + else + transmitNextState <= T_TRANSMIT; + end if; + when T_WAITFORFIFO => + bsm_trans <= x"2"; + if (TX_DONE_IN = '1') then + transmitNextState <= T_IDLE; + else + transmitNextState <= T_WAITFORFIFO; + end if; + when others => + bsm_trans <= x"f"; + transmitNextState <= T_IDLE; + end case; +end process TransmitStateMachine; + +FifoAvailProc : process (TX_MAC_CLK) +begin + if rising_edge(TX_MAC_CLK) then + if RESET = '1' then + tx_fifoavail_i <= '0'; + elsif (transmitCurrentState = T_TRANSMIT) then + tx_fifoavail_i <= '1'; + else + tx_fifoavail_i <= '0'; + end if; + end if; +end process FifoAvailProc; + +FifoEmptyProc : process(transmitCurrentState, START_OF_PACKET_IN, TX_EMPTY_IN) +begin + if (transmitCurrentState = T_WAITFORFIFO) then + FifoEmpty <= '1'; + elsif (transmitCurrentState = T_TRANSMIT) then + FifoEmpty <= TX_EMPTY_IN; + elsif (((transmitCurrentState = T_IDLE) or (transmitCurrentState = T_WAITFORFIFO)) and (START_OF_PACKET_IN = '1')) then + FifoEmpty <= '0'; + else + FifoEmpty <= '1'; + end if; +end process FifoEmptyProc; + +tx_fifoeof_i <= '1' when ((DATA_ENDFLAG_IN = '1') and (transmitCurrentState = T_TRANSMIT)) + else '0'; + +-- main MAC state machine +MacStateMachineProc : process (CLK) +begin + if rising_edge(CLK) then + if RESET = '1' then + macCurrentState <= M_RESETING; + else + macCurrentState <= macNextState; + end if; + end if; +end process MacStateMachineProc; + +MacStatesMachine: process(macCurrentState, reading_done) +begin + case macCurrentState is + when M_RESETING => + bsm_mac <= x"0"; + macNextState <= M_INIT; + when M_IDLE => + bsm_mac <= x"1"; + macNextState <= M_IDLE; + when M_INIT => + bsm_mac <= x"2"; + if (reading_done = '1') then + macNextState <= M_IDLE; + else + macNextState <= M_INIT; + end if; + when others => + bsm_mac <= x"f"; + macNextState <= M_RESETING; + end case; +end process MacStatesMachine; + + +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +-- MAC initialization statemachine, memory and address counters +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- + +-- state machine used to initialize MAC registers with data saved in macInitDataInv2.mem via macInitMem +MacInitStateMachineProc : process (CLK) +begin + if rising_edge(CLK) then + if RESET = '1' then + macInitState <= I_IDLE; + else + macInitState <= macInitNextState; + end if; + end if; +end process MacInitStateMachineProc; + +MacInitStateMachine : process (macInitState, macCurrentState, init_done, HREADY_IN, reading_done, HDATA_EN_IN, enabled) +begin + case macInitState is + when I_IDLE => + bsm_init <= x"0"; + if (macCurrentState = M_INIT) then + macInitNextState <= I_WRITE; + else + macInitNextState <= I_IDLE; + end if; + when I_INCRADDRESS => + bsm_init <= x"1"; + if ((init_done = '0') and (enabled = '0') and (reading_done = '0')) then -- write to regs 2 and up + macInitNextState <= I_PAUSE; + elsif ((init_done = '1') and (enabled = '0') and (reading_done = '0')) then -- write to regs 0 and 1 + macInitNextState <= I_PAUSE3; + elsif ((init_done = '1') and (enabled = '1') and (reading_done = '0')) then -- read all regs to fifo + macInitNextState <= I_PAUSE2; + else + macInitNextState <= I_ENDED; + end if; + when I_PAUSE => + bsm_init <= x"2"; + if (HREADY_IN = '1') then + macInitNextState <= I_WRITE; + else + macInitNextState <= I_PAUSE; + end if; + when I_WRITE => + bsm_init <= x"3"; + if (HREADY_IN = '0') then + macInitNextState <= I_INCRADDRESS; + else + macInitNextState <= I_WRITE; + end if; + when I_PAUSE2 => + bsm_init <= x"4"; + if (HREADY_IN = '1') then + macInitNextState <= I_READ; + else + macInitNextState <= I_PAUSE2; + end if; + when I_READ => + bsm_init <= x"5"; + if (HDATA_EN_IN = '0') then + macInitNextState <= I_INCRADDRESS; + else + macInitNextState <= I_READ; + end if; + when I_PAUSE3 => + bsm_init <= x"6"; + if (HREADY_IN = '1') then + macInitNextState <= I_WRITE; + else + macInitNextState <= I_PAUSE3; + end if; + when I_ENDED => + bsm_init <= x"7"; + macInitNextState <= I_ENDED; + when others => + bsm_init <= x"f"; + macInitNextState <= I_IDLE; + end case; +end process MacInitStateMachine; + +addrSig <= addr2 when ((reading_done = '0') and (init_done = '1') and (enabled = '1')) + else macInitMemAddr; + +-- initialization ROM +MacInitMemory : mac_init_mem +port map ( + Address => macInitMemAddr, + OutClock => CLK, + OutClockEn => macInitMemEn, + Reset => RESET, + Q => macInitMemQ +); + +-- MAC ready signal (?) +enabledProc : process (CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + enabled <= '0'; + elsif ((reading_done = '0') and (init_done = '1') and (macInitMemAddr = "000010")) then -- write only to the first register (mode) + enabled <= '1'; + elsif (macInitState = I_IDLE) then + enabled <= '0'; + end if; + end if; +end process enabledProc; + +add2 : process (CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + addr2 <= "111111"; + elsif ((macInitState = I_INCRADDRESS) and (init_done = '1') and (enabled = '1')) then + addr2 <= addr2 + "1"; + elsif (macInitState = I_IDLE) then + addr2 <= "111111"; + end if; + end if; +end process add2; + +readingDoneProc : process (CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + reading_done <= '0'; + elsif (macInitState = I_IDLE) then + reading_done <= '0'; + elsif (addr2 = "110101") then -- read all registers + reading_done <= '1'; + end if; + end if; +end process readingDoneProc; + +initDoneProc : process (CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + init_done <= '0'; + elsif (macInitState = I_IDLE) then + init_done <= '0'; + elsif (macInitMemAddr = "110101") then -- write to all registers + init_done <= '1'; + end if; + end if; +end process initDoneProc; + +-- HWRITE signal (registered) +hwriteProc : process (CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + hwrite_n_i <= '1'; + elsif ((macInitState = I_WRITE) and (HREADY_IN = '1')) then + hwrite_n_i <= '0'; + else + hwrite_n_i <= '1'; + end if; + end if; +end process hwriteProc; + +-- HREAD signal (registered) +hreadProc : process (CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + hread_n_i <= '1'; + elsif ((macInitState = I_READ) and (HREADY_IN = '1')) then + hread_n_i <= '0'; + else + hread_n_i <= '1'; + end if; + end if; +end process hreadProc; + +-- HCS signal (registered) +hcsProc : process (CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + hcs_n_i <= '1'; + elsif ((macInitState = I_WRITE) and (HREADY_IN = '1')) then + hcs_n_i <= '0'; + elsif ((macInitState = I_READ) and (HREADY_IN = '1')) then + hcs_n_i <= '0'; + else + hcs_n_i <= '1'; + end if; + end if; +end process hcsProc; + +-- address lines for the initialization memory +macInitMemAddrProc : process (CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + macInitMemAddr <= "000010"; + elsif (resetAddr = '1') then + macInitMemAddr <= "000000"; + else + if (macInitState = I_INCRADDRESS) then + macInitMemAddr <= macInitMemAddr + "1"; + elsif (macInitState = I_IDLE) then + macInitMemAddr <= "000010"; + end if; + end if; + end if; +end process macInitMemAddrProc; + +-- address counter reset signal (registered) +resetAddrProc : process (CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + resetAddr <= '0'; + elsif (macInitState = I_IDLE) then + resetAddr <= '0'; + elsif (macInitMemAddr = "110101") then + resetAddr <= '1'; + elsif (macInitState = I_PAUSE3) then + resetAddr <= '0'; + end if; + end if; +end process resetAddrProc; + +macInitMemEn <= '1' when (macCurrentState = M_INIT) + else '0'; + + + +-- Outputs +HADDR_OUT <= b"00" & addrSig; +HDATA_OUT <= macInitMemQ; +HCS_OUT <= hcs_n_i; +HWRITE_OUT <= hwrite_n_i; +HREAD_OUT <= hread_n_i; +TX_FIFOAVAIL_OUT <= tx_fifoavail_i; +TX_FIFOEOF_OUT <= tx_fifoeof_i; +TX_FIFOEMPTY_OUT <= FifoEmpty; + +BSM_INIT_OUT <= bsm_init; +BSM_MAC_OUT <= bsm_mac; +BSM_TRANS_OUT <= bsm_trans; +DBG_RD_DONE_OUT <= reading_done; +DBG_INIT_DONE_OUT <= init_done; +DBG_ENABLED_OUT <= enabled; +DEBUG_OUT <= debug; + +end trb_net16_gbe_frame_trans; + + +--MAC : tsmac3 +--port map( +-- -------------------------------------------------------------------------- +-- --------------- clock, reset, clock enable ------------------------------- +-- hclk => CLK, -- (in) host clock (100MHz) +-- txmac_clk => TX_MAC_CLK, -- (in) GbE clock (125MHz) +-- rxmac_clk => '0', -- (in) not used (no receiving on GbE) +-- reset_n => GSR_N, -- (in) global set/reset +-- txmac_clk_en => TSM_TX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation +-- rxmac_clk_en => TSM_RX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation +-- -------------------------------------------------------------------------- +-- --------------- SGMII receive interface ---------------------------------- +-- rxd => x"00", -- (in) receive data from SGMII core +-- rx_dv => '0', -- (in) data valid from SGMII core +-- rx_er => '0', -- (in) receive data error +-- col => TSM_COL_IN, -- (in) collision from SGMII core +-- crs => TSM_CRS_IN, -- (in) carrier sense from SGMII core +-- -------------------------------------------------------------------------- +-- --------------- SGMII transmit interface --------------------------------- +-- txd => CH_TXD_OUT, -- (out) transmit data to SGMII core +-- tx_en => CH_TX_EN_OUT, -- (out) transmit enable +-- tx_er => CH_TX_ER_OUT, -- (out) transmit error +-- -------------------------------------------------------------------------- +-- --------------- CPU configuration interface ------------------------------ +-- haddr => haddr, -- (in) host address bus for configuration +-- hdatain => hdataout, -- (in) host data bus for write accesses +-- hcs_n => hcs, -- (in) host chip select signal +-- hwrite_n => hwrite, -- (in) host write strobe signal +-- hread_n => hread, -- (in) host read strobe signal +-- hdataout => hdatain, -- (out) host data bus for read accesses +-- hdataout_en_n => hdataout_en, -- (out) read data valid signal +-- hready_n => hready, -- (out) data acknowledge signal +-- cpu_if_gbit_en => open, -- (out) status bit +-- -------------------------------------------------------------------------- +-- --------------- Transmit FIFO interface ---------------------------------- +-- tx_fifodata => ft_data(7 downto 0), -- (in) transmit FIFO data bus +-- tx_fifoavail => mac_fifoavail, -- (in) transmit FIFO data available +-- tx_fifoeof => mac_fifoeof, -- (in) transmit FIFO end of frame +-- tx_fifoempty => mac_fifoempty, -- (in) transmit FIFO empty +-- tx_macread => mac_tx_rd_en, -- (out) transmit FIFO read +-- tx_done => mac_tx_done, -- (out) transmit done (without errors) +-- tx_sndpaustim => x"0000", -- (in) PAUSE frame timer +-- tx_sndpausreq => '0', -- (in) PAUSE frame request +-- tx_fifoctrl => '0', -- (in) FIFO control frame ('0' = data, '1' = control) +-- tx_discfrm => open, -- (out) discard frame +-- tx_staten => open, -- (out) transmit statistics vector enable +-- tx_statvec => open, -- (out) transmit statistics vector +-- -------------------------------------------------------------------------- +-- --------------- Receive FIFO interface ----------------------------------- +-- rx_dbout => open, -- (out) receive FIFO data output +-- rx_fifo_full => '0', -- (in) receive FIFO full +-- ignore_pkt => '0', -- (in) ignore next packet +-- rx_fifo_error => open, -- (out) receive FIFO error +-- rx_stat_vector => open, -- (out) receive statistics vector +-- rx_stat_en => open, -- (out) receive statistics vector enable +-- rx_write => open, -- (out) receive FIFO write +-- rx_eof => open, -- (out) end of frame +-- rx_error => open -- (out) receive packet error +--); + + + + + + +--MAC : tsmac3 +--port map( +----------------- clock and reset port declarations ------------------ +-- hclk => LVDS_CLK_200P, +-- txmac_clk => TX_MAC_CLK, +-- rxmac_clk => '0', +-- reset_n => GSR_N, -- done +-- txmac_clk_en => TSM_TX_CLK_EN_IN, -- done +-- rxmac_clk_en => TSM_RX_CLK_EN_IN, -- done +--------------------- Input signals to the GMII ---------------- NOT USED +-- rxd => x"00", +-- rx_dv => '0', +-- rx_er => '0', +-- col => TSM_COL_IN, -- done +-- crs => TSM_CRS_IN, -- done +-- -------------------- Input signals to the CPU I/F ------------------- +-- haddr(5 downto 0) => addrSig, -- done +-- haddr(7 downto 6) => "00", +-- hdatain => macInitMemQ, -- done +-- hcs_n => hcs_n_i, -- done +-- hwrite_n => hwrite_n_i, -- done +-- hread_n => hread_n_i, -- done +------------------ Input signals to the Tx MAC FIFO I/F --------------- +-- tx_fifodata => DATA_IN(7 downto 0), -- done +-- tx_fifoavail => tx_fifoavail_i, -- done +-- tx_fifoeof => tx_fifoeof_i, -- done +-- tx_fifoempty => FifoEmpty, -- done +-- tx_sndpaustim => x"0000", +-- tx_sndpausreq => '0', +-- tx_fifoctrl => '0', -- always data frame +------------------ Input signals to the Rx MAC FIFO I/F --------------- +-- rx_fifo_full => '0', +-- ignore_pkt => '0', +---------------------- Output signals from the GMII ----------------------- +-- txd => CH_TXD_OUT, -- done +-- tx_en => CH_TX_EN_OUT, -- done +-- tx_er => CH_TX_ER_OUT, -- done +---------------------- Output signals from the CPU I/F ------------------- +-- hdataout => hdataout_i, -- done +-- hdataout_en_n => hdataout_en_n_i, -- done +-- hready_n => hready_n_i, -- done +-- cpu_if_gbit_en => gbe_enabled, -- done +------------------ Output signals from the Tx MAC FIFO I/F --------------- +-- tx_macread => FifoRd, -- done +-- tx_discfrm => tx_discfrm_i, -- not used +-- tx_staten => tx_staten_i, -- done +-- tx_statvec => tx_statvec_i, -- done +-- tx_done => tx_done_i, -- done +------------------ Output signals from the Rx MAC FIFO I/F --------------- +-- rx_fifo_error => open, +-- rx_stat_vector => open, +-- rx_dbout => open, +-- rx_write => open, +-- rx_stat_en => open, +-- rx_eof => rx_eof_i, -- done +-- rx_error => rx_error_i -- done +--); diff --git a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd new file mode 100755 index 0000000..ef7d4e2 --- /dev/null +++ b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd @@ -0,0 +1,901 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +use IEEE.std_logic_arith.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +entity trb_net16_gbe_packet_constr is +port( + RESET : in std_logic; + CLK : in std_logic; + -- ports for user logic + PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic + PC_DATA_IN : in std_logic_vector(7 downto 0); + PC_READY_OUT : out std_logic; + PC_START_OF_SUB_IN : in std_logic; + PC_END_OF_DATA_IN : in std_logic; + -- queue and subevent layer headers + PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap + PC_PADDING_IN : in std_logic; -- gk 29.03.10 + PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap + PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap + PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! + PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap + PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP + -- FrameConstructor ports + FC_WR_EN_OUT : out std_logic; + FC_DATA_OUT : out std_logic_vector(7 downto 0); + FC_H_READY_IN : in std_logic; + FC_READY_IN : in std_logic; + FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); + FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); + FC_IDENT_OUT : out std_logic_vector(15 downto 0); + FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); + FC_SOD_OUT : out std_logic; + FC_EOD_OUT : out std_logic; + -- debug ports + BSM_CONSTR_OUT : out std_logic_vector(3 downto 0); + BSM_LOAD_OUT : out std_logic_vector(3 downto 0); + BSM_SAVE_OUT : out std_logic_vector(3 downto 0); + DBG_SHF_EMPTY : out std_logic; + DBG_SHF_FULL : out std_logic; + DBG_SHF_WR_EN : out std_logic; + DBG_SHF_RD_EN : out std_logic; + DBG_SHF_Q : out std_logic_vector(7 downto 0); + DBG_DF_EMPTY : out std_logic; + DBG_DF_FULL : out std_logic; + DBG_DF_WR_EN : out std_logic; + DBG_DF_RD_EN : out std_logic; + DBG_DF_Q : out std_logic_vector(7 downto 0); + DBG_ALL_CTR : out std_logic_vector(4 downto 0); + DBG_SUB_CTR : out std_logic_vector(4 downto 0); + DBG_MY_CTR : out std_logic_vector(1 downto 0); + DBG_BYTES_LOADED : out std_logic_vector(15 downto 0); + DBG_SIZE_LEFT : out std_logic_vector(31 downto 0); + DBG_SUB_SIZE_TO_SAVE : out std_logic_vector(31 downto 0); + DBG_SUB_SIZE_LOADED : out std_logic_vector(31 downto 0); + DBG_SUB_BYTES_LOADED : out std_logic_vector(31 downto 0); + DBG_QUEUE_SIZE : out std_logic_vector(31 downto 0); + DBG_ACT_QUEUE_SIZE : out std_logic_vector(31 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end trb_net16_gbe_packet_constr; + +architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is + +-- FIFO for packet payload data +component fifo_64kx8 +port ( + Data : in std_logic_vector(7 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(7 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +-- FIFO for SubEventHeader information +component fifo_2048x8 is +port ( + Data : in std_logic_vector(7 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(7 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +signal df_wr_en : std_logic; +signal df_rd_en : std_logic; +signal df_q : std_logic_vector(7 downto 0); +signal df_q_reg : std_logic_vector(7 downto 0); +signal df_empty : std_logic; +signal df_full : std_logic; + +signal fc_data : std_logic_vector(7 downto 0); +signal fc_wr_en : std_logic; +signal fc_sod : std_logic; +signal fc_eod : std_logic; +signal fc_ident : std_logic_vector(15 downto 0); -- change this to own counter! +signal fc_flags_offset : std_logic_vector(15 downto 0); + +signal shf_data : std_logic_vector(7 downto 0); +signal shf_wr_en : std_logic; +signal shf_rd_en : std_logic; +signal shf_q : std_logic_vector(7 downto 0); +signal shf_empty : std_logic; +signal shf_full : std_logic; + +type constructStates is (CIDLE, SAVE_DATA, WAIT_FOR_LOAD); +signal constructCurrentState, constructNextState : constructStates; +signal constr_state : std_logic_vector(3 downto 0); +signal all_int_ctr : integer range 0 to 31; +signal all_ctr : std_logic_vector(4 downto 0); + +type saveSubStates is (SIDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRIG_NR, SAVE_TERM); +signal saveSubCurrentState, saveSubNextState : saveSubStates; +signal save_state : std_logic_vector(3 downto 0); +signal sub_int_ctr : integer range 0 to 31; +signal sub_ctr : std_logic_vector(4 downto 0); +signal my_int_ctr : integer range 0 to 3; +signal my_ctr : std_logic_vector(1 downto 0); + +type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP); +signal loadCurrentState, loadNextState: loadStates; +signal load_state : std_logic_vector(3 downto 0); + +signal queue_size : std_logic_vector(31 downto 0); -- sum of all subevents sizes plus their headers and queue headers and termination +signal queue_size_temp : std_logic_vector(31 downto 0); +signal actual_queue_size : std_logic_vector(31 downto 0); -- queue size used during loading process when queue_size is no more valid +signal bytes_loaded : std_logic_vector(15 downto 0); -- size of actual constructing frame +signal sub_size_to_save : std_logic_vector(31 downto 0); -- size of subevent to save to shf +signal sub_size_loaded : std_logic_vector(31 downto 0); -- size of subevent actually being transmitted +signal sub_bytes_loaded : std_logic_vector(31 downto 0); -- amount of bytes of actual subevent sent +signal actual_packet_size : std_logic_vector(15 downto 0); -- actual size of whole udp packet +signal size_left : std_logic_vector(31 downto 0); +signal fc_ip_size : std_logic_vector(15 downto 0); +signal fc_udp_size : std_logic_vector(15 downto 0); +signal max_frame_size : std_logic_vector(15 downto 0); +signal divide_position : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term +signal debug : std_logic_vector(31 downto 0); +signal pc_ready : std_logic; + +signal pc_sub_size : std_logic_vector(31 downto 0); +signal pc_trig_nr : std_logic_vector(31 downto 0); +signal pc_padding : std_logic; -- gk 29.03.10 +signal rst_after_sub_comb : std_logic; -- gk 08.04.10 +signal rst_after_sub : std_logic; -- gk 08.04.10 +signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10 + +begin + +-- Fakes +debug <= (others => '0'); + +my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order +load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2))); -- gk 08.04.10 + +all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for debugging +sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging +my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging + +pc_padding <= PC_PADDING_IN; -- gk 29.03.10 used to correct the subevent size written to subevent headers + +-- Fixed numbers + +--max_frame_size <= x"0578"; -- 1400 +max_frame_size <= PC_MAX_FRAME_SIZE_IN; + +-- Ready signal for PacketConstructor +pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '0'; + +-- store event information on Start_of_Subevent +THE_EVT_INFO_STORE_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if( PC_START_OF_SUB_IN = '1' ) then + pc_sub_size <= PC_SUB_SIZE_IN; + pc_trig_nr <= PC_TRIG_NR_IN; + end if; + end if; +end process; + +-- Data FIFO for incoming packet data from IPU buffer +DATA_FIFO : fifo_64kx8 +port map( + Data => PC_DATA_IN, + WrClock => CLK, + RdClock => CLK, + WrEn => df_wr_en, + RdEn => df_rd_en, + Reset => RESET, + RPReset => RESET, + Q => df_q, + Empty => df_empty, + Full => df_full +); +-- Write enable for the data FIFO +-- !!!combinatorial signal!!! +-- could be avoided as IPU2GBE does only send data in case of PC_READY. +df_wr_en <= '1' when ((PC_WR_EN_IN = '1') and (constructCurrentState /= WAIT_FOR_LOAD)) + else '0'; + +-- Output register for data FIFO +dfQProc : process(CLK) +begin + if rising_edge(CLK) then + df_q_reg <= df_q; + end if; +end process dfQProc; + +-- Construction state machine +constructMachineProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + constructCurrentState <= CIDLE; + else + constructCurrentState <= constructNextState; + end if; + end if; +end process constructMachineProc; + +constructMachine : process(constructCurrentState, PC_WR_EN_IN, PC_END_OF_DATA_IN, loadCurrentState, saveSubCurrentState, sub_int_ctr) +begin + case constructCurrentState is + when CIDLE => + constr_state <= x"0"; + if( PC_WR_EN_IN = '1' ) then + constructNextState <= SAVE_DATA; + else + constructNextState <= CIDLE; + end if; + when SAVE_DATA => + constr_state <= x"1"; + if( PC_END_OF_DATA_IN = '1' ) then + constructNextState <= WAIT_FOR_LOAD; + else + constructNextState <= SAVE_DATA; + end if; + when WAIT_FOR_LOAD => + constr_state <= x"2"; + if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted + constructNextState <= CIDLE; + else + constructNextState <= WAIT_FOR_LOAD; + end if; + when others => + constr_state <= x"f"; + constructNextState <= CIDLE; + end case; +end process constructMachine; + + +--*********************** +-- SUBEVENT HEADERS WRITE AND READ +--*********************** + +SUBEVENT_HEADERS_FIFO : fifo_2048x8 +port map( + Data => shf_data, + WrClock => CLK, + RdClock => CLK, + WrEn => shf_wr_en, + RdEn => shf_rd_en, + Reset => RESET, + RPReset => RESET, + Q => shf_q, + Empty => shf_empty, + Full => shf_full +); + +-- write enable for SHF +shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA)) + else '0'; + +-- data multiplexing for SHF (convert 32bit LWs to 8bit) +-- CHANGED. +-- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC. +shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN, + pc_trig_nr, my_int_ctr, fc_data) +begin + case saveSubCurrentState is + when SIDLE => shf_data <= x"ac"; + when SAVE_SIZE => shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8); + when SAVE_DECODING => shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8); + when SAVE_ID => shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8); + when SAVE_TRIG_NR => shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8); + when SAVE_TERM => shf_data <= fc_data; + when others => shf_data <= x"00"; + end case; +end process shfDataProc; + +saveSubMachineProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + saveSubCurrentState <= SIDLE; + else + saveSubCurrentState <= saveSubNextState; + end if; + end if; +end process saveSubMachineProc; + +saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, FC_H_READY_IN) +begin + case saveSubCurrentState is + when SIDLE => + save_state <= x"0"; + if (PC_START_OF_SUB_IN = '1') then + saveSubNextState <= SAVE_SIZE; + -- this branch is dangerous! + elsif (loadCurrentState = WAIT_FOR_FC) and (FC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len + saveSubNextState <= SAVE_TERM; + else + saveSubNextState <= SIDLE; + end if; + when SAVE_SIZE => + save_state <= x"1"; + if (sub_int_ctr = 3) then + saveSubNextState <= SAVE_DECODING; + else + saveSubNextState <= SAVE_SIZE; + end if; + when SAVE_DECODING => + save_state <= x"2"; + if (sub_int_ctr = 3) then + saveSubNextState <= SAVE_ID; + else + saveSubNextState <= SAVE_DECODING; + end if; + when SAVE_ID => + save_state <= x"3"; + if (sub_int_ctr = 3) then + saveSubNextState <= SAVE_TRIG_NR; + else + saveSubNextState <= SAVE_ID; + end if; + when SAVE_TRIG_NR => + save_state <= x"4"; + if (sub_int_ctr = 3) then + saveSubNextState <= SIDLE; + else + saveSubNextState <= SAVE_TRIG_NR; + end if; + when SAVE_TERM => + save_state <= x"5"; + if (sub_int_ctr = 31) then + saveSubNextState <= SIDLE; + else + saveSubNextState <= SAVE_TERM; + end if; + when others => + save_state <= x"f"; + saveSubNextState <= SIDLE; + end case; +end process; + +-- This counter is used for breaking down 32bit information words into 8bit bytes for +-- storing them in the SHF. +-- It is also used for the termination 32byte sequence. +subIntProc: process( CLK ) +begin + if rising_edge(CLK) then + if (RESET = '1') or (saveSubCurrentState = SIDLE) then + sub_int_ctr <= 0; + elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then + sub_int_ctr <= 0; + elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then + sub_int_ctr <= 0; + elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then + sub_int_ctr <= sub_int_ctr + 1; + end if; + end if; +end process subIntProc; + +--*********************** +-- SIZE COUNTERS FOR SAVING SIDE +--*********************** + +-- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size +-- that's why they are removed if pc_padding flag is asserted +sub_size_to_save <= x"10" + pc_sub_size when pc_padding = '0' else x"c" + pc_sub_size; -- subevent headers + data + +-- BUG HERE BUG HERE BUG HERE BUG HERE +-- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents +queueSizeProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (loadCurrentState = CLEANUP) then + queue_size <= x"00000028"; -- + 8B for queue headers and 20B for termination + elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then + queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers + end if; + end if; +end process queueSizeProc; + + +--*********************** +-- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION +--*********************** + +loadMachineProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + loadCurrentState <= LIDLE; + else + loadCurrentState <= loadNextState; + end if; + end if; +end process loadMachineProc; + +loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty, + sub_bytes_loaded, sub_size_loaded, size_left, FC_H_READY_IN, max_frame_size, + bytes_loaded, divide_position) +begin + case loadCurrentState is + when LIDLE => + load_state <= x"0"; + if ((constructCurrentState = WAIT_FOR_LOAD) and (df_empty = '0')) then + loadNextState <= WAIT_FOR_FC; + else + loadNextState <= LIDLE; + end if; + when WAIT_FOR_FC => + load_state <= x"1"; + if (FC_H_READY_IN = '1') then + loadNextState <= PUT_Q_LEN; + else + loadNextState <= WAIT_FOR_FC; + end if; + when PUT_Q_LEN => + load_state <= x"2"; + if (all_int_ctr = 3) then + loadNextState <= PUT_Q_DEC; + else + loadNextState <= PUT_Q_LEN; + end if; + when PUT_Q_DEC => + load_state <= x"3"; + if (all_int_ctr = 3) then + loadNextState <= LOAD_SUB; + else + loadNextState <= PUT_Q_DEC; + end if; + when LOAD_SUB => + load_state <= x"4"; + if (bytes_loaded = max_frame_size - 1) then + loadNextState <= DIVIDE; + elsif (all_int_ctr = 15) then + loadNextState <= PREP_DATA; + else + loadNextState <= LOAD_SUB; + end if; + when PREP_DATA => + load_state <= x"5"; + loadNextState <= LOAD_DATA; + when LOAD_DATA => + load_state <= x"6"; + if (bytes_loaded = max_frame_size - 1) then + loadNextState <= DIVIDE; + elsif (sub_bytes_loaded = sub_size_loaded) then -- if all subevent bytes are loaded + if (size_left = x"00000021") then -- and there is no more data, only termination left + loadNextState <= LOAD_TERM; -- add termination and close packet + else -- there is more data in fifo + loadNextState <= LOAD_SUB; -- add another subevent + end if; + else + loadNextState <= LOAD_DATA; + end if; + when DIVIDE => + load_state <= x"7"; + if (FC_H_READY_IN = '1') then + if (divide_position = "00") then + loadNextState <= PREP_DATA; + elsif (divide_position = "01") then + loadNextState <= LOAD_SUB; + else + loadNextState <= LOAD_TERM; + end if; + else + loadNextState <= DIVIDE; + end if; + when LOAD_TERM => + load_state <= x"8"; + if (bytes_loaded = max_frame_size - 1) and (all_int_ctr /= 31) then + loadNextState <= DIVIDE; + elsif (all_int_ctr = 31) then + loadNextState <= CLEANUP; + else + loadNextState <= LOAD_TERM; + end if; + when CLEANUP => + load_state <= x"9"; + loadNextState <= LIDLE; + when others => + load_state <= x"f"; + loadNextState <= LIDLE; + end case; +end process loadMachine; + +dividePositionProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + divide_position <= "00"; + elsif (bytes_loaded = max_frame_size - 1) then + if (loadCurrentState = LIDLE) then + divide_position <= "00"; + elsif (loadCurrentState = LOAD_DATA) then + if (sub_bytes_loaded = sub_size_loaded) and (size_left = x"00000021") then + divide_position <= "11"; + elsif (sub_bytes_loaded = sub_size_loaded) and (size_left /= x"00000021") then + divide_position <= "01"; + else + divide_position <= "00"; + end if; + elsif (loadCurrentState = LOAD_SUB) then + if (all_int_ctr = 15) then + divide_position <= "00"; + else + divide_position <= "01"; + end if; + elsif (loadCurrentState = LOAD_TERM) then + divide_position <= "11"; + end if; + end if; + end if; +end process dividePositionProc; + +allIntCtrProc : process(CLK) +begin + if rising_edge(CLK) then + case loadCurrentState is + + when LIDLE => all_int_ctr <= 0; + + when WAIT_FOR_FC => all_int_ctr <= 0; + + when PUT_Q_LEN => + if (all_int_ctr = 3) then + all_int_ctr <= 0; + else + all_int_ctr <= all_int_ctr + 1; + end if; + + when PUT_Q_DEC => + if (all_int_ctr = 3) then + all_int_ctr <= 0; + else + all_int_ctr <= all_int_ctr + 1; + end if; + + when LOAD_SUB => + if (all_int_ctr = 15) then + all_int_ctr <= 0; + else + all_int_ctr <= all_int_ctr + 1; + end if; + + when LOAD_DATA => all_int_ctr <= 0; + + when LOAD_TERM => + if (all_int_ctr = 31) then + all_int_ctr <= 0; + else + all_int_ctr <= all_int_ctr + 1; + end if; + + when DIVIDE => null; --all_int_ctr <= all_int_ctr; + + when CLEANUP => all_int_ctr <= 0; + + when PREP_DATA => all_int_ctr <= 0; + end case; + end if; +end process allIntCtrProc; + +dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded, + sub_size_loaded, all_int_ctr) +begin + if (loadCurrentState = LOAD_DATA) then +-- if (bytes_loaded >= max_frame_size - x"1") then +-- df_rd_en <= '0'; +-- elsif (sub_bytes_loaded >= sub_size_loaded) then +-- df_rd_en <= '0'; + if (bytes_loaded = max_frame_size - x"1") then + df_rd_en <= '0'; + elsif (sub_bytes_loaded = sub_size_loaded) then + df_rd_en <= '0'; + else + df_rd_en <= '1'; + end if; + elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 15) and (bytes_loaded /= max_frame_size - x"1") then + df_rd_en <= '1'; + elsif (loadCurrentState = PREP_DATA) then + df_rd_en <= '1'; + else + df_rd_en <= '0'; + end if; +end process dfRdEnProc; + +shfRdEnProc : process(loadCurrentState, all_int_ctr) +begin + if (loadCurrentState = LOAD_SUB) then + shf_rd_en <= '1'; + elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then + shf_rd_en <= '1'; + elsif (loadCurrentState = PUT_Q_DEC) and (all_int_ctr = 3) then + shf_rd_en <= '1'; + else + shf_rd_en <= '0'; + end if; +end process shfRdEnProc; + + +fcWrEnProc : process(loadCurrentState) +begin + if (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then + fc_wr_en <= '1'; + elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then + fc_wr_en <= '1'; + else + fc_wr_en <= '0'; + end if; +end process fcWrEnProc; + +-- was all_int_ctr +fcDataProc : process(loadCurrentState, queue_size_temp, PC_QUEUE_DEC_IN, shf_q, df_q_reg, load_int_ctr) +begin + case loadCurrentState is + when LIDLE => fc_data <= x"af"; + when WAIT_FOR_FC => fc_data <= x"bf"; + -- gk 08.04.10 my_int_ctr changed to load_int_ctr + when PUT_Q_LEN => fc_data <= queue_size_temp(load_int_ctr * 8 + 7 downto load_int_ctr * 8); + when PUT_Q_DEC => fc_data <= PC_QUEUE_DEC_IN(load_int_ctr * 8 + 7 downto load_int_ctr * 8); + when LOAD_SUB => fc_data <= shf_q; + when PREP_DATA => fc_data <= df_q_reg; + when LOAD_DATA => fc_data <= df_q_reg; + when LOAD_TERM => fc_data <= shf_q; + when DIVIDE => fc_data <= x"cf"; + when CLEANUP => fc_data <= x"df"; + when others => fc_data <= x"00"; + end case; +end process fcDataProc; + + +--*********************** +-- SIZE COUNTERS FOR LOADING SIDE +--*********************** + +queue_size_temp <= queue_size - x"20"; -- size of data without termination + +-- gk 08.04.10 +rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or + ((loadCurrentState = LOAD_DATA) and (sub_bytes_loaded = sub_size_loaded) and (size_left /= x"00000021")) + else '0'; + +-- gk 08.04.10 +RST_AFTER_SUB_PROC : process(CLK) +begin + if(rising_edge(CLK)) then + if(RESET = '1') then + rst_after_sub <= '0'; + else + rst_after_sub <= rst_after_sub_comb; + end if; + end if; +end process RST_AFTER_SUB_PROC; + +-- counts all bytes loaded to divide data into frames +bytesLoadedProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = DIVIDE) or (loadCurrentState = CLEANUP) then + bytes_loaded <= x"0000"; + elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then + bytes_loaded <= bytes_loaded + x"1"; + end if; + end if; +end process bytesLoadedProc; + +-- size of subevent loaded from memory +subSizeLoadedProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10 + sub_size_loaded <= x"00000000"; + elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr < 4) then + -- was all_int_ctr + -- gk 08.04.10 my_int_ctr changed to load_int_ctr + sub_size_loaded(7 + load_int_ctr * 8 downto load_int_ctr * 8) <= shf_q; + -- gk 29.03.10 here the padding bytes have to be added to the loadedSize in order to load the correct amount of bytes from fifo + elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 5) and (sub_size_loaded(2) = '1') then + sub_size_loaded <= sub_size_loaded + x"4"; + end if; + end if; +end process subSizeLoadedProc; + +-- counts only raw data bytes being loaded +subBytesLoadedProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (loadCurrentState = LIDLE) or (sub_bytes_loaded = sub_size_loaded) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10 + sub_bytes_loaded <= x"00000011"; -- subevent headers doesnt count + elsif (loadCurrentState = LOAD_DATA) then + sub_bytes_loaded <= sub_bytes_loaded + x"1"; + end if; + end if; +end process subBytesLoadedProc; + +-- counts the size of the large udp packet +actualPacketProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then + actual_packet_size <= x"0008"; + elsif (fc_wr_en = '1') then + actual_packet_size <= actual_packet_size + x"1"; + end if; + end if; +end process actualPacketProc; + +actualQueueSizeProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (loadCurrentState = CLEANUP) then + actual_queue_size <= (others => '0'); + elsif (loadCurrentState = LIDLE) then + actual_queue_size <= queue_size; + end if; + end if; +end process actualQueueSizeProc; + +-- amount of bytes left to send in current packet +sizeLeftProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (loadCurrentState = CLEANUP) then + size_left <= (others => '0'); + elsif (loadCurrentState = LIDLE) then + size_left <= queue_size; + elsif (fc_wr_en = '1') then + size_left <= size_left - 1; + end if; + end if; +end process sizeLeftProc; + +-- HOT FIX: don't rely on CTS information, count the packets on your own. +-- In this case, we increment the fragmented packet ID with EOD from ipu2gbe. +THE_FC_IDENT_COUNTER_PROC: process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + fc_ident <= (others => '0'); + elsif (PC_END_OF_DATA_IN = '1') then + fc_ident <= fc_ident + 1; + end if; + end if; +end process THE_FC_IDENT_COUNTER_PROC; + +fc_flags_offset(15 downto 14) <= "00"; + +moreFragmentsProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then + fc_flags_offset(13) <= '0'; + elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1')) then + if ((actual_queue_size - actual_packet_size) < max_frame_size) then + fc_flags_offset(13) <= '0'; -- no more fragments + else + fc_flags_offset(13) <= '1'; -- more fragments + end if; + end if; + end if; +end process moreFragmentsProc; + +eodProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + fc_eod <= '0'; + elsif (loadCurrentState = LOAD_DATA) and (bytes_loaded = max_frame_size - 2) then + fc_eod <= '1'; + elsif (loadCurrentState = LOAD_SUB) and (bytes_loaded = max_frame_size - 2) then + fc_eod <= '1'; + elsif (loadCurrentState = LOAD_TERM) and ((bytes_loaded = max_frame_size - 2) or (all_int_ctr = 30)) then + fc_eod <= '1'; + else + fc_eod <= '0'; + end if; + end if; +end process eodProc; + +sodProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + fc_sod <= '0'; + elsif (loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1') then + fc_sod <= '1'; + elsif (loadCurrentState = DIVIDE) and (FC_READY_IN = '1') then + fc_sod <= '1'; + else + fc_sod <= '0'; + end if; + end if; +end process sodProc; + +offsetProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then + fc_flags_offset(12 downto 0) <= (others => '0'); + elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) then + fc_flags_offset(12 downto 0) <= actual_packet_size(15 downto 3); + end if; + end if; +end process offsetProc; + +fcIPSizeProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET= '1') then + fc_ip_size <= (others => '0'); + elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1')) then + if (size_left >= max_frame_size) then + fc_ip_size <= max_frame_size; + else + fc_ip_size <= size_left(15 downto 0); + end if; + end if; + end if; +end process fcIPSizeProc; + +fcUDPSizeProc : process(CLK) + begin + if rising_edge(CLK) then + if (RESET = '1') then + fc_udp_size <= (others => '0'); + elsif (loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1') then + fc_udp_size <= queue_size(15 downto 0); + end if; + end if; +end process fcUDPSizeProc; + + +-- outputs +PC_READY_OUT <= pc_ready; +FC_WR_EN_OUT <= fc_wr_en; +FC_DATA_OUT <= fc_data; +FC_IP_SIZE_OUT <= fc_ip_size; +FC_UDP_SIZE_OUT <= fc_udp_size; +FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0); +FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8); +FC_FLAGS_OFFSET_OUT <= fc_flags_offset; +FC_SOD_OUT <= fc_sod; +FC_EOD_OUT <= fc_eod; +BSM_CONSTR_OUT <= constr_state; +BSM_LOAD_OUT <= load_state; +BSM_SAVE_OUT <= save_state; +DBG_SHF_EMPTY <= shf_empty; +DBG_SHF_FULL <= shf_full; +DBG_SHF_WR_EN <= shf_wr_en; +DBG_SHF_RD_EN <= shf_rd_en; +DBG_SHF_Q <= shf_q; +DBG_DF_EMPTY <= df_empty; +DBG_DF_FULL <= df_full; +DBG_DF_WR_EN <= df_wr_en; +DBG_DF_RD_EN <= df_rd_en; +DBG_DF_Q <= df_q; +DBG_ALL_CTR <= all_ctr; +DBG_SUB_CTR <= sub_ctr; +DBG_MY_CTR <= my_ctr; +DBG_BYTES_LOADED <= bytes_loaded; +DBG_SIZE_LEFT <= size_left; +DBG_SUB_SIZE_TO_SAVE <= sub_size_to_save; +DBG_SUB_SIZE_LOADED <= sub_size_loaded; +DBG_SUB_BYTES_LOADED <= sub_bytes_loaded; +DBG_QUEUE_SIZE <= queue_size; +DBG_ACT_QUEUE_SIZE <= actual_queue_size; + +DEBUG_OUT <= debug; + +end trb_net16_gbe_packet_constr; \ No newline at end of file diff --git a/gbe_ecp2m/trb_net16_ipu2gbe.vhd b/gbe_ecp2m/trb_net16_ipu2gbe.vhd new file mode 100755 index 0000000..0507ccc --- /dev/null +++ b/gbe_ecp2m/trb_net16_ipu2gbe.vhd @@ -0,0 +1,898 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +use IEEE.std_logic_arith.all; + +library work; + +entity trb_net16_ipu2gbe is +port( + CLK : in std_logic; + RESET : in std_logic; + -- IPU interface directed toward the CTS + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_READ_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data from Frontends + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_BUSY_IN : in std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + -- slow control interface + START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size + BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address + CONFIG_DONE_IN : in std_logic; -- configuration finished + DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE + DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet + MULTI_EVT_ENABLE_IN : in std_logic; -- enable multi event packets + MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 + -- PacketConstructor interface + PC_WR_EN_OUT : out std_logic; + PC_DATA_OUT : out std_logic_vector (7 downto 0); + PC_READY_IN : in std_logic; + PC_SOS_OUT : out std_logic; + PC_EOD_OUT : out std_logic; + PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); + PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); + PC_PADDING_OUT : out std_logic; + -- Debug + BSM_SAVE_OUT : out std_logic_vector(3 downto 0); + BSM_LOAD_OUT : out std_logic_vector(3 downto 0); + DBG_REM_CTR_OUT : out std_logic_vector(3 downto 0); + DBG_CTS_CTR_OUT : out std_logic_vector(2 downto 0); + DBG_SF_WCNT_OUT : out std_logic_vector(15 downto 0); + DBG_SF_RCNT_OUT : out std_logic_vector(16 downto 0); + DBG_SF_DATA_OUT : out std_logic_vector(15 downto 0); + DBG_SF_RD_EN_OUT : out std_logic; + DBG_SF_WR_EN_OUT : out std_logic; + DBG_SF_EMPTY_OUT : out std_logic; + DBG_SF_AEMPTY_OUT : out std_logic; + DBG_SF_FULL_OUT : out std_logic; + DBG_SF_AFULL_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end entity; + +architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is + +component fifo_32kx16x8_mb +port( + Data : in std_logic_vector(15 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + AmEmptyThresh : in std_logic_vector(15 downto 0); + AmFullThresh : in std_logic_vector(14 downto 0); + Q : out std_logic_vector(7 downto 0); + WCNT : out std_logic_vector(15 downto 0); + RCNT : out std_logic_vector(16 downto 0); + Empty : out std_logic; + AlmostEmpty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic +); +end component; + +type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE); +signal saveCurrentState, saveNextState : saveStates; +signal state : std_logic_vector(3 downto 0); +signal data_req_comb : std_logic; +signal data_req : std_logic; -- request data signal, will be used for fee_read generation +signal rst_saved_ctr_comb : std_logic; +signal rst_saved_ctr : std_logic; + +signal fee_read_comb : std_logic; +signal fee_read : std_logic; -- fee_read signal +signal saved_ctr : std_logic_vector(16 downto 0); +signal ce_saved_ctr : std_logic; + +-- header data +signal cts_rnd : std_logic_vector(15 downto 0); +signal cts_rnd_saved : std_logic; +signal cts_trg : std_logic_vector(15 downto 0); +signal cts_trg_saved : std_logic; +signal cts_len : std_logic_vector(16 downto 0); +signal cts_len_saved : std_logic; + +-- CTS interface +signal cts_error_pattern : std_logic_vector(31 downto 0); +signal cts_length : std_logic_vector(15 downto 0); +signal cts_readout_finished : std_logic; +signal cts_dataready : std_logic; +signal cts_data : std_logic_vector(31 downto 0); + +-- Split FIFO signals +signal sf_data : std_logic_vector(15 downto 0); +signal sf_wr_en_comb : std_logic; +signal sf_wr_en : std_logic; -- write signal for FIFO +signal sf_rd_en_comb : std_logic; +signal sf_rd_en : std_logic; -- read signal for FIFO +signal sf_rd_valid_comb : std_logic; +signal sf_rd_valid : std_logic; +signal sf_wcnt : std_logic_vector(15 downto 0); +signal sf_rcnt : std_logic_vector(16 downto 0); +signal sf_empty : std_logic; +signal sf_aempty : std_logic; +signal sf_full : std_logic; +signal sf_afull : std_logic; + +------------------------------------------------------------------- +type loadStates is (LIDLE, INIT, REMOVE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC); +signal loadCurrentState, loadNextState : loadStates; +signal state2 : std_logic_vector(3 downto 0); + +signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data +signal rst_rem_ctr_comb : std_logic; +signal rst_rem_ctr : std_logic; -- reset the remove counter +signal rst_regs_comb : std_logic; +signal rst_regs : std_logic; -- reset storage registers +signal rem_phase_comb : std_logic; +signal rem_phase : std_logic; -- header remove phase +signal data_phase_comb : std_logic; +signal data_phase : std_logic; -- data transport phase from split fifo to PC +signal pad_phase_comb : std_logic; +signal pad_phase : std_logic; -- padding phase +signal calc_pad_comb : std_logic; +signal calc_pad : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE +signal pad_data_comb : std_logic; +signal pad_data : std_logic; -- reset PC_DATA register to known padding byte value + +signal pc_sos_comb : std_logic; +signal pc_sos : std_logic; -- start of data signal +signal pc_eod_comb : std_logic; +signal pc_eod : std_logic; -- end of data signal + +signal ce_rem_ctr_comb : std_logic; +signal ce_rem_ctr : std_logic; -- count enable for remove counter +signal remove_done_comb : std_logic; +signal remove_done : std_logic; -- end of header stripping process +signal read_done_comb : std_logic; +signal read_done : std_logic; -- end of data phase (read phase from SF) + +signal pc_data : std_logic_vector(7 downto 0); +signal pc_data_q : std_logic_vector(7 downto 0); +signal pc_trig_nr : std_logic_vector(15 downto 0); +signal pc_sub_size : std_logic_vector(17 downto 0); +signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo +signal padding_needed : std_logic; +signal pc_wr_en_comb : std_logic; +signal pc_wr_en_q : std_logic; +signal pc_wr_en_qq : std_logic; +signal pc_wr_en_qqq : std_logic; +signal pc_eod_q : std_logic; +signal pc_eod_qq : std_logic; + +signal debug : std_logic_vector(31 downto 0); + +-- gk +signal bank_select : std_logic_vector(3 downto 0); +signal save_addr_comb : std_logic; +signal save_addr : std_logic; +signal addr_saved_comb : std_logic; +signal addr_saved : std_logic; +signal start_config : std_logic; +signal config_done : std_logic; +signal add_sub_state : std_logic; +signal add_sub_state_comb : std_logic; +signal add_sub_ctr : std_logic_vector(3 downto 0); +signal load_sub : std_logic; +signal load_sub_comb : std_logic; +signal load_sub_done : std_logic; +signal load_sub_done_comb : std_logic; +signal load_sub_ctr : std_logic_vector(3 downto 0); +signal load_sub_ctr_comb : std_logic; +signal actual_message_size : std_logic_vector(31 downto 0); +signal rst_msg : std_logic; +signal rst_msg_comb : std_logic; + +begin + +-- Fake signals +--START_CONFIG_OUT <= '0'; -- gk 27.03.10 +BANK_SELECT_OUT <= bank_select; -- gk 27.03.10 +START_CONFIG_OUT <= start_config; -- gk 27.03.10 +config_done <= CONFIG_DONE_IN; -- gk 29.03.10 +-- gk 27.03.10 +bank_select_proc : process( CLK ) +begin + if rising_edge( CLK ) then + -- gk 29.03.10 for debug only: should round robin over 4 addresses with each subevent +-- if( (RESET = '1') or (bank_select > "0011") ) then +-- bank_select <= "0000"; +-- elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then +-- bank_select <= bank_select + x"1"; +-- end if; + -- gk 29.03.10 + if( (RESET = '1') or (rst_regs = '1') ) then + bank_select <= "0000"; + elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then + bank_select <= CTS_INFORMATION_IN(3 downto 0); + end if; + end if; +end process bank_select_proc; + +-- gk 29.03.10 +start_config_proc : process( CLK ) +begin + if rising_edge( CLK ) then + if( (RESET = '1') or (rst_regs = '1') or (config_done = '1') ) then + start_config <= '0'; + elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then + start_config <= '1'; + end if; + end if; +end process start_config_proc; + +-- CTS interface signals +cts_error_pattern <= (others => '0'); -- FAKE + +cts_length <= x"0000"; -- length of data payload is always 0 +cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1' + +cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0'; + +cts_dataready <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE) + else '0'; + +-- Byte swapping... done here. TAKE CARE! +-- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes +-- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port. +-- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped +-- for GbE inside the packet constructor. +-- +-- Long live the Endianess! + +-- Sync all critical pathes +THE_SYNC_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to a process + sf_wr_en <= sf_wr_en_comb; + ce_rem_ctr <= ce_rem_ctr_comb; + sf_rd_en <= sf_rd_en_comb; + fee_read <= fee_read_comb; + read_done <= read_done_comb; + pc_eod_qq <= pc_eod_q; + pc_eod_q <= pc_eod; + pc_wr_en_qqq <= pc_wr_en_qq; + pc_wr_en_qq <= pc_wr_en_q; + pc_wr_en_q <= pc_wr_en_comb; + end if; +end process THE_SYNC_PROC; + +-- gk 27.03.10 data selector for sf to write the evt builder address on top of data +SF_DATA_PROC : process( CLK ) +begin + if( rising_edge(CLK) ) then + if( save_addr = '1' ) then + sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address + sf_data(15 downto 4) <= x"abc"; + -- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent + elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then + sf_data <= x"5555"; + elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then + sf_data <= x"0001"; + elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then + sf_data <= FEE_STATUS_BITS_IN(31 downto 16); + elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then + sf_data <= FEE_STATUS_BITS_IN(15 downto 0); + else + sf_data <= FEE_DATA_IN; + end if; + end if; +end process SF_DATA_PROC; + +-- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY +fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled + else '0'; + +-- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY +-- gk 27.03.10 +--sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled +-- else '0'; +sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled + (save_addr = '1') or + (add_sub_state = '1') -- gk 29.03.10 save the subsubevent + else '0'; + +-- Counter for header word storage +THE_CTS_SAVED_CTR: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_saved_ctr = '1') ) then + saved_ctr <= (others => '0'); + elsif( ce_saved_ctr = '1' ) then + saved_ctr <= saved_ctr + 1; + end if; + end if; +end process THE_CTS_SAVED_CTR; + +-- gk 27.03.10 do not count evt builder address as saved ipu bytes +--ce_saved_ctr <= sf_wr_en; +ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en; + +-- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO +saveMachineProc: process( CLK ) +begin + if rising_edge(CLK) then + if RESET = '1' then + saveCurrentState <= SIDLE; + data_req <= '0'; + rst_saved_ctr <= '0'; + save_addr <= '0'; -- gk 27.03.10 + addr_saved <= '0'; -- gk 27.03.10 + add_sub_state <= '0'; -- gk 29.03.10 + else + saveCurrentState <= saveNextState; + data_req <= data_req_comb; + rst_saved_ctr <= rst_saved_ctr_comb; + save_addr <= save_addr_comb; -- gk 27.03.10 + addr_saved <= addr_saved_comb; -- gk 27.03.10 + add_sub_state <= add_sub_state_comb; -- gk 29.03.10 + end if; + end if; +end process saveMachineProc; + +saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN ) +begin + saveNextState <= SIDLE; + data_req_comb <= '0'; + rst_saved_ctr_comb <= '0'; + save_addr_comb <= '0'; -- gk 27.03.10 + addr_saved_comb <= '0'; -- gk 27.03.10 + add_sub_state_comb <= '0'; -- gk 29.03.10 + case saveCurrentState is + when SIDLE => + state <= x"0"; + if (CTS_START_READOUT_IN = '1') then + saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10 + data_req_comb <= '1'; + rst_saved_ctr_comb <= '1'; + else + saveNextState <= SIDLE; + end if; + -- gk 27.03.10 + when SAVE_EVT_ADDR => + state <= x"5"; + saveNextState <= WAIT_FOR_DATA; + data_req_comb <= '1'; + save_addr_comb <= '1'; + when WAIT_FOR_DATA => + state <= x"1"; + if (FEE_BUSY_IN = '1') then + saveNextState <= SAVE_DATA; + data_req_comb <= '1'; + else + saveNextState <= WAIT_FOR_DATA; + data_req_comb <= '1'; + end if; + addr_saved_comb <= '1'; -- gk 27.03.10 + when SAVE_DATA => + state <= x"2"; + if (FEE_BUSY_IN = '0') then + saveNextState <= TERMINATE; + else + saveNextState <= SAVE_DATA; + data_req_comb <= '1'; + end if; + when TERMINATE => + state <= x"3"; + if (CTS_READ_IN = '1') then + saveNextState <= SCLOSE; + else + saveNextState <= TERMINATE; + end if; + when SCLOSE => + state <= x"4"; + if (CTS_START_READOUT_IN = '0') then + saveNextState <= ADD_SUBSUB1; --SIDLE; -- gk 29.03.10 + else + saveNextState <= SCLOSE; + end if; + -- gk 29.03.10 new states during which the subsub bytes are saved + when ADD_SUBSUB1 => + state <= x"6"; + add_sub_state_comb <= '1'; + saveNextState <= ADD_SUBSUB2; + when ADD_SUBSUB2 => + state<= x"7"; + add_sub_state_comb <= '1'; + saveNextState <= ADD_SUBSUB3; + when ADD_SUBSUB3 => + state<= x"8"; + add_sub_state_comb <= '1'; + saveNextState <= ADD_SUBSUB4; + when ADD_SUBSUB4 => + state<= x"9"; + add_sub_state_comb <= '1'; + saveNextState <= SIDLE; + when others => + state <= x"f"; + saveNextState <= SIDLE; + end case; +end process saveMachine; + +-- gk 29.03.10 +ADD_SUB_CTR_PROC : process( CLK ) +begin + if( rising_edge( CLK ) ) then + if( (RESET = '1') or (rst_saved_ctr = '1') ) then + add_sub_ctr <= (others => '0'); + elsif( add_sub_state = '1' ) then + add_sub_ctr <= add_sub_ctr + 1; + end if; + end if; +end process ADD_SUB_CTR_PROC; + +-- save triggerRnd from incoming data for cts response +CTS_RND_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_saved_ctr = '1') ) then + cts_rnd <= (others => '0'); + cts_rnd_saved <= '0'; + elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then + cts_rnd <= sf_data; + cts_rnd_saved <= '1'; + end if; + end if; +end process CTS_RND_PROC; + +-- save triggerNr from incoming data for cts response +CTS_TRG_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_saved_ctr = '1') ) then + cts_trg <= (others => '0'); + cts_trg_saved <= '0'; + elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then + cts_trg <= sf_data; + cts_trg_saved <= '1'; + end if; + end if; +end process CTS_TRG_PROC; + +-- save size from incoming data for cts response (future) and to get rid of padding +CTS_SIZE_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_saved_ctr = '1') ) then + cts_len <= (others => '0'); + cts_len_saved <= '0'; + elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then + cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words + cts_len(0) <= '0'; + elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then + cts_len <= cts_len + x"4"; + cts_len_saved <= '1'; + end if; + end if; +end process CTS_SIZE_PROC; + +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + +-- Split FIFO +THE_SPLIT_FIFO: fifo_32kx16x8_mb +port map( + -- Byte swapping for correct byte order on readout side of FIFO + Data(15 downto 8) => sf_data(7 downto 0), + Data(7 downto 0) => sf_data(15 downto 8), + WrClock => CLK, + RdClock => CLK, + WrEn => sf_wr_en, + RdEn => sf_rd_en, + Reset => RESET, + RPReset => RESET, + AmEmptyThresh => b"0000_0000_0000_0010", -- one byte ahead + AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751 + Q => pc_data, --open, + WCNT => sf_wcnt, + RCNT => sf_rcnt, + Empty => sf_empty, + AlmostEmpty => sf_aempty, + Full => sf_full, + AlmostFull => sf_afull +); + +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + +-- write signal for PC data +pc_wr_en_comb <= (data_phase and sf_rd_en) or pad_phase or (load_sub and sf_rd_en); -- gk 30.03.10 + +-- FIFO data delay process (also forces padding bytes to known value) +THE_DATA_DELAY_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if( pad_data = '1' ) then + pc_data_q <= x"aa"; -- padding for 64bit + else + pc_data_q <= pc_data; + end if; + end if; +end process THE_DATA_DELAY_PROC; + +-- Statemachine for reading the data payload from the SPLIT_FIFO and feeding +-- it into the packet constructor +loadMachineProc : process(CLK) +begin + if rising_edge(CLK) then + if RESET = '1' then + loadCurrentState <= LIDLE; + rst_rem_ctr <= '0'; + rem_phase <= '0'; + calc_pad <= '0'; + data_phase <= '0'; + pad_phase <= '0'; + pc_sos <= '0'; + pc_eod <= '0'; + rst_regs <= '0'; + pad_data <= '0'; + load_sub <= '0'; -- gk 30.03.10 + rst_msg <= '0'; -- gk 08.04.10 + else + loadCurrentState <= loadNextState; + rst_rem_ctr <= rst_rem_ctr_comb; + rem_phase <= rem_phase_comb; + calc_pad <= calc_pad_comb; + data_phase <= data_phase_comb; + pad_phase <= pad_phase_comb; + pc_sos <= pc_sos_comb; + pc_eod <= pc_eod_comb; + rst_regs <= rst_regs_comb; + pad_data <= pad_data_comb; + load_sub <= load_sub_comb; -- gk 30.03.10 + rst_msg <= rst_msg_comb; -- gk 08.04.10 + end if; + end if; +end process loadMachineProc; + +sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and (remove_done = '0') ) or + ( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0') ) or + ( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) -- gk 30.03.10 + else '0'; + +ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') ) + else '0'; + +loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, PC_READY_IN, load_sub_done ) +begin + loadNextState <= LIDLE; + rst_rem_ctr_comb <= '0'; + rem_phase_comb <= '0'; + calc_pad_comb <= '0'; + data_phase_comb <= '0'; + pad_phase_comb <= '0'; + pc_sos_comb <= '0'; + pc_eod_comb <= '0'; + rst_regs_comb <= '0'; + pad_data_comb <= '0'; + load_sub_comb <= '0'; -- gk 30.03.10 + rst_msg_comb <= '0'; -- gk 08.04.10 + case loadCurrentState is + when LIDLE => + state2 <= x"0"; + if( (sf_aempty = '0') and (PC_READY_IN = '1') ) then + loadNextState <= INIT; + rst_rem_ctr_comb <= '1'; + rst_regs_comb <= '1'; + rst_msg_comb <= '1'; -- gk 08.04.10 + else + loadNextState <= LIDLE; + end if; + when INIT => + state2 <= x"1"; + loadNextState <= REMOVE; + rem_phase_comb <= '1'; + -- gk 08.04.10 changed to gather more subevents into one queue + when REMOVE => + state2 <= x"2"; + if( remove_done = '1' ) then + if(actual_message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then + loadNextState <= CALCA; + calc_pad_comb <= '1'; + else + loadNextState <= CALCC; + end if; + else + loadNextState <= REMOVE; + rem_phase_comb <= '1'; + end if; + when CALCA => + state2 <= x"3"; + loadNextState <= CALCB; + pc_sos_comb <= '1'; + when CALCB => + -- we need a branch in case of length "0"!!!! + state2 <= x"4"; + loadNextState <= LOAD; + data_phase_comb <= '1'; + when LOAD => + state2 <= x"5"; + -- gk 31.03.10 after loading subevent data read the subsubevent from sf + if ( read_done = '1' ) then + loadNextState <= LOAD_SUBSUB; + -- gk 31.03.10 moved to the load_subsub state +-- if ( (read_done = '1') and (padding_needed = '0') ) then +-- loadNextState <= LOAD_SUBSUB; --CALCC; --gk 30.03.10 +-- elsif( (read_done = '1') and (padding_needed = '1') ) then +-- loadNextState <= PAD0; +-- pad_phase_comb <= '1'; + else + loadNextState <= LOAD; + data_phase_comb <= '1'; + end if; + -- gk 31.03.10 + when LOAD_SUBSUB => + state2 <= x"d"; + if( load_sub_done = '1' ) then + if( padding_needed = '0' ) then + loadNextState <= INIT; --CALCC; -- gk 08.04.10 + rst_rem_ctr_comb <= '1'; -- gk 08.04.10 + rst_regs_comb <= '1'; -- gk 08.04.10 + else + loadNextState <= PAD0; + pad_phase_comb <= '1'; + end if; + else + loadNextState <= LOAD_SUBSUB; + load_sub_comb <= '1'; + end if; + when PAD0 => + state2 <= x"6"; + loadNextState <= PAD1; + pad_phase_comb <= '1'; + pad_data_comb <= '1'; + when PAD1 => + state2 <= x"7"; + loadNextState <= PAD2; + pad_phase_comb <= '1'; + pad_data_comb <= '1'; + when PAD2 => + state2 <= x"8"; + loadNextState <= PAD3; + pad_phase_comb <= '1'; + pad_data_comb <= '1'; + when PAD3 => + state2 <= x"9"; + loadNextState <= INIT; --CALCC; --LOAD_SUBSUB; --CALCC; -- gk 30.03.10 -- gk 31.03.10 -- gk 08.04.10 + pad_data_comb <= '1'; + rst_rem_ctr_comb <= '1'; -- gk 08.04.10 + rst_regs_comb <= '1'; -- gk 08.04.10 + -- gk 31.03.10 the load_subsub state moved straight after load and before padding + -- gk 30.03.10 +-- when LOAD_SUBSUB => +-- state2 <= x"d"; +-- if( load_sub_done = '1' ) then +-- loadNextState <= CALCC; +-- else +-- loadNextState <= LOAD_SUBSUB; +-- load_sub_comb <= '1'; +-- end if; + when CALCC => + state2 <= x"a"; + loadNextState <= CLOSE; + pc_eod_comb <= '1'; + when CLOSE => + state2 <= x"b"; + loadNextState <= WAIT_PC; + --rst_regs_comb <= '1'; -- gk 08.04.10 + rst_msg_comb <= '1'; -- gk 08.04.10 + when WAIT_PC => + state2 <= x"c"; + if( PC_READY_IN = '1' ) then + loadNextState <= CALCA; --LIDLE; -- gk 08.04.10 + calc_pad_comb <= '1'; -- gk 08.04.10 + else + loadNextState <= WAIT_PC; + end if; + when others => + state2 <= x"f"; + loadNextState <= LIDLE; + end case; +end process loadMachine; + +-- gk 30.03.10 +load_sub_ctr_comb <= '1' when ( (load_sub = '1') and (load_sub_done = '0') and (sf_aempty = '0') ) + else '0'; + +-- gk 30.03.10 +LOAD_SUB_CTR_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10 + load_sub_ctr <= (others => '0'); + elsif( (load_sub_ctr_comb = '1') ) then + load_sub_ctr <= load_sub_ctr + 1; + end if; + end if; +end process LOAD_SUB_CTR_PROC; + +-- gk 30.03.10 +load_sub_done_comb <= '1' when (load_sub_ctr = x"7") else '0'; + +-- gk 30.03.10 +LOAD_SUB_DONE_PROC : process(CLK) +begin + if rising_edge(CLK) then + if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10 + load_sub_done <= '0'; + else + load_sub_done <= load_sub_done_comb; + end if; + end if; +end process LOAD_SUB_DONE_PROC; + +-- Counter for stripping the unneeded parts of the data stream, and saving the important parts +THE_REMOVE_CTR: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_rem_ctr = '1') ) then + rem_ctr <= (others => '0'); + elsif( (ce_rem_ctr = '1') ) then + rem_ctr <= rem_ctr + 1; + end if; + end if; +end process THE_REMOVE_CTR; + +remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt address + +THE_REM_DONE_SYNC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_rem_ctr = '1') ) then + remove_done <= '0'; + else + remove_done <= remove_done_comb; + end if; + end if; +end process THE_REM_DONE_SYNC; + +-- extract the trigger number from splitfifo data +THE_TRG_NR_PROC: process( CLK ) +begin + if rising_edge(CLK) then + if ( (RESET = '1') or (rst_regs = '1') ) then + pc_trig_nr <= (others => '0'); + elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then -- x"4" gk 29.03.10 + pc_trig_nr(7 downto 0) <= pc_data; + elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then -- x"3" gk 29.03.10 + pc_trig_nr(15 downto 8) <= pc_data; + end if; + end if; +end process THE_TRG_NR_PROC; + +-- check for padding +THE_PADDING_NEEDED_PROC: process( CLK ) +begin + if rising_edge(CLK) then + if ( (RESET = '1') or (rst_regs = '1') ) then + padding_needed <= '0'; + elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then + padding_needed <= '1'; + elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then + padding_needed <= '0'; + end if; + end if; +end process THE_PADDING_NEEDED_PROC; + +-- extract the subevent size from the splitfifo data, convert it from 32b to 8b units, +-- and in case of padding needed increase it accordingly +THE_SUB_SIZE_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_regs = '1') ) then + pc_sub_size <= (others => '0'); + elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10 + pc_sub_size(9 downto 2) <= pc_data; + elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10 + pc_sub_size(17 downto 10) <= pc_data; + -- gk 30.03.10 bug fixed in the way that is written below + -- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save + elsif( (calc_pad = '1') and (padding_needed = '1') ) then + pc_sub_size <= pc_sub_size + 4 + 8; -- BUG: SubEvtSize does NOT include 64bit padding!!! + elsif( (calc_pad = '1') and (padding_needed = '0') ) then + pc_sub_size <= pc_sub_size + 8; + end if; + end if; +end process THE_SUB_SIZE_PROC; + +-- number of bytes to read from split fifo +THE_READ_SIZE_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_rem_ctr = '1') ) then + read_size <= (others => '0'); + elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10 + read_size(9 downto 2) <= pc_data; + elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10 + read_size(17 downto 10) <= pc_data; +-- elsif( ((calc_pad = '1') and (read_done = '0')) ) then +-- read_size <= read_size - 2; + elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then + read_size <= read_size - 1; + end if; + end if; +end process THE_READ_SIZE_PROC; + +ACTUAL_MSG_SIZE_PROC : process(CLK) +begin + if(rising_edge(CLK)) then + if( (RESET = '1') or (rst_msg = '1') ) then + actual_message_size <= (others => '0'); + elsif( (calc_pad = '1') and (padding_needed = '1') ) then + actual_message_size <= actual_message_size + pc_sub_size + 4 + 8; + elsif( (calc_pad = '1') and (padding_needed = '0') ) then + actual_message_size <= actual_message_size + pc_sub_size + 8; + end if; + end if; +end process ACTUAL_MSG_SIZE_PROC; + +read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2" + +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + +-- Debug signals +debug(31) <= remove_done; +debug(30) <= read_done; +debug(29) <= ce_rem_ctr; +debug(28) <= rst_rem_ctr; +debug(27) <= rst_regs; +debug(26) <= rem_phase; +debug(25) <= data_phase; +debug(24) <= pad_phase; +debug(23) <= pad_data; +debug(22 downto 17) <= (others => '0'); +debug(16 downto 0) <= saved_ctr; + +-- Outputs +FEE_READ_OUT <= fee_read; +CTS_ERROR_PATTERN_OUT <= cts_error_pattern; +CTS_DATA_OUT <= cts_data; +CTS_DATAREADY_OUT <= cts_dataready; +CTS_READOUT_FINISHED_OUT <= cts_readout_finished; +CTS_LENGTH_OUT <= cts_length; + +PC_SOS_OUT <= pc_sos; +PC_EOD_OUT <= pc_eod_q; +PC_DATA_OUT <= pc_data_q; +PC_WR_EN_OUT <= pc_wr_en_qq; +PC_TRIG_NR_OUT <= x"0000" & pc_trig_nr; +PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size; +PC_PADDING_OUT <= padding_needed; + +BSM_SAVE_OUT <= state; +BSM_LOAD_OUT <= state2; +DBG_CTS_CTR_OUT <= saved_ctr(2 downto 0); +DBG_REM_CTR_OUT <= rem_ctr; +DBG_SF_DATA_OUT <= sf_data; +DBG_SF_WCNT_OUT <= sf_wcnt; +DBG_SF_RCNT_OUT <= read_size(16 downto 0); --sf_rcnt; +DBG_SF_RD_EN_OUT <= sf_rd_en; +DBG_SF_WR_EN_OUT <= sf_wr_en; +DBG_SF_EMPTY_OUT <= sf_empty; +DBG_SF_AEMPTY_OUT <= sf_aempty; +DBG_SF_FULL_OUT <= sf_full; +DBG_SF_AFULL_OUT <= sf_afull; + +DEBUG_OUT <= debug; + +end architecture; \ No newline at end of file diff --git a/gbe_ecp2m/trb_net16_lsm_sfp_gbe.vhd b/gbe_ecp2m/trb_net16_lsm_sfp_gbe.vhd new file mode 100755 index 0000000..7624a16 --- /dev/null +++ b/gbe_ecp2m/trb_net16_lsm_sfp_gbe.vhd @@ -0,0 +1,236 @@ +-- LinkStateMachine for SFPs (GigE) + +-- Still missing: link reset features, fifo full error handling, signals on stat_op +-- Take care: all input signals must be synchronous to SYSCLK, +-- all output signals are synchronous to SYSCLK. +-- Clock Domain Crossing is in your responsibility! + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +--use work.trb_net_std.all; + +entity trb_net16_lsm_sfp_gbe is +port( SYSCLK : in std_logic; -- fabric clock (100MHz) + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available + -- status signals + SFP_MISSING_IN : in std_logic; -- SFP Missing ('1' = no SFP mounted, '0' = SFP in place) + SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established) + SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost) + SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked) + SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked) + -- control signals + FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset + LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset + USER_RESET_OUT : out std_logic; -- FPGA reset for user logic + -- debug signals + TIMING_CTR_OUT : out std_logic_vector(18 downto 0); + BSM_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture lsm_sfp_gbe of trb_net16_lsm_sfp_gbe is + +-- state machine signals +type STATES is ( QRST, SLEEP, DELAY, USERRST, LINK ); +signal CURRENT_STATE, NEXT_STATE: STATES; + +signal state_bits : std_logic_vector(3 downto 0); +signal next_ce_tctr : std_logic; +signal ce_tctr : std_logic; +signal next_rst_tctr : std_logic; +signal rst_tctr : std_logic; +signal next_quad_rst : std_logic; +signal quad_rst : std_logic; +signal next_lane_rst : std_logic; +signal lane_rst : std_logic; +signal next_user_rst : std_logic; +signal user_rst : std_logic; +signal sfp_missing_q : std_logic; +signal sfp_missing_qq : std_logic; +signal sfp_los_q : std_logic; +signal sfp_los_qq : std_logic; +signal sd_rxclk_bad_q : std_logic; +signal sd_rxclk_bad_qq : std_logic; +signal sd_rxclk_bad_qqq : std_logic; +signal sd_txclk_bad_q : std_logic; +signal sd_txclk_bad_qq : std_logic; +signal sd_txclk_bad_qqq : std_logic; +signal sd_rxclk_warn_comb : std_logic; +signal sd_rxclk_warn : std_logic; -- rising edge on rlol detected +signal sd_txclk_warn_comb : std_logic; +signal sd_txclk_warn : std_logic; -- rising edge on plol detected +signal timing_ctr : std_logic_vector(18 downto 0); +signal debug : std_logic_vector(31 downto 0); + +begin + +-- Debug signals +debug(31 downto 4) <= (others => '0'); +debug(3) <= sd_txclk_warn; +debug(2) <= sd_rxclk_warn; +debug(1) <= rst_tctr; +debug(0) <= ce_tctr; + +-- synchronize external signals from SFP +THE_SYNC_PROC: process( sysclk ) +begin + if( rising_edge(sysclk) ) then + -- SFP input signals + sfp_missing_qq <= sfp_missing_q; + sfp_missing_q <= sfp_missing_in; + sfp_los_qq <= sfp_los_q; + sfp_los_q <= sfp_los_in; + -- SerDes input signals + sd_rxclk_bad_qqq <= sd_rxclk_bad_qq; + sd_rxclk_bad_qq <= sd_rxclk_bad_q; + sd_rxclk_bad_q <= sd_rxclk_bad_in; + sd_txclk_bad_qqq <= sd_txclk_bad_q; + sd_txclk_bad_qq <= sd_txclk_bad_q; + sd_txclk_bad_q <= sd_txclk_bad_in; + -- edge detectors + sd_rxclk_warn <= sd_rxclk_warn_comb; + sd_txclk_warn <= sd_txclk_warn_comb; + end if; +end process THE_SYNC_PROC; + +-- combinatorial part of edge detectors (rlol, see remark on page 8-63 in HB1003.pdf) +sd_rxclk_warn_comb <= '1' when ( (sd_rxclk_bad_qqq = '0') and (sd_rxclk_bad_qq = '1') ) else '0'; +sd_txclk_warn_comb <= '1' when ( (sd_txclk_bad_qqq = '0') and (sd_txclk_bad_qq = '1') ) else '0'; + +-------------------------------------------------------------------------- +-- Main control state machine, startup control for SFP +-------------------------------------------------------------------------- + +-- Timing counter for reset sequencing +THE_TIMING_COUNTER_PROC: process( sysclk, clear ) +begin + if( clear = '1' ) then + timing_ctr <= (others => '0'); + elsif( rising_edge(sysclk) ) then + if ( (rst_tctr = '1') or (sd_rxclk_warn = '1') or (sd_txclk_warn = '1') ) then + timing_ctr <= (others => '0'); + elsif( ce_tctr = '1' ) then + timing_ctr <= timing_ctr + 1; + end if; + end if; +end process THE_TIMING_COUNTER_PROC; + +-- State machine +-- state registers +STATE_MEM: process( sysclk, clear ) +begin + if( clear = '1' ) then + CURRENT_STATE <= QRST; + ce_tctr <= '0'; + rst_tctr <= '0'; + quad_rst <= '1'; + lane_rst <= '1'; + user_rst <= '1'; + elsif( rising_edge(sysclk) ) then + CURRENT_STATE <= NEXT_STATE; + ce_tctr <= next_ce_tctr; + rst_tctr <= next_rst_tctr; + quad_rst <= next_quad_rst; + lane_rst <= next_lane_rst; + user_rst <= next_user_rst; + end if; +end process STATE_MEM; + +-- state transitions +PROC_STATE_TRANSFORM: process( CURRENT_STATE, sfp_missing_qq, sfp_los_qq, sd_txclk_bad_qqq, sd_rxclk_bad_qqq, + timing_ctr(8), timing_ctr(18), timing_ctr(17), + reset ) +begin + NEXT_STATE <= QRST; -- avoid latches + next_ce_tctr <= '0'; + next_rst_tctr <= '0'; + next_quad_rst <= '0'; + next_lane_rst <= '0'; + next_user_rst <= '0'; + case CURRENT_STATE is + when QRST => -- initial state, we stay there unless CLEAR is deasserted. + state_bits <= x"0"; + if( (timing_ctr(8) = '1') ) then + NEXT_STATE <= SLEEP; -- release QUAD_RST, wait for lock of RxClock and TxClock + next_lane_rst <= '1'; + next_user_rst <= '1'; + next_rst_tctr <= '1'; + else + NEXT_STATE <= QRST; -- count delay + next_ce_tctr <= '1'; + next_quad_rst <= '1'; + next_lane_rst <= '1'; + next_user_rst <= '1'; + end if; + when SLEEP => -- we check for SFP presence and signal + state_bits <= x"1"; + if( (sfp_missing_qq = '0') and (sfp_los_qq = '0') ) then + NEXT_STATE <= DELAY; -- do a correctly timed QUAD reset (about 150ns) + next_ce_tctr <= '1'; + next_lane_rst <= '1'; + next_user_rst <= '1'; + else + NEXT_STATE <= SLEEP; -- wait for SFP present signal + next_lane_rst <= '1'; + next_user_rst <= '1'; + end if; + when DELAY => -- we wait approx. 4ms and check for PLL lock in the SerDes + state_bits <= x"2"; + if( (timing_ctr(18) = '1') and (timing_ctr(17) = '1') and (sd_rxclk_bad_qqq = '0') and (sd_txclk_bad_qqq = '0') ) then + NEXT_STATE <= USERRST; -- we release lane reset + next_ce_tctr <= '1'; + next_user_rst <= '1'; + else + NEXT_STATE <= DELAY; + next_ce_tctr <= '1'; + next_lane_rst <= '1'; + next_user_rst <= '1'; + end if; + when USERRST => -- short delay for user reset + state_bits <= x"3"; + if( (timing_ctr(18) = '0') and (timing_ctr(17) = '0') ) then + NEXT_STATE <= LINK; + next_rst_tctr <= '1'; + else + NEXT_STATE <= USERRST; + next_ce_tctr <= '1'; + next_user_rst <= '1'; + end if; + when LINK => -- operational + state_bits <= x"4"; + NEXT_STATE <= LINK; + when others => + NEXT_STATE <= QRST; + end case; + + -- emergency jumps in case of SFP problems + if( ((sfp_missing_qq = '1') or (sfp_los_qq = '1') or (RESET = '1')) and CURRENT_STATE /= QRST ) then + NEXT_STATE <= SLEEP; -- wait for SFP present signal + next_rst_tctr <= '1'; + next_lane_rst <= '1'; + next_user_rst <= '1'; + end if; +end process; + +-------------------------------------------------------------------------- +-- Output signals +-------------------------------------------------------------------------- +full_reset_out <= quad_rst; +lane_reset_out <= lane_rst; +user_reset_out <= user_rst; + +-------------------------------------------------------------------------- +-- Debug output +-------------------------------------------------------------------------- +timing_ctr_out <= timing_ctr; +bsm_out <= state_bits; +debug_out <= debug; + +end architecture; \ No newline at end of file diff --git a/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd b/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd new file mode 100755 index 0000000..e2eeff5 --- /dev/null +++ b/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd @@ -0,0 +1,373 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +entity trb_net16_med_ecp_sfp_gbe_8b is +port( + RESET : in std_logic; + GSR_N : in std_logic; + CLK_125_OUT : out std_logic; + CLK_RX_OUT : out std_logic; + CLK_TX_OUT : out std_logic; + --SGMII connection to frame transmitter (tsmac) + FT_TX_CLK_EN_OUT : out std_logic; + FT_RX_CLK_EN_OUT : out std_logic; + FT_COL_OUT : out std_logic; + FT_CRS_OUT : out std_logic; + FT_TXD_IN : in std_logic_vector(7 downto 0); + FT_TX_EN_IN : in std_logic; + FT_TX_ER_IN : in std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic; -- SFP disable + -- Autonegotiation stuff + MR_RESET_IN : in std_logic; + MR_MODE_IN : in std_logic; + MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0); -- should be x"0020 + MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0); -- advert page from link partner + MR_AN_PAGE_RX_OUT : out std_logic; + MR_AN_COMPLETE_OUT : out std_logic; + MR_AN_ENABLE_IN : in std_logic; + MR_RESTART_AN_IN : in std_logic; + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) +); +end entity; + +architecture trb_net16_med_ecp_sfp_gbe_8b of trb_net16_med_ecp_sfp_gbe_8b is + +-- Placer Directives +attribute HGROUP : string; +-- for whole architecture +attribute HGROUP of trb_net16_med_ecp_sfp_gbe_8b : architecture is "media_interface_group"; +attribute syn_sharing : string; +attribute syn_sharing of trb_net16_med_ecp_sfp_gbe_8b : architecture is "off"; + +component serdes_gbe_0_extclock_8b is +GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt"); +port( refclkp : in std_logic; + refclkn : in std_logic; + hdinp0 : in std_logic; + hdinn0 : in std_logic; + hdoutp0 : out std_logic; + hdoutn0 : out std_logic; + ff_rxiclk_ch0 : in std_logic; + ff_txiclk_ch0 : in std_logic; + ff_ebrd_clk_0 : in std_logic; + ff_txdata_ch0 : in std_logic_vector (7 downto 0); + ff_rxdata_ch0 : out std_logic_vector (7 downto 0); + ff_tx_k_cntrl_ch0 : in std_logic; + ff_rx_k_cntrl_ch0 : out std_logic; + ff_rxfullclk_ch0 : out std_logic; + ff_xmit_ch0 : in std_logic; + ff_correct_disp_ch0 : in std_logic; + ff_disp_err_ch0 : out std_logic; + ff_cv_ch0 : out std_logic; + ff_rx_even_ch0 : out std_logic; + ffc_rrst_ch0 : in std_logic; + ffc_lane_tx_rst_ch0 : in std_logic; + ffc_lane_rx_rst_ch0 : in std_logic; + ffc_txpwdnb_ch0 : in std_logic; + ffc_rxpwdnb_ch0 : in std_logic; + ffs_rlos_lo_ch0 : out std_logic; + ffs_ls_sync_status_ch0 : out std_logic; + ffs_rlol_ch0 : out std_logic; + oob_out_ch0 : out std_logic; + ffc_macro_rst : in std_logic; + ffc_quad_rst : in std_logic; + ffc_trst : in std_logic; + ff_txfullclk : out std_logic; + ff_txhalfclk : out std_logic; + refck2core : out std_logic; + ffs_plol : out std_logic + ); +end component; + +component sgmii_gbe_pcs32 +port( rst_n : in std_logic; + signal_detect : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + operational_rate : in std_logic_vector(1 downto 0); + debug_link_timer_short : in std_logic; + rx_compensation_err : out std_logic; + tx_clk_125 : in std_logic; + tx_clock_enable_source : out std_logic; + tx_clock_enable_sink : in std_logic; + tx_d : in std_logic_vector(7 downto 0); + tx_en : in std_logic; + tx_er : in std_logic; + rx_clk_125 : in std_logic; + rx_clock_enable_source : out std_logic; + rx_clock_enable_sink : in std_logic; + rx_d : out std_logic_vector(7 downto 0); + rx_dv : out std_logic; + rx_er : out std_logic; + col : out std_logic; + crs : out std_logic; + tx_data : out std_logic_vector(7 downto 0); + tx_kcntl : out std_logic; + tx_disparity_cntl : out std_logic; + serdes_recovered_clk : in std_logic; + rx_data : in std_logic_vector(7 downto 0); + rx_even : in std_logic; + rx_kcntl : in std_logic; + rx_disp_err : in std_logic; + rx_cv_err : in std_logic; + rx_err_decode_mode : in std_logic; + mr_an_complete : out std_logic; + mr_page_rx : out std_logic; + mr_lp_adv_ability : out std_logic_vector(15 downto 0); + mr_main_reset : in std_logic; + mr_an_enable : in std_logic; + mr_restart_an : in std_logic; + mr_adv_ability : in std_logic_vector(15 downto 0) + ); +end component; + +component trb_net16_lsm_sfp_gbe is +port( SYSCLK : in std_logic; -- fabric clock (100MHz) + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available + -- status signals + SFP_MISSING_IN : in std_logic; -- SFP Missing ('1' = no SFP mounted, '0' = SFP in place) + SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established) + SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost) + SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked) + SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked) + -- control signals + FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset + LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset + USER_RESET_OUT : out std_logic; -- FPGA reset for user logic + -- debug signals + TIMING_CTR_OUT : out std_logic_vector(18 downto 0); + BSM_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end component; + +signal refclkcore : std_logic; + +signal sd_link_ok : std_logic; +signal sd_link_error : std_logic_vector(2 downto 0); + +signal sd_tx_data : std_logic_vector(7 downto 0); +signal sd_tx_kcntl : std_logic; +signal sd_tx_correct_disp : std_logic; +signal sd_tx_clk : std_logic; + +signal sd_rx_data : std_logic_vector(7 downto 0); +signal sd_rx_even : std_logic; +signal sd_rx_kcntl : std_logic; +signal sd_rx_disp_error : std_logic; +signal sd_rx_cv_error : std_logic; +signal sd_rx_clk : std_logic; + +signal pcs_mr_an_complete : std_logic; +signal pcs_mr_ability : std_logic_vector(15 downto 0); +signal pcs_mr_page_rx : std_logic; +signal pcs_mr_reset : std_logic; + +signal pcs_tx_clk_en : std_logic; +signal pcs_rx_clk_en : std_logic; +signal pcs_rx_comp_err : std_logic; + +signal pcs_rx_d : std_logic_vector(7 downto 0); +signal pcs_rx_dv : std_logic; +signal pcs_rx_er : std_logic; + +signal sd_rx_debug : std_logic_vector(15 downto 0); +signal sd_tx_debug : std_logic_vector(15 downto 0); + +signal buf_stat_debug : std_logic_vector(63 downto 0); + +signal quad_rst : std_logic; +signal lane_rst : std_logic; +signal user_rst : std_logic; + +signal reset_bsm : std_logic_vector(3 downto 0); +signal reset_debug : std_logic_vector(31 downto 0); + +begin + +-- Reset state machine for SerDes +THE_RESET_STATEMACHINE: trb_net16_lsm_sfp_gbe +port map( SYSCLK => refclkcore, + RESET => '0', -- really? + CLEAR => RESET, -- from 100MHz PLL, includes async part + -- status signals + SFP_MISSING_IN => SD_PRSNT_N_IN, + SFP_LOS_IN => SD_LOS_IN, + SD_LINK_OK_IN => '1', -- not used + SD_LOS_IN => '0', -- not used + SD_TXCLK_BAD_IN => sd_link_error(2), -- plol + SD_RXCLK_BAD_IN => sd_link_error(1), -- rlol + -- control signals + FULL_RESET_OUT => quad_rst, + LANE_RESET_OUT => lane_rst, + USER_RESET_OUT => user_rst, + -- debug signals + TIMING_CTR_OUT => open, + BSM_OUT => reset_bsm, + DEBUG_OUT => reset_debug + ); + +-- SerDes for GbE +SERDES_GBE : serdes_gbe_0_extclock_8b +port map( -- SerDes connection to outside world + refclkp => SD_REFCLK_P_IN, -- SerDes REFCLK diff. input + refclkn => SD_REFCLK_N_IN, + hdinp0 => SD_RXD_P_IN, -- SerDes RX diff. input + hdinn0 => SD_RXD_N_IN, + hdoutp0 => SD_TXD_P_OUT, -- SerDes TX diff. output + hdoutn0 => SD_TXD_N_OUT, + refck2core => refclkcore, -- reference clock from input + -- RX part + ff_rxfullclk_ch0 => sd_rx_clk, -- RX full clock output + ff_rxiclk_ch0 => sd_rx_clk, + ff_ebrd_clk_0 => sd_rx_clk, -- EB ist not used as recommended by Lattice + ff_rxdata_ch0 => sd_rx_data, -- RX data output + ff_rx_k_cntrl_ch0 => sd_rx_kcntl, -- RX komma output + ff_rx_even_ch0 => sd_rx_even, -- for autonegotiation (output) + ff_disp_err_ch0 => sd_rx_disp_error, -- RX disparity error + ff_cv_ch0 => sd_rx_cv_error, -- RX code violation error + -- TX part + ff_txfullclk => sd_tx_clk, -- TX full clock output + ff_txiclk_ch0 => sd_tx_clk, + ff_txhalfclk => open, + ff_txdata_ch0 => sd_tx_data, -- TX data input + ff_tx_k_cntrl_ch0 => sd_tx_kcntl, -- TX komma input + ff_xmit_ch0 => '0', -- for autonegotiation (input) + ff_correct_disp_ch0 => sd_tx_correct_disp, -- controls disparity at IPG start (input) + -- Resets and power down + ffc_quad_rst => quad_rst, -- async reset for whole QUAD (active high) + ffc_lane_tx_rst_ch0 => lane_rst, -- async reset for TX channel + ffc_lane_rx_rst_ch0 => lane_rst, -- async reset for RX channel + ffc_rrst_ch0 => '0', -- '0' for normal operation + ffc_macro_rst => '0', -- '0' for normal operation + ffc_trst => '0', -- '0' for normal operation + ffc_txpwdnb_ch0 => '1', -- must be '1' + ffc_rxpwdnb_ch0 => '1', -- must be '1' + -- Status outputs + ffs_ls_sync_status_ch0 => sd_link_ok, -- synced to kommas? + ffs_rlos_lo_ch0 => sd_link_error(0), -- loss of signal in RX channel + ffs_rlol_ch0 => sd_link_error(1), -- loss of lock in RX PLL + ffs_plol => sd_link_error(2), -- loss of lock in TX PLL + oob_out_ch0 => open -- not needed + ); + +SD_RX_DATA_PROC: process( sd_rx_clk ) +begin + if( rising_edge(sd_rx_clk) ) then + sd_rx_debug(15 downto 12) <= (others => '0'); + sd_rx_debug(11) <= sd_rx_disp_error; + sd_rx_debug(10) <= sd_rx_even; + sd_rx_debug(9) <= sd_rx_cv_error; + sd_rx_debug(8) <= sd_rx_kcntl; + sd_rx_debug(7 downto 0) <= sd_rx_data; + end if; +end process SD_RX_DATA_PROC; + +SD_TX_DATA_PROC: process( sd_tx_clk ) +begin + if( rising_edge(sd_tx_clk) ) then + sd_tx_debug(15 downto 10) <= (others => '0'); + sd_tx_debug(9) <= sd_tx_correct_disp; + sd_tx_debug(8) <= sd_tx_kcntl; + sd_tx_debug(7 downto 0) <= sd_tx_data; + end if; +end process SD_TX_DATA_PROC; + +buf_stat_debug(63 downto 40) <= (others => '0'); +buf_stat_debug(39 downto 36) <= reset_debug(3 downto 0); +buf_stat_debug(35 downto 32) <= reset_bsm; +-- logic analyzer signals +buf_stat_debug(31) <= pcs_mr_page_rx; +buf_stat_debug(30) <= pcs_mr_reset; --pcs_mr_an_complete; +buf_stat_debug(28 downto 26) <= reset_bsm(2 downto 0); +buf_stat_debug(25 downto 23) <= sd_link_error(2 downto 0); +buf_stat_debug(22) <= sd_link_ok; +buf_stat_debug(21 downto 12) <= sd_tx_debug(9 downto 0); +buf_stat_debug(11 downto 0) <= sd_rx_debug(11 downto 0); + + +SGMII_GBE_PCS : sgmii_gbe_pcs32 +port map( rst_n => GSR_N, + signal_detect => sd_link_ok, + gbe_mode => '1', + sgmii_mode => MR_MODE_IN, + operational_rate => "10", + debug_link_timer_short => '0', + rx_compensation_err => pcs_rx_comp_err, + -- MAC interface + tx_clk_125 => refclkcore, -- original clock from SerDes + tx_clock_enable_source => pcs_tx_clk_en, + tx_clock_enable_sink => pcs_tx_clk_en, + tx_d => FT_TXD_IN, -- TX data from MAC + tx_en => FT_TX_EN_IN, -- TX data enable from MAC + tx_er => FT_TX_ER_IN, -- TX error from MAC + rx_clk_125 => refclkcore, -- original clock from SerDes + rx_clock_enable_source => pcs_rx_clk_en, + rx_clock_enable_sink => pcs_rx_clk_en, + rx_d => pcs_rx_d, -- RX data to MAC + rx_dv => pcs_rx_dv, -- RX data enable to MAC + rx_er => pcs_rx_er, -- RX error to MAC + col => FT_COL_OUT, + crs => FT_CRS_OUT, + -- SerDes interface + tx_data => sd_tx_data, -- TX data to SerDes + tx_kcntl => sd_tx_kcntl, -- TX komma control to SerDes + tx_disparity_cntl => sd_tx_correct_disp, -- idle parity state control in IPG (to SerDes) + serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream + rx_data => sd_rx_data, -- RX data from SerDes + rx_kcntl => sd_rx_kcntl, -- RX komma control from SerDes + rx_err_decode_mode => '0', -- receive error control mode fixed to normal + rx_even => '0', -- unused (receive error control mode = normal, tie to GND) + rx_disp_err => sd_rx_disp_error, -- RX disparity error from SerDes + rx_cv_err => sd_rx_cv_error, -- RX code violation error from SerDes + -- Autonegotiation stuff + mr_an_complete => pcs_mr_an_complete, + mr_page_rx => pcs_mr_page_rx, + mr_lp_adv_ability => pcs_mr_ability, + mr_main_reset => pcs_mr_reset, + mr_an_enable => MR_AN_ENABLE_IN, + mr_restart_an => MR_RESTART_AN_IN, + mr_adv_ability => MR_ADV_ABILITY_IN + ); + +pcs_mr_reset <= MR_RESET_IN or RESET or user_rst; + +FT_TX_CLK_EN_OUT <= pcs_tx_clk_en; -- to MAC +FT_RX_CLK_EN_OUT <= pcs_rx_clk_en; -- to MAC + +MR_AN_LP_ABILITY_OUT <= pcs_mr_ability; +MR_AN_COMPLETE_OUT <= pcs_mr_an_complete; +MR_AN_PAGE_RX_OUT <= pcs_mr_page_rx; + +-- Clock games +CLK_125_OUT <= refclkcore; +CLK_RX_OUT <= sd_rx_clk; +CLK_TX_OUT <= sd_tx_clk; + +-- Fakes +STAT_OP <= (others => '0'); +SD_TXDIS_OUT <= '0'; -- enable +STAT_DEBUG <= buf_stat_debug; + +end architecture; \ No newline at end of file