From: Tobias Weber <toweber86@gmail.com>
Date: Thu, 31 Aug 2017 07:31:40 +0000 (+0200)
Subject: creating new directories for Mupix6 and Mupix8 source code.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=2cddc07c1c317e0cad7630c9952410a06d487380;p=trb3.git

creating new directories for Mupix6 and Mupix8 source code.
---

diff --git a/mupix/compile_GSI.pl b/mupix/Mupix6/compile_GSI.pl
similarity index 100%
rename from mupix/compile_GSI.pl
rename to mupix/Mupix6/compile_GSI.pl
diff --git a/mupix/config.vhd b/mupix/Mupix6/config.vhd
similarity index 100%
rename from mupix/config.vhd
rename to mupix/Mupix6/config.vhd
diff --git a/mupix/cores/fifo_32_data.ipx b/mupix/Mupix6/cores/fifo_32_data.ipx
similarity index 100%
rename from mupix/cores/fifo_32_data.ipx
rename to mupix/Mupix6/cores/fifo_32_data.ipx
diff --git a/mupix/cores/fifo_32_data.lpc b/mupix/Mupix6/cores/fifo_32_data.lpc
similarity index 100%
rename from mupix/cores/fifo_32_data.lpc
rename to mupix/Mupix6/cores/fifo_32_data.lpc
diff --git a/mupix/cores/fifo_32_data.vhd b/mupix/Mupix6/cores/fifo_32_data.vhd
similarity index 100%
rename from mupix/cores/fifo_32_data.vhd
rename to mupix/Mupix6/cores/fifo_32_data.vhd
diff --git a/mupix/cores/fifo_32x2k.ipx b/mupix/Mupix6/cores/fifo_32x2k.ipx
similarity index 100%
rename from mupix/cores/fifo_32x2k.ipx
rename to mupix/Mupix6/cores/fifo_32x2k.ipx
diff --git a/mupix/cores/fifo_32x2k.lpc b/mupix/Mupix6/cores/fifo_32x2k.lpc
similarity index 100%
rename from mupix/cores/fifo_32x2k.lpc
rename to mupix/Mupix6/cores/fifo_32x2k.lpc
diff --git a/mupix/cores/fifo_32x2k.vhd b/mupix/Mupix6/cores/fifo_32x2k.vhd
similarity index 100%
rename from mupix/cores/fifo_32x2k.vhd
rename to mupix/Mupix6/cores/fifo_32x2k.vhd
diff --git a/mupix/cores/fifo_36x2k_oreg.ipx b/mupix/Mupix6/cores/fifo_36x2k_oreg.ipx
similarity index 100%
rename from mupix/cores/fifo_36x2k_oreg.ipx
rename to mupix/Mupix6/cores/fifo_36x2k_oreg.ipx
diff --git a/mupix/cores/fifo_36x2k_oreg.lpc b/mupix/Mupix6/cores/fifo_36x2k_oreg.lpc
similarity index 100%
rename from mupix/cores/fifo_36x2k_oreg.lpc
rename to mupix/Mupix6/cores/fifo_36x2k_oreg.lpc
diff --git a/mupix/cores/fifo_36x2k_oreg.vhd b/mupix/Mupix6/cores/fifo_36x2k_oreg.vhd
similarity index 100%
rename from mupix/cores/fifo_36x2k_oreg.vhd
rename to mupix/Mupix6/cores/fifo_36x2k_oreg.vhd
diff --git a/mupix/cores/fifo_4k32_async.ipx b/mupix/Mupix6/cores/fifo_4k32_async.ipx
similarity index 100%
rename from mupix/cores/fifo_4k32_async.ipx
rename to mupix/Mupix6/cores/fifo_4k32_async.ipx
diff --git a/mupix/cores/fifo_4k32_async.lpc b/mupix/Mupix6/cores/fifo_4k32_async.lpc
similarity index 100%
rename from mupix/cores/fifo_4k32_async.lpc
rename to mupix/Mupix6/cores/fifo_4k32_async.lpc
diff --git a/mupix/cores/fifo_4k32_async.vhd b/mupix/Mupix6/cores/fifo_4k32_async.vhd
similarity index 100%
rename from mupix/cores/fifo_4k32_async.vhd
rename to mupix/Mupix6/cores/fifo_4k32_async.vhd
diff --git a/mupix/cores/pll_in200_out100_50.ipx b/mupix/Mupix6/cores/pll_in200_out100_50.ipx
similarity index 100%
rename from mupix/cores/pll_in200_out100_50.ipx
rename to mupix/Mupix6/cores/pll_in200_out100_50.ipx
diff --git a/mupix/cores/pll_in200_out100_50.lpc b/mupix/Mupix6/cores/pll_in200_out100_50.lpc
similarity index 100%
rename from mupix/cores/pll_in200_out100_50.lpc
rename to mupix/Mupix6/cores/pll_in200_out100_50.lpc
diff --git a/mupix/cores/pll_in200_out100_50.vhd b/mupix/Mupix6/cores/pll_in200_out100_50.vhd
similarity index 100%
rename from mupix/cores/pll_in200_out100_50.vhd
rename to mupix/Mupix6/cores/pll_in200_out100_50.vhd
diff --git a/mupix/sources/BlockMemory.vhd b/mupix/Mupix6/sources/BlockMemory.vhd
similarity index 100%
rename from mupix/sources/BlockMemory.vhd
rename to mupix/Mupix6/sources/BlockMemory.vhd
diff --git a/mupix/sources/CRC.vhd b/mupix/Mupix6/sources/CRC.vhd
similarity index 100%
rename from mupix/sources/CRC.vhd
rename to mupix/Mupix6/sources/CRC.vhd
diff --git a/mupix/sources/EventBuffer.vhd b/mupix/Mupix6/sources/EventBuffer.vhd
similarity index 100%
rename from mupix/sources/EventBuffer.vhd
rename to mupix/Mupix6/sources/EventBuffer.vhd
diff --git a/mupix/sources/FIFO.vhd b/mupix/Mupix6/sources/FIFO.vhd
similarity index 100%
rename from mupix/sources/FIFO.vhd
rename to mupix/Mupix6/sources/FIFO.vhd
diff --git a/mupix/sources/FIFO_FWFT.vhd b/mupix/Mupix6/sources/FIFO_FWFT.vhd
similarity index 100%
rename from mupix/sources/FIFO_FWFT.vhd
rename to mupix/Mupix6/sources/FIFO_FWFT.vhd
diff --git a/mupix/sources/Histogram.vhd b/mupix/Mupix6/sources/Histogram.vhd
similarity index 100%
rename from mupix/sources/Histogram.vhd
rename to mupix/Mupix6/sources/Histogram.vhd
diff --git a/mupix/sources/HitbusHistogram.vhd b/mupix/Mupix6/sources/HitbusHistogram.vhd
similarity index 100%
rename from mupix/sources/HitbusHistogram.vhd
rename to mupix/Mupix6/sources/HitbusHistogram.vhd
diff --git a/mupix/sources/MuPix3_PixCtr.vhd b/mupix/Mupix6/sources/MuPix3_PixCtr.vhd
similarity index 100%
rename from mupix/sources/MuPix3_PixCtr.vhd
rename to mupix/Mupix6/sources/MuPix3_PixCtr.vhd
diff --git a/mupix/sources/MuPix3_board.vhd b/mupix/Mupix6/sources/MuPix3_board.vhd
similarity index 100%
rename from mupix/sources/MuPix3_board.vhd
rename to mupix/Mupix6/sources/MuPix3_board.vhd
diff --git a/mupix/sources/MuPix3_boardinterface.vhd b/mupix/Mupix6/sources/MuPix3_boardinterface.vhd
similarity index 100%
rename from mupix/sources/MuPix3_boardinterface.vhd
rename to mupix/Mupix6/sources/MuPix3_boardinterface.vhd
diff --git a/mupix/sources/MuPix3_interface.vhd b/mupix/Mupix6/sources/MuPix3_interface.vhd
similarity index 100%
rename from mupix/sources/MuPix3_interface.vhd
rename to mupix/Mupix6/sources/MuPix3_interface.vhd
diff --git a/mupix/sources/MupixDigiConverter.vhd b/mupix/Mupix6/sources/MupixDigiConverter.vhd
similarity index 100%
rename from mupix/sources/MupixDigiConverter.vhd
rename to mupix/Mupix6/sources/MupixDigiConverter.vhd
diff --git a/mupix/sources/ResetHandler.vhd b/mupix/Mupix6/sources/ResetHandler.vhd
similarity index 100%
rename from mupix/sources/ResetHandler.vhd
rename to mupix/Mupix6/sources/ResetHandler.vhd
diff --git a/mupix/sources/SignalDelay.vhd b/mupix/Mupix6/sources/SignalDelay.vhd
similarity index 100%
rename from mupix/sources/SignalDelay.vhd
rename to mupix/Mupix6/sources/SignalDelay.vhd
diff --git a/mupix/sources/StdTypes.vhd b/mupix/Mupix6/sources/StdTypes.vhd
similarity index 100%
rename from mupix/sources/StdTypes.vhd
rename to mupix/Mupix6/sources/StdTypes.vhd
diff --git a/mupix/sources/TimeWalk.vhd b/mupix/Mupix6/sources/TimeWalk.vhd
similarity index 100%
rename from mupix/sources/TimeWalk.vhd
rename to mupix/Mupix6/sources/TimeWalk.vhd
diff --git a/mupix/sources/TimeWalkWithFiFo.vhd b/mupix/Mupix6/sources/TimeWalkWithFiFo.vhd
similarity index 100%
rename from mupix/sources/TimeWalkWithFiFo.vhd
rename to mupix/Mupix6/sources/TimeWalkWithFiFo.vhd
diff --git a/mupix/sources/TriggerHandler.vhd b/mupix/Mupix6/sources/TriggerHandler.vhd
similarity index 100%
rename from mupix/sources/TriggerHandler.vhd
rename to mupix/Mupix6/sources/TriggerHandler.vhd
diff --git a/mupix/sources/graycounter.vhd b/mupix/Mupix6/sources/graycounter.vhd
similarity index 100%
rename from mupix/sources/graycounter.vhd
rename to mupix/Mupix6/sources/graycounter.vhd
diff --git a/mupix/sources/injection_generator.vhd b/mupix/Mupix6/sources/injection_generator.vhd
similarity index 100%
rename from mupix/sources/injection_generator.vhd
rename to mupix/Mupix6/sources/injection_generator.vhd
diff --git a/mupix/sources/mupix_components.vhd b/mupix/Mupix6/sources/mupix_components.vhd
similarity index 100%
rename from mupix/sources/mupix_components.vhd
rename to mupix/Mupix6/sources/mupix_components.vhd
diff --git a/mupix/sources/spi_if.vhd b/mupix/Mupix6/sources/spi_if.vhd
similarity index 100%
rename from mupix/sources/spi_if.vhd
rename to mupix/Mupix6/sources/spi_if.vhd
diff --git a/mupix/tb/CRCTest.vhd b/mupix/Mupix6/tb/CRCTest.vhd
similarity index 100%
rename from mupix/tb/CRCTest.vhd
rename to mupix/Mupix6/tb/CRCTest.vhd
diff --git a/mupix/tb/HitbusHistogramTest.vhd b/mupix/Mupix6/tb/HitbusHistogramTest.vhd
similarity index 100%
rename from mupix/tb/HitbusHistogramTest.vhd
rename to mupix/Mupix6/tb/HitbusHistogramTest.vhd
diff --git a/mupix/tb/MuPixInterfaceTest.vhd b/mupix/Mupix6/tb/MuPixInterfaceTest.vhd
similarity index 100%
rename from mupix/tb/MuPixInterfaceTest.vhd
rename to mupix/Mupix6/tb/MuPixInterfaceTest.vhd
diff --git a/mupix/tb/MupixShiftReg.vhd b/mupix/Mupix6/tb/MupixShiftReg.vhd
similarity index 100%
rename from mupix/tb/MupixShiftReg.vhd
rename to mupix/Mupix6/tb/MupixShiftReg.vhd
diff --git a/mupix/tb/PixCtrlTest.vhd b/mupix/Mupix6/tb/PixCtrlTest.vhd
similarity index 100%
rename from mupix/tb/PixCtrlTest.vhd
rename to mupix/Mupix6/tb/PixCtrlTest.vhd
diff --git a/mupix/tb/TRBSimulation.vhd b/mupix/Mupix6/tb/TRBSimulation.vhd
similarity index 100%
rename from mupix/tb/TRBSimulation.vhd
rename to mupix/Mupix6/tb/TRBSimulation.vhd
diff --git a/mupix/trb3_periph.p2t b/mupix/Mupix6/trb3_periph.p2t
similarity index 100%
rename from mupix/trb3_periph.p2t
rename to mupix/Mupix6/trb3_periph.p2t
diff --git a/mupix/Mupix6/trb3_periph.prj b/mupix/Mupix6/trb3_periph.prj
new file mode 100644
index 0000000..f02c1d8
--- /dev/null
+++ b/mupix/Mupix6/trb3_periph.prj
@@ -0,0 +1,167 @@
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology LATTICE-ECP3
+set_option -part LFE3_150EA
+set_option -package FN672C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb3_periph"
+set_option -resource_sharing true
+
+# map options
+set_option -frequency 200
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+#set_option -force_gsr 
+set_option -force_gsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb3_periph.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+
+
+#add_file options
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib "work" "../../base/trb3_components.vhd"
+
+add_file -vhdl -lib work "../../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_addresses.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/bus_register_handler.vhd"
+
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" 
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/spi_flash_and_fpga_reload.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../../trbnet/optical_link/f_divider.vhd"
+
+add_file -vhdl -lib work "../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
+add_file -vhdl -lib work "../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
+add_file -vhdl -lib work "../../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "../../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
+
+add_file -vhdl -lib "work" "../../base/cores/pll_in200_out100.vhd"
+
+#MuPix Files
+add_file -vhdl -lib "work" "trb3_periph.vhd"
+
+add_file -vhdl -lib "work" "sources/mupix_components.vhd"
+add_file -vhdl -lib "work" "sources/BlockMemory.vhd"
+add_file -vhdl -lib "work" "sources/EventBuffer.vhd"
+add_file -vhdl -lib "work" "sources/graycounter.vhd"
+add_file -vhdl -lib "work" "sources/Histogram.vhd"
+add_file -vhdl -lib "work" "sources/HitbusHistogram.vhd"
+add_file -vhdl -lib "work" "sources/injection_generator.vhd"
+add_file -vhdl -lib "work" "sources/MuPix3_board.vhd"
+add_file -vhdl -lib "work" "sources/MuPix3_interface.vhd"
+add_file -vhdl -lib "work" "sources/MuPix3_PixCtr.vhd"
+add_file -vhdl -lib "work" "sources/spi_if.vhd"
+add_file -vhdl -lib "work" "sources/MuPix3_boardinterface.vhd"
+add_file -vhdl -lib "work" "sources/TriggerHandler.vhd"
+add_file -vhdl -lib "work" "cores/fifo_32x2k.vhd"
+add_file -vhdl -lib "work" "sources/ResetHandler.vhd"
+add_file -vhdl -lib "work" "cores/fifo_4k32_async.vhd"
+add_file -vhdl -lib "work" "sources/TimeWalk.vhd"
+add_file -vhdl -lib "work" "sources/TimeWalkWithFiFo.vhd"
+add_file -vhdl -lib "work" "sources/SignalDelay.vhd"
+add_file -vhdl -lib "work" "sources/StdTypes.vhd"
\ No newline at end of file
diff --git a/mupix/trb3_periph.vhd b/mupix/Mupix6/trb3_periph.vhd
similarity index 100%
rename from mupix/trb3_periph.vhd
rename to mupix/Mupix6/trb3_periph.vhd
diff --git a/mupix/trb3_periph_constraints.lpf b/mupix/Mupix6/trb3_periph_constraints.lpf
similarity index 100%
rename from mupix/trb3_periph_constraints.lpf
rename to mupix/Mupix6/trb3_periph_constraints.lpf
diff --git a/mupix/trb3_periph.prj b/mupix/trb3_periph.prj
deleted file mode 100644
index a46de10..0000000
--- a/mupix/trb3_periph.prj
+++ /dev/null
@@ -1,167 +0,0 @@
-
-# implementation: "workdir"
-impl -add workdir -type fpga
-
-# device options
-set_option -technology LATTICE-ECP3
-set_option -part LFE3_150EA
-set_option -package FN672C
-set_option -speed_grade -8
-set_option -part_companion ""
-
-# compilation/mapping options
-set_option -default_enum_encoding sequential
-set_option -symbolic_fsm_compiler 1
-set_option -top_module "trb3_periph"
-set_option -resource_sharing true
-
-# map options
-set_option -frequency 200
-set_option -fanout_limit 100
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
-#set_option -force_gsr 
-set_option -force_gsr false
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
-set_option -compiler_compatible true
-
-
-# simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 1
-
-# automatic place and route (vendor) options
-set_option -write_apr_constraint 0
-
-# set result format/file last
-project -result_format "edif"
-project -result_file "workdir/trb3_periph.edf"
-
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -project_relative_includes 1
-impl -active "workdir"
-
-####################
-
-
-
-#add_file options
-add_file -vhdl -lib work "config.vhd"
-add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib "work" "../base/trb3_components.vhd"
-
-add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
-
-add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
-add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
-add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
-add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
-
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" 
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
-
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
-add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
-
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
-
-add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
-
-#MuPix Files
-add_file -vhdl -lib "work" "trb3_periph.vhd"
-
-add_file -vhdl -lib "work" "sources/mupix_components.vhd"
-add_file -vhdl -lib "work" "sources/BlockMemory.vhd"
-add_file -vhdl -lib "work" "sources/EventBuffer.vhd"
-add_file -vhdl -lib "work" "sources/graycounter.vhd"
-add_file -vhdl -lib "work" "sources/Histogram.vhd"
-add_file -vhdl -lib "work" "sources/HitbusHistogram.vhd"
-add_file -vhdl -lib "work" "sources/injection_generator.vhd"
-add_file -vhdl -lib "work" "sources/MuPix3_board.vhd"
-add_file -vhdl -lib "work" "sources/MuPix3_interface.vhd"
-add_file -vhdl -lib "work" "sources/MuPix3_PixCtr.vhd"
-add_file -vhdl -lib "work" "sources/spi_if.vhd"
-add_file -vhdl -lib "work" "sources/MuPix3_boardinterface.vhd"
-add_file -vhdl -lib "work" "sources/TriggerHandler.vhd"
-add_file -vhdl -lib "work" "cores/fifo_32x2k.vhd"
-add_file -vhdl -lib "work" "sources/ResetHandler.vhd"
-add_file -vhdl -lib "work" "cores/fifo_4k32_async.vhd"
-add_file -vhdl -lib "work" "sources/TimeWalk.vhd"
-add_file -vhdl -lib "work" "sources/TimeWalkWithFiFo.vhd"
-add_file -vhdl -lib "work" "sources/SignalDelay.vhd"
-add_file -vhdl -lib "work" "sources/StdTypes.vhd"
\ No newline at end of file